Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This invention provides a semiconductor device that can easily ensure a large contact between the sintered metal and the bonded interface. The semiconductor device comprises: a first component made of metal; and a second component including a semiconductor chip. The first component and the second component are bonded by sintering. Undulations are formed at the bonded interface of at least one of the first and second components, with the interval between the undulations being 10 μm or less.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] For high-heat-resistant power semiconductor modules used in electrified railways, electric vehicles, and industrial applications, there is a need to improve power cycle life. To meet this need, using sintering bonding with excellent heat resistance to bond the semiconductor chip to the substrate has become an effective solution, replacing the conventional solder bonding.

[0003] As for the technology related to sintering bonding, there are patent documents 1 and 2, for example.

[0004] In patent document 1 Figure 5 Paragraphs 0040-0044 describe the following technique: After forming pits on the surface of a substrate using a laser to achieve an anchoring effect, a paste-like sinterable metal bonding material is printed, the printed sinterable metal bonding material is dried, a semiconductor element is mounted and temporarily fixed on the dried sinterable metal bonding material, and then the substrate and semiconductor element are bonded by applying pressure and heating the sinterable metal bonding material.

[0005] Furthermore, Patent Document 2 describes how mixing sheet-like particles can suppress volume shrinkage during bonding, enabling sintering without pressure.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: International Publication No. 2019 / 087920

[0009] Patent Document 2: Japanese Patent Application Publication No. 2021-64612 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] In solder joints, the metal of the solder melts and wets the joint interface, thereby ensuring contact at the interface during the joint.

[0012] On the other hand, in sintering bonding, the sintered metal does not melt but is bonded through diffusion in a powder state, making it difficult to ensure interface contact compared to solder.

[0013] In contrast, as described in Patent Document 1, a technique is generally used to ensure interface contact by applying pressure to press the chip or wiring against the powder.

[0014] In addition, as another example, such as as described in Patent Document 2, a technique is disclosed that suppresses volume shrinkage during bonding by mixing sheet-like particles, thereby easily ensuring contact even without pressure.

[0015] However, even with applied pressure, it is sometimes difficult to ensure uniform contact with solid powder. Furthermore, due to concerns about damage to the chip, large pressures cannot be applied without limit.

[0016] Furthermore, even when volume shrinkage is suppressed by particle combination without pressure, it is still difficult to ensure interface contact compared to sintering techniques that actively wet and expand solder by melting the metal and ensure contact by suppressing some deviations through pressure.

[0017] To address the aforementioned problems, the present invention aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can easily ensure a large contact between the sintered metal and the interface to be bonded.

[0018] Furthermore, the above-mentioned and other objectives of the present invention, as well as the novel features of the present invention, become clear from the description and drawings herein.

[0019] Methods for solving problems

[0020] The first semiconductor device of the present invention comprises: a first component made of metal; and a second component including a semiconductor chip, wherein the first component and the second component are joined by sintering, and an unevenness is formed at the interface of at least one of the first component and the second component, the interval between the unevenness and the unevenness being 10 μm or less.

[0021] The second semiconductor device of the present invention comprises: a first component made of metal; and a second component including a semiconductor chip, wherein the first component and the second component are joined by sintering, and the interface of at least one of the first component and the second component is composed of grains with a particle size of 10 μm or less.

[0022] The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device by bonding a first component made of metal and a second component including a semiconductor chip by sintering. The bonding interface of at least one of the first component and the second component has an unevenness with a spacing of less than 10 μm, and then a sintering metal is supplied to the bonding interface with the unevenness to perform sintering bonding.

[0023] Invention Effects

[0024] According to the present invention described above, by forming fine irregularities with a spacing of less than 10 μm at the bonding interface, or by having the bonding interface composed of grains with a particle size of less than 10 μm, atomic diffusion during sintering bonding is promoted, the mutual diffusion between the sintered metal and the bonding interface becomes more active, and the bonding contacts become tighter. Thus, a bonding layer that is not easily peeled off and is easily thermally conductive can be obtained.

[0025] Furthermore, the issues, structures, and effects other than those described above will be clarified through the following description of the implementation methods. Attached Figure Description

[0026] Figure 1 This is a schematic cross-sectional view showing the structure of the semiconductor module in Embodiment 1.

[0027] Figure 2 This is a cross-sectional view showing an example of the structure of the bonded interface of the semiconductor module in Embodiment 1.

[0028] Figure 3 This is a schematic diagram illustrating diffusion during sintering.

[0029] Figure 4 A and B in the diagram represent cross-sectional views showing diffusion at the interface during typical sintering bonding.

[0030] Figure 5 A and B are cross-sectional views showing diffusion at the interface during sintering bonding in the semiconductor device of the present invention.

[0031] Figure 6 This is an SEM image of the surface state of the Ni film after etching.

[0032] Figure 7 Image A is a SEM image of a cross-section during the sintering and bonding of a typical Ni film. Image B is a SEM image of a cross-section during the sintering and bonding of a Ni film with uneven surfaces.

[0033] Figure 8 It is a cross-sectional view representing the phenomenon described in the Wenzel formula.

[0034] Figure 9 This is a cross-sectional view of the sintered joint of an existing semiconductor module.

[0035] Figure 10 This is a cross-sectional view of the sintered joint of the semiconductor module in Example 2.

[0036] Figure 11 A and B are cross-sectional views illustrating a method for manufacturing a semiconductor module according to Embodiment 3. Detailed Implementation

[0037] The embodiments and examples of the present invention will be described below using text and accompanying drawings. However, the structures, materials, and other specific configurations shown in the present invention are not limited to the embodiments described herein, and can be appropriately combined and modified without changing the spirit of the invention. Furthermore, elements not directly related to the present invention are omitted from the illustrations.

[0038] The first semiconductor device of the present invention comprises: a first component made of metal; and a second component including a semiconductor chip, wherein the first component and the second component are joined by sintering.

[0039] Furthermore, the first semiconductor device of the present invention has an uneven surface formed at the bonding interface of at least one of the first component and the second component, wherein the spacing between the uneven surface is 10 μm or less.

[0040] The second semiconductor device of the present invention comprises: a first component made of metal; and a second component including a semiconductor chip, wherein the first component and the second component are joined by sintering.

[0041] Furthermore, in the second semiconductor device of the present invention, the bonding interface of at least one of the first component and the second component is composed of grains with a particle size of 10 μm or less.

[0042] The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device by bonding a first component made of metal and a second component including a semiconductor chip by sintering.

[0043] Furthermore, in the semiconductor device manufacturing method of the present invention, a rough surface with a spacing of 10 μm or less is formed at the interface to be bonded in at least one of the first component and the second component, and then sintering metal is supplied to the interface to be bonded with the rough surface to perform sintering bonding.

[0044] According to the first semiconductor device and the method for manufacturing the semiconductor device of the present invention, an unevenness with a spacing of less than 10 μm is formed at the interface to be bonded in at least one of the first component and the second component, thereby promoting the diffusion of atoms during sintering bonding, making the interdiffusion between the sintered metal and the interface to be bonded more active, and making the bonding contacts tighter. As a result, a bonding layer that is not easy to peel off and is easy to conduct heat can be obtained.

[0045] According to the second semiconductor device of the present invention, the interface of at least one of the first and second components is composed of grains with a particle size of 10 μm or less. Therefore, the small grain size results in a greater number of grain boundaries. This promotes atomic diffusion during sintering, increases the interdiffusion between the sintered metal and the interface, and densifies the bonding contacts. Consequently, a bonding layer that is difficult to peel off and readily conducts heat can be obtained.

[0046] In the first semiconductor device described above, the unevenness spacing can be configured to be 0.1 μm or less.

[0047] In this structure, the particles of typical sintered metals are submicron in diameter, so unevenness is created near all particles that are located on average around the bonding interface. This facilitates further improvement in the quality of the sintered bond.

[0048] In the first semiconductor device described above, the depth of the unevenness can be configured to be 0.1 μm or more.

[0049] In this structure, by making the depth of the unevenness greater than 0.1 μm, it is easy to form a dense region of sintered metal.

[0050] In the aforementioned first semiconductor device, the diameter of the uneven opening can be less than 10 μm.

[0051] In this structure, by making the opening diameter of the concave and convex parts less than 10 μm, it is difficult for sintered metal particles to enter the concave and convex parts. Therefore, the thickness difference of the sintered metal inside and outside the concave and convex parts can be reduced, and the pressure applied during sintering can be uniformly transmitted.

[0052] In the aforementioned first semiconductor device, the diameter of the uneven opening can be less than 0.01 μm.

[0053] In this structure, by making the opening diameter of the concave and convex parts less than 0.01 μm, even when the sintered metal particles are submicron in diameter, the sintered metal particles are difficult to enter the concave and convex parts. Therefore, the thickness difference of the sintered metal inside and outside the concave and convex parts can be almost eliminated, and the pressure during sintering can be uniformly transmitted.

[0054] In the first semiconductor device described above, it is possible to configure the irregularities to form along the grain boundaries of the component.

[0055] In this configuration, the irregularities are formed along the grain boundaries of the component, thus sintering metal can easily enter the grain boundaries of the component. This, in turn, improves the quality of the sintered bond.

[0056] In the first semiconductor device described above, it can be configured such that the region with uneven surfaces extends outwards from the sintered region.

[0057] In this structure, an uneven area is formed in the region that extends outward from the sintered bonding region. Therefore, when the sintered metal paste is heated to remove the solvent, the uneven area that extends outward from the sintered bonding region can be used to facilitate the removal of the solvent.

[0058] In the first semiconductor device described above, the sintering metal that can be configured to sinter together the first component and the second component is copper.

[0059] In this configuration, due to the low diffusion rate of copper, sintering of the bonding layer caused by self-heating is unlikely to occur during the operation of the manufactured semiconductor device. Therefore, even if the sintering density of the bonding layer is low at the moment the bonding of the first and second components is completed, the reliability of the manufactured semiconductor device can be maintained.

[0060] In the first semiconductor device described above, a bonding interface with uneven surfaces can be formed by grains with a particle size of 10 μm or less.

[0061] In this configuration, the grain size is small, thus increasing the number of grain boundaries. This promotes atomic diffusion during sintering and enhances the interdiffusion between the sintered metal and the interface being bonded, resulting in denser bonding contacts. Consequently, a bonding layer that is difficult to peel off and readily conducts heat can be obtained.

[0062] In the above-described semiconductor device manufacturing method, during sintering bonding, it is possible to apply a pressure of 0.01 MPa to 1.00 MPa, or to perform bonding without applying pressure.

[0063] In this structure, since bonding is performed with less pressure or without pressure, damage to semiconductor chips and the like can be suppressed.

[0064] The first and second semiconductor devices described above include: a first component made of metal; and a second component including a semiconductor chip, which is a structure in which the first component and the second component are joined together by sintering.

[0065] Furthermore, the first and second semiconductor devices described above also include wiring for connecting to semiconductor chips, for example, forming a semiconductor module.

[0066] In the aforementioned semiconductor device and semiconductor device manufacturing method, the first component made of metal can be a wiring (wiring layer, wiring film), metal plate, etc., made of metal.

[0067] Furthermore, the metal used as the wiring layer can be, for example, Cu or Al. Additionally, Ni, Au, Ag, Pd, or other metals are sometimes formed as a coating on the surface of the wiring layer metal.

[0068] Furthermore, the first component can be a single-layer structure or a structure consisting of multiple layers. In either structure, the surfaces that are sintered and in contact with the sintered metal are the bonding interfaces.

[0069] In the above-described semiconductor device and method of manufacturing semiconductor device, the second component including the semiconductor chip can be configured such that a bonding material is formed on the outermost surface of the lower surface of the semiconductor chip.

[0070] As a semiconductor chip, it is possible to use semiconductor chips made of various semiconductor materials such as silicon and SiC.

[0071] Metals such as Ni, Cu, Au, Ag, and Pd can be used as the bonding materials.

[0072] Furthermore, the second component can be a single-layer structure or a structure consisting of multiple layers. In either structure, the surfaces that are sintered and in contact with the sintered metal are the joined interfaces.

[0073] In the aforementioned semiconductor device and its manufacturing method, metal powders such as Ag powder and Cu powder can be used as the sintering metal for sintering bonding.

[0074] In the aforementioned semiconductor device and its manufacturing method, the bumps and depressions can be formed by etching, laser processing, ion milling, etc.

[0075] Regarding the combination of the bonded material and the sintered metal, for Ag powder, the bonded material is mostly Au or Ag, and for Cu powder, the bonded material is mostly Ni or Cu, but it is not limited to these combinations.

[0076] In the first semiconductor device and the method for manufacturing the semiconductor device described above, the bumps and depressions are formed at the interface between the first component and the second component, or between the two components.

[0077] The spacing between the bumps and depressions is less than 10 μm.

[0078] Here, the "interval" between the protrusions and concaves in this invention is defined as the distance between the centers of the concave portions of adjacent protrusions and concaves for multiple protrusions and concaves.

[0079] The smaller the spacing between the bumps and recesses, the better. However, if it is less than 0.1 μm, considering that the particles of general sintered metals are submicron in diameter, it is easy to improve the quality by setting the bumps and recesses near all the particles that are located on average near the bonding interface.

[0080] On the other hand, from the point of view of thermal resistance, even on a slightly larger scale, as long as the joint is tight, the heat dissipation path can be adequately ensured. Therefore, the aforementioned spacing of less than 10 μm is preferred.

[0081] Furthermore, if the opening diameter of the irregularity is large, particles of the sintered metal before sintering can easily enter the irregularity. However, in this case, the difference in thickness between the sintered metal inside and outside the irregularity becomes larger, causing the shrinkage during sintering to vary depending on the location, making it difficult to uniformly transmit pressure. Therefore, an opening diameter that makes it difficult for particles to enter is preferred. When the particles of the sintered metal are submicron in diameter, the opening diameter of the irregularity is preferably 0.01 μm or less. However, if the case of including coarse particles at the micron level is considered, the opening diameter of the irregularity can also be around 10 μm or less.

[0082] In addition, when the depth of the unevenness (the depth of the opening) is, for example, around 0.1 μm, it is easy to form a dense area of ​​sintered metal, but it is not necessarily limited to this.

[0083] For example, Japanese Patent Application Publication No. 2020-68360 discloses a technique in which, when bonding a metal plate to an electronic component using a bonding material, the metal plate is etched to deepen the grain boundaries, thereby increasing the surface area and achieving an anchoring effect to improve the bonding strength. However, in this technique, the opening width of the etched recess is described as approximately 3 μm to 10 μm, the depth of the recess is 2 μm to 20 μm, and the grain size of the metal plate is 100 μm to 600 μm.

[0084] Considering that the size of sintered particles is generally submicron in diameter, in this technology, pores with depths tens of times greater than the particle size are arranged at large intervals of 100μm to 600μm, which is inconsistent with the present invention’s objective of obtaining an overall uniform interface through diffusion promotion.

[0085] Furthermore, according to the present invention, the bonding quality of the interface can be improved, thereby correspondingly reducing the pressure applied during sintering. Therefore, the technology of the present invention is particularly effective for sintering bonding that typically requires pressure in the range of 10 MPa, when used in conjunction with processes using micro-pressures such as 0.01 MPa to 1.00 MPa, or pressureless processes that do not require pressure.

[0086] In addition, as sintering metals, the aforementioned silver or copper powders are generally used.

[0087] Here, because copper diffuses at a slower rate than silver, it is difficult for the sintering of the bonding layer to occur due to self-heating during the operation of the manufactured semiconductor device. Therefore, even if the sintering density of the bonding layer is low at the moment the first and second components are joined, the reliability of the manufactured semiconductor device can be maintained. For this reason, compared to using silver as the sintering metal, using copper allows for a reduction in the stress during sintering compared to previous methods, from the viewpoint that the reliability of the manufactured semiconductor module can be ensured even with a low sintering density of the bonding layer.

[0088] Therefore, the technology of the present invention is particularly effective when copper is used as the sintering metal and in conjunction with a process with low pressure.

[0089] Example

[0090] Hereinafter, specific embodiments of the semiconductor device of the present invention will be described with reference to the accompanying drawings.

[0091] In the following embodiments, the semiconductor device of the present invention includes a semiconductor chip and a wiring layer, constituting a semiconductor module in which the semiconductor chip and the wiring layer are bonded together by sintering.

[0092] Furthermore, in each figure and embodiment, the same or similar constituent elements are labeled with the same reference numerals, and repeated descriptions are omitted.

[0093] (Example 1)

[0094] Reference Figures 1-7 The semiconductor module of Example 1 will be described.

[0095] Figure 1 This is a schematic cross-sectional view showing the structure of the semiconductor module in Embodiment 1.

[0096] like Figure 1 As shown, the semiconductor module 20 of this embodiment includes a semiconductor chip 1, a sintered metal layer 2, a substrate 3, a base plate 4, a sintered metal layer under the substrate 5, a wire 6, a terminal 7, a housing 8, a sealing resin 9, and a cover 10.

[0097] The substrate 3 has an insulating substrate 3c, a wiring layer 3a disposed on the surface side of the insulating substrate 3c, and a back metal layer 3b disposed on the back side of the insulating substrate 3c. The wiring layer 3a is composed of multiple wiring patterns. The wiring layer 3a may use a conductive metal such as copper. The back metal layer 3b may use copper, for example.

[0098] The semiconductor chip 1 is bonded to the wiring layer 3a via a sintered metal layer 2. The semiconductor chip 1 can use, for example, switching elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), or diodes. The sintered metal layer 2 can be, for example, a sintered copper layer or a sintered silver layer.

[0099] exist Figure 1 In the process, two semiconductor chips 1 are sintered together via a sintered metal layer 2 and a wiring layer 3a, respectively.

[0100] The base plate 4 functions as a heat dissipation component. The base plate 4 is bonded to the back metal layer 3b of the substrate 3 via an under-substrate sintered metal layer 5 beneath the substrate 3. A housing 8 is bonded to the base plate 4, for example, via an adhesive not shown.

[0101] The conductor 6 is a conductive conductor that electrically connects the semiconductor chips 1 to each other, the wiring layers 3a to each other, and the semiconductor chips 1 to the wiring layers 3a.

[0102] Terminal 7 is connected to wiring layer 3a at one end, and a portion of the other end is led out to the outside of housing 8 to function as an external connection terminal.

[0103] For example, silicone gel, epoxy resin, etc. can be used as the sealing resin 9.

[0104] A cover 10 is disposed on the sealing resin 9, and the cover 10 is bonded to the housing 8 by an adhesive (not shown).

[0105] Figure 2 This is a cross-sectional view illustrating an example of the structure of the bonding interface of the semiconductor module 20 in Embodiment 1. In Embodiment 1, the wiring layer 3a is provided, particularly on the surface of the semiconductor chip 1, which forms the bonding interface of the semiconductor module 20. Figure 2 The fine bumps and depressions shown are 11 and 12.

[0106] exist Figure 2 In the semiconductor chip 1, there are: a first layer 1A, which includes a semiconductor element made of silicon or SiC and other electrode films; and a second layer 1B, which exposes a bonding material such as Ni. Fine irregularities 11 are formed on the underside of the second layer 1B. In addition, fine irregularities 12 are formed on the upper side of the wiring layer 3a, which exposes the bonding material such as Cu.

[0107] In addition, Figure 2 In the semiconductor chip 1, fine irregularities 11 and 12 are formed on both the second layer 1B and the wiring layer 3a, but it can also be configured such that irregularities are formed only on one of the second layer 1B and the wiring layer 3a.

[0108] On the outermost surface of the second layer 1B of the semiconductor chip 1, in addition to Ni as mentioned above, Cu, Au, Ag, Pd, etc. can also be used as the bonding material.

[0109] In addition, Ag powder and Cu powder can be used as sintering metals for sintering bonding.

[0110] Regarding the combination of materials for the sintered metal and the bonding material on the outermost surface, for Ag powder, Au and Ag are mostly chosen for the outermost surface, and for Cu powder, Ni and Cu are mostly chosen for the outermost surface, but it is not limited to these combinations.

[0111] In addition, for example, in a semiconductor chip 1 such as a power semiconductor element, a wiring layer 3a composed of metal wiring is sometimes formed by plating or the like, but in this case, at least at the bonding interface located on the outermost surface of the layer structure, unevenness is provided.

[0112] The semiconductor module 20 of Example 1 can be manufactured, for example, as described below.

[0113] First, fine irregularities are formed on the outermost surface of at least one of the semiconductor chip 1 or the wiring layer 3a. The fine irregularities can be formed by etching, laser processing, ion milling, etc.

[0114] Next, a paste supply process is carried out, in which a paste for sintering material that becomes sintered metal layer 2 is supplied to wiring layer 3a using a printer and distributor.

[0115] Then, a pre-drying process is performed to remove the solvent components contained in the paste by applying heat to the paste. However, this pre-drying process may be omitted depending on the situation, or the solvent components may be removed by heating during the sintering process.

[0116] Next, a chip setting process is performed to mount the semiconductor chip 1 on the sintering material.

[0117] Finally, a sintering process is performed to bond the materials by applying heat and pressure. Alternatively, depending on the bonding materials used, a sintering process may be performed without applying pressure.

[0118] Here, the diffusion of atoms during sintering is explained.

[0119] Sintering can be understood as the following phenomenon: through diffusion, the atoms constituting the sintered metal exchange with the atoms constituting the bonded material, thus gradually becoming one.

[0120] At this point, there are three main diffusion modes of atoms.

[0121] One type is surface diffusion. This type of diffusion moves along the surface with the fewest obstacles, and therefore has the fastest speed.

[0122] Next, there is grain boundary diffusion, which propagates along the grain boundaries. Although this grain boundary diffusion is not as fast as surface diffusion, it is the second fastest diffusion because other atoms diffuse within the sparse grain boundaries.

[0123] Finally, there is volume diffusion. This is the diffusion of atoms moving through the interior of dense particles, and therefore it is the slowest.

[0124] Thus, sintering becomes a phenomenon that occurs through three diffusion modes.

[0125] Figure 3This is a schematic diagram illustrating diffusion during sintering.

[0126] exist Figure 3 The diagram shows the diffusion state when two sintered metals 21 and 22 are sintered together, and the atoms 23 constituting the sintered metals 21 and 22 diffuse in the three modes described above.

[0127] Arrow 31 indicates surface diffusion, in which atoms diffuse to the outermost surface of the particles in sintered metals 21 and 22.

[0128] Arrow 32 indicates grain boundary diffusion, in which atoms diffuse near the grain boundary 24 of the particles of sintered metals 21 and 22.

[0129] Arrow 33 indicates volume diffusion, in which atoms diffuse inside the particles of sintered metals 21 and 22.

[0130] like Figure 3 As shown in the figure above, atoms 23 of the sintered metals 21 and 22 diffuse through surface diffusion 31, grain boundary diffusion 32, and volume diffusion 33, as... Figure 3 As shown in the figure below, two sintered metals 21 and 22 are joined at grain boundary 23.

[0131] Next, refer to Figure 4 A and Figure 4 Section B describes the bonding mechanism of the sintered metal and the interface to be bonded in a general sintering bonding process, which serves as a comparative comparison with the present invention.

[0132] Figure 4 A and Figure 4 B is a cross-sectional view representing diffusion at the interface during typical sintering.

[0133] exist Figure 4 A and Figure 4 In section B, a variation is shown where the component 14, having grain boundaries 24, is sintered and bonded to the sintered metal 13. Furthermore, the lower surface of the component 14 becomes the interface with the sintered metal 13.

[0134] When the sintering temperature is reached by heating, such as Figure 4 As shown in A, atoms 23 constituting the sintered metal 13 penetrate into the joined interface via diffusion through the contact points between the particles of the sintered metal 13 and the joined interface of the component 14. At this time, surface diffusion 31 is the fastest occurring, and therefore dominates. However, some atoms 23 penetrate deeper into the component 14 via the grain boundaries 24 included in the joined interface. Here, volume diffusion also occurs slightly, but is slower than other modes and therefore not dominant. Thus, as... Figure 4As shown in B, the sintered metal 13 extends thinly at the interface with the component 14, and a portion penetrates into the depth direction of the component 14. Therefore, it is believed that a bonding interface with a certain degree of strength can be obtained.

[0135] In addition, at this time, the diffusion of atoms constituting the bonded interface into the particles of the sintered metal 13 also occurs simultaneously, but it is not shown in the figure for the sake of simplicity.

[0136] In contrast, refer to Figure 5 A and Figure 5 Section B explains the bonding mechanism between the sintered metal and the interface to be bonded in the sintering bonding process of the semiconductor device of the present invention.

[0137] Figure 5 A and Figure 5 B is a cross-sectional view showing diffusion at the interface during sintering bonding in the semiconductor device of the present invention.

[0138] exist Figure 5 A and Figure 5 In B, with Figure 4 A and Figure 4 Similarly, in case B, a variation is shown where the component 14 having grain boundaries 24 is sintered and bonded to the sintered metal 13. Moreover, the lower surface of the component 14 becomes the interface with the sintered metal 13.

[0139] like Figure 5 As shown in Figure A, the grain boundary 24 of the interface to which component 14 is joined is processed to have an unevenness 15 in the depth direction. Furthermore, Figure 5 The dent 15 shown in A is formed along the grain boundary 24 in a manner that is deepest near the grain boundary 24 of the component 14.

[0140] Figure 5 The component 14 in the state shown in A can be fabricated, for example, by selectively processing the vicinity of the grain boundary 24 deep relative to the joined interface of component 14 using etching.

[0141] In the case of such a bonded interface, when heated to the sintering temperature, such as Figure 5 As shown in A, the atoms 23 constituting the sintered metal 13 can penetrate into the depth direction of the component 14 to a certain extent through the surface of the uneven 15 at the fastest surface diffusion 31 speed.

[0142] In addition, such as Figure 5As shown in Figure A, when the unevenness 15 deepens near the grain boundary 24, the unevenness 15 connects with the grain boundary 24. Therefore, the atoms 23 constituting the sintered metal 13 can penetrate into the inner side of the component 14 at the speed of grain boundary diffusion 32. Thus, the sintered metal 13 can penetrate a considerable amount into the depth direction of the component 14. This also means that the contact amount at the interface between the sintered metal 13 and the component 14 increases, and therefore the interdiffusion at the interface between the sintered metal 13 and the component 14 becomes more active, such as... Figure 5 As shown in B, the interface formed by the joint is located near the front end of the concave-convex joint 15. Figure 5 The atoms in the trapezoidal portion (25) enclosed by the dashed line of B eventually become dispersed. Thus, as... Figure 5 As indicated by the arrow in B, a sintered metal layer with a certain thickness is obtained.

[0143] Figure 5 A and Figure 5 The example shown in B illustrates an example with a protrusion 15 formed by deep drilling near the grain boundary 24. However, even if only a fine protrusion is provided instead of near the grain boundary, the effect of penetration along the depth direction through surface diffusion can be obtained. Therefore, although the effect is slightly worse, the reliability can be improved compared to the case without processing.

[0144] The method for creating an uneven surface is not limited to etching; any method that can process the surface into the desired size, such as laser processing or ion milling, is acceptable.

[0145] Assuming the above mechanism, the actual trial results are shown below. This trial produced a structure in which copper was sintered onto a Ni film.

[0146] Here, the surface state of the Ni film after etching was observed using SEM (scanning electron microscope). Figure 6 SEM images of the surface state of the Ni film after etching are shown as observation results.

[0147] like Figure 6 As shown, grooves are formed on the surface in the shape of a contour. This is presumably because, through etching, for example, grain boundaries are selectively processed to a deeper depth.

[0148] In addition, for typical Ni films and Figure 6 The films shown were sintered and bonded, and the results of comparing the interface structures are presented below. Figure 7 A and Figure 7 B. Figure 7 A is a SEM image of the cross section during the sintering bonding of a typical Ni film. Figure 7 B is an SEM image of the cross-section during the sintering and bonding of Ni films with uneven surfaces.

[0149] Compare Figure 7 A and Figure 7 As shown in B, for the bonding state with an uneven interface, the contact points between the sintered copper and Ni become denser. Therefore, it can be concluded that an interface structure that is not easily peeled off and has excellent heat dissipation is obtained.

[0150] In this embodiment, the semiconductor module 20 has fine irregularities at the bonding interface in one or both of the semiconductor chip 1 and the wiring layer 3a, which are sintered together by the sintered metal layer 2. These fine irregularities promote atomic diffusion during sintering, making the interdiffusion between the sintered metal and the bonding interface more active and resulting in denser bonding contacts. This leads to a bonding layer that is difficult to peel off and easily conducts heat.

[0151] (Example 2)

[0152] Next, the semiconductor module of Example 2 will be described.

[0153] The semiconductor module of Example 2 also has the same characteristics as the semiconductor module 20 of Example 1. Figure 1 The structure shown is the same as the structure shown.

[0154] In the semiconductor module of Example 2, as described in detail later, a fine undulation extension formed at the bonding interface extends to a region further outward than the sintered bonding region.

[0155] Before describing the structure of the semiconductor module in Example 2, the wettability of the solvent used to coat the sintered metal at the bonding interface of the sintered bonding will be explained.

[0156] Generally, rough surfaces with uneven surfaces have properties that enhance wettability than flat surfaces. This can be represented by the Wenzel formula shown in equation (1) below.

[0157] cоsθw=rcоsθ(1)

[0158] (θw: contact angle on the rough surface, θ: contact angle on the flat surface, r: area ratio of the rough surface to the flat surface)

[0159] Figure 8 It is a cross-sectional view representing the phenomenon described in the Wenzel formula. Figure 8 The two figures in the upper section illustrate the phenomenon in the case of hydrophilic surfaces. Figure 8 The two figures in the lower section illustrate the phenomenon in the case of hydrophobic surfaces. Figure 8 In the upper and lower sections, the left diagram shows the case where the surface is flat, and the right diagram shows the case where the surface is rough, consisting of bumps and depressions. Additionally, the illustration of the bumps and depressions of the rough surface is omitted in the right diagram.

[0160] like Figure 8 As shown in the upper paragraph, in a hydrophilic surface with good wettability (θ < 90°), the contact angle of the rough surface on the right is smaller than that of the flat surface on the left (θw < θ), so the rough surface is easier to wet.

[0161] On the other hand, such as Figure 8 As shown in the lower section, in a hydrophobic surface with poor wettability (θ > 90°), the contact angle of the rough surface on the right is larger than that of the flat surface on the left (because θw > θ), and the rough surface is difficult to wet.

[0162] Next, a comparison will be made between an existing semiconductor module with a flat sintered bonding interface and a semiconductor module of Example 2 with a rough, uneven sintered bonding interface.

[0163] Figure 9 This is a cross-sectional view of the sintered joint of an existing semiconductor module where the joined interface is a flat surface.

[0164] Figure 10 This is a cross-sectional view of the sintered joint of a semiconductor module in Embodiment 2, where the interface to be joined by sintering is a rough surface with unevenness.

[0165] exist Figure 9 as well as Figure 10 In the middle, the first component (e.g., Figure 1 The wiring layer 3a) 43 shown and the second component (e.g., including Figure 1 The changes in the state of the semiconductor chip 1) during sintering with sintered metal powder 41 are shown sequentially from the left to the right of the three figures.

[0166] exist Figure 9 as well as Figure 10 In the middle, the figure on the left shows the state in which a paste containing sintered metal powder 41 dispersed in solvent 42 is supplied to the first component 43, and the second component 44 is placed on the paste.

[0167] exist Figure 9 In the existing semiconductor module shown, during the sintering bonding process, the solvent 42 is vaporized by heating, as shown in the central figure, and discharged through the gaps in the sintered metal powder 41.

[0168] However, the solvent 42 can only escape from the gaps between the sintered metal powder 41, and these gaps are narrow. Therefore, if rapid heating is used to shorten the sintering bonding process, the residual solvent 42 that has not been completely removed will vaporize, increasing the internal pressure and causing the sintered metal powder 41 to splash and become voids. If voids are formed at the sintered joint, the strength of the sintered joint will weaken, and the reliability of the joint will decrease.

[0169] exist Figure 10 In the semiconductor module of Embodiment 2 shown, unevenness 45 and 46 are formed at the bonding interfaces of the first component 43 and the second component 44, respectively, thereby enhancing the wetting force of the solvent 42 and actively draining the solvent 42 along the surfaces of the unevenness 45 and 46, thus preventing the residue of the solvent 42.

[0170] Furthermore, in Example 2, in particular, as Figure 10 As shown, the areas with the irregularities 45 and 46 are extended outwards than the areas sintered together by the sintering paste supplied for bonding. Therefore, compared to the case where the areas with the irregularities 45 and 46 are the same size as the areas supplied with the sintering paste, the solvent 42 is more easily discharged.

[0171] In the configuration of Example 2, it is further preferred that the solvent 42 to be dried and the surface provided with unevenness 45, 46 are configured as... Figure 8 The description describes a combination of easily wettable raw materials. As a result, the solvent, in a liquid state, actively drains away from the bonding surface, thus achieving drying in a shorter time compared to a flat surface. This structure not only promotes diffusion at the bonding interface but also prevents incomplete bonding and reduced bonding strength caused by solvent residue, further improving product reliability.

[0172] The above illustrates a technique that improves the quality of the joint interface by creating uneven surfaces at the joint to promote diffusion in the depth direction.

[0173] As a derivative of the same approach, it is also possible to consider not setting fine bumps and depressions on the surface, but instead using grain refinement technology to form a state with many grain boundaries at the interface.

[0174] The following example of using this method will be described as Example 3.

[0175] (Example 3)

[0176] Reference Figure 11 A and Figure 11 B will describe the semiconductor module of Example 3.

[0177] The semiconductor module of Example 3 also has the same characteristics as the semiconductor module 20 of Example 1. Figure 1 The structure shown is the same as the structure shown.

[0178] Figure 11 A and Figure 11 B is a cross-sectional view showing the manufacturing method of the semiconductor module in Example 3.

[0179] In the semiconductor module of Example 3, such as Figure 11A and Figure 11 As shown in B, the spacing of the grain boundaries 24 of the component 14 bonded to the sintered metal 13 is shortened, thereby increasing the number of grain boundaries 24. Thus, to increase the number of grain boundaries 24, a technique for refining the grains is used. In this embodiment, any method can be used as a technique for refining the grains.

[0180] In this embodiment, by increasing the number of grain boundaries 24 of component 14, such as Figure 11 As shown in B, in the depth direction of component 14, there are more paths for sintered metal 13 to penetrate into grain boundary diffusion 32, thus improving the quality of the bonding interface.

[0181] More specifically, if the size of the miniaturized grains is less than 10 μm, and the bonding interface is composed of grains less than 10 μm, the effect of improving the quality of the bonding interface is enhanced.

[0182] Furthermore, it is also possible to combine a structure that refines the grains at the bonding interface, as in the semiconductor module of Example 3, with a structure that forms fine irregularities at the bonding interface, as in the semiconductor modules of Examples 1 to 2.

[0183] This invention is not limited to the embodiments and structures described in the examples, and various modifications can be made within the scope of the technical concept of this invention. Furthermore, some or all of the structures described in the various embodiments can be combined and applied.

[0184] Symbol Explanation

[0185] 1: Semiconductor chip; 1A: First layer; 1B: Second layer; 2: Sintered metal layer; 3: Substrate; 3a: Wiring layer; 3b: Back metal layer; 3c: Insulating substrate; 4: Base plate; 5: Under-substrate sintered metal layer; 6: Wire; 7: Terminal; 8: Housing; 9: Sealing resin; 10: Cover; 11, 12, 15, 45, 46: Uneven surface; 13, 21, 22: Sintered metal; 14: Component; 20: Semiconductor module; 23: Atom; 24: Grain boundary; 31: Surface diffusion; 32: Grain boundary diffusion; 33: Volume diffusion; 41: Sintered metal powder; 42: Solvent; 43: First component; 44: Second component.

Claims

1. A semiconductor device, characterized in that, have: The first component, which is made of metal; and The second component includes a semiconductor chip. The first component and the second component are joined together by sintering. The interface of at least one of the first component and the second component is formed with irregularities, the interval between the irregularities being less than 10 μm.

2. The semiconductor device according to claim 1, characterized in that, The spacing between the uneven surfaces is less than 0.1 μm.

3. The semiconductor device according to claim 1, characterized in that, The depth of the unevenness is 0.1 μm or more.

4. The semiconductor device according to claim 1, characterized in that, The diameter of the opening of the concave and convex shapes is less than 10 μm.

5. The semiconductor device according to claim 1, characterized in that, The diameter of the opening of the concave and convex surfaces is less than 0.01 μm.

6. The semiconductor device according to claim 1, characterized in that, The irregularities are formed along the grain boundaries of the component.

7. The semiconductor device according to claim 1, characterized in that, The region with the aforementioned unevenness extends outwards from the sintered bonded region.

8. The semiconductor device according to claim 1, characterized in that, The sintered metal used to sinter the first component and the second component is copper.

9. The semiconductor device according to claim 1, characterized in that, The bonded interface, which has the aforementioned unevenness, is composed of grains with a particle size of less than 10 μm.

10. A semiconductor device, characterized in that, have: The first component, which is made of metal; and The second component includes a semiconductor chip. The first component and the second component are joined together by sintering. The interface of at least one of the first component and the second component is composed of grains with a particle size of less than 10 μm.

11. A method for manufacturing a semiconductor device, comprising a method for manufacturing a semiconductor device by bonding a first component made of metal and a second component including a semiconductor chip by sintering, characterized in that... At least one of the first component and the second component has an uneven surface with a spacing of less than 10 μm formed at the interface where they are joined. Then, sintering metal is supplied to the interface to be joined, where the irregularities are formed, and sintering is performed.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, During the sintering process, the bonding is performed with a pressure of 0.01 MPa to 1.00 MPa or without pressure.

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