A brainwave signal acquisition and wireless display system

Abstract

This invention discloses an electroencephalogram (EEG) signal acquisition and wireless display system, comprising: a dry electrode array for acquiring weak EEG signals from the scalp surface; a dry electrode active buffer unit for providing high input impedance isolation and low output impedance driving for the weak EEG signals; a reference electrode and a right leg drive / common-mode feedback unit for providing the reference electrode signal to an eight-channel analog signal conditioning unit as a common differential reference; an eight-channel analog signal conditioning unit for processing the buffered signal output from the dry electrode active buffer unit; a reference voltage and a multi-channel ADC sampling unit for sampling / converting the conditioned eight-channel analog EEG signals into digital signals; a motion sensor unit for acquiring acceleration and angular velocity data; a main control and wireless communication unit for reading digital signals and motion data; and a host computer real-time visualization unit for receiving EEG data packets and motion data.

Description

Technical Field

[0001] This invention belongs to the fields of bioelectrical signal acquisition, non-invasive brain-computer interface (BCI), electroencephalography (EEG) acquisition hardware, analog front-end signal conditioning, embedded wireless communication and real-time visualization of host computer, and particularly relates to an EEG signal acquisition and wireless display system. Background Technology

[0002] Brain-computer interface (BCI) systems typically acquire, amplify, filter, digitize, and process brain signals to enable information exchange between the human brain and external devices. Non-invasive BCIs, which do not require implanted electrodes, offer advantages such as high safety, wide applicability, and convenient experimental deployment, and are widely used in neurorehabilitation, human-computer interaction, attention and fatigue monitoring, teaching and research, and wearable physiological monitoring.

[0003] Existing non-invasive EEG acquisition systems have the following main shortcomings: 1. Wet electrode systems rely on conductive paste or electrolytes, requiring a long preparation time before wearing. During long-term monitoring, they are prone to problems such as drying out, skin discomfort, and complicated cleaning and maintenance, making them unsuitable for portable, long-term, and rapidly deployable brain-computer interface applications.

[0004] 2. While dry electrodes offer rapid deployment and good comfort, the contact impedance between them and the skin is high and varies with contact status, frequency, and scalp movement. Several electrode signals pass directly through the leads to the amplifier stage, and weak µV-level EEG signals are easily overwhelmed by contact impedance fluctuations, lead movement noise, power frequency interference, and environmental electromagnetic interference.

[0005] 3. Common low-cost EEG acquisition modules often use single-ended input or simple amplification structures, lacking high input impedance buffers near the electrode ends. The design of reference electrodes, ground electrodes, and common-mode feedback is inadequate, resulting in limited common-mode interference suppression capabilities and a tendency to produce baseline drift and motion artifacts.

[0006] 4. Multi-channel acquisition systems have high requirements for synchronous sampling, data caching, and real-time transmission. Traditional wired acquisition methods involve many cables, affecting wearability and movement; low-cost wireless modules, if they do not decouple sampling and transmission tasks, are prone to transmission delays, packet loss, interface lag, or misalignment of multi-channel data.

[0007] 5. Existing experimental EEG devices often have closed hardware and insufficient interface expansion, making it difficult to meet the needs of dry electrode adaptation, simulation front-end debugging, wireless communication, motion artifact reference, real-time visualization on the host computer, and miniaturization of wearable devices.

[0008] Therefore, it is necessary to provide a non-invasive brain-computer interface system designed around the high impedance characteristics of dry electrodes and multi-channel real-time transmission scenarios. Through the collaborative structure of active electrode buffering, differential common-mode suppression, analog filtering, independent ADC sampling, motion reference, wireless transmission, and upper computer visualization, the system can improve signal acquisition stability, system integration, and application expansion capabilities. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention proposes an EEG signal acquisition and wireless display system. This system can overcome the shortcomings of existing dry electrode EEG acquisition systems in terms of contact impedance fluctuations, common-mode noise, signal chain integration, wireless real-time transmission, and visual debugging.

[0010] To achieve the above objectives, the present invention provides a brainwave signal acquisition and wireless display system, comprising: Dry electrode array, dry electrode active buffer unit, reference electrode and right leg drive / common mode feedback unit, eight-channel analog signal conditioning unit, reference voltage and multi-channel ADC sampling unit, motion sensor unit, main control and wireless communication unit and host computer real-time visualization unit; The dry electrode array is used to collect weak electroencephalogram (EEG) signals from the scalp surface; The dry electrode active buffer unit is used to isolate weak EEG signals with high input impedance and drive them with low output impedance. The reference electrode and the right leg drive / common mode feedback unit are used to provide the reference electrode signal to the eight-channel analog signal conditioning unit as a common differential reference, and extract the common mode component from each channel common mode node, and feed it back to the right leg / reference ground electrode after inversion, filtering, buffering and current limiting protection. The eight-channel analog signal conditioning unit is used to perform differential amplification, high-pass filtering, low-pass filtering and gain amplification on the buffered signal output by the dry electrode active buffer unit. The reference voltage and multi-channel ADC sampling unit are used to sample / convert the conditioned eight-channel analog EEG signals into digital signals according to a preset channel sequence. The motion sensor unit is used to collect acceleration and angular velocity data related to head movement, posture changes, and electrode disturbances; The main control and wireless communication unit is used to read digital signals through the SPI interface, synchronously receive motion data from the motion sensor unit, and cache and frame the EEG data and motion data before sending them to the host computer through the wireless network. The host computer real-time visualization unit is used to receive EEG data packets and motion data through a wireless network, parse, verify and buffer the data packets, and display eight-channel EEG waveforms and motion status in real time.

[0011] Optionally, the dry electrode array includes at least eight Ag / AgCl dry electrodes, one earlobe reference electrode, and one right leg / reference ground electrode. The eight Ag / AgCl dry electrodes correspond to eight EEG sampling channels, the earlobe reference electrode is connected to the inverting input of the differential amplifier of each channel or the common reference input, and the right leg / reference ground electrode is connected to the output of the right leg drive / common mode feedback unit.

[0012] Optionally, the dry electrode active buffer unit includes eight identical voltage follower modules, each voltage follower module including an FPC connector, an input current-limiting resistor, a bidirectional electrostatic discharge protection device, an RC low-pass filter network, a power supply decoupling capacitor, and a rail-to-rail low-power operational amplifier.

[0013] Optionally, the input current-limiting resistor is connected in series in the dry electrode signal input path, the bidirectional electrostatic protection device is composed of two anti-parallel diodes and connected between the operational amplifier input terminal and the power supply ground, the RC low-pass filter network is composed of a capacitor and a resistor and connected to the non-inverting input terminal of the operational amplifier, the operational amplifier adopts unity-gain negative feedback connection to form a voltage follower, and the output terminal of the voltage follower is sent to the eight-channel analog signal conditioning unit after passing through a small-value series resistor.

[0014] Optionally, the eight-channel analog signal conditioning unit includes eight identical or similar channel circuits, each channel including: an instrumentation amplifier, a pre-amplifier RC current limiting / filtering structure, a first-order high-pass filter, a second-order Sallen-Key low-pass filter, an inverting gain amplifier, and a bias reference input node.

[0015] Optionally, the non-inverting input of the instrumentation amplifier is connected to the buffered output signal of the corresponding sampling electrode, the inverting input of the instrumentation amplifier is connected to the earlobe reference electrode signal, the output of the instrumentation amplifier is connected to the first-order high-pass filter, the output of the first-order high-pass filter is connected to the second-order Sallen-Key low-pass filter, the output of the second-order Sallen-Key low-pass filter is connected to the inverting gain amplifier, and the output of the inverting gain amplifier is connected to the reference voltage and the multi-channel ADC sampling unit.

[0016] Optionally, the reference electrode and right leg drive / common mode feedback unit include: a common mode extraction network and an operational amplifier buffer circuit; The common-mode extraction network extracts common-mode components from the common-mode nodes of each channel of the high-resistance resistor network. The operational amplifier buffer circuit inverts, filters, and buffers the extracted common-mode components. The output of the operational amplifier buffer circuit is connected to the right leg / reference ground electrode via a current limiting or protection structure.

[0017] Optionally, the system further includes: a power management unit and a PCB carrier structure; The power management unit is used to convert the external input power into multiple stable voltages, and provide domain-isolated power supply to the dry electrode active buffer unit, the eight-channel analog signal conditioning unit, the reference voltage and multi-channel ADC sampling unit, the motion sensor unit and the main control and wireless communication unit, respectively, so as to reduce the coupling interference of power ripple and digital switching noise to the analog front end. The PCB support structure is used to support various functional units. Through the modular layout of separating the main control board and the eight-channel signal conditioning board, the analog sensitive circuits and digital high-speed circuits are physically isolated and the spatial layout is optimized, the critical signal paths are shortened, and the signal integrity and electromagnetic compatibility between the units are ensured.

[0018] Compared with the prior art, the present invention has the following advantages and technical effects: 1. Active buffering of the electrode ends enables the dry electrode signal to obtain high input impedance isolation before entering the long trace and differential amplification of the subsequent stage, reducing the attenuation and distortion of µV-level EEG signals caused by high contact impedance, contact impedance variation with frequency and wire movement.

[0019] 2. The eight-channel differential amplification, earlobe reference electrode, and right leg drive / common-mode feedback work together to improve the ability to suppress power frequency interference and human body common-mode voltage, and reduce baseline drift.

[0020] 3. A first-order high-pass filter, a second-order low-pass filter, and a subsequent gain amplifier form an analog front-end suitable for the EEG frequency band, which can suppress DC bias, low-frequency motion drift, high-frequency electromyography interference, and the risk of ADC input overrange.

[0021] 4. The AD7689 multi-channel ADC is connected to the ESP32-S3 via SPI, and with the help of FreeRTOS task decoupling, it can achieve real-time coordination of sampling, buffering, packetization and wireless transmission.

[0022] 5. Lightweight UDP transmission and a ring buffer display structure on the host computer reduce communication overhead, enabling real-time visualization of eight-channel data, which facilitates experimental debugging, EEG observation, and algorithm verification.

[0023] 6. The main control board and the signal conditioning board are separated, which is beneficial for the low-noise layout of the analog front end, while retaining the expansion capabilities of display, TF card, buttons, peripherals and wireless communication.

[0024] 7. Domain-specific power supply, negative voltage charge pump, and local decoupling structure reduce the impact of power supply ripple and wireless digital noise on the analog front end, improving the stability of portable systems. Attached Figure Description

[0025] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural diagram of an electroencephalogram (EEG) signal acquisition and wireless display system according to an embodiment of the present invention; Figure 2 This is a power management and power supply framework diagram according to an embodiment of the present invention; Figure 3 This is a single-channel analog front-end signal chain diagram according to an embodiment of the present invention; Figure 4 This is a block diagram of the dry electrode active buffer and input protection according to an embodiment of the present invention; Figure 5 This is a link diagram of the reference voltage, earlobe reference, and RL reference ground in an embodiment of the present invention. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0028] This embodiment proposes a brainwave signal acquisition and wireless display system, specifically including: Dry electrode array, dry electrode active buffer unit, reference electrode and right leg drive / common mode feedback unit, eight-channel analog signal conditioning unit, reference voltage and multi-channel ADC sampling unit, motion sensor unit, main control and wireless communication unit and host computer real-time visualization unit; The dry electrode array is used to non-invasively acquire weak electroencephalogram (EEG) signals from the scalp surface. The dry electrode active buffer unit is used to isolate weak EEG signals with high input impedance and drive them with low output impedance. The reference electrode and the right leg drive / common mode feedback unit are used to provide the reference electrode signal to the eight-channel analog signal conditioning unit as a common differential reference, and extract the common mode component from each channel common mode node, and feed it back to the right leg / reference ground electrode after inversion, filtering, buffering and current limiting protection. The eight-channel analog signal conditioning unit is used to perform differential amplification, high-pass filtering, low-pass filtering and gain amplification on the buffered signal output by the dry electrode active buffer unit. The reference voltage and multi-channel ADC sampling unit are used to sample / convert the conditioned eight-channel analog EEG signals into digital signals according to a preset channel sequence. The motion sensor unit is used to collect acceleration and angular velocity data related to head movement, posture changes, and electrode disturbances; The main control and wireless communication unit is used to read digital signals through the SPI interface, synchronously receive motion data from the motion sensor unit, and cache and frame the EEG data and motion data before sending them to the host computer through the wireless network. The host computer real-time visualization unit is used to receive EEG data packets and motion data through a wireless network, parse, verify and buffer the data packets, and display eight-channel EEG waveforms and motion status in real time.

[0029] Specifically, such as Figure 1 As shown, the system includes multiple sampling electrodes, reference electrodes, and ground electrodes placed on the surface of the human head. The sampling electrodes and reference electrodes are connected to a front-end voltage follower, the output of which is connected to a differential amplifier circuit. The differential amplifier circuit amplifies the weak EEG differential signal between the sampling electrodes and the reference electrodes and suppresses common-mode interference. The amplified signal is then processed by a gain amplifier circuit and a bandpass filter before being input to an analog-to-digital converter (ADC). The ADC converts the analog EEG signal into a digital signal and transmits it to the ESP32 main control unit. The ESP32 main control unit buffers, frames, and performs preliminary processing of the multi-channel EEG data before transmitting it to a host computer via UDP wireless communication. The host computer then performs real-time waveform display, data storage, and subsequent algorithm processing.

[0030] The system consists of eight Ag / AgCl dry electrodes, an earlobe reference electrode, a ground electrode, a dry electrode voltage follower array, an eight-channel analog front-end, an AD7689 analog-to-digital converter, an ESP32S3 main control unit, a Wi-Fi wireless transmission link, and a PyQt host computer. After the eight dry electrodes acquire scalp EEG signals, they are first buffered and protected by a TLV271 voltage follower array before entering the analog front-end for differential amplification, filtering, and post-gain processing. The processed analog signals are converted to digital signals by the AD7689. The ESP32S3 reads the sampled data via the SPI interface and sends it to the host computer via the UDP protocol for real-time waveform display and data storage.

[0031] Furthermore, the dry electrode array includes at least eight Ag / AgCl dry electrodes, one earlobe reference electrode, and one right leg / reference ground electrode. The eight Ag / AgCl dry electrodes correspond to eight EEG sampling channels, the earlobe reference electrode is connected to the inverting input of the differential amplifier of each channel or the common reference input, and the right leg / reference ground electrode is connected to the output of the right leg drive / common mode feedback unit.

[0032] Specifically, such as Figure 4 As shown, this unit connects to the dry electrode, power supply, ground, and buffer output via an FPC interface. After the dry electrode signal enters the circuit, it is first current-limited by R1, and then protected against electrostatic discharge and overvoltage by bidirectional ESD devices D1 and D2. C2, C3, and R3 form an input-side low-pass and bleeder network to suppress high-frequency noise and input drift. The TLV271IDBVR operates in unity-gain voltage follower mode, ensuring high-impedance isolation and low-impedance drive of the dry electrode signal before it enters the subsequent differential amplifier circuit. C1 is an AVCC power supply decoupling capacitor, and R2 is used for output isolation, improving the stability of the buffer driving the subsequent circuit.

[0033] Furthermore, the dry electrode active buffer unit includes eight identical voltage follower modules, each voltage follower module including an FPC connector, an input current-limiting resistor, a bidirectional electrostatic discharge protection device, an RC low-pass filter network, a power supply decoupling capacitor, and a rail-to-rail low-power operational amplifier.

[0034] Furthermore, the input current-limiting resistor is connected in series in the dry electrode signal input path, the bidirectional electrostatic protection device is composed of two anti-parallel diodes and connected between the operational amplifier input terminal and the power supply ground, the RC low-pass filter network is composed of a capacitor and a resistor and connected to the non-inverting input terminal of the operational amplifier, the operational amplifier adopts unity-gain negative feedback connection to form a voltage follower, and the output terminal of the voltage follower is sent to the eight-channel analog signal conditioning unit after passing through a small-value series resistor.

[0035] Furthermore, the eight-channel analog signal conditioning unit includes eight identical or similar channel circuits, each channel including: an instrumentation amplifier, a pre-amplifier RC current limiting / filtering structure, a first-order high-pass filter, a second-order Sallen-Key low-pass filter, an inverting gain amplifier, and a bias reference input node.

[0036] Furthermore, the non-inverting input of the instrumentation amplifier is connected to the buffered output signal of the corresponding sampling electrode, the inverting input of the instrumentation amplifier is connected to the earlobe reference electrode signal, the output of the instrumentation amplifier is connected to the first-order high-pass filter, the output of the first-order high-pass filter is connected to the second-order Sallen-Key low-pass filter, the output of the second-order Sallen-Key low-pass filter is connected to the inverting gain amplifier, and the output of the inverting gain amplifier is connected to the reference voltage and the multi-channel ADC sampling unit.

[0037] Specifically, such as Figure 3 As shown, a single acquisition channel includes dry electrode input, input protection, voltage follower, instrumentation differential amplifier, high-pass filter, second-order Sallen-Key low-pass filter, post-stage inverting amplifier, bias superposition, and ADC input. The weak EEG signal acquired by the Ag / AgCl dry electrode is current-limited by R1 and clamped by bidirectional ESD before entering the TLV271 voltage follower. The voltage follower is used to increase the input impedance and decrease the output impedance. The buffered sampled signal and the earlobe reference signal are input together to the INA826 instrumentation amplifier to achieve differential amplification and common-mode noise suppression. The post-stage filtering and gain circuit is used to remove DC drift and high-frequency interference and adjust the signal to the effective sampling range of the AD7689.

[0038] like Figure 5 As shown, ADC_REF provides a 2.5V reference voltage, and a midpoint reference voltage of approximately 1.25V is generated by voltage division using two 470kΩ resistors R5 and R9. This midpoint voltage provides DC bias for the subsequent amplifier circuits of each channel and the ADC input signal, enabling bipolar EEG signals to be adapted to the sampling range of a single-supply ADC. The left earlobe reference electrode serves as the common inverting input node IN_N, connected to the inverting terminals of the eight INA826 differential amplifier channels. The common-mode or feedback nodes of each channel are buffered by OP2177 to form RL_OUT, which is connected to the RL reference ground electrode to provide a human body reference path or common-mode feedback path, thereby improving the system's common-mode noise suppression capability.

[0039] The OUT0 to OUT7 signals from the eight-channel analog front-end are connected to the analog inputs of the AD7689BCPZRL7 eight-channel SARADC. The AD7689 connects to the ESP32S3 master control unit via an SPI interface, with SPI signals including ADC_MISO, ADC_SCLK, ADC_MOSI, and ADC_CS / CNV. The ESP32S3 runs the SPI driver and FreeRTOS real-time tasks to read, buffer, queue, manage queues, and frame data from the ADC samples. The framed data is then sent to the host computer via a Wi-Fi module using UDPSocket. The system also includes a Type-C and CH340K debugging link for firmware download and serial log output, and local data recording can be achieved via a TF card or SPI memory.

[0040] Furthermore, the reference electrode and right leg drive / common mode feedback unit include: a common mode extraction network and an operational amplifier buffer circuit; The common-mode extraction network extracts common-mode components from the common-mode nodes of each channel of the high-resistance resistor network. The operational amplifier buffer circuit inverts, filters, and buffers the extracted common-mode components. The output of the operational amplifier buffer circuit is connected to the right leg / reference ground electrode via a current limiting or protection structure.

[0041] Furthermore, the system also includes: a power management unit and a PCB support structure; The power management unit is used to convert the external input power into multiple stable voltages, and provide domain-isolated power supply to the dry electrode active buffer unit, the eight-channel analog signal conditioning unit, the reference voltage and multi-channel ADC sampling unit, the motion sensor unit and the main control and wireless communication unit, respectively, so as to reduce the coupling interference of power ripple and digital switching noise to the analog front end. The PCB support structure is used to support various functional units. Through the modular layout of separating the main control board and the eight-channel signal conditioning board, the analog sensitive circuits and digital high-speed circuits are physically isolated and the spatial layout is optimized, the critical signal paths are shortened, and the signal integrity and electromagnetic compatibility between the units are ensured.

[0042] Specifically, such as Figure 2As shown, the system supports Type-CVBUS input and lithium battery VBAT input. Input power is processed by the SLM6800 charging and power path management circuit before entering the system power bus. The system power supply generates +5V through a TPS54302 DC-DC step-down circuit, and then generates 3.3V through regulators such as the ME6217C33, powering the ESP32S3, ADC digital interface, CH340K, TF card, and other digital peripherals. The analog front-end is powered by an AVCC analog positive power supply and an AVEE analog negative power supply generated by an SGM3204 charge pump to meet the operating requirements of the TLV271, INA826, OPA2177, and AD7689 analog sections. ADC_REF and REF1P25 are used to provide the ADC reference voltage and analog midpoint bias, respectively. This power architecture, through the partitioned design of digital power, analog power, negative voltage power, and reference voltage, reduces the impact of power ripple and digital switching noise on EEG acquisition signals.

[0043] After the system powers on, the ESP32S3 first initializes hardware and software resources such as GPIO, SPI, Wi-Fi, timers, and FreeRTOS queues. Then, it configures the AD7689's channel sequence, sampling parameters, and reference voltage. Once the Wi-Fi connection is established, the controller creates a UDP socket. The sampling timer periodically triggers the ADC acquisition task. The ESP32S3 reads data from the eight channels of the ADC via SPI and preprocesses and frames the sampled data. The data frame includes a frame header, sequence number, timestamp, CH0 to CH7 sample values, and a checksum field. The framed data is written to the FreeRTOS queue or a circular buffer, and then sent to the host computer in a non-blocking manner via the UDP send task. If a Wi-Fi disconnection or transmission anomaly is detected, the system performs reconnection, packet loss counting, and status reporting.

[0044] After the host computer program starts, it loads the PyQt graphical interface, including channel selection, parameter settings, and waveform display windows. Then, it creates a UDP listening thread and binds it to a specified IP address and port. Upon receiving UDP packets, the host computer checks the frame header, data length, and checksum field. If the data frame is valid, it parses the sampled values, timestamps, and frame numbers from CH0 to CH7 and writes them to the display buffer. The system can perform digital filtering, normalization, or artifact marking as needed and draw multi-channel EEG waveforms in real time. When the user chooses to save the data, the host computer writes the parsed sampled data to a CSV or binary file for subsequent signal processing and brain-computer interface algorithm verification.

[0045] The PCB is functionally divided into analog sensitive area, reference and ground plane area, digital and communication area, and power supply area. The electrode / FPC input area is placed close to ESD protection devices, and the TLV271 buffer array is placed close to the electrode input to shorten the signal path and reduce input noise coupling. The INA826 / OPA2177 analog front-end is kept away from the high-speed digital signal and Wi-Fi antenna areas, and the AD7689 ADC is placed close to the analog front-end to reduce the analog signal transmission path. Digital functional modules such as the ESP32S3, Type-C / CH340K, Wi-Fi module, and TF card are concentrated in the digital area. The DC-DC switching power supply area is kept at a distance from the analog front-end, and the LDO, charge pump, and filter network are placed close to the analog load. The analog ground return path is kept continuous, and the digital return path avoids crossing the analog input area, thereby reducing the impact of switching power supply noise, wireless communication interference, and digital crosstalk on the EEG acquisition signal.

[0046] The following is a detailed description of this embodiment: 1. When wearing the device, place the eight Ag / AgCl dry electrodes on the corresponding positions on the scalp. Connect the earlobe reference electrode to the reference input terminal IN_N, and connect the right leg / reference ground electrode to the RL or GND connection terminal. The sampling electrodes are connected to the corresponding voltage follower input terminal via FPC or short wire. Specifically, the dry electrode material is not limited to Ag / AgCl; gold-plated, silver-plated, conductive rubber, conductive fabric, microneedle-type non-invasive dry electrodes, or other electrode materials capable of forming stable contact with the scalp can also be used.

[0047] 2. After the electrode voltage follower is powered on, the µV-level EEG signal acquired by the dry electrodes first passes through a current-limiting resistor and an ESD protection network, then through an RC network to suppress high-frequency interference, and is buffered by a unity-gain voltage follower composed of operational amplifiers such as the TLV271. The buffered signal is output to the eight-channel analog front-end in a low-impedance form. Specifically, the voltage follower is not limited to the TLV271; other operational amplifiers with high input impedance, low input bias current, low noise, low power consumption, and rail-to-rail input / output capabilities can also be used.

[0048] 3. In each channel, the sampling electrode buffer signal is used as the IN_Pi input, and the earlobe reference electrode signal is used as the IN_N input. Both are fed into the INA826 instrumentation amplifier for differential amplification. The primary gain is set by an approximately 6.6kΩ gain resistor, enabling the weak EEG signal to be amplified by approximately 8.48 times, while suppressing power frequency interference and environmental noise shared by both inputs. The instrumentation amplifier is not limited to the INA826; the INA333, AD822x series, low-noise bioelectric instrumentation amplifiers, or integrated bioelectric analog front-ends can also be used.

[0049] 4. The INA826 output signal enters a first-order high-pass filter consisting of a 4.7µF capacitor and a 330kΩ resistor to remove DC bias, electrode polarization voltage, and low-frequency drift below approximately 0.1Hz. The signal then enters a second-order Sallen-Key low-pass filter consisting of low-noise operational amplifiers such as OP2177 / OPA2188 and an RC network to suppress high-frequency noise and EMG interference outside the EEG band.

[0050] 5. The low-pass filtered signal enters the inverting gain amplification stage. The inverting stage can use a 20kΩ input resistor, a 470kΩ feedback resistor, and a 1nF feedback capacitor to achieve approximately 23.5 times gain and high-frequency compensation. A 1.25V bias reference is also introduced in the subsequent stage to adapt the amplified bioelectrical signal to the ADC input range. The ADC is not limited to the AD7689; the ADS1299, ADS1298, ADS131M series, multi-channel parallel ADCs, or higher-precision / higher-sampling-rate SAR / ΔΣ ADCs can also be used. If a dedicated EEG acquisition chip is used, the pre-stage filtering and gain structure can be simplified accordingly.

[0051] 6. Connect the outputs OUT0 to OUT7 of each channel to the IN0 to IN7 input terminals of the AD7689. Set decoupling capacitors of 10µF and 100nF at the reference voltage terminal of the AD7689. Connect the digital signals such as ADC_MISO, ADC_SCLK, ADC_CS, ADC_MOSI or CNV / DIN / SCK / SDO to the SPI interface of the ESP32-S3.

[0052] 7. After booting, the ESP32-S3 initializes SPI, Wi-Fi, timers, GPIO, necessary peripherals, and FreeRTOS tasks. The sampling task triggers AD7689 channel conversion at a preset sampling rate and reads eight-channel ADC data. The buffering task writes multiple sets of sampled data into a memory buffer. The sending task encapsulates the data into data packets containing packet sequence numbers and eight-channel arrays and sends them via UDP. The master controller is not limited to the ESP32-S3; it can also be the ESP32-C series, STM32, nRF52 / nRF53, Raspberry Pi, PicoW, or other microcontrollers or systems-on-a-chip with SPI / wireless communication capabilities. The wireless transmission method is not limited to UDP and Wi-Fi; it can also use TCP, BLE, USB CDC, serial port, LoRa, or other communication methods.

[0053] 8. If the system is equipped with an ICM-42688-P motion sensor, the main controller can synchronously read acceleration and angular velocity data and send them in the same packet as the ADC data or record them as an additional field to support motion artifact recognition, head motion marking and subsequent algorithm compensation.

[0054] 9. The host computer software starts a UDP listening thread to receive data packets from the ESP32-S3 and parses them into JSON or binary format. The parsed eight-channel data is written to an 8×N circular buffer, and the waveform display timer refreshes the display of waveforms from the most recent few seconds at approximately 50ms intervals. The software can also display data packet sequence numbers, reception timestamps, hexadecimal messages, network status, and error messages. The host computer is not limited to PyQt; it can use Qt / C++, LabVIEW, MATLAB, PythonDash, WebSocket web interface, mobile app, or cloud data platform.

[0055] 10. In terms of power supply, the system can be powered by a Type-C 5V input or a lithium battery. The power input, after passing through charging management, reverse connection protection, switching, and filtering, enters a DC-DC step-down circuit to generate +5V. This is then converted to a 3.3V digital power supply and an AVCC analog power supply via an LDO, and an AVEE negative voltage is generated by a charge pump. Decoupling capacitors are placed near the analog operational amplifiers, ADC reference, and electrode buffer modules. Power management is not limited to SLM6800, TPS54302, ME6217, and SGM3204; equivalent charging chips, DC-DC converters, low-noise LDOs, inverting charge pumps, or isolated power modules can be used. Power supply methods can also include single-cell lithium batteries, dual-cell lithium batteries, direct USB power supply, or medical-grade external adapters.

[0056] 11. In the PCB implementation, the eight-channel analog front-end, ADC reference, right leg driver, and dry electrode interface are concentrated in the analog area of ​​the signal conditioning board, while the ESP32-S3, Flash, USB, TF card, display, buttons, and wireless antenna are concentrated in the digital area of ​​the main control board. Power, ground, SPI, and GPIO are transmitted between the two boards via headers to prevent the wireless antenna and DC-DC switching nodes from being close to the weak analog input. The number of system channels is not limited to eight channels and can be expanded to 4, 16, 32, or more channels. The reference electrode can be set to a single reference, average reference, or switchable reference structure. The PCB structure can be a separate main control board and analog front-end board, or an integrated multilayer board. Connector types can include headers, board-to-board connectors, FPC, coaxial cables, or shielded cables.

[0057] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A brainwave signal acquisition and wireless display system, characterized in that, include: Dry electrode array, dry electrode active buffer unit, reference electrode and right leg drive / common mode feedback unit, eight-channel analog signal conditioning unit, reference voltage and multi-channel ADC sampling unit, motion sensor unit, main control and wireless communication unit and host computer real-time visualization unit; The dry electrode array is used to collect weak electroencephalogram (EEG) signals from the scalp surface; The dry electrode active buffer unit is used to isolate weak EEG signals with high input impedance and drive them with low output impedance. The reference electrode and the right leg drive / common mode feedback unit are used to provide the reference electrode signal to the eight-channel analog signal conditioning unit as a common differential reference, and extract the common mode component from each channel common mode node, and feed it back to the right leg / reference ground electrode after inversion, filtering, buffering and current limiting protection. The eight-channel analog signal conditioning unit is used to perform differential amplification, high-pass filtering, low-pass filtering and gain amplification on the buffered signal output by the dry electrode active buffer unit. The reference voltage and multi-channel ADC sampling unit are used to sample / convert the conditioned eight-channel analog EEG signals into digital signals according to a preset channel sequence. The motion sensor unit is used to collect acceleration and angular velocity data related to head movement, posture changes, and electrode disturbances; The main control and wireless communication unit is used to read digital signals through the SPI interface, synchronously receive motion data from the motion sensor unit, and cache and frame the EEG data and motion data before sending them to the host computer through the wireless network. The host computer real-time visualization unit is used to receive EEG data packets and motion data through a wireless network, parse, verify and buffer the data packets, and display eight-channel EEG waveforms and motion status in real time.

2. The EEG signal acquisition and wireless display system according to claim 1, characterized in that, The dry electrode array includes at least eight Ag / AgCl dry electrodes, one earlobe reference electrode, and one right leg / reference ground electrode. The eight Ag / AgCl dry electrodes correspond to eight EEG sampling channels. The earlobe reference electrode is connected to the inverting input of the differential amplifier of each channel or the common reference input. The right leg / reference ground electrode is connected to the output of the right leg drive / common mode feedback unit.

3. The EEG signal acquisition and wireless display system according to claim 1, characterized in that, The dry electrode active buffer unit includes eight identical voltage follower modules, each of which includes an FPC connector, an input current-limiting resistor, a bidirectional electrostatic discharge protection device, an RC low-pass filter network, a power supply decoupling capacitor, and a rail-to-rail low-power operational amplifier.

4. The EEG signal acquisition and wireless display system according to claim 3, characterized in that, The input current-limiting resistor is connected in series in the dry electrode signal input path. The bidirectional electrostatic discharge protection device consists of two diodes connected in reverse parallel and is connected between the input terminal of the operational amplifier and the power supply ground. The RC low-pass filter network consists of a capacitor and a resistor and is connected to the non-inverting input terminal of the operational amplifier. The operational amplifier adopts unity-gain negative feedback connection to form a voltage follower. The output terminal of the voltage follower is sent to the eight-channel analog signal conditioning unit after passing through a small-value series resistor.

5. The EEG signal acquisition and wireless display system according to claim 1, characterized in that, The eight-channel analog signal conditioning unit includes eight identical channel circuits, each channel including: an instrumentation amplifier, a pre-RC current limiting / filtering structure, a first-order high-pass filter, a second-order Sallen-Key low-pass filter, an inverting gain amplifier, and a bias reference input node.

6. The EEG signal acquisition and wireless display system according to claim 5, characterized in that, The non-inverting input of the instrumentation amplifier is connected to the buffered output signal of the corresponding sampling electrode, the inverting input of the instrumentation amplifier is connected to the earlobe reference electrode signal, the output of the instrumentation amplifier is connected to the first-order high-pass filter, the output of the first-order high-pass filter is connected to the second-order Sallen-Key low-pass filter, the output of the second-order Sallen-Key low-pass filter is connected to the inverting gain amplifier, and the output of the inverting gain amplifier is connected to the reference voltage and the multi-channel ADC sampling unit.

7. The EEG signal acquisition and wireless display system according to claim 1, characterized in that, The reference electrode and the right leg drive / common mode feedback unit include: a common mode extraction network and an operational amplifier buffer circuit; The common-mode extraction network extracts common-mode components from the common-mode nodes of each channel of the high-resistance resistor network. The operational amplifier buffer circuit inverts, filters, and buffers the extracted common-mode components. The output of the operational amplifier buffer circuit is connected to the right leg / reference ground electrode via a current limiting or protection structure.

8. The EEG signal acquisition and wireless display system according to claim 1, characterized in that, The system also includes: a power management unit and a PCB support structure; The power management unit is used to convert the external input power into multiple stable voltages, and provide domain-isolated power supply to the dry electrode active buffer unit, the eight-channel analog signal conditioning unit, the reference voltage and multi-channel ADC sampling unit, the motion sensor unit and the main control and wireless communication unit, respectively, so as to reduce the coupling interference of power ripple and digital switching noise to the analog front end. The PCB support structure is used to support various functional units. Through the modular layout of separating the main control board and the eight-channel signal conditioning board, the analog sensitive circuits and digital high-speed circuits are physically isolated and the spatial layout is optimized, the critical signal paths are shortened, and the signal integrity and electromagnetic compatibility between the units are ensured.

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