Wafer thinning method and apparatus, storage medium, program product

Abstract

The application provides a wafer thinning method and device, a storage medium and a program product, and belongs to the fields of precision grinding equipment and semiconductor manufacturing technology. The thinning method is applied to a target wafer prepared through a bare chip to wafer process, and comprises the following steps: acquiring geometric distribution information of a plurality of bare chips on a base wafer; determining a rotation control strategy according to the geometric distribution information, wherein the rotation control strategy comprises a target rotation number of a wafer bearing table and a target rotation angle corresponding to each rotation; controlling the target wafer to perform intermittent rotation according to the rotation control strategy, and measuring the thickness of the target wafer by using a contact type thickness measuring device in the interval of the intermittent rotation, so as to obtain measured thicknesses at different positions; determining the maximum value in the measured thicknesses as an initial thickness; and performing grinding treatment on the bare chips based on the initial thickness, so as to thin the bare chips.

Description

Technical Field

[0001] This application belongs to the field of precision grinding equipment and semiconductor manufacturing technology, and more specifically, it relates to a wafer thinning method and equipment, storage medium, and program product. Background Technology

[0002] In the die-to-wafer process, pre-processed dies are bonded one by one onto a substrate wafer to form the target wafer. After bonding, the top surface of the die on the target wafer needs to be mechanically ground to reduce the overall thickness and improve heat dissipation. However, due to inherent differences in die thickness, uneven bonding adhesive coating thickness, inconsistent bonding pressure distribution in the wafer's radial direction, and localized warping caused by the mismatch in thermal expansion coefficients between silicon and the substrate material, the top surfaces of the bonded dies often exhibit micrometer-level height differences. This height difference means that the surface of the target wafer is not an ideal plane, but rather has a non-uniform topological structure with localized protrusions.

[0003] The aforementioned non-uniformity poses a significant challenge to subsequent precision machining. In downstream processes such as wafer-level packaging, mechanical grinding inevitably introduces a subsurface damage layer (SSD). If the surface quality and damage layer depth after grinding are not properly controlled, when fabricating the dielectric layer of the redistribution layer (RDL) on the silicon surface, the increased surface roughness and decreased chemical bonding ability caused by SSD can easily lead to interface failures (such as delamination and peeling) between the RDL dielectric layer and the silicon layer in subsequent thermal processes, severely affecting packaging reliability.

[0004] In existing technologies, contact thickness gauges are typically used to perform dynamic thickness scanning during the continuous rotation of the wafer. However, the probe is easily scratched by the sharp edges of the bare chip, and dynamic measurement is difficult to accurately capture the maximum thickness, which in turn affects the accuracy control of subsequent grinding. Summary of the Invention

[0005] In view of the above problems, this application provides a wafer thinning method and apparatus, storage medium, and program product, thereby solving or at least alleviating one or more of the above-mentioned problems and other problems existing in the prior art.

[0006] A first aspect of this application provides a wafer thinning method, which is applied to a target wafer fabricated based on a die-to-wafer process. The target wafer includes a substrate wafer and a plurality of bare chips bonded to the substrate wafer. The wafer thinning method includes:

[0007] Obtain the geometric distribution information of multiple bare chips on the substrate wafer;

[0008] The rotation control strategy corresponding to the target wafer is determined based on the geometric distribution information; the rotation control strategy includes: the number of target rotations of the wafer carrier stage and the target rotation angle corresponding to each rotation;

[0009] The target wafer is controlled to rotate intermittently according to the rotation control strategy. During the intervals of the intermittent rotation, the thickness of the target wafer is measured using a contact thickness measurement device to obtain the measured thickness at different locations on the target wafer. The thickness of the target wafer is the overall thickness of the substrate wafer and the bare chip.

[0010] The maximum value among the measured thicknesses is determined as the initial thickness of the target wafer;

[0011] The bare chip on the upper surface of the target wafer is ground based on the initial thickness to reduce the thickness of the bare chip and achieve wafer thinning.

[0012] In one embodiment, the geometric distribution information includes at least one of the following: the size of each bare chip, the distribution location of each bare chip on the substrate wafer, and the distribution density of bare chips on the substrate wafer;

[0013] The rotation control strategy corresponding to the target wafer is determined based on the geometric distribution information, including:

[0014] Obtain the baseline control strategy corresponding to the target wafer; the baseline control strategy includes: the initial number of rotations of the wafer carrier stage carrying the target wafer;

[0015] The initial number of rotations is adjusted using at least one piece of information from the geometric distribution to obtain the target number of rotations;

[0016] The target rotation angle is determined based on the number of target rotations and at least one piece of information.

[0017] In one embodiment, one gap of intermittent rotation corresponds to the measurement thickness at a location of the target wafer, and in each gap, the contact thickness measuring device measures the thickness of the target wafer multiple times.

[0018] The thickness at each location on the target wafer was obtained in the following way:

[0019] The median of the thickness of the target wafer obtained from multiple measurements by the contact thickness measuring device at the corresponding rotation gap is determined as the measured thickness at that position.

[0020] In one embodiment, the wafer thinning method further includes:

[0021] The difference between the maximum and minimum values ​​of each measured thickness is determined as the maximum difference;

[0022] If the maximum difference exceeds the predetermined threshold, an alarm signal will be issued, and the wafer thinning equipment will be triggered to perform a shutdown operation.

[0023] In one embodiment, the initial thickness is measured before grinding the bare chip on the upper surface of the target wafer to determine the grinding start position; the wafer thinning method further includes:

[0024] After the grinding of the bare chip on the upper surface of the target wafer begins, the thickness of the target wafer is measured using a non-contact thickness measurement device. The thickness measured within the target measurement range is determined as the effective thickness measured by the non-contact thickness measurement device. The effective thickness is used for thickness monitoring during the grinding process of the target wafer.

[0025] In one embodiment, the method for determining the target measurement range includes:

[0026] If the ground thickness of the target wafer does not exceed the predetermined thickness change threshold from the start of grinding the target wafer, the target measurement range is determined based on the initial thickness and the predetermined first measurement fluctuation value.

[0027] If, from the start of grinding the target wafer, the ground thickness exceeds the thickness variation threshold, a target measurement range determination operation is performed. Starting from the moment the ground thickness exceeds the thickness variation threshold, a target measurement range determination operation is performed once every time the thickness variation value of the target wafer exceeds the thickness variation threshold. The target measurement range determination operation includes:

[0028] The target measurement range is determined based on the real-time thickness of the target wafer and a predetermined second measurement float value.

[0029] In one embodiment, grinding is performed on the bare chip on the upper surface of the target wafer based on an initial thickness, including:

[0030] The grinding start position is determined based on the initial thickness. The Z-axis of the grinding device in the wafer thinning equipment is controlled to move to the grinding start position to start feeding, and it is determined whether the spindle of the grinding device is in contact with the target wafer.

[0031] After determining that the spindle is in contact with the target wafer, the thickness is monitored based on the effective thickness measured by the non-contact thickness measurement device, and the bare chip on the upper surface of the target wafer is ground.

[0032] In one embodiment, the wafer thinning method further includes:

[0033] During the grinding process, at least one of the following is collected: real-time current of the spindle, vibration signal of the spindle, and acoustic emission signal at the grinding device; and feature values ​​corresponding to at least one signal are extracted.

[0034] Based on eigenvalues ​​and geometric distribution information, the subsurface damage layer depth of the target wafer in the current grinding area is predicted using a pre-calibrated subsurface damage depth correlation model.

[0035] If the depth of the subsurface damage layer exceeds the predetermined damage threshold, adjust the grinding parameters corresponding to the grinding process, or adjust the polishing parameters of the subsequent chemical mechanical polishing process.

[0036] The subsurface damage depth correlation model is trained based on historical grinding data, which includes: real-time spindle operating parameters, geometric distribution information, and the corresponding measured values ​​of subsurface damage layer depth.

[0037] A second aspect of this application provides a wafer thinning apparatus, comprising:

[0038] A wafer carrier stage is used to support and rotate wafers.

[0039] The grinding device is lifted and positioned above the wafer carrier stage. The grinding device includes a spindle, a Z-axis, and grinding wheels for grinding wafers.

[0040] The controller is used to implement the wafer thinning method described above.

[0041] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described wafer thinning method.

[0042] A fourth aspect of this application provides a computer program product, including a computer program or computer-executable instructions, which, when executed by a processor, implement the steps of the above-described wafer thinning method.

[0043] The beneficial effects of the embodiments of this application are as follows:

[0044] First, by using intermittent rotation measurement based on the geometric distribution information of the bare chip, static single-point measurement is performed using a contact thickness gauge in the static gap of the wafer carrier stage. This avoids the risk of relative sliding and scratching between the probe and the sharp edge of the bare chip during continuous rotation, while improving the accuracy of non-uniform surface thickness measurement.

[0045] Secondly, during the grinding process, the spindle current, vibration signal and acoustic emission signal are collected in real time, their feature values ​​are extracted and combined with the geometric distribution information of the bare chip, and the subsurface damage layer depth of the current grinding area is predicted by a pre-calibrated correlation model. When the predicted value exceeds the predetermined threshold, the grinding feed speed is automatically adjusted to reduce the cutting load of a single abrasive grain, thereby controlling the subsurface damage layer depth within the process requirements and improving the grinding surface quality.

[0046] Finally, based on the thickness distribution map, predicted subsurface damage layer depth, and wafer warpage monitoring values ​​obtained during the intermittent rotation measurement stage, a process quality report can be generated and used as compensation input for downstream processes. Because this application controls the subsurface damage layer depth within a predetermined threshold, it provides a high-quality surface foundation for downstream precision processes (such as chemical mechanical polishing and dielectric layer deposition), indirectly reducing the risk of downstream interface failure. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of a wafer thinning apparatus provided in one embodiment of this application;

[0049] Figure 2 This is a schematic flowchart of a wafer thinning method provided in an embodiment of this application;

[0050] Figure 3 This is a schematic diagram of the structure of a target wafer provided in an embodiment of this application;

[0051] Figure 4 This is a schematic diagram of the structure of a bare chip provided in an embodiment of this application;

[0052] Figure 5 This is a schematic diagram illustrating the process of measuring the thickness of a target wafer using a contact-type thickness measuring device, as provided in an embodiment of this application.

[0053] Figure 6 A schematic diagram illustrating the process of measuring the thickness of a target wafer using a non-contact thickness measurement device, as provided in an embodiment of this application.

[0054] Figure 7 A schematic flowchart of a wafer thinning method provided in another embodiment of this application;

[0055] Figure 8 A schematic flowchart of a wafer thinning method provided in another embodiment of this application;

[0056] Figure 9 A schematic diagram of a structure in which the dielectric layers of the SSD and RDL exhibit obvious delamination, provided in an embodiment of this application;

[0057] Figure 10 A schematic diagram of a structure in which the SSD and RDL dielectric layers do not show obvious delamination, provided in an embodiment of this application;

[0058] Figure 11 A closed-loop diagram of the training and application of a subsurface damage depth correlation model provided in an embodiment of this application;

[0059] Figure 12 This is a schematic diagram of a process for determining whether the spindle is in contact with the target wafer, provided in an embodiment of this application.

[0060] Figure 13 This is a schematic diagram of the overall process for thickness measurement during wafer grinding, provided in an embodiment of this application.

[0061] Figure 14 This is a structural block diagram of a wafer thinning apparatus provided in one embodiment of this application;

[0062] Figure label:

[0063] 10. Rotary worktable; 11. Wafer carrier stage; 12. Grinding device; 13. Contact thickness measurement device; 14. Non-contact thickness measurement device; 121. Grinding wheel; 122. Spindle; 123. Z-axis; H1. RDL dielectric layer; H2. Subsurface damage layer in silicon layer; H3. Part of silicon layer excluding subsurface damage layer; Q1. Contact position between silicon layer and RDL dielectric layer. Detailed Implementation

[0064] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the specific implementation of this application should fall within the protection scope of the embodiments of this application.

[0065] To keep the drawings concise, each drawing only schematically shows the parts relevant to the disclosure; these do not represent the actual structure of the product. Furthermore, for ease of understanding, in some drawings, only one of components with the same structure or function is schematically shown, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one," and "several" includes "two" and "more than two."

[0066] In this document, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0067] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0068] In the description of this embodiment, terms such as "upper," "lower," "left," and "right" are based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of description and simplification of operation, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0069] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0070] It should be understood that, unless the context clearly states otherwise, the terms "comprising," "including," or "having" as used herein refer to the presence of an element, but do not exclude the presence or addition of one or more other elements. Furthermore, "comprising" and / or "including" as used herein specify the presence of shapes, numbers, steps, operations, members, elements, and / or combinations thereof, and do not exclude the presence or addition of one or more other shapes, numbers, operations, elements, and / or combinations thereof. Some embodiments of this application are described in detail below with reference to the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features can be combined with each other. The steps in the following method embodiments are for illustrative purposes only and are not intended to limit this application.

[0071] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0072] First, let me explain the wafer thinning scenario involved in the embodiments of this application: Please refer to Figure 1 , Figure 1 The wafer thinning apparatus provided in this embodiment includes: three wafer carrier stages 11, a grinding device 12, a contact thickness measuring device (referred to as IPG in the following embodiment) 13, a non-contact thickness measuring device (referred to as NCG in the following embodiment) 14, and a controller ( Figure 1 (Not shown in the image). The three wafer carrier stages 11 are identical in structure and function, each carrying a wafer and used to support and rotate the wafer. The three wafer carrier stages 11 can rotate around the axis of the rotary table 10, allowing the wafer to rotate between different workstations to achieve wafer loading, rough grinding, and fine grinding.

[0073] In this embodiment, the grinding device 12 of the wafer thinning equipment includes a grinding wheel 121, a spindle 122, and a Z-axis 123. The grinding wheel 121 is mounted on the end of the spindle 122 and is driven to rotate by the spindle 122. The spindle 122 is connected to the Z-axis 123 to achieve vertical movement, thereby realizing axial infeed grinding and enabling the wafer to reach the required thickness for the process.

[0074] In this embodiment, the initial thickness of the wafer needs to be measured before grinding begins, so that the grinding process can be based on this initial thickness. Once grinding begins, the wafer thickness also needs to be monitored in real time to provide timely warnings in case of deviations during the grinding process, thus preventing wafer damage. To balance measurement accuracy and convenience, this embodiment uses an IPG to measure the initial thickness of the wafer and an NCG to measure the thickness of the wafer in real time during the grinding process. Depending on the actual situation, other types of thickness detection devices can also be used to measure the wafer thickness, or a combination of various thickness detection devices can be used to measure the wafer thickness; this embodiment does not limit this approach.

[0075] In this embodiment, the controller is used to issue control commands to cause the grinding device 12 to grind the wafer on the wafer carrier stage 11, or to cause the contact thickness measuring device 13 and the non-contact thickness measuring device 14 to measure the thickness of the wafer on the wafer carrier stage 11, or to cause other components in the wafer grinding process to receive commands and complete the operations corresponding to the commands.

[0076] Based on the aforementioned wafer thinning scenarios, this application provides a wafer thinning method. Figure 2 This is a schematic flowchart of a wafer thinning method provided in an embodiment of this application. The wafer thinning method can be executed by a controller and is applied to a target wafer fabricated based on a bare chip to wafer process. The target wafer includes a substrate wafer and multiple bare chips bonded to the substrate wafer.

[0077] For information on the target wafer, please refer to [link / reference]. Figure 3 and Figure 4 , Figure 3 A schematic diagram of the target wafer structure is provided. Figure 3 In this diagram, each small grid represents a bare chip, and each bare chip is bonded to the surface of the substrate wafer. Figure 4 A schematic diagram of a bare chip structure is provided, with reference to... Figure 4 Each bare die comprises a silicon (Si) layer and a dielectric layer, with the dielectric layer of each bare die bonded to a substrate wafer. Based on this, if the surface bonded to each bare die on the substrate wafer is defined as the upper surface of the substrate wafer, then the thickness of the target wafer includes the thickness between the lower surface of the substrate wafer and the surface of the Si layer of each bare die.

[0078] Based on the wafer thinning scenario provided in the embodiments of this application and the structural properties of the target wafer, it can be found that, due to the difference in Si layer height among the bare chips, when the wafer carrier is in a continuous rotating state, measuring the thickness of the target wafer using IPG may cause scratches on the edges of the bare chips on the target wafer, thereby reducing the yield.

[0079] To address the aforementioned problems, this application provides a wafer thinning method. This method can reduce dicing risks, improve wafer thickness measurement accuracy, and maximize the efficiency of wafer thickness measurement. The method may include:

[0080] S101: Obtain the geometric distribution information of multiple bare chips on the substrate wafer.

[0081] In this embodiment, the geometric distribution information may include at least one of the following: the size of each bare chip, the distribution position of each bare chip on the substrate wafer, and the distribution density of bare chips on the substrate wafer. The size of the bare chip includes, but is not limited to, length, width, height, and the ratio of Si layer to dielectric layer; the distribution position includes, but is not limited to, the coordinate information of the bare chip, the center distance between each bare chip and adjacent bare chips, the row spacing, and the column spacing; the distribution density includes, but is not limited to, the number and density distribution of bare chips per unit area. The aforementioned density distribution represents the difference in the number of multiple bare chips in different regions of the substrate wafer, and this density distribution can be determined by the following method:

[0082] The substrate wafer is uniformly divided into multiple regions, and the number of bare chips in each region is calculated. The number of bare chips in each region is used as the density distribution of multiple bare chips on the substrate wafer.

[0083] S102: Determine the rotation control strategy corresponding to the target wafer based on the geometric distribution information.

[0084] The rotation control strategy includes the number of target rotations of the wafer carrier stage carrying the target wafer and the target rotation angle corresponding to each rotation.

[0085] In this embodiment, determining the rotation control strategy corresponding to the target wafer based on geometric distribution information may include: directly determining the target number of rotations of the wafer carrier stage and the target rotation angle corresponding to each rotation based on the geometric distribution information; or first determining the target number of rotations of the wafer carrier stage based on the geometric distribution information, and then determining the target rotation angle corresponding to each rotation based on the target number of rotations; or first determining the target rotation angle of the wafer carrier stage based on the geometric distribution information, and then determining the target number of rotations based on the target rotation angle.

[0086] In this embodiment, if the number of rotations of the wafer carrier stage is too small, the obtained wafer thickness data will be insufficient, and measurement accuracy cannot be guaranteed; if the number of rotations of the wafer carrier stage is too large, the measurement efficiency will be affected. Therefore, this embodiment adaptively determines the target number of rotations of the wafer carrier stage and the target rotation angle corresponding to each rotation through geometric distribution information, which can select appropriate rotation numbers and rotation angles, ensuring both measurement accuracy and measurement efficiency.

[0087] In one embodiment, determining the target rotation angle corresponding to each rotation of the wafer carrier stage based on the target number of rotations can be achieved through the following method:

[0088] Let N be the number of target rotations, then the target rotation angle Ang corresponding to each rotation of the wafer carrier stage can be: , This indicates rounding up to the nearest integer.

[0089] In one embodiment, determining the target rotation number of the wafer carrier stage based on the target rotation angle can be achieved as follows: Let the target rotation angle be Ang, then the target rotation number N can be: .

[0090] In another embodiment, to achieve a better balance between measurement accuracy and measurement efficiency, especially when the bare chips are non-uniformly distributed on the substrate wafer, this application also provides a non-uniformly spaced rotation strategy. Specifically, the step of determining the target rotation angle based on the target number of rotations and at least one piece of information may further include:

[0091] First, the substrate wafer is divided into multiple regions based on geometric distribution information (such as the distribution density or location of the bare chips) to form multiple measurement sectors. For example, the substrate wafer can be divided according to the distribution density and / or location of the bare chips, and regions with a bare chip distribution density greater than a first preset threshold are marked as high-density sectors, while regions with a distribution density less than a second preset threshold are marked as low-density sectors. The second preset threshold is less than the first preset threshold.

[0092] Then, different measurement densities are assigned to different sectors, thereby determining the corresponding rotation angle. For example, for high-density sectors, since there are more bare chips per unit area and the height difference changes more frequently, more measurement points need to be assigned to ensure that the maximum thickness is captured, so a smaller target rotation angle (e.g., 15°) is assigned to them; for low-density sectors, the bare chips are sparse and the height change is relatively gentle, so fewer measurement points can be assigned to improve measurement efficiency, so a larger target rotation angle (e.g., 45°) is assigned to them.

[0093] An exemplary algorithm for determining the target rotation angle is as follows:

[0094] Let the number of target rotations be N. Divide the 360° circle into k consecutive angular intervals according to the density of the bare chip. Each angle interval represents a sector. Based on this, the weighting coefficient of each angle interval can be determined according to its distribution density, and the number of rotations can be assigned to each angle interval according to the weighting coefficient. The weighting coefficient is positively correlated with the distribution density of bare chips in the corresponding angle interval; that is, the greater the distribution density of bare chips in a certain angle interval, the greater the weighting coefficient corresponding to that angle interval.

[0095] In this embodiment, one feasible implementation is to directly allocate the number of rotations based on an integer allocation method, according to weighting coefficients. Once the number of rotations for each angle interval is determined, the target rotation angle for each angle interval can be determined using the following formula:

[0096]

[0097] in, It is the target rotation angle corresponding to the j-th angle interval. It is the angle size of the j-th angle interval. , It is the number of rotations assigned to the j-th angle interval.

[0098] In this embodiment, in addition to the integer allocation method, for the sake of calculation simplicity, the number of rotations in the j-th angle interval can also be allocated based on the following formula:

[0099]

[0100] in, This represents the weight coefficient corresponding to the j-th angle interval. The number of rotations for each angle interval j can be determined by... The result can be obtained by rounding down, rounding up, or rounding to the nearest whole number; this embodiment does not limit the specific method used.

[0101] S103: Control the target wafer to rotate intermittently according to the rotation control strategy, so as to measure the thickness of the corresponding position of the target wafer during the rotation gap.

[0102] In this embodiment, after determining the target number of rotations of the wafer carrier stage and the target rotation angle corresponding to each rotation, the wafer carrier stage can drive the target wafer to rotate intermittently. Intermittent rotation refers to the following: the wafer carrier stage first drives the target wafer to rotate once according to a preset target rotation angle, then stops rotating, allowing the IPG to measure the thickness of the target wafer while it is stationary. After the thickness measurement is completed, the wafer carrier stage drives the target wafer to perform the next rotation (maintaining the same direction as the previous rotation) according to the preset target rotation angle, then stops rotating again to measure the thickness. After the thickness measurement is completed, the wafer carrier stage drives the target wafer to perform the next rotation according to the preset target rotation angle... This rotation and stopping process is repeated until the number of rotations of the target wafer reaches the preset target number, indicating that the intermittent rotation is complete.

[0103] For reference Figure 5 This embodiment provides a procedure for measuring the thickness of a target wafer using IPG:

[0104] like Figure 5 As shown, after the measurement begins, the wafer carrier stage rotates Ang according to the target rotation angle. If the rotation is not completed, it continues to rotate. If the rotation is completed, the IPG descends to the position of contact with the target wafer to measure the wafer thickness. At this time, the thickness of the target wafer at the current rotation angle is recorded. After the measurement is completed, the IPG is raised. If the number of rotations of the wafer carrier stage has not reached N, the wafer carrier stage continues to rotate according to the target rotation angle. If the number of rotations of the wafer carrier stage reaches N, the difference between the maximum and minimum values ​​among the N measurement points is compared to obtain the maximum thickness deviation value. If the maximum thickness deviation value is greater than a predetermined threshold, an alarm is triggered; if the maximum thickness deviation value is less than or equal to the predetermined threshold, the maximum thickness among the N measurement points is taken as the initial thickness of the target wafer, and the measurement is completed.

[0105] In one embodiment, one gap of intermittent rotation corresponds to the measured thickness at a location on the target wafer, and the IPG measures the thickness of the target wafer multiple times during each gap.

[0106] The thickness at each location on the target wafer was obtained in the following way:

[0107] At the corresponding rotation gap, the median of the thickness of the target wafer obtained from multiple IPG measurements is determined as the measured thickness at that position.

[0108] In this embodiment, during the static interval between every two rotations, the IPG performs a measurement action, bringing the measurement probe into contact with the surface to be measured on the target wafer, and acquiring thickness data at the current position based on the contact measurement principle. This thickness data includes multiple sample points measured by the IPG at that position. Based on this, the median, average, or mode of the multiple sample points at the current position can be calculated as the measured thickness of the target wafer at that position; this embodiment does not limit this.

[0109] In one embodiment, after the IPG completes a round of measurement, the measured thickness at different locations on the target wafer is obtained. That is, the measured thickness of the target wafer at N locations is obtained by rotating the wafer carrier stage N times. Then, the initial thickness of the target wafer can be determined by using the measured thickness of the target wafer at these N locations.

[0110] S104: Determine the maximum value among the measured thicknesses as the initial thickness of the target wafer.

[0111] In this embodiment, since the target wafer is fabricated using a die-to-wafer process, its surface is composed of a substrate wafer and multiple raised bare chips. The overall surface is not a single plane, and the measured thickness varies significantly at different locations. Determining the maximum value among the measured thicknesses as the initial thickness of the target wafer accurately reflects its maximum profile height, avoiding problems such as excessive thinning, bare chip damage, or over-cutting of the substrate wafer caused by using a smaller thickness value as a reference.

[0112] S105: Grinding the bare chip on the upper surface of the target wafer based on the initial thickness to reduce the thickness of the bare chip and achieve wafer thinning.

[0113] In this embodiment, steps S101-S104 provide a wafer thickness measurement method, which can more accurately calculate the initial thickness of the target wafer. Based on this, after determining the initial thickness of the target wafer, the controller can determine the grinding start position based on the initial thickness of the target wafer, and control the Z-axis to move to the grinding start position to start feeding to grind the bare chip on the upper surface of the target wafer, thinning the bare chip, and realizing the thinning of the target wafer.

[0114] As can be seen from the above, firstly, this embodiment uses intermittent rotation measurement based on the geometric distribution information of the bare chip to perform static single-point measurement using a contact thickness gauge in the static gap of the wafer carrier stage, thus avoiding the risk of relative sliding and scratching between the probe and the sharp edge of the bare chip during continuous rotation.

[0115] Secondly, the wafer rotation control strategy in this embodiment is determined based on the geometric distribution information of the bare chip on the substrate wafer. Compared with the scheme of fixed number of rotations, it can avoid too many or too few rotations, thereby reducing the risk of dicing, improving the accuracy of wafer thickness measurement, and maximizing the efficiency of wafer thickness measurement. This also enables the embodiments of this application to better adapt to different wafer thickness measurement scenarios and wafer thinning scenarios.

[0116] In one embodiment of this application, determining the rotation control strategy corresponding to the target wafer based on geometric distribution information includes:

[0117] Obtain the baseline control strategy corresponding to the target wafer; the baseline control strategy includes: the initial number of rotations of the wafer carrier stage carrying the target wafer;

[0118] The initial number of rotations is adjusted using at least one piece of information from the geometric distribution to obtain the target number of rotations;

[0119] The target rotation angle is determined based on the number of target rotations and at least one piece of information.

[0120] In this embodiment, the initial number of rotations of the wafer carrier stage carrying the target wafer can be preset based on experience. For example, the initial number of rotations of the wafer carrier stage can be preset to 8 times; it can also be determined based on the diameter of the substrate wafer in the target wafer.

[0121] The method for determining the initial number of rotations based on the diameter of the substrate wafer may include:

[0122] The initial number of rotations of the wafer stage is determined based on a pre-defined positive correlation between the number of rotations and the diameter of the substrate wafer. This positive correlation means that the change in the substrate wafer diameter and the change in the initial number of rotations of the wafer stage follow a consistent trend; that is, the larger the substrate wafer diameter, the more initial rotations are required. For example, an 8-inch substrate wafer might require 8 initial rotations, and a 12-inch substrate wafer might require 12. This embodiment considers that a larger substrate wafer diameter likely results in a higher number of bare chips, and in this case, increasing the initial number of rotations effectively ensures measurement accuracy. Conversely, when the substrate wafer diameter is small, the number of bare chips may be lower, and in this case, the initial number of rotations can be appropriately reduced to improve measurement efficiency.

[0123] In this embodiment, considering that the initial rotation number of the wafer carrier stage is predetermined based on the inherent properties of the target wafer, if the actual distribution characteristics of the bare chips on the target wafer on the substrate wafer are ignored, and thickness measurement is directly performed based on this initial rotation number, it may still be impossible to balance measurement accuracy and measurement efficiency. Therefore, this embodiment also utilizes at least one of the geometric distribution information of the bare chips to adaptively adjust the initial rotation number, thereby obtaining a target rotation number that better fits the wafer structure. Specifically, adjusting the initial rotation number using at least one of the geometric distribution information to obtain the target rotation number includes:

[0124] The target number of rotations can be obtained by adjusting one of the following information: the size of each bare chip, the distribution position of each bare chip on the substrate wafer, and the distribution density of bare chips on the substrate wafer; or by adjusting any two of the geometric distribution information; or by adjusting all three of the geometric distribution information.

[0125] The method of adjusting the initial number of rotations based on the size of each bare chip to obtain the target number of rotations can include:

[0126] The rotation number fluctuation value is determined based on the size of each bare chip, and the initial rotation number is corrected based on the rotation number fluctuation value to obtain the target rotation number of the target wafer.

[0127] In this embodiment, a mapping table between the size parameters of the bare chip and the rotational number fluctuation value can be pre-established. This pre-established mapping table is used to determine the rotational number fluctuation value corresponding to the size of each bare chip. The mapping table characterizes the correlation between the size parameters of the bare chip and the rotational number fluctuation value (the rotational number fluctuation value is an integer). For example, the larger the length, width, and height of the bare chip, the smaller the rotational number fluctuation value; conversely, the smaller the length, width, and height of the bare chip, the larger the rotational number fluctuation value. The rotational number fluctuation value can be positive or negative.

[0128] The initial number of rotations is adjusted based on the distribution position of each bare chip on the substrate wafer to obtain the target number of rotations, which may include:

[0129] The center distance, row spacing, or column spacing of each bare chip to its adjacent bare chips are compared with the corresponding preset distance threshold to obtain the comparison results.

[0130] The initial number of rotations is adjusted based on the comparison results to obtain the target number of rotations.

[0131] When adjusting the initial rotation count, one of the center distance, row spacing, or column spacing can be compared with the corresponding preset distance threshold. If the value is greater than the preset distance threshold, it indicates that the bare chip distribution is relatively sparse, and the initial rotation count can be reduced to obtain the target rotation count. If the value is less than or equal to the preset distance threshold, it indicates that the bare chip distribution is relatively dense, and the initial rotation count can be increased to obtain the target rotation count. In this embodiment, the value by which the initial rotation count is increased or decreased can be set according to actual process requirements.

[0132] The method of adjusting the initial number of rotations based on the distribution density of bare chips on the substrate wafer to obtain the target number of rotations may include:

[0133] If the bare chips are uniformly distributed on the substrate wafer, the initial number of rotations is adjusted based on the number of bare chips per unit area to obtain the target number of rotations.

[0134] If the bare chips are not uniformly distributed on the substrate wafer, the target wafer is divided into multiple regions to obtain multiple sectors. The initial number of rotations for each sector is adjusted based on the distribution density of the bare chips in each sector to obtain the target number of rotations for each sector. The target number of rotations for each sector is then added together to obtain the target number of rotations for the target wafer.

[0135] In this embodiment, if the bare chips are uniformly distributed on the substrate wafer, there is no need to divide the wafer into regions. Based on this, for target wafers with a number of bare chips per unit area greater than a preset threshold, the number of rotations can be increased from the initial number of rotations; for target wafers with a number of bare chips per unit area less than or equal to the preset threshold, the number of rotations can be decreased from the initial number of rotations. If the bare chips are not uniformly distributed on the substrate wafer, to ensure measurement accuracy, the target wafer can be divided into multiple regions to obtain multiple sectors, and the initial number of rotations corresponding to different sectors can be adjusted. The adjustment method for the initial number of rotations corresponding to each sector can be determined based on the comparison result of the number of bare chips per unit area in each sector with the preset threshold.

[0136] In one embodiment, if the initial number of rotations is adjusted using any two pieces of information from the geometric distribution information to obtain the target number of rotations, or if the initial number of rotations is adjusted using three pieces of information from the geometric distribution information to obtain the target number of rotations, then the target number of rotations calculated based on each piece of geometric distribution information can be weighted and summed according to the predetermined weights corresponding to each piece of geometric distribution information to obtain the final target number of rotations.

[0137] In this embodiment, after determining the target rotation number N, this embodiment can... The target rotation angle is calculated, and the wafer carrier stage rotates accordingly to enable the IPG to measure the thickness of the target wafer. Alternatively, this embodiment can first determine the target rotation angle, and then... The number of target rotations is calculated. The method for determining the target rotation angle is similar to that for determining the number of target rotations, and will not be repeated in this embodiment. Through the adaptive adjustment of the target rotation number, this embodiment can improve the accuracy and effectiveness of wafer thickness measurement.

[0138] In one embodiment of this application, the wafer thinning method may further include:

[0139] The difference between the maximum and minimum values ​​of each measured thickness is determined as the maximum difference;

[0140] If the maximum difference exceeds the predetermined threshold, an alarm signal will be issued, and the wafer thinning equipment will be triggered to perform a shutdown operation.

[0141] In this embodiment, the target wafer consists of a substrate wafer and multiple bare chips bonded to it. The differences in the measured thickness at different locations mainly originate from the height difference between the bare chips and the substrate wafer, the flatness of the bonding interface, and the overall warpage deformation of the wafer. The difference between the maximum and minimum values ​​of each measured thickness (maximum difference) reflects the overall height fluctuation of the target wafer surface.

[0142] If the maximum difference exceeds a predetermined threshold (which can be set within the range of 5μm to 20μm), it indicates that the surface height difference of the target wafer exceeds the allowable range of the process, potentially indicating issues such as bare die bonding misalignment, excessively high local bumps, severe wafer warpage, or abnormal thickness distribution. Continuing wafer grinding under these conditions can easily lead to over-grinding of the bare die, over-cutting of the substrate wafer, or even wafer failure. Furthermore, abrupt changes in wafer surface height can cause uneven grinding stress, potentially leading to wafer breakage, equipment collisions, and other safety risks. Therefore, when the maximum difference exceeds the predetermined threshold, an alarm signal can be triggered, causing the wafer thinning equipment to stop to prevent damage to the target wafer.

[0143] In one embodiment of this application, the initial thickness is measured before grinding the bare chips on the upper surface of the target wafer. After grinding begins, to minimize wafer damage and achieve rapid wafer thickness measurement, NCG is typically used. However, during the grinding process of the target wafer, since the height of the Si layer varies among the bare chips, using NCG to measure wafer thickness results in significant thickness deviations, easily triggering abnormal alarms and hindering continuous grinding. To address the above problems, the wafer thinning method provided in this embodiment may further include:

[0144] After grinding the bare chip on the surface of the target wafer begins, the thickness of the target wafer is measured using NCG (Non-Gas Grafting). The thickness measured within the target measurement range is defined as the effective thickness obtained by NCG measurement, which is used for thickness monitoring during the target wafer grinding process. This target measurement range is dynamically adjusted according to the grinding progress and changes in the real-time thickness of the wafer.

[0145] In this embodiment, reference Figure 4 ,from Figure 4 As can be seen, because the height of the Si layer varies in each bare chip, the thickness deviation at different locations on the target wafer measured by NCG is large. This easily triggers measurement anomaly alarms during data anomaly detection, leading to a shutdown of the wafer thinning equipment and preventing continuous grinding. This embodiment addresses this deficiency by setting a target measurement range during NCG measurement. Only measurements within this range are considered valid values ​​for the target wafer thickness, while invalid values ​​outside this range are discarded. This approach maximizes the possibility of continuous grinding and improves wafer grinding efficiency.

[0146] In this embodiment, it is particularly important to note that during the wafer thinning process based on bare die to wafer fabrication, online monitoring using a non-contact thickness measurement device (NCG) faces a unique challenge: the Si layer of the bonded bare die itself exhibits micron-level height differences (see [link to documentation]). Figure 4Even when the wafer is being uniformly ground, the raw thickness data obtained by NCG measurement will show periodic large fluctuations consistent with the distribution pattern of the bare chip.

[0147] If a traditional fixed threshold method is used, such as simply setting a fixed measurement range centered on the initial thickness (e.g., initial thickness ± a fixed value), then these thickness fluctuations caused by differences in the height of the bare die itself, which are actually normal process variations, are very likely to exceed the set fixed measurement range. This can lead to the NCG system misjudging them as "measurement anomalies" or "thickness mutations." This will cause the wafer thinning equipment to frequently trigger false alarms and perform unnecessary shutdowns, severely impacting production continuity.

[0148] To address this issue, this application creatively proposes a dynamic measurement range adjustment mechanism. The core idea of ​​this mechanism is that the validity benchmark for NCG thickness is not static, but rather should adaptively "float" with changes in the grinding process and the real-time wafer thickness. By dynamically binding the measurement range to the real-time wafer thickness (e.g., setting the range to real-time thickness ± a second measurement fluctuation value), normal thickness fluctuations caused by differences in bare die height can be effectively filtered out. An alarm is only triggered when a genuine thickness anomaly exceeding the dynamic range occurs (such as wafer breakage or uneven grinding). This ensures that in bare die to wafer process scenarios, non-contact thickness measurement can truly serve continuous and stable grinding process monitoring.

[0149] In one embodiment, the method for determining the target measurement range may include:

[0150] If the ground thickness of the target wafer does not exceed the predetermined thickness change threshold from the start of grinding the target wafer, the target measurement range is determined based on the initial thickness and the predetermined first measurement fluctuation value.

[0151] If the ground thickness of the target wafer exceeds the thickness change threshold from the start of grinding, a target measurement range determination operation is performed. Starting from the moment the ground thickness of the target wafer exceeds the thickness change threshold, a target measurement range determination operation is performed once every time the thickness change value of the target wafer exceeds the thickness change threshold. The thickness change value of the target wafer refers to the change in the real-time thickness of the target wafer relative to the target wafer thickness at that moment since the last update of the target measurement range.

[0152] The target measurement range determination operation includes: determining the target measurement range based on the real-time thickness of the target wafer and a predetermined second measurement float value.

[0153] In this embodiment, the thickness variation threshold can be set according to the grinding process requirements or the thickness fluctuation of the wafer, for example, it can be set to 1μm~2μm, and in this embodiment, 1μm is preferred. The thickness variation threshold is negatively correlated with the thickness fluctuation of the wafer; that is, the more significant the thickness fluctuation of the wafer, the smaller the thickness variation threshold.

[0154] In one embodiment, reference may be made to Figure 6 , Figure 6 A procedure is provided for measuring the thickness of a target wafer based on NCG during the target wafer grinding process:

[0155] like Figure 6 As shown, after the target wafer begins grinding, the first measurement fluctuation value of the NCG can be obtained, and the target measurement range is determined based on the initial thickness and the first measurement fluctuation value. During the wafer grinding process, the NCG continuously monitors the thickness of the target wafer. If the thickness reaches the target set thickness, the grinding is considered complete. If the thickness does not reach the target set thickness, grinding continues, and it is determined whether the thickness of the target wafer is within the target measurement range. If the thickness of the target wafer is not within the target measurement range, it is determined whether the number of consecutive abnormal thicknesses exceeds the set counting threshold. If so, the wafer thinning equipment will alarm, and grinding will stop. If the thickness of the target wafer is within the target measurement range, the thickness change value of the target wafer is monitored in real time to see if it is greater than the preset thickness change threshold. If so, the target measurement range is updated according to the current thickness of the target wafer, and grinding continues; otherwise, grinding continues, and the thickness is monitored in real time to see if it is within the target measurement range.

[0156] In this embodiment, from the start of grinding the target wafer, the target measurement range needs to be determined for the first time (based on the initial thickness and a predetermined first measurement fluctuation value). At this time, since the height difference of the Si layer between the bare chips is relatively large, in order to prevent the wafer thinning equipment from triggering false alarms and performing unnecessary shutdown operations, the first measurement fluctuation value can be set relatively large in this embodiment to ensure the continuity of wafer grinding. As the grinding process is updated, the height difference of the Si layer between the bare chips becomes smaller. In this embodiment, the target measurement range is determined by the real-time thickness of the target wafer and a predetermined second measurement fluctuation value. At this time, in order to ensure effective monitoring of wafer thickness anomalies during continuous grinding, the second measurement fluctuation value can be set relatively small to adapt to the actual grinding scenario. In this embodiment, the first measurement fluctuation value can be 30 μm, and the range of the second measurement fluctuation value can be 1 μm to 2 μm, preferably 1 μm.

[0157] Specifically, in this embodiment, if after each update of the target measurement range it is determined that the thickness change value of the target wafer is greater than a preset thickness change threshold, the target measurement range can be updated again based on the real-time thickness of the target wafer and a predetermined second measurement fluctuation value to ensure the effectiveness of the target measurement range. In this embodiment, at the start of wafer grinding, the target measurement range is... After wafer grinding begins and the target measurement range is updated, its range is: ,in, This indicates the real-time thickness of the target wafer at each determination of the target measurement range, and the start time of grinding. This is the initial thickness; This indicates the first measurement fluctuation value. This indicates the second measurement fluctuation value.

[0158] This embodiment, by setting a target measurement range, avoids the problem of large thickness deviations in NCG measurements caused by different Si layer heights of each bare chip, which prevents continuous grinding and improves the efficiency of wafer grinding.

[0159] In another embodiment of this application, reference may be made to Figure 7 Grinding the bare chip on the target wafer based on the initial thickness can specifically include:

[0160] S701: Determine the grinding start position based on the initial thickness, control the Z-axis of the grinding device in the wafer thinning equipment to move to the grinding start position to start feeding, and determine whether the spindle of the grinding device is in contact with the target wafer.

[0161] S702: After determining that the spindle is in contact with the target wafer, the thickness is monitored based on the effective thickness measured by the non-contact thickness measuring device, and the bare chip on the target wafer is ground.

[0162] In one embodiment, determining whether the spindle of the wafer thinning equipment is in contact with the target wafer includes:

[0163] Obtain the real-time current of the spindle;

[0164] The relative change between the real-time current and the corresponding idle current of the spindle is used to determine whether the spindle is in contact with the target wafer.

[0165] In this embodiment, the determination of whether the spindle is in contact with the target wafer is based on the relative change between the real-time current and the idle current corresponding to the spindle, including:

[0166] The change in current is obtained based on the real-time current and the idle current corresponding to the spindle.

[0167] Calculate the ratio of the change in current to the idle current;

[0168] If the ratio is greater than the first value, it is determined that the spindle is in contact with the target wafer; if the ratio is less than or equal to the first value, it is determined that the spindle is not in contact with the target wafer.

[0169] In this embodiment, after the initial thickness measurement of the target wafer is completed, the spindle will idle at a set speed, generating idle current during the idling process. This idle current can be the average current value of the spindle motor during the idle cutting process; for example, the average of the sums of n idle currents during the idling process can be taken as the aforementioned average current value. The value of n can be determined according to actual needs.

[0170] When the spindle contacts the target wafer and begins grinding, the real-time current of the spindle increases compared to the idle state. During the idle cutting process, by detecting the real-time current of the spindle motor and comparing it with the idle current, it can be determined whether the spindle has made contact with the target wafer.

[0171] Specifically, the change in current of the spindle motor within a preset time period can be determined. And calculate the change in current and the idling current. ratio The change in current is the measured real-time current I of the spindle motor relative to the idle current. The change in quantity.

[0172] when At that time, it was determined that the spindle had made contact with the target wafer, where This is a constant, and its specific value can be set according to actual needs. This embodiment does not impose any limitations on it.

[0173] In one embodiment, the real-time current of the spindle can be the average of several current values ​​collected within a preset time. The number of currents that can be collected within the preset time is determined according to the actual situation, and the preset time can be 2 seconds.

[0174] In one embodiment, if no detection is detected when the Z-axis descent distance is greater than twice the air cut distance... If the equipment fails to respond, an equipment warning will be issued and grinding will be stopped. The air-cut distance refers to the distance the Z-axis moves from the moment the Z-axis motor starts driving the spindle downwards towards the target wafer until the spindle contacts the surface of the target wafer.

[0175] In another embodiment of this application, reference may be made to Figure 8 Wafer thinning methods may also include:

[0176] S801: During the grinding process, at least one of the following is collected: real-time current of the spindle, vibration signal of the spindle, and acoustic emission signal at the grinding device, and feature value corresponding to at least one signal is extracted.

[0177] S802: Based on eigenvalues ​​and geometric distribution information, the subsurface damage layer depth of the target wafer in the current grinding area is predicted through a pre-calibrated subsurface damage depth correlation model.

[0178] S803: If the depth of the subsurface damage layer exceeds the predetermined damage threshold, adjust the grinding parameters corresponding to the grinding process, or adjust the polishing parameters of the subsequent chemical mechanical polishing process.

[0179] The subsurface damage depth correlation model is trained based on historical grinding data, which includes: real-time spindle operating parameters, geometric distribution information, and the corresponding measured values ​​of subsurface damage layer depth.

[0180] In this embodiment, the following problems still exist after the wafer is ground:

[0181] The surface of the Si layer on a bare chip on a wafer may contain damage layers such as microcracks and dislocations, with depths reaching 1-3 μm. If these damage layers are not completely removed, the dielectric layer of the RDL (Reverse Diode) will deposit on the Si layer surface, resulting in decreased adhesion and making it highly susceptible to delamination during subsequent thermal processes, thus affecting the packaging performance of the final wafer product. For more information on this issue, please refer to [link to relevant documentation]. Figure 9 and Figure 10 , Figure 9 This is a schematic diagram showing a clear delamination of the dielectric layers of the SSD and RDL. Figure 10 This is a schematic diagram showing a structure where there is no obvious delamination between the SSD and RDL dielectric layers. (Example:) Figure 9 As shown, when there are microcracks, dislocations, and other damage layers on the Si layer surface, and the SSD depth is greater than 1.2 μm, the surface roughness of the Si layer increases significantly, and the chemical bonding and mechanical adhesion between the RDL dielectric layer and the damaged layer surface decrease significantly. After subsequent thermal processing, the SSD and RDL dielectric layer are very prone to delamination at position Q1. Figure 10 As shown, when the SSD is absent on the Si layer surface or the SSD depth is controlled within 1.2 μm, the subsequent chemical mechanical polishing process can completely remove the damaged layer, exposing a smooth Si layer surface. Based on this, the RDL dielectric layer forms a good mechanical and chemical bond with the smooth Si layer surface, maintaining interface integrity after thermal processing. No delamination occurs between the SSD and the RDL dielectric layer at position Q1.

[0182] Therefore, in order to effectively solve this problem, this embodiment monitors not only the wafer grinding thickness but also the subsurface damage layer depth to reduce the probability of RDL dielectric layer delamination, thereby improving the packaging performance of wafer products.

[0183] In this embodiment, various data can be collected by sensors to calculate the subsurface damage layer depth based on this data. The sensors described in this embodiment include, but are not limited to, current sensors, triaxial accelerometers, and acoustic emission sensors. Specifically, the current sensor can be installed at the spindle drive motor to collect the real-time current of the spindle; the triaxial accelerometer can be installed at the spindle bearing housing to collect the vibration signal of the spindle; and the acoustic emission sensor can be installed at the grinding wheel guard to collect the acoustic emission signal from the grinding device. Based on this, the subsurface damage layer depth of the current grinding area of ​​the target wafer can be determined using the real-time current of the spindle, the vibration signal, and the acoustic emission signal from the grinding device.

[0184] Specifically, in this embodiment, the current sensor can collect the real-time current of the spindle at a sampling frequency of 1kHz, and the controller extracts the characteristics of the real-time current of the spindle as the first characteristic value. After the triaxial accelerometer collects the vibration signal of the spindle, the vibration signal can be filtered and amplified. Based on this, the controller can extract the root mean square value of the vibration acceleration in the filtered and amplified vibration signal as the second characteristic value. The frequency range of the acoustic emission sensor can be 100kHz-1MHz. After the acoustic emission sensor collects the acoustic emission signal at the grinding device, the acoustic emission signal can be filtered and amplified, and the controller can extract the root mean square value of the filtered and amplified acoustic emission signal as the third characteristic value.

[0185] Based on this, the above three feature values ​​and the received geometric distribution information of the current grinding sector can be input into a pre-calibrated subsurface damage depth correlation model to obtain the SSD prediction value of the target wafer in the current sector. The subsurface damage depth correlation model can be a pre-trained multiple linear regression model, and the geometric distribution information can be the bare chip distribution density of the current sector. In this embodiment, the above SSD prediction value can be compared with a predetermined damage threshold. If the SSD prediction value is greater than the predetermined damage threshold, the following steps can be performed:

[0186] Adjust the grinding parameters corresponding to the grinding process to avoid excessive subsurface damage layer, which could cause RDL dielectric layer delamination.

[0187] Alternatively, the polishing parameters of the subsequent chemical mechanical polishing process can be adjusted to ensure the packaging performance of the final wafer product.

[0188] In this embodiment, the predetermined damage threshold can be 1.2 μm.

[0189] Please refer to Figure 11 , Figure 11 This is a closed-loop diagram illustrating the training and application of a subsurface damage depth correlation model provided in an embodiment of this application. (See diagram below.) Figure 11As shown, during the model training phase, historical wafer grinding data can be obtained as a training set. This historical grinding data may include multiple sets of real-time spindle operating parameters, geometric distribution information of the corresponding grinding sectors, and measured values ​​of the subsurface damage layer depth obtained through transmission electron microscopy. Each set of real-time spindle operating parameters may include historical real-time spindle current, historical root mean square vibration acceleration, and root mean square acoustic emission. The geometric distribution information of the corresponding grinding sectors may include the bare die distribution density. Based on this, a subsurface damage depth correlation model can be obtained by fitting a multiple linear regression algorithm using the above training set. In one possible implementation, the subsurface damage depth correlation model can be expressed by the following equation:

[0190]

[0191] In the formula, This represents the subsurface damage layer depth predicted by the model for the current sector. , For real-time current With idle current The difference, This is the normalized value of the root mean square value of the vibration acceleration. This is the normalized value of the root mean square value of the acoustic emission signal. This is the normalized value of the geometric distribution density of the bare chip in the grinding sector. This is the global compensation offset constant for the model. These are all pre-set weighting coefficients for each parameter.

[0192] like Figure 11 As shown, during the model application phase, the controller extracts features from the real-time spindle current, vibration signal, and acoustic emission signal collected during the grinding process to obtain corresponding feature values. These feature values, along with the geometric distribution density of the bare chip in the current grinding sector, are input into the trained subsurface damage depth correlation model to obtain the SSD prediction value for the current grinding region. The controller compares the SSD prediction value for the current grinding region with a predetermined damage threshold (e.g., 1.2 μm): if the SSD prediction value for the current grinding region is less than or equal to 1.2 μm, the current grinding parameters are maintained and grinding continues; if the SSD prediction value for the current grinding region is greater than 1.2 μm, an adjustment strategy is triggered: the controller outputs a parameter adjustment command.

[0193] In this embodiment, the aforementioned parameter adjustment command includes, but is not limited to: reducing the Z-axis feed rate of the current grinding sector to reduce the single abrasive grain cutting load, or sending a command to the downstream Chemical Mechanical Polishing (CMP) process to extend the polishing time and increase the downforce, thereby ensuring that the subsurface damage layer is fully removed and preventing the dielectric layer of the redistribution layer from delaminating due to insufficient adhesion during subsequent thermal curing and reflow soldering processes. The adjustment ratios of each parameter in the parameter adjustment command can be set according to actual needs. For example, it can be set to reduce the Z-axis feed rate of the current grinding sector by 20%, or to send a command to the downstream CMP process to extend the polishing time by 15% and increase the downforce by 10%, etc. This embodiment does not specifically limit this.

[0194] In summary, the wafer thinning method provided in this application can automatically generate a process quality report based on the thickness distribution map, subsurface damage layer depth prediction value, and wafer warpage monitoring value obtained during the intermittent rotation measurement stage. This report is then sent to the downstream chemical mechanical polishing equipment and redistribution layer preparation equipment in real time, driving the polishing equipment to adjust polishing parameters and the downstream process equipment to adjust relevant process parameters. This transforms the quality information of the grinding process into compensation input for the downstream process, avoiding the global degradation of redistribution layer preparation caused by the local optima of the grinding process. This achieves a leap from single-process control to overall line yield collaborative optimization.

[0195] In this embodiment, reference can be made to Figure 12 , Figure 12 A process for determining whether the spindle is in contact with the target wafer is provided:

[0196] like Figure 12 As shown, firstly, the current monitoring process is initiated. The controller controls the spindle to rotate at a preset speed while simultaneously monitoring the real-time spindle speed. If the spindle speed is detected to be below the set speed, speed monitoring continues until the set speed is reached. Once the spindle speed reaches the set speed, the controller collects the current data of the current spindle within 2 seconds and calculates the average current value during this time period. This serves as the idle current. Furthermore, upon receiving the idle current, the controller controls the Z-axis feed to the grinding start position. If the Z-axis does not reach the preset position, it continues feeding until it reaches the grinding start position. The Z-axis feeds slowly downwards at a set speed, while the controller monitors the spindle current I in real time. When the spindle is confirmed to be in contact with the target wafer, the judgment process ends. If the current change condition is not met when the Z-axis descent distance is greater than twice the cut distance, an alarm is triggered and the grinding action is stopped to avoid wafer damage caused by abnormal Z-axis feed.

[0197] This embodiment measures the initial thickness of the target wafer using the wafer thickness measurement method described in the above embodiment before wafer thinning, which can effectively reduce the risk of scratching the target wafer. By measuring the thickness of the target wafer and controlling the grinding of the target wafer using the wafer thickness measurement method described in the above embodiment during the wafer thinning process, it can effectively ensure that the wafer is in a continuous grinding state, thereby improving the efficiency of wafer grinding.

[0198] refer to Figure 13 This embodiment also provides an overall process for wafer grinding:

[0199] like Figure 13 As shown, before the wafer grinding begins, the IPG (Integrated Photonic Gear) acquires the initial thickness of the target wafer using a static measurement method. This static measurement method means that when the target wafer is in a static state, the IPG acquires thickness data by contacting the surface of the target wafer. After the IPG measurement is completed, it is in a raised state and does not contact the target wafer during the wafer grinding process. After the IPG measurement is completed and raised, the Z-axis of the grinding device descends, causing the spindle to contact the target wafer, and the target wafer begins the grinding process. The NCG (Non-Grinding Component) monitors the wafer thickness change in real time during the wafer grinding process, and the grinding ends when the target wafer thickness reaches the target set thickness.

[0200] Corresponding to the wafer thinning method in the above embodiments, this embodiment also provides a wafer thinning apparatus, see reference. Figure 14 , Figure 14 This is a structural block diagram of a wafer thinning apparatus provided according to an embodiment of this application. For ease of explanation, only the parts relevant to the embodiment of this application are shown. Figure 14 As shown, the wafer thinning apparatus 1400 of this embodiment may include:

[0201] The acquisition module 1401 is used to acquire the geometric distribution information of multiple bare chips on the substrate wafer;

[0202] The strategy determination module 1402 is used to determine the rotation control strategy corresponding to the target wafer based on the geometric distribution information; the rotation control strategy includes: the number of target rotations of the wafer carrier stage carrying the target wafer and the target rotation angle corresponding to each rotation;

[0203] The control and measurement module 1403 is used to control the target wafer to rotate intermittently according to the rotation control strategy, and to measure the thickness of the target wafer using a contact thickness measurement device during the intervals of the intermittent rotation, so as to obtain the measured thickness at different positions on the target wafer; the thickness of the target wafer is the overall thickness of the substrate wafer and the bare chip bonded to it.

[0204] The initial thickness determination module 1404 is used to determine the maximum value among the various measured thicknesses as the initial thickness of the target wafer;

[0205] The wafer grinding module 1405 is used to grind the bare chip on the upper surface of the target wafer based on the initial thickness in order to thin the bare chip and achieve wafer thinning.

[0206] The acquisition module 1401, strategy determination module 1402, control and measurement module 1403, initial thickness determination module 1404 and wafer grinding module 1405 are respectively coupled to at least one processor, and the corresponding operations are performed by at least one processor.

[0207] The specific implementation of each module of the wafer thinning device 1400 in this embodiment can be referred to the corresponding content of S101~S105 in the wafer thinning method of the above embodiment, and will not be repeated in this embodiment.

[0208] In this application embodiment, the processor may be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Correspondingly, the processor described in this application embodiment can also work with other devices to execute the operations corresponding to the "acquisition module 1401, strategy determination module 1402, control and measurement module 1403, initial thickness determination module 1404, and wafer grinding module 1405". Other components include, but are not limited to, a memory, a communication interface, and a communication bus. The processor, memory, and communication interface communicate with each other via the communication bus. The memory stores at least one executable instruction, which causes the processor to perform the operations corresponding to the "acquisition module 1401, strategy determination module 1402, control and measurement module 1403, initial thickness determination module 1404, and wafer grinding module 1405". The memory may include read-only memory and random access memory, and provides instructions and data to the processor.

[0209] In one embodiment of this application, a wafer thickness measurement method is also provided, which may include the above-described steps S101 to S104, as well as the detailed implementation of steps S101 to S104.

[0210] Accordingly, in one embodiment of this application, a wafer thickness measuring device is also provided, which may include the above-mentioned acquisition module 1401, strategy determination module 1402, control and measurement module 1403 and initial thickness determination module 1404.

[0211] In one embodiment of this application, a wafer thickness measurement system is also provided. The wafer thickness measurement system in this embodiment may include... Figure 1 The contact thickness measuring device 13, the non-contact thickness measuring device 14, and the controller are included. Figure 1 (not shown in the image), wherein the controller is used to perform the steps of the above wafer thickness measurement method.

[0212] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to complete the process. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0213] The computer-readable storage medium can be an internal storage unit of the wafer thinning apparatus in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be an external storage device of the wafer thinning apparatus, such as a pluggable hard disk, a smart media card (SMC), a secure digital card (SD), a flash card, etc., provided with the wafer thinning apparatus.

[0214] This application provides a computer program product, which includes computer-executable instructions or a computer program stored in a computer-readable storage medium. A processor of a wafer thinning apparatus reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the wafer thinning apparatus to perform the steps of the wafer thinning method described in this application embodiment. Alternatively, a processor of a wafer thinning device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the wafer thinning device to perform the wafer thinning method described in this application embodiment.

[0215] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0216] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the wafer thinning equipment described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0217] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer thinning method, characterized in that, The method is applied to a target wafer fabricated using a die-to-wafer process, the target wafer comprising a substrate wafer and a plurality of bare chips bonded to the substrate wafer; The method includes: Obtain the geometric distribution information of the plurality of bare chips on the substrate wafer; The rotation control strategy corresponding to the target wafer is determined based on the geometric distribution information; the rotation control strategy includes: the target number of rotations of the wafer carrier stage and the target rotation angle corresponding to each rotation; The target wafer is controlled to rotate intermittently according to the rotation control strategy, and the thickness of the target wafer is measured using a contact thickness measurement device during the intervals of the intermittent rotation to obtain the measured thickness at different positions on the target wafer. The thickness of the target wafer is the overall thickness of the substrate wafer and the bare chip. The maximum value among the measured thicknesses is determined as the initial thickness of the target wafer; The bare chip on the upper surface of the target wafer is ground based on the initial thickness to reduce the thickness of the bare chip and achieve wafer thinning.

2. The wafer thinning method as described in claim 1, characterized in that, The geometric distribution information includes at least one of the following: the size of each bare chip, the distribution position of each bare chip on the substrate wafer, and the distribution density of the bare chips on the substrate wafer; The step of determining the rotation control strategy corresponding to the target wafer based on the geometric distribution information includes: Obtain the reference control strategy corresponding to the target wafer; the reference control strategy includes: the initial number of rotations of the wafer carrier stage carrying the target wafer; The initial number of rotations is adjusted using at least one of the geometric distribution information to obtain the target number of rotations; The target rotation angle is determined based on the number of target rotations and the at least one piece of information.

3. The wafer thinning method as described in claim 1, characterized in that, The intermittent rotation interval corresponds to the measurement thickness at a position of the target wafer. In each interval, the contact thickness measuring device measures the thickness of the target wafer multiple times. The thickness at each location on the target wafer was obtained in the following manner: At the corresponding rotation gap, the median of the thickness of the target wafer obtained by the contact thickness measuring device through multiple measurements is determined as the measured thickness at that position.

4. The wafer thinning method as described in claim 1, characterized in that, Also includes: Calculate the difference between the maximum and minimum values ​​of each of the measured thicknesses, and use this as the maximum difference; If the maximum difference exceeds a predetermined threshold, an alarm signal is issued, and the wafer thinning equipment is triggered to perform a shutdown operation.

5. The wafer thinning method as described in claim 1, characterized in that, The initial thickness is measured before grinding the bare chip on the upper surface of the target wafer, and is used to determine the grinding start position; the method further includes: After grinding of the bare chip on the upper surface of the target wafer begins, the thickness of the target wafer is measured using a non-contact thickness measuring device, and the thickness within the target measurement range is determined as the effective thickness measured by the non-contact thickness measuring device. The effective thickness is used for thickness monitoring during the grinding process of the target wafer.

6. The wafer thinning method as described in claim 5, characterized in that, The method for determining the target measurement range includes: If, from the start of grinding the target wafer, the ground thickness of the target wafer has not exceeded a predetermined thickness change threshold, then the target measurement range is determined based on the initial thickness and a predetermined first measurement fluctuation value. If, from the start time of grinding the target wafer, the ground thickness of the target wafer exceeds the thickness change threshold, then a target measurement range determination operation is performed. Furthermore, starting from the moment the ground thickness of the target wafer exceeds the thickness change threshold, the target measurement range determination operation is performed once every time the thickness change value of the target wafer exceeds the thickness change threshold. The target measurement range determination operation includes: The target measurement range is determined based on the real-time thickness of the target wafer and a predetermined second measurement float value.

7. The wafer thinning method as described in claim 5 or 6, characterized in that, The grinding process of the bare chip on the upper surface of the target wafer based on the initial thickness includes: Based on the initial thickness, the grinding start position is determined, and the Z-axis of the grinding device in the wafer thinning equipment is controlled to move to the grinding start position to start feeding. It is also determined whether the spindle of the grinding device is in contact with the target wafer. After determining that the spindle is in contact with the target wafer, the thickness is monitored based on the effective thickness measured by the non-contact thickness measuring device, and the bare chip on the upper surface of the target wafer is ground.

8. The wafer thinning method as described in claim 7, characterized in that, Also includes: During the grinding process, at least one of the following is collected: the real-time current of the spindle, the vibration signal of the spindle, and the acoustic emission signal at the grinding device; and the feature value corresponding to at least one signal is extracted. Based on the feature values ​​and the geometric distribution information, the subsurface damage layer depth of the current grinding area of ​​the target wafer is predicted using a pre-calibrated subsurface damage depth correlation model. If the depth of the subsurface damage layer exceeds a predetermined damage threshold, the grinding parameters corresponding to the grinding process are adjusted, or the polishing parameters of the subsequent chemical mechanical polishing process are adjusted. The subsurface damage depth correlation model is trained based on historical grinding data, which includes: real-time spindle operating parameters, geometric distribution information, and corresponding measured values ​​of subsurface damage layer depth.

9. A wafer thinning apparatus, characterized in that, include: A wafer carrier stage is used to support and rotate wafers. A grinding device is lifted and positioned above the wafer support stage. The grinding device includes a spindle, a Z-axis, and grinding wheels for grinding wafers. A controller for implementing the wafer thinning method as described in any one of claims 1-8.

10. A computer storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the wafer thinning method as described in any one of claims 1-8.

11. A computer program product, characterized in that, Includes computer instructions that instruct a computing device to perform operations corresponding to the wafer thinning method as described in any one of claims 1-8.

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