Overvoltage monitoring circuit and chip

Abstract

This disclosure provides an overvoltage monitoring circuit and chip. The overvoltage monitoring circuit is integrated into a pre-defined chip, which includes an internal reference source module and a feedback sampling module. The overvoltage monitoring circuit includes a voltage signal isolation module, a voltage boosting module, and an output voltage comparison module connected in sequence. The input terminal of the isolation module is connected to the internal reference source, and an external reference source connection terminal is provided between the output terminal and the voltage boosting module. When an external reference source is connected, the isolation module blocks the interference of the external voltage to the internal reference; the voltage boosting module boosts the external reference voltage to a first preset monitoring reference voltage; the voltage comparison module compares the reference voltage with the feedback voltage output by the feedback sampling module and outputs the overvoltage monitoring result. In this disclosure, the overvoltage monitoring circuit achieves isolation between the internal and external reference sources, and the output overvoltage monitoring reference point can follow the changes of the external reference source, enabling the chip to achieve reliable output overvoltage protection when using internal or external references.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design, and in particular to an overvoltage monitoring circuit and chip. Background Technology

[0002] Buck converter chips are widely used in electronic devices to convert higher input voltages into stable, lower output voltages. To prevent damage to the internal circuitry from excessively high input voltage and to downstream loads from excessively high output voltage, buck chips are typically equipped with input and output overvoltage monitoring circuits. Traditional output overvoltage monitoring circuits determine this by monitoring whether the voltage at the feedback pin FB exceeds a preset proportion of the internal fixed reference voltage VREF. However, when the buck chip needs to synchronize with an external high-precision reference voltage source, the internal fixed reference VREF is no longer used as a comparison reference. In this case, the traditional monitoring method fails, and it cannot generate an overvoltage protection reference point that follows changes in the external reference. Summary of the Invention

[0003] The technical problem to be solved by this disclosure is to overcome the defects of the BUCK chip in the prior art, such as the failure of output overvoltage protection when synchronizing with an external reference source. The purpose is to provide an overvoltage monitoring circuit and chip.

[0004] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0005] In a first aspect, this disclosure provides an overvoltage monitoring circuit, which is integrated into a preset chip, the preset chip including an internal reference source module and a feedback sampling module;

[0006] The overvoltage monitoring circuit includes a voltage signal isolation module, a voltage boosting module, and an output voltage comparison module that are connected in sequence.

[0007] The input terminal of the voltage signal isolation module is electrically connected to the voltage output terminal of the internal reference source module, and the feedback sampling module is electrically connected to the output voltage comparison module.

[0008] An external reference source connection is provided between the output terminal of the voltage signal isolation module and the input terminal of the voltage boost module;

[0009] When an external reference source is connected through the external reference source connection terminal, the voltage signal isolation module is used to isolate the internal reference voltage output by the internal reference source module, so as to block the interference of the external reference voltage of the external reference source to the internal reference source module.

[0010] The voltage boosting module is used to receive the external reference voltage and boost the external reference voltage to a first preset monitoring reference voltage, so as to output it to the output voltage comparison module;

[0011] The output voltage comparison module is used to receive and compare the first preset monitoring reference voltage and the feedback voltage output by the feedback sampling module, so as to output a first target monitoring result characterizing whether the feedback voltage is overvoltage.

[0012] Optionally, the voltage signal isolation module includes a first voltage buffer;

[0013] The first input terminal of the first voltage buffer is used to receive the internal reference voltage output by the internal reference source module, and the second input terminal of the first voltage buffer is electrically connected to the output terminal of the first voltage buffer.

[0014] The output terminal of the first voltage buffer is electrically connected in sequence to the external reference source connection terminal and the input terminal of the voltage boosting module.

[0015] Optionally, when only the internal reference source module provides a voltage source, the voltage signal isolation module is used to receive the internal reference voltage output by the internal reference source module, so as to output the internal reference voltage to the voltage boost module;

[0016] The voltage boosting module is used to receive the internal reference voltage and boost the internal reference voltage to a second preset monitoring reference voltage, so as to output it to the output voltage comparison module;

[0017] The output voltage comparison module is used to receive and compare the second preset monitoring reference voltage and the feedback voltage output by the feedback sampling module, so as to output a second target monitoring result characterizing whether the feedback voltage is overvoltage.

[0018] Optionally, the voltage boosting module includes a second voltage buffer, a first resistor, and a second resistor;

[0019] The first input terminal of the second voltage buffer is electrically connected to the output terminal of the voltage signal isolation module;

[0020] The second input terminal of the second voltage buffer is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, respectively.

[0021] The output terminal of the second voltage buffer is electrically connected to the first input terminal of the first resistor and the input terminal of the output voltage comparison module, respectively.

[0022] Optionally, the output voltage comparison module includes a first comparator;

[0023] The first input terminal of the first comparator is electrically connected to the output terminal of the voltage boosting module, and the second input terminal of the first comparator is electrically connected to the output terminal of the feedback sampling module.

[0024] The first preset monitoring reference voltage is received via the first input terminal of the first comparator, the feedback voltage is received via the second input terminal of the first comparator, and the output terminal of the first comparator is used to output the first target monitoring result.

[0025] or,

[0026] The second preset monitoring reference voltage is received via the first input terminal of the first comparator, and the feedback voltage is received via the second input terminal of the first comparator. The output terminal of the first comparator is used to output the second target monitoring result.

[0027] Optionally, the voltage values ​​of the first preset monitoring reference voltage and the second preset monitoring reference voltage are determined based on the resistance values ​​of the first resistor and the second resistor.

[0028] And / or,

[0029] The overvoltage monitoring circuit also includes a voltage monitoring module, which is used to acquire the voltage value of the external reference voltage.

[0030] In a second aspect, this disclosure provides a chip that includes the overvoltage monitoring circuit described in the first aspect.

[0031] Optionally, the chip includes a BUCK chip.

[0032] Optionally, the chip further includes an internal reference source module, an input voltage comparison module, a voltage feedback module, and a feedback sampling module;

[0033] The input terminal of the input voltage comparison module is electrically connected to the voltage output terminal of the internal reference source module and the input terminal of the voltage signal isolation module.

[0034] The input terminal of the voltage feedback module is electrically connected to the output terminal of the voltage signal isolation module and the output terminal of the feedback sampling module;

[0035] The input terminal of the feedback sampling module is electrically connected to the output terminal of the voltage feedback module;

[0036] The input voltage comparison module is used to receive and compare the third preset monitoring reference voltage and the internal reference voltage, so as to output a third target monitoring result that characterizes whether the internal reference voltage is overvoltage.

[0037] Optionally, the internal reference source module includes a bandgap reference unit;

[0038] The bandgap reference unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0039] The source of the first transistor and the source of the second transistor are both used to receive the power supply voltage. The gate of the first transistor is electrically connected to the gate of the second transistor, and the gate of the first transistor is electrically connected to the drain of the first transistor.

[0040] The drain of the first transistor is electrically connected to the collector of the third transistor, and the drain of the second transistor is electrically connected to the collector of the fourth transistor.

[0041] The base of the third transistor is electrically connected to the base of the fourth transistor;

[0042] The emitter of the third transistor is grounded through the third resistor and the fourth resistor in sequence;

[0043] The emitter of the fourth transistor is grounded through the fourth resistor;

[0044] The fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor are connected in series between the source of the second transistor and ground;

[0045] The node between the sixth resistor and the seventh resistor outputs the internal reference voltage;

[0046] And / or,

[0047] The feedback sampling module includes a ninth resistor and a tenth resistor;

[0048] The first end of the ninth resistor is electrically connected to the output end of the voltage feedback module, the second end of the ninth resistor is electrically connected to the first end of the tenth resistor, and the second end of the tenth resistor is grounded.

[0049] The node between the ninth resistor and the tenth resistor is used to output the feedback voltage;

[0050] And / or,

[0051] The input voltage comparison module includes an eleventh resistor, a twelfth resistor, and a second comparator;

[0052] The first input terminal of the second comparator is electrically connected to the voltage output terminal of the internal reference source module;

[0053] The second input terminal of the second comparator is electrically connected to the second terminal of the eleventh resistor and the first terminal of the twelfth resistor, respectively.

[0054] The first terminal of the eleventh resistor is used to receive external input voltage, and the second terminal of the twelfth resistor is grounded.

[0055] The output of the second comparator outputs the monitoring result of the third target.

[0056] The positive and progressive effects of this disclosure are as follows:

[0057] In this disclosure, by introducing a first voltage buffer, the internal reference source and the external reference source are isolated, so that they do not interfere with each other and the independence of input overvoltage monitoring is guaranteed. By combining the second voltage buffer and the voltage boosting circuit, the output overvoltage monitoring reference point that tracks the changes of the external reference source can be dynamically generated, so that the BUCK chip can achieve reliable output overvoltage protection whether using the internal reference or synchronizing the external reference. In addition, the circuit structure of this disclosure is simple, requiring only two voltage buffers and a small number of resistors, which is low in cost, easy to integrate, and highly practical. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of the overvoltage monitoring circuit of Embodiment 1 of this disclosure.

[0059] Figure 2 This is a circuit diagram of the overvoltage monitoring circuit of Embodiment 2 of this disclosure.

[0060] Figure 3 This is a schematic diagram of the overvoltage monitoring circuit and chip module of Embodiment 3 of this disclosure.

[0061] Figure 4 This is a circuit diagram of the overvoltage monitoring circuit and chip in Embodiment 3 of this disclosure. Detailed Implementation

[0062] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0063] Example 1

[0064] This embodiment provides an overvoltage monitoring circuit, which is integrated into a preset chip, preferably a BUCK chip.

[0065] like Figure 1 As shown, the preset chip 200 includes an internal reference source module 210 and a feedback sampling module 220. The overvoltage monitoring circuit 100 includes a voltage signal isolation module 110, a voltage boosting module 120, and an output voltage comparison module 130 connected in sequence.

[0066] The input terminal of the voltage signal isolation module 110 is electrically connected to the voltage output terminal of the internal reference source module 210, and is used to receive the internal reference voltage VREF output by the internal reference source module 210. The output terminal of the voltage signal isolation module 110 is electrically connected to the input terminal of the voltage boost module 120, and an external reference source connection terminal 140 is provided between the two.

[0067] External reference source connection terminal 140 is a dedicated pin (e.g. Figure 2 The TRK pin (in the circuit) is used to connect to an external high-precision reference voltage source when needed, to access the external reference voltage Vtrk. The external reference source connection terminal 140 is located between the output of the isolation module and the input of the lift module, enabling the entire circuit to intelligently determine the current source of the reference.

[0068] The output terminal of the feedback sampling module 220 is electrically connected to the input terminal of the output voltage comparison module 130, and is used to provide the output voltage comparison module 130 with a feedback voltage FB that reflects the preset chip output voltage state.

[0069] In this embodiment, the overvoltage monitoring circuit has two operating modes. The first is the external reference source synchronization mode, and the second is the internal reference source mode. Specifically:

[0070] In external reference source synchronization mode, the external reference source is connected through external reference source connection terminal 140. At this time, the function of voltage signal isolation module 110 is to isolate the internal reference voltage VREF output by internal reference source module 210, and at the same time block the interference of external strong source Vtrk to VREF, ensuring that other circuits inside the chip that depend on VREF are not affected.

[0071] While VREF is isolated, the voltage boost module 120 receives the external reference voltage Vtrk from the external reference connection terminal 140 and uses its internal analog signal processing circuit to precisely boost Vtrk, generating a dynamically following first preset monitoring reference voltage a*Vtrk, where a is a preset overvoltage protection proportional coefficient, and the value of a is greater than 1. According to the general design conventions of the power management chip industry, in order to protect the downstream load from damage by excessive voltage, the overvoltage protection threshold usually needs to reserve a certain safety redundancy. In this embodiment, a can be set to 120%. This reference voltage is not a fixed value, but changes in real time with the change of the external reference Vtrk, thus perfectly adapting to application scenarios where the external reference source is variable.

[0072] The first preset monitoring reference voltage is then output to the output voltage comparison module 130. The output voltage comparison module 130 is used to receive and compare the first preset monitoring reference voltage with the feedback voltage FB output by the feedback sampling module 220, and finally output a first target monitoring result that characterizes whether the feedback voltage is overvoltage.

[0073] When the feedback voltage FB is higher than the first preset monitoring reference voltage, it means that the output voltage has exceeded the safety threshold. The output voltage comparison module 130 flips its output state, the logic level changes from low to high, and generates and outputs the first target monitoring result OUT_OVP. This signal is directly used to trigger the protection action of the preset chip (such as shutting down the charging circuit).

[0074] The second mode is the internal reference source mode, where the TRK pin is floating when no external reference source is connected. In this mode, the voltage signal isolation module 110 is in the conducting state, acting as a voltage follower with high input impedance and low output impedance, transmitting the internal reference voltage VREF to the voltage boost module 120 without loss. At this time, a voltage that completely follows VREF is generated at TRK, meaning the voltage at the TRK pin is exactly equal to VREF.

[0075] Next, the voltage boost module 120 receives VREF and boosts it to a second preset monitoring reference voltage, for example, 120%*VREF, and outputs it to the output voltage comparison module 130. The output voltage comparison module 130 receives and compares the second preset monitoring reference voltage with the feedback voltage FB. When FB exceeds this fixed reference point, it outputs the second target monitoring result, triggering the same overvoltage protection mechanism.

[0076] The overvoltage monitoring circuit provided in this disclosure achieves switching and mutual isolation between the internal and external reference sources by placing a voltage signal isolation module between the internal reference source module and the external reference source connection terminal. Simultaneously, a voltage boost module dynamically generates an overvoltage protection reference point that follows changes in the external reference, ensuring reliable output overvoltage protection for the chip regardless of the reference source mode.

[0077] Example 2

[0078] This embodiment further refines the specific circuit structure and corresponding working principle of each module based on embodiment 1.

[0079] Figure 2 The circuit diagram of the overvoltage monitoring circuit of this embodiment is shown. The voltage signal isolation module 110 includes a first voltage buffer ( Figure 2 The first voltage buffer BUF is shown in the figure. Its non-inverting input (first input) is connected to the voltage output of the internal reference source module 210 to receive the internal reference voltage VREF.

[0080] The inverting input (second input) of the first voltage buffer BUF is shorted to its output to form a unity-gain buffer. Its output is connected to the external reference source connection terminal TRK, and then to the subsequent voltage boost module 120.

[0081] When an external reference source is connected to the external reference voltage Vtrk through the TRK pin, due to the high input impedance and low output impedance characteristics of the BUF, the fluctuations of the external high voltage source Vtrk are effectively isolated and cannot be reversed to its input terminal through the BUF, thereby protecting the stability of the internal reference voltage VREF.

[0082] When no external reference source is available, BUF acts as a high-drive voltage follower, copying VREF to the TRK pin.

[0083] The voltage boost module 120 includes a second voltage buffer ( Figure 2 The diagram shows BUF_OUT and the first resistor ( Figure 2 The diagram shows Rv1 and the second resistor (Rv1). Figure 2 (Rv2 is shown in the figure). The non-inverting input (first input) of the second voltage buffer BUF_OUT is connected to the external reference source connection terminal TRK to receive Vtrk or VREF voltage; its inverting input (second input) is connected to the second terminal of the first resistor Rv1 and the first terminal of the second resistor Rv2 respectively; its output is connected to the first terminal of the first resistor Rv1 and the input terminal of the output voltage comparison module 130 respectively.

[0084] This connection method constitutes a non-inverting amplifier circuit, whose voltage gain is determined by the resistor ratio, thereby generating a voltage of 120%*TRK at the output of BUF_OUT. Here, 120%*TRK means that the voltage at the TRK pin is boosted by 20%, that is, the boosted voltage value is 120% of the TRK pin voltage. 120% is a preferred ratio value, not an absolutely fixed unique value.

[0085] The boost ratio is determined by the resistance ratio of Rv2 to Rv1, i.e., the amplification factor is 1+Rv2 / Rv1. By setting the resistance ratio of Rv2 to Rv1 to 1:5, a voltage gain of 1.2 times can be obtained, thereby boosting the TRK pin voltage to 120%*TRK, which serves as the reference threshold for overvoltage monitoring.

[0086] The output voltage comparison module 130 includes a first comparator ( Figure 2 The diagram shows COMP_OUT. The inverting input of the first comparator COMP_OUT is connected to the output of the voltage boost module 120, and the non-inverting input is connected to the output of the feedback sampling module 220 to receive the feedback voltage FB. The output of the first comparator COMP_OUT directly outputs the overvoltage monitoring result signal OUT_OVP. When the feedback voltage FB exceeds the reference voltage 120%*TRK, COMP_OUT flips, and the OUT_OVP signal goes high, indicating an output overvoltage.

[0087] This embodiment employs a voltage buffer BUF as a voltage signal isolation module, achieving a high input impedance to low output impedance conversion with a minimally simplistic circuit structure, reliably blocking interference paths from the external reference voltage Vtrk to the internal precision reference source VREF. Simultaneously, another voltage buffer BUF_OUT, along with resistor networks Rv1 and Rv2, forms a voltage boosting module, capable of flexibly and accurately generating and dynamically tracking an overvoltage monitoring reference voltage of 120%*TRK. Therefore, this disclosure requires only the addition of two voltage buffers and two resistors, providing the chip with a powerful ability to adapt to both internal and external reference sources at extremely low cost and with an easily integrated structure, achieving a simplified solution for complex functions.

[0088] Example 3

[0089] Based on Embodiments 1 and 2, this embodiment provides the connection relationships between the chip's internal overvoltage monitoring circuit and other related modules, and further refines the specific circuit implementation methods of some modules.

[0090] The overvoltage monitoring circuit is integrated into a chip, preferably a BUCK chip. However, those skilled in the art will understand that the overvoltage monitoring circuit disclosed herein is also applicable to BOOST chips (boost converter chips), BUCK-BOOST chips (buck-boost converter chips), LDO chips (linear regulator chips), battery charging management chips, or other power management integrated circuits that require synchronization with an external reference source.

[0091] like Figure 3 As shown, the chip includes an internal reference source module 210, a voltage signal isolation module 110, an external reference source connection terminal 140, a voltage boost module 120, an output voltage comparison module 130, a feedback sampling module 220, an input voltage comparison module 230, and a voltage feedback module 240.

[0092] The voltage output terminal of the internal reference source module 210 is electrically connected to the input terminals of the input voltage comparison module 230 and the voltage signal isolation module 110, respectively, to provide the same internal reference voltage VREF to both. This connection method ensures that a stable and consistent reference source can be obtained for both input overvoltage monitoring and output overvoltage monitoring.

[0093] The output terminal of the voltage signal isolation module 110 is electrically connected to the external reference source connection terminal 140. The external reference source connection terminal 140 is electrically connected to the input terminals of the voltage boost module 120 and the voltage feedback module 240, respectively. The output terminal of the voltage boost module 120 is electrically connected to the input terminal of the output voltage comparison module 130, and is used to provide it with a first preset monitoring reference voltage or a second preset monitoring reference voltage.

[0094] The output terminal of the voltage feedback module 240 is electrically connected to the input terminal of the feedback sampling module 220. The output terminal of the feedback sampling module 220 is electrically connected to the input terminals of the output voltage comparison module 130 and the voltage feedback module 240, and is used to provide feedback voltage FB to the output voltage comparison module 130 and the voltage feedback module 240. The output terminal of the output voltage comparison module 130 is used to output the first target monitoring result or the second target monitoring result.

[0095] The input terminal of the input voltage comparison module 230 is electrically connected to the voltage output terminal of the internal reference source module 210, and receives the internal reference voltage VREF. The output terminal of the input voltage comparison module 230 is used to output the monitoring result of the third target. The input voltage comparison module 230 always uses the internally fixed VREF as the comparison reference and independently completes the overvoltage judgment of the input voltage, unaffected by whether an external reference source is connected.

[0096] The voltage signal isolation module 110 includes a first voltage buffer ( Figure 4 The first voltage buffer BUF is shown in the diagram. Its non-inverting input receives the internal reference voltage VREF, its inverting input is shorted to the output, and its output is connected to an external reference source. Figure 4 TRK is shown in the image.

[0097] The voltage boost module 120 includes a second voltage buffer ( Figure 4 The diagram shows BUF_OUT and the first resistor ( Figure 4 The diagram shows Rv1 and the second resistor (Rv1). Figure 4 (Rv2 is shown in the figure). The non-inverting input of the second voltage buffer BUF_OUT is connected to the TRK node; the inverting input of the second voltage buffer BUF_OUT is connected to the connection point between the second end of the first resistor Rv1 and the first end of the second resistor Rv2; the output of the second voltage buffer BUF_OUT is connected to the first end of the first resistor Rv1 and serves as the output node of the voltage boosting module 120, outputting a first preset monitoring reference voltage or a second preset monitoring reference voltage.

[0098] The output voltage comparison module 130 includes a first comparator ( Figure 4 (COMP_OUT is shown in the diagram). The inverting input of the first comparator COMP_OUT is connected to the output of the voltage boosting module 120, and the non-inverting input of the first comparator COMP_OUT is connected to the output of the feedback sampling module 220 to receive the feedback voltage FB.

[0099] The feedback sampling module 220 includes a ninth resistor ( Figure 4 The diagram shows Rfb1 and the tenth resistor ( Figure 4(Rfb2 is shown in the figure). The first terminal of the ninth resistor Rfb1 is connected to the output voltage VO, the second terminal of the ninth resistor Rfb1 is electrically connected to the first terminal of the tenth resistor Rfb2, and the second terminal of the tenth resistor Rfb2 is grounded; the node between the ninth resistor Rfb1 and the tenth resistor Rfb2 is used for the output feedback voltage FB.

[0100] The internal reference source module 210 includes a bandgap reference unit for generating a stable internal reference voltage VREF. The bandgap reference unit includes a first transistor (…). Figure 4 The diagram shows Q1 and the second transistor (Q1). Figure 4 The diagram shows Q2 and the third transistor (Q2). Figure 4 The diagram shows Q3 and the fourth transistor (Q4). Figure 4 The diagram shows Q4 and the third resistor ( Figure 4 R3 and the fourth resistor are shown in the figure. Figure 4 R4 and the fifth resistor are shown in the diagram. Figure 4 R5 and the sixth resistor are shown in the figure. Figure 4 R6 and the seventh resistor are shown in the figure. Figure 4 R7 is shown in the diagram, along with the eighth resistor (R7). Figure 4 R8 is shown in the image.

[0101] In this configuration, the source of the first transistor Q1 and the source of the second transistor Q2 are both used to receive the power supply voltage VDD. The gate of the first transistor Q1 is electrically connected to the gate of the second transistor Q2, and the gate of the first transistor Q1 is electrically connected to the drain of the first transistor Q1. The drain of the first transistor Q1 is electrically connected to the collector of the third transistor Q3, and the drain of the second transistor Q2 is electrically connected to the collector of the fourth transistor Q4. The base of the third transistor Q3 is electrically connected to the base of the fourth transistor Q4.

[0102] The emitter of the third transistor Q3 is grounded through the third resistor R3 and the fourth resistor R4 in sequence, and the emitter of the fourth transistor Q4 is grounded through the fourth resistor R4; the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are connected in series between the source of the second transistor Q2 and ground; the node between the sixth resistor R6 and the seventh resistor R7 outputs the internal reference voltage VREF.

[0103] Voltage feedback module 240 includes logic and drive circuitry ( Figure 4 The diagram shows Logic & Driver, and the upper power transistor ( Figure 4 The middle part shows MP), lower power transistor ( Figure 4 The diagram shows MN), inductance ( Figure 4 The diagram shows L) and the output capacitor ( Figure 4The diagram shows Cout. The output of the logic and driver circuit is electrically connected to the gate of the upper power transistor MP and the gate of the lower power transistor MN; the input of the logic and driver circuit also receives external control signals (…). Figure 4 The diagram shows PWM_SHOT and the external on-time control signal ( Figure 4 (TON_SHOT is shown in the image).

[0104] The source of the upper power transistor MP receives the input voltage VIN. The drain of the upper power transistor MP is electrically connected to the drain of the lower power transistor MN, and the source of the lower power transistor MN is grounded. The node between the drain of the upper power transistor MP and the drain of the lower power transistor MN is electrically connected to the first end of the inductor L, and the second end of the inductor L is connected to the output voltage VO. The output capacitor Cout is connected between the output voltage VO and ground.

[0105] The input voltage comparison module 230 includes an eleventh resistor ( Figure 4 The diagram shows Ri2 and the twelfth resistor ( Figure 4 The diagram shows Ri1 and the second comparator (Ri1). Figure 4 The diagram shows COMP_VIN. The first terminal of the eleventh resistor Ri2 is used to receive the external input voltage VIN. The second terminal of the eleventh resistor Ri2 is electrically connected to the first terminal of the twelfth resistor Ri1, and the second terminal of the twelfth resistor Ri1 is grounded. The inverting input terminal of the second comparator COMP_VIN is electrically connected to the internal reference voltage VREF. The non-inverting input terminal of the second comparator COMP_VIN is electrically connected to the second terminal of the eleventh resistor Ri2 and the first terminal of the twelfth resistor Ri1. The output terminal of the second comparator COMP_VIN outputs the third target monitoring result VIN_OVP.

[0106] The specific working principles of the above-mentioned bandgap reference unit, voltage feedback module, and input voltage comparison module are clear to those skilled in the art and will not be elaborated further.

[0107] The overvoltage monitoring circuit and chip disclosed herein achieve physical isolation and seamless switching between the internal and external reference sources by introducing a voltage buffer as a voltage signal isolation module between the internal and external reference sources. This ensures that input overvoltage monitoring and output overvoltage monitoring each use independent and appropriate reference sources without interference. Simultaneously, the voltage boosting module, composed of the voltage buffer and resistor network, dynamically generates an output overvoltage protection reference point that follows changes in the external reference voltage. This ensures reliable output overvoltage protection regardless of whether the chip uses an internal fixed reference source or a synchronous external variable reference source.

[0108] The entire circuit structure requires only two voltage buffers and a small number of resistors, resulting in extremely low cost, ease of integration, and a balance between functional completeness and design simplicity. Therefore, this disclosure solves the industry problem of complete failure of output overvoltage protection in traditional BUCK chips when synchronizing with an external reference source, providing power management chips with an overvoltage protection solution that combines high reliability, strong adaptability, and low cost.

[0109] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. An overvoltage monitoring circuit, characterized in that, The overvoltage monitoring circuit is integrated into a preset chip, which includes an internal reference source module and a feedback sampling module. The overvoltage monitoring circuit includes a voltage signal isolation module, a voltage boosting module, and an output voltage comparison module that are connected in sequence. The input terminal of the voltage signal isolation module is electrically connected to the voltage output terminal of the internal reference source module, and the feedback sampling module is electrically connected to the output voltage comparison module. An external reference source connection is provided between the output terminal of the voltage signal isolation module and the input terminal of the voltage boost module; When an external reference source is connected through the external reference source connection terminal, the voltage signal isolation module is used to isolate the internal reference voltage output by the internal reference source module, so as to block the interference of the external reference voltage of the external reference source to the internal reference source module. The voltage boosting module is used to receive the external reference voltage and boost the external reference voltage to a first preset monitoring reference voltage, so as to output it to the output voltage comparison module; The output voltage comparison module is used to receive and compare the first preset monitoring reference voltage and the feedback voltage output by the feedback sampling module, so as to output a first target monitoring result characterizing whether the feedback voltage is overvoltage.

2. The overvoltage monitoring circuit as described in claim 1, characterized in that, The voltage signal isolation module includes a first voltage buffer; The first input terminal of the first voltage buffer is used to receive the internal reference voltage output by the internal reference source module, and the second input terminal of the first voltage buffer is electrically connected to the output terminal of the first voltage buffer. The output terminal of the first voltage buffer is electrically connected in sequence to the external reference source connection terminal and the input terminal of the voltage boosting module.

3. The overvoltage monitoring circuit as described in claim 2, characterized in that, When only the internal reference source module provides the voltage source, the voltage signal isolation module is used to receive the internal reference voltage output by the internal reference source module, and output the internal reference voltage to the voltage boost module; The voltage boosting module is used to receive the internal reference voltage and boost the internal reference voltage to a second preset monitoring reference voltage, so as to output it to the output voltage comparison module; The output voltage comparison module is used to receive and compare the second preset monitoring reference voltage and the feedback voltage output by the feedback sampling module, so as to output a second target monitoring result characterizing whether the feedback voltage is overvoltage.

4. The overvoltage monitoring circuit as described in claim 3, characterized in that, The voltage boost module includes a second voltage buffer, a first resistor, and a second resistor; The first input terminal of the second voltage buffer is electrically connected to the output terminal of the voltage signal isolation module; The second input terminal of the second voltage buffer is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, respectively. The output terminal of the second voltage buffer is electrically connected to the first input terminal of the first resistor and the input terminal of the output voltage comparison module, respectively.

5. The overvoltage monitoring circuit as described in claim 4, characterized in that, The output voltage comparison module includes a first comparator; The first input terminal of the first comparator is electrically connected to the output terminal of the voltage boosting module, and the second input terminal of the first comparator is electrically connected to the output terminal of the feedback sampling module. The first preset monitoring reference voltage is received via the first input terminal of the first comparator, the feedback voltage is received via the second input terminal of the first comparator, and the output terminal of the first comparator is used to output the first target monitoring result. or, The second preset monitoring reference voltage is received via the first input terminal of the first comparator, and the feedback voltage is received via the second input terminal of the first comparator. The output terminal of the first comparator is used to output the second target monitoring result.

6. The overvoltage monitoring circuit as described in claim 5, characterized in that, The voltage values ​​of the first preset monitoring reference voltage and the second preset monitoring reference voltage are determined based on the resistance values ​​of the first resistor and the second resistor. And / or, The overvoltage monitoring circuit also includes a voltage monitoring module, which is used to acquire the voltage value of the external reference voltage.

7. A chip, characterized in that, The chip includes an overvoltage monitoring circuit as described in any one of claims 1-6.

8. The chip as described in claim 7, characterized in that, The chip includes a BUCK chip.

9. The chip as described in claim 8, characterized in that, The chip also includes an internal reference source module, an input voltage comparison module, a voltage feedback module, and a feedback sampling module; The input terminal of the input voltage comparison module is electrically connected to the voltage output terminal of the internal reference source module and the input terminal of the voltage signal isolation module. The input terminal of the voltage feedback module is electrically connected to the output terminal of the voltage signal isolation module and the output terminal of the feedback sampling module; The input terminal of the feedback sampling module is electrically connected to the output terminal of the voltage feedback module; The input voltage comparison module is used to receive and compare the third preset monitoring reference voltage and the internal reference voltage, so as to output a third target monitoring result that characterizes whether the internal reference voltage is overvoltage.

10. The chip as described in claim 9, characterized in that, The internal reference source module includes a bandgap reference unit; The bandgap reference unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The source of the first transistor and the source of the second transistor are both used to receive the power supply voltage. The gate of the first transistor is electrically connected to the gate of the second transistor, and the gate of the first transistor is electrically connected to the drain of the first transistor. The drain of the first transistor is electrically connected to the collector of the third transistor, and the drain of the second transistor is electrically connected to the collector of the fourth transistor. The base of the third transistor is electrically connected to the base of the fourth transistor; The emitter of the third transistor is grounded through the third resistor and the fourth resistor in sequence; The emitter of the fourth transistor is grounded through the fourth resistor; The fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor are connected in series between the source of the second transistor and ground; The node between the sixth resistor and the seventh resistor outputs the internal reference voltage; And / or, The feedback sampling module includes a ninth resistor and a tenth resistor; The first end of the ninth resistor is electrically connected to the output end of the voltage feedback module, the second end of the ninth resistor is electrically connected to the first end of the tenth resistor, and the second end of the tenth resistor is grounded. The node between the ninth resistor and the tenth resistor is used to output the feedback voltage; And / or, The input voltage comparison module includes an eleventh resistor, a twelfth resistor, and a second comparator; The first input terminal of the second comparator is electrically connected to the voltage output terminal of the internal reference source module; The second input terminal of the second comparator is electrically connected to the second terminal of the eleventh resistor and the first terminal of the twelfth resistor, respectively. The first terminal of the eleventh resistor is used to receive external input voltage, and the second terminal of the twelfth resistor is grounded. The output of the second comparator outputs the monitoring result of the third target.

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