Test circuit, method, computer device and storage medium of charger

Abstract

The application relates to a test circuit, a method, computer equipment and a storage medium of a charger. The test circuit can realize output deception holding of a PD3.0 charging protocol charger to be tested by introducing a voltage stabilizer component, a voltage division resistance network and a standardized connection component, provides low-cost auxiliary test equipment for engineers in the related field, and in addition, in an EMC test scene of product authentication, the deception holding scheme of the application can avoid EMC radiation introduction caused by other deception holding schemes (such as a protocol analyzer), and the influence of interference sources is reduced.

Description

Technical Field

[0001] This invention relates to the field of testing equipment, and in particular to a test circuit, method, computer device, and storage medium for a charger. Background Technology

[0002] With the widespread adoption of Type-C interfaces in electronic products, more and more companies are launching chargers that comply with the PD3.0 charging protocol. The PD3.0 charging protocol, developed by the USB-IF Association, is a charging protocol standard for USB Type-C ports and is one of the mainstream fast charging protocols currently used in the power supply of various devices. As car chargers, power adapters, and other charger products continue to iterate and upgrade, the inventors discovered that traditional testing methods suffer from low efficiency and high costs. Summary of the Invention

[0003] Therefore, it is necessary to provide a low-cost and high-efficiency test circuit, method, computer equipment, and storage medium for a charger.

[0004] To achieve the above objectives, in one aspect, embodiments of this application provide a test circuit for a charger, comprising:

[0005] A connection component includes a first interface for connecting a charger and a second interface for connecting a test load; the first interface and the second interface are connected.

[0006] Voltage regulator assembly;

[0007] A voltage divider resistor network; wherein, the first end of the voltage divider resistor network is connected to the output end of the voltage regulator component, the second end is connected to the first communication pin of the first interface and the first communication pin of the second interface respectively, and the third end is grounded.

[0008] In one embodiment, the voltage divider resistor network includes a first resistor and a second resistor;

[0009] The first end of the first resistor is connected to the output end of the voltage regulator assembly, and the second end is connected to the first communication pin of the first interface, the first communication pin of the second interface, and the first end of the second resistor, respectively; the second end of the second resistor is grounded.

[0010] In one embodiment, the voltage divider resistor network further includes a third resistor and a fourth resistor;

[0011] The first end of the third resistor is connected to the output of the voltage regulator assembly, and the second end is connected to the second communication pin of the second interface and the first end of the fourth resistor, respectively; the second end of the fourth resistor is grounded.

[0012] In one embodiment, an interface electrostatic discharge (ESD) protection circuit is also included;

[0013] The interface electrostatic discharge protection circuit includes a first ESD transistor, a second ESD transistor, a third ESD transistor, and a fourth ESD transistor;

[0014] One end of the first ESD transistor is connected to the first communication pin of the first interface and the first communication pin of the second interface, and the other end is grounded; one end of the second ESD transistor is connected to the second communication pin of the second interface, and the other end is grounded; one end of the third ESD transistor is connected to the first data transmission pin of the first interface and the first data transmission pin of the second interface, and the other end is grounded; one end of the fourth ESD transistor is connected to the second data transmission pin of the first interface and the second data transmission pin of the second interface, and the other end is grounded.

[0015] In one embodiment, an anti-static circuit for the housing is also included;

[0016] The anti-static circuit of the casing includes a first capacitor and a fifth resistor; one end of the first capacitor is connected to one end of the fifth resistor and ground, and the other end is connected to the other end of the fifth resistor and the casing of the connecting component.

[0017] In one embodiment, the voltage regulator assembly includes a voltage regulator chip, a first filter capacitor, and a second filter capacitor;

[0018] The first terminal of the voltage regulator chip is grounded, the second terminal is connected to one end of the first filter capacitor, the first interface and the second interface respectively, and the output terminal is connected to one end of the second filter capacitor and the first terminal of the voltage divider resistor network respectively; the other end of the first filter capacitor is grounded; the other end of the second filter capacitor is grounded.

[0019] In one embodiment, the test load includes a protocol tester and / or a resistive load.

[0020] On one hand, embodiments of the present invention also provide a testing method for a charger, applied to the test circuit of the aforementioned charger, wherein the test load includes a protocol tester and / or a resistive load; the method includes:

[0021] The first interface of the test circuit is connected to the charger so that an effective voltage is formed on the first communication pin of the first interface; wherein, the power chip of the charger that detects the effective voltage performs a voltage output action.

[0022] Connect the second interface of the test circuit to the protocol tester, and use the protocol tester to set the output voltage of the charger.

[0023] Remove the protocol tester and connect the resistive load to the second interface.

[0024] On the one hand, embodiments of this application also provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and a computer-readable storage medium stores a computer program, wherein the computer program is configured to perform the steps of the above-described method when it is run.

[0025] On the other hand, embodiments of the present invention also provide a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0026] One of the above technical solutions has the following advantages and beneficial effects:

[0027] The aforementioned test circuit, by introducing a voltage regulator component, a voltage divider resistor network, and standardized connection components, can achieve output decoy hold for the PD3.0 charging protocol charger under test at a lower cost, providing engineers in related fields with low-cost auxiliary test equipment. In addition, in EMC testing scenarios for product certification, using the decoy hold scheme of this invention can minimize the introduction of EMC radiation caused by other decoy hold schemes (such as protocol analyzers), reducing the impact of interference sources. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0030] Figure 1 This is a first schematic circuit diagram of a test circuit for a charger in one embodiment;

[0031] Figure 2 This is a schematic circuit diagram of a voltage divider resistor network in one embodiment;

[0032] Figure 3 This is a schematic circuit diagram of the anti-static circuit for the housing in one embodiment;

[0033] Figure 4 This is a schematic circuit diagram of a voltage regulator assembly in one embodiment;

[0034] Figure 5 This is a schematic flowchart of a charger testing method in one embodiment;

[0035] Figure 6This is a second schematic circuit diagram of the test circuit for the charger in one embodiment;

[0036] Figure 7 This is a test equipment connection diagram for a test method that applies a charger in one embodiment. Detailed Implementation

[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0039] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module" and "part" may be used interchangeably.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0041] In one embodiment, such as Figure 1 As shown, a test circuit for a charger is provided, including:

[0042] The connection component includes a first interface 101 for connecting a charger and a second interface 102 for connecting a test load; the first interface 101 and the second interface 102 are connected.

[0043] Voltage regulator assembly 20;

[0044] Voltage divider resistor network 30; wherein, the first end of the voltage divider resistor network 30 is connected to the output end of the voltage regulator assembly 20, the second end is connected to the first communication pin 1011 of the first interface 101 and the first communication pin 1021 of the second interface 102 respectively, and the third end is grounded.

[0045] The connection components are plug-in ports, such as a USB Type-C interface, specifically male or female connectors. The input / output direction can be flexibly configured depending on the charger and load interfaces. The first interface is for connecting the charger and typically includes power pins and communication pins. The power pins transmit electrical energy, while the first communication pin is mainly used to transmit control signals or data. The second interface is for connecting the test load, with a similar structure to the first interface, also including power pins and a first communication pin. The voltage regulator component can be any device in the art capable of providing a stable voltage output, ensuring the voltage divider network operates under stable voltage conditions. The voltage divider network can be any circuit structure in the art capable of providing a specific voltage to the first communication pin when the charger is connected. The test load includes a protocol tester and / or a resistive load.

[0046] Specifically, the first and second interfaces are connected, primarily through the connection of their various pins, such as power pins, communication pins, and other data transmission pins. When the charger is connected to the first interface and the test load is connected to the second interface, electrical energy can be transferred from the charger to the test load through the connection components. Simultaneously, the communication pins allow signal exchange between the charger and the test load, or between other parts of the system. A voltage divider resistor network uses series and parallel resistors to distribute voltage. According to Ohm's law, voltage is distributed between resistors such that the voltage drop across each resistor is proportional to its resistance value. By selecting appropriate resistor values, the desired output voltage can be obtained. In a specific example, the voltage divider resistor network may include a voltage divider resistor Rd, which pulls down the voltage of the first communication pin. This, together with the pull-up resistor Rp within the charger's built-in protocol chip, forms an Rp / Rd voltage divider resistor network, providing a specific level to the first communication pin so that the protocol chip recognizes the inserted valid load, thereby achieving decoy hold. One end of the voltage divider resistor Rd is connected to the output of the voltage regulator component and the first communication pin, while the other end is grounded.

[0047] The aforementioned test circuit, by introducing a voltage regulator component, a voltage divider resistor network, and standardized connection components, can achieve output decoy hold for the PD3.0 charging protocol charger under test at a lower cost, providing engineers in related fields with low-cost auxiliary test equipment. In addition, in EMC testing scenarios for product certification, using the decoy hold scheme of this invention can minimize the introduction of EMC radiation caused by other decoy hold schemes (such as protocol analyzers), reducing the impact of interference sources.

[0048] In one embodiment, such as Figure 2 As shown, the voltage divider resistor network includes a first resistor R1 and a second resistor R2;

[0049] The first end of the first resistor R1 is connected to the output end of the voltage regulator assembly 20, and the second end is connected to the first communication pin CC1 of the first interface 101, the first communication pin CC1 of the second interface 102, and the first end of the second resistor R4; the second end of the second resistor R2 is grounded.

[0050] Specifically, the output level of the voltage regulator component 20 can be represented by V_Pull. By pulling it up to V_Pull through the first resistor R1, it can provide a PD3.0 protocol-induced pull-up for some chargers that do not have a built-in protocol IC for pull-up.

[0051] In one embodiment, such as Figure 2 As shown, the voltage divider resistor network also includes a third resistor R3 and a fourth resistor R4;

[0052] The first end of the third resistor R3 is connected to the output end of the voltage regulator assembly 20, and the second end is connected to the second communication pin CC2 of the second interface 102 and the first end of the fourth resistor R4 respectively; the second end of the fourth resistor R4 is grounded.

[0053] Specifically, after voltage division by the third and fourth resistors, the voltage is connected to the CC2 pin of the second interface, which can reserve configuration positions for other configuration decoy functions.

[0054] In one embodiment, an interface electrostatic discharge (ESD) protection circuit is also included;

[0055] The interface electrostatic discharge protection circuit includes a first ESD transistor, a second ESD transistor, a third ESD transistor, and a fourth ESD transistor;

[0056] One end of the first ESD transistor is connected to the first communication pin of the first interface and the first communication pin of the second interface, and the other end is grounded; one end of the second ESD transistor is connected to the second communication pin of the second interface, and the other end is grounded; one end of the third ESD transistor is connected to the first data transmission pin of the first interface and the first data transmission pin of the second interface, and the other end is grounded; one end of the fourth ESD transistor is connected to the second data transmission pin of the first interface and the second data transmission pin of the second interface, and the other end is grounded.

[0057] The aforementioned ESD tube provides electrostatic protection for the connection components, preventing externally introduced static electricity from damaging the circuitry, charger, load, etc.

[0058] In one embodiment, such as Figure 3 As shown, it also includes an anti-static circuit for the outer casing;

[0059] The anti-static circuit of the casing includes a first capacitor C1 and a fifth resistor R5; one end of the first capacitor C1 is connected to one end of the fifth resistor R5 and ground, and the other end is connected to the other end of the fifth resistor R5 and the casing Earth of the connecting component.

[0060] The first capacitor C1 and the fifth resistor R5 are connected in parallel to the housing of the connecting component and the signal ground GND of this scheme. This eliminates the noise of the housing and avoids affecting the signal ground. At the same time, it forces the signal current on the circuit board to flow into the internal signal ground, rather than to the housing and shielding layer of the connecting component, while maintaining the continuity of the shielding layer of the data line.

[0061] In one embodiment, such as Figure 4 As shown, the voltage regulator assembly includes a voltage regulator chip U1, a first filter capacitor C2, and a second filter capacitor C3.

[0062] The first terminal of the voltage regulator chip U1 is grounded, and the second terminal is connected to one end of the first filter capacitor C2, the first interface 101 and the second interface 102 respectively. The output terminal is connected to one end of the second filter capacitor C2 and the first terminal of the voltage divider resistor network 30 respectively. The other end of the first filter capacitor C2 is grounded, and the other end of the second filter capacitor C3 is grounded.

[0063] Specifically, the second terminal of the voltage regulator chip U1 is connected to the power pin of the first interface and the power pin of the second interface, respectively.

[0064] In one embodiment, such as Figure 5 As shown, a test method for a charger is also provided, applied to the test circuit of the aforementioned charger, wherein the test load includes a protocol tester and / or a resistive load; the method includes:

[0065] S10, connect the first interface of the test circuit to the charger so that an effective voltage is formed on the first communication pin of the first interface; wherein, the power chip of the charger that detects the effective voltage performs a voltage output action.

[0066] S20, connect the second interface of the test circuit to the protocol tester, and use the protocol tester to complete the setting operation of the charger's output voltage;

[0067] S30, remove the protocol tester and connect the resistive load to the second interface.

[0068] Specifically, the first interface of the test circuit is connected to the charger. This can be done by connecting the Type-C male connector in the test circuit to the Type-C female connector in the charger. The pull-down resistor in the test circuit and the pull-up resistor inside the PD3.0 protocol chip on the charger together form a voltage divider network, thereby forming an effective voltage on the first communication pin.

[0069] When the charger's DFP (Downstream Facing Port) detects that the level Vcc1 on the first communication pin CC1 is within the valid range, it recognizes that a UFP (Upstream Facing Port) has been inserted. Subsequently, the charger's protocol chip notifies the charger's power chip to turn on the Type-C_VBUS output voltage Vsafe5V to prepare for the subsequent PD3.0 protocol authentication handshake and negotiation.

[0070] After the Type-C_VBUS output of the charger is turned on, connect a dedicated protocol tester to the second interface, such as the Type-C female connector. Use the protocol tester to perform a protocol handshake setting on the charger output in order to trick the voltage of the power transmission object that needs to be tested.

[0071] After setting the charger's output voltage, remove the protocol tester. At this point, the decoy holding scheme maintains the corresponding PD3.0 protocol output, keeps the connection active, and prevents the charger's protocol chip from resetting the PD3.0 protocol, thereby achieving continuous maintenance of the protocol output.

[0072] To better understand the test circuit and test method of this application, a practical example is provided below for further explanation. Please refer to [link / reference]. Figure 6 ;

[0073] The test circuit includes input / output connectors (i.e., the first and second interfaces mentioned above) USB1 and USB2; voltage regulator chip U1; first filter capacitor C2 and second filter capacitor C3; electrostatic discharge and high-frequency bypass filter capacitor (i.e., the first capacitor mentioned above) C1; pull-up and pull-down resistors R1, R2, R3, and R4 for the CC1 and CC2 protocol communication pins; interface electrostatic discharge protection ESD transistors (i.e., the first, second, third, and fourth ESD transistors mentioned above) G1, G2, G3, and G4; and an anti-static resistor R5 for the casing.

[0074] USB1 and USB2 are Type-C male and female connectors for connecting the charger and the test load. They are used to connect in series between the charger and the test load. The male and female connectors can be flexibly configured to allow for different input / output directions depending on the charger and load interfaces. U1 is a linear regulator IC that provides a regulated pull-up voltage for the CC1 and CC2 protocol communication pins. Pin 1 of U1 is grounded (GND). Pin 2 of U1 is connected to the A4 / A9 / B4 / B9 pins of USB1 and USB2 to the Type-C_VBUS, and C1 is connected in parallel to ground (GND). Pin 3 of U1 is the output pin, connected in parallel to C2 to ground (GND). After linear regulation by pin 3 of U1, the V_Pull voltage is obtained, which is usually +3.3V.

[0075] Pin A5 of USB1 is connected to pin A5 of USB2, with resistor R2 connected in parallel to ground. R2 is typically 5.1KΩ. This pulls down the CC1 configuration pin of the charger connected to the decoy holding board. Together with the Rp resistor (pull-up) within the charger's built-in protocol IC, this forms an Rp / Rd voltage divider network, providing a specific voltage level for CC1 to identify the valid load insertion by the protocol IC. The R1 pull-up resistor is connected to the V_Pull level and then to the CC1 pin, providing a decoy pull-up for the PD3.0 protocol for chargers without a built-in protocol IC pull-up. The voltage divider network formed by resistors R3 and R4 is connected to the CC2 network on pin B5 of USB2, reserving configuration space for other decoy configuration functions.

[0076] G1, G2, G3, and G4 are ESD protection transistors connected to the pins of the CC1, CC2, Type-C_DP, and Type-C_DM networks of USB1 and USB2, providing ESD protection for the USB1 and USB2 connectors and preventing damage to the circuitry, charger, and load from externally introduced static electricity. The parallel connection of C1 and R5 connects the casings of USB1 and USB2 to the signal ground (GND) of this solution, eliminating casing noise to avoid affecting the signal ground. This also forces the signal current on the board to flow into the internal signal ground, rather than to the USB casing and shielding layer, while maintaining the continuity of the data cable shielding.

[0077] The working principle of the above circuit is as follows: The USB PD3.0 charging protocol uses the CC (Configuration channel) pin of the USB Type-C interface as a data transmission channel to negotiate the charging voltage, current, and power transmission direction between the charger DFP and the powered device UFP. The CC signal pin has two lines, CC1 and CC2. The DFP can determine whether a device has been inserted based on the voltage on the two CC lines.

[0078] When the USB1 Type-C male connector of the decoy hold solution is connected to the charger's output Type-C female connector, the CC1 pull-down resistor Rd and the pull-up resistor Rp inside the charger's PD3.0 protocol-supporting chip, which is connected to Type-C_VBUS, form a voltage divider network Rp / Rd, creating an effective voltage Vcc1 on the CC1 pin. At this time, the charger's DFP detects that the level Vcc1 on the CC1 pin is within the effective range, recognizing that a powered device UFP has been inserted. The charger's protocol chip instructs the charger's power chip to turn on the Type-C_VBUS output voltage Vsafe5V, preparing for the next step of PD3.0 protocol authentication handshake and negotiation. This allows the charger and device to assess the charger's charging capabilities and the charging power supported by the device.

[0079] After enabling the charger's Type-C VBUS output, connect a dedicated protocol tester to the USB2 Type-C female connector. Use the tester to perform a protocol handshake on the charger's output, tricking the user into revealing the required PDO voltage. Once the charger's output voltage is set, remove the tester. The trick-and-hold mechanism will then maintain the corresponding PD3.0 protocol output, ensuring a valid connection and preventing the charger's protocol chip from resetting the PD3.0 protocol, thus maintaining the protocol output. The connection diagram is shown below. Figure 7 As shown.

[0080] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0081] The first interface of the test circuit is connected to the charger so that an effective voltage is formed on the first communication pin of the first interface; wherein, the power chip of the charger that detects the effective voltage performs a voltage output action.

[0082] Connect the second interface of the test circuit to the protocol tester, and use the protocol tester to set the output voltage of the charger.

[0083] Remove the protocol tester and connect the resistive load to the second interface.

[0084] In one embodiment, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps.

[0085] The first interface of the test circuit is connected to the charger so that an effective voltage is formed on the first communication pin of the first interface; wherein, the power chip of the charger that detects the effective voltage performs a voltage output action.

[0086] Connect the second interface of the test circuit to the protocol tester, and use the protocol tester to set the output voltage of the charger.

[0087] Remove the protocol tester and connect the resistive load to the second interface.

[0088] In specific implementation, the embodiments of this application can be referred to the above embodiments, and have corresponding technical effects.

[0089] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0090] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0093] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0094] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0095] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0096] If the aforementioned function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks. It should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0097] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A test circuit for a charger, characterized in that, include: A connection component includes a first interface for connecting a charger and a second interface for connecting a test load; the first interface and the second interface are connected. Voltage regulator assembly; A voltage divider resistor network; wherein, the first end of the voltage divider resistor network is connected to the output end of the voltage regulator assembly, the second end is connected to the first communication pin of the first interface and the first communication pin of the second interface respectively, and the third end is grounded.

2. The test circuit for the charger according to claim 1, characterized in that, The voltage divider resistor network includes a first resistor and a second resistor; The first end of the first resistor is connected to the output end of the voltage regulator assembly, and the second end is connected to the first communication pin of the first interface, the first communication pin of the second interface, and the first end of the second resistor, respectively; the second end of the second resistor is grounded.

3. The test circuit for the charger according to claim 2, characterized in that, The voltage divider resistor network also includes a third resistor and a fourth resistor; The first end of the third resistor is connected to the output end of the voltage regulator assembly, and the second end is connected to the second communication pin of the second interface and the first end of the fourth resistor respectively; the second end of the fourth resistor is grounded.

4. The test circuit for the charger according to claim 1, characterized in that, It also includes interface electrostatic discharge protection circuitry; The interface electrostatic discharge protection circuit includes a first ESD transistor, a second ESD transistor, a third ESD transistor, and a fourth ESD transistor. One end of the first ESD transistor is connected to the first communication pin of the first interface and the first communication pin of the second interface, and the other end is grounded; one end of the second ESD transistor is connected to the second communication pin of the second interface, and the other end is grounded; one end of the third ESD transistor is connected to the first data transmission pin of the first interface and the first data transmission pin of the second interface, and the other end is grounded; one end of the fourth ESD transistor is connected to the second data transmission pin of the first interface and the second data transmission pin of the second interface, and the other end is grounded.

5. The test circuit for the charger according to claim 1, characterized in that, It also includes an anti-static circuit for the casing; The anti-static circuit of the casing includes a first capacitor and a fifth resistor; one end of the first capacitor is connected to one end of the fifth resistor and ground, and the other end is connected to the other end of the fifth resistor and the casing of the connecting assembly.

6. The test circuit for the charger according to claim 1, characterized in that, The voltage regulator assembly includes a voltage regulator chip, a first filter capacitor, and a second filter capacitor; The first terminal of the voltage regulator chip is grounded, the second terminal is connected to one end of the first filter capacitor, the first interface and the second interface respectively, and the output terminal is connected to one end of the second filter capacitor and the first terminal of the voltage divider resistor network respectively; the other end of the first filter capacitor is grounded; the other end of the second filter capacitor is grounded.

7. The test circuit for the charger according to claim 1, characterized in that, The test load includes a protocol tester and / or a resistive load.

8. The test method for the charger according to claim 1, characterized in that, A test circuit applied to a charger as described in any one of claims 1-7, wherein the test load includes a protocol tester and / or a resistive load; the method includes: The first interface of the test circuit is connected to the charger so that an effective voltage is formed on the first communication pin of the first interface; wherein, the power chip of the charger that detects the effective voltage performs a voltage output operation. Connect the second interface of the test circuit to the protocol tester, and use the protocol tester to set the output voltage of the charger. Remove the protocol tester and connect the resistive load to the second interface.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program is configured to perform the steps of the method of claim 8 when executed.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 8.

Images