A method for testing IGBT latching

Abstract

The application discloses an IGBT latch test method. The IGBT latch test circuit comprises: a control circuit outputting a first driving signal, and a to-be-tested IGBT being turned on or turned off according to the first driving signal. The control circuit outputs a second driving signal to a test current generating module, and the test current generating module generates a test current to a first end of the to-be-tested IGBT according to the second driving signal. The control circuit outputs a third driving signal to a switch module; a power supply end of the switch module is connected to a second power supply voltage, the switch module is connected to the to-be-tested IGBT, and the switch module is turned on or turned off according to the third driving signal, and the second power supply voltage is communicated with the first end of the to-be-tested IGBT when the switch module is turned on. A first current sampling module samples a current of the to-be-tested IGBT and outputs a first current sampling signal to the control circuit. The control circuit determines whether the to-be-tested IGBT is latched according to the first current sampling signal. The technical scheme of the application improves the reliability of the latch test circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and in particular to an IGBT latch-up testing method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), power semiconductor devices, possess numerous superior properties such as high input impedance, fast switching speed, low on-state voltage drop, and strong current carrying capacity. They are currently widely used in power electronics fields such as new energy power generation, industrial frequency conversion, home appliance electronic control, and high-power switching power supplies. The operational stability and reliability of IGBTs determine the operational safety and lifespan of the entire power electronic equipment system.

[0003] However, IGBT devices contain parasitic transistor structures, which are highly susceptible to latch-up. Once latch-up occurs, the device will be in an uncontrolled conduction state, unable to be turned off by the gate signal, ultimately leading to overpower burnout, breakdown failure, and other malfunctions. For example, if the current is too high when the IGBT is conducting, the internal PNP transistor may be activated, triggering the parasitic thyristor. Excessively high collector-emitter voltage in the IGBT can cause avalanche breakdown of the internal PNP transistor, triggering the parasitic thyristor to conduct. Rapid current changes can also trigger parasitic transistors within the IGBT. High temperatures can also lower the on-state voltage of parasitic transistors, making them easier to trigger.

[0004] However, existing IGBT latch-up testing technologies have poor controllability and reliability. Summary of the Invention

[0005] This invention provides an IGBT latch-up test method to make the test current controllable and improve the reliability of the IGBT latch-up test circuit.

[0006] According to one aspect of the present invention, an IGBT latch-up test circuit is provided. The IGBT latch-up test circuit provided in the embodiment of the present invention includes a control circuit, a test current generation module, a switching module, and a first current sampling module. The first output terminal of the control circuit is connected to the control terminal of the IGBT under test and is used to output the first drive signal. The IGBT under test is turned on or off according to the first drive signal. The second output terminal of the control circuit is connected to the control terminal of the test current generation module, and is used to output a second drive signal to the test current generation module. The power supply terminal of the test current generation module is connected to the first power supply voltage. The test current generation module is connected to the IGBT under test. The test current generation module is used to generate a test current to the first terminal of the IGBT under test according to the second drive signal. The third output terminal of the control circuit is connected to the control terminal of the switching module and is used to output a third drive signal to the switching module. The power supply terminal of the switching module is connected to the second power supply voltage. The switching module is connected to the IGBT under test. The switching module is used to turn on or off according to the third drive signal, and when it is turned on, it connects the second power supply voltage to the first terminal of the IGBT under test. The first current sampling module is connected to the second terminal of the IGBT under test. The first current sampling module is used to sample the current of the IGBT under test and output the first current sampling signal to the first input terminal of the control circuit. The control circuit is used to determine whether the IGBT under test is latched based on the first current sampling signal.

[0007] Optionally, the IGBT latch-up test circuit provided in this embodiment of the invention further includes a second current sampling module; The second current sampling module is connected between the output of the test current generation module and the first terminal of the IGBT under test. It is used to sample the test current and feed back the second current sampling signal to the second input of the control circuit.

[0008] Optionally, the test current generation module includes: a first transistor, a first resistor, and a second resistor; The first end of the first resistor serves as the control terminal of the test current generation module, and the second end of the first resistor is connected to the control terminal of the first transistor. The first end of the first transistor serves as the power supply terminal of the test current generation module, and the second end of the first transistor serves as the output terminal of the test current generation module. The second resistor is connected between the control terminal of the first transistor and the second end of the first transistor.

[0009] Optionally, the first transistor includes a MOSFET, and the second drive signal includes a PWM signal; the MOSFET is used to output a test current according to the second drive signal and the first power supply voltage.

[0010] Optionally, the switching module includes a second transistor, a third resistor, and a fourth resistor; The first end of the third resistor serves as the control terminal of the switching module, the second end of the third resistor is connected to the control terminal of the second transistor, the first end of the second transistor serves as the power supply terminal of the switching module, the second end of the second transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the first end of the IGBT under test.

[0011] Optionally, the first current sampling module includes a first sampling resistor and a first current sampling unit; The first terminal of the first sampling resistor is connected to the second terminal of the IGBT under test, and the second terminal of the first sampling resistor is grounded. The first input terminal of the first current sampling unit is connected to the first terminal of the first sampling resistor, and the second input terminal of the first current sampling unit is connected to the second terminal of the first sampling resistor. The first current sampling unit is used to obtain the current of the IGBT under test according to the voltage across the first sampling resistor, and output the first current sampling signal to the first input terminal of the control circuit. The second current sampling module includes a second sampling resistor and a second current sampling unit; The first end of the second sampling resistor is connected to the output end of the test current generation module, and the second end of the second sampling resistor is connected to the first end of the IGBT under test. The first input terminal of the second current sampling unit is connected to the first terminal of the second sampling resistor, and the second input terminal of the second current sampling unit is connected to the second terminal of the second sampling resistor. The second current sampling unit is used to obtain the test current based on the voltage across the second sampling resistor and output the second current sampling signal to the second input terminal of the control circuit.

[0012] Optionally, the control circuit includes a control module, a first drive module, a second drive module, and a third drive module; The first drive module is connected to the control module, and the output terminal of the first drive module serves as the first output terminal of the control circuit. The first drive module is used to generate a first drive signal based on the first control signal output by the control module and output it to the control terminal of the IGBT under test. The second drive module is connected to the control module, and the output terminal of the second drive module serves as the second output terminal of the control circuit. The second drive module is used to generate a second drive signal based on the second control signal output by the control module and output it to the control terminal of the test current generation module. The third drive module is connected to the control module, and the output terminal of the third drive module serves as the third output terminal of the control circuit. The third drive module is used to generate a third drive signal based on the third control signal output by the control module and output it to the control terminal of the switch module. The first input terminal of the control module serves as the first input terminal of the control circuit and is used to receive the first current sampling signal; the second input terminal of the control module serves as the second input terminal of the control circuit and is used to receive the second current sampling signal.

[0013] According to another aspect of the present invention, an IGBT latch-up test method is also provided, applied to an IGBT latch-up test circuit in any embodiment of the present invention. The IGBT latch-up test method includes: The control circuit outputs a first drive signal from the first output terminal to the control terminal of the IGBT under test, and controls the IGBT under test to turn on according to the first drive signal. The control circuit outputs a second drive signal from the second output terminal to the control terminal of the test current generation module, and controls the test current generation module to generate a test current according to the second drive signal. After the first interval, the control circuit outputs a third drive signal to the switching module at the third output terminal. The control switching module is turned on according to the third drive signal, so that the second power supply voltage is connected to the first terminal of the IGBT under test. After the second time interval, the test current generation module stops outputting current and the IGBT under test is disconnected. The first current sampling module is controlled to sample the current of the IGBT under test; If the first current sampling signal is greater than or equal to the preset threshold, it is determined that the IGBT under test has latched up; if the first current sampling signal is less than the preset threshold, the magnitude and duration of the test current are adjusted until the IGBT under test latches up.

[0014] Optional adjustments to the magnitude and duration of the test current include: The magnitude of the test current is adjusted by adjusting the duty cycle of the second drive signal, and the duration of the test current is adjusted by adjusting the output time of the second drive signal.

[0015] Optionally, the control test current generation module generates the test current according to the second drive signal, including: The second current sampling module is controlled to sample the test current, and the duty cycle of the second drive signal is controlled by a PID algorithm to adjust the magnitude of the test current.

[0016] The technical solution of this invention provides a disturbance condition for the IGBT under test by generating a test current to the first terminal of the IGBT based on a second drive signal using a test current generation module. After a first time interval, a switching module is turned on, connecting a second power supply voltage to the first terminal of the IGBT under test, providing freewheeling current to the IGBT. The current of the IGBT under test is sampled by a first current sampling module, and the control circuit determines whether the IGBT under test is latched based on the first current sampling signal. If not triggered, the magnitude and / or duration of the test current can be precisely controlled until the first current sampling signal I1 is greater than or equal to a preset threshold, triggering latch-up. In summary, the technical solution of this invention provides an adjustable test current magnitude and duration for latch-up testing, and after the test current generation module provides the test current, it provides freewheeling current to the IGBT under test through the second power supply voltage. This ensures that latch-up of the IGBT under test can be detected without damaging the IGBT, improving the reliability of the latch-up test circuit.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a CMOS topology provided in an embodiment of the present invention; Figure 2 An equivalent circuit diagram of a CMOS topology provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal structure of an IGBT provided in an embodiment of the present invention; Figure 4 A schematic diagram of an IGBT topology provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an IGBT latch-up test circuit provided in an embodiment of the present invention; Figure 6 A schematic diagram of another IGBT latch-up test circuit provided in an embodiment of the present invention; Figure 7 A circuit structure diagram of an IGBT latch-up test circuit provided in an embodiment of the present invention; Figure 8 A flowchart of an IGBT latch-up test method provided in an embodiment of the present invention; Figure 9 A flowchart of another IGBT latch-up test method provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of a CMOS topology provided in an embodiment of the present invention. Figure 2 An equivalent circuit diagram of a CMOS topology provided in an embodiment of the present invention, such as... Figure 1 As shown, P-sub represents a P-type substrate, PW represents a P-type well, and NW represents an N-type well. A P-type doped region formed by ion implantation in P-sub constitutes an N-type field-effect transistor (NMOS); an N-type doped region formed by ion implantation in P-sub constitutes a P-type field-effect transistor (PMOS). n+ indicates a high-concentration N-type doped region formed in PW, and p+ indicates a high-concentration P-type doped region formed in NW. VDD represents the positive power supply terminal of the CMOS, and VSS represents the negative power supply terminal. The input connects to the gates of the NMOS and PMOS, controlling their on / off states. The output connects to the drains of the NMOS and PMOS as the CMOS output terminal. Metal interconnects connect the gates, sources, and drains of the NMOS and PMOS to realize the CMOS circuit function. Rp represents the parasitic resistance of the P-type substrate, and Rn represents the parasitic resistance of the N-type substrate. CMOS processes generally have defects. In a CMOS topology, there is often an NPN parasitic transistor and a PNP parasitic transistor. The equivalent circuit diagram formed by the NPN parasitic transistor, the PNP parasitic transistor, the parasitic resistance Rp of the P-type substrate, and the parasitic resistance Rn of the N-type substrate is shown below. Figure 2As shown. Ip represents the disturbance current generated by the parasitic resistance Rp of the P-type substrate. When the CMOS is subjected to external interference, a disturbance current Ip will be generated in the parasitic resistance Rp of the P-type substrate, which will then generate a large voltage drop across the parasitic resistance Rp of the P-type substrate. When the voltage drop across the parasitic resistance Rp of the P-type substrate reaches 0.6-0.7V, the NPN parasitic transistor will turn on. After the NPN parasitic transistor turns on, a current IC will appear at the collector of the NPN parasitic transistor. The current IC causes a voltage drop across the parasitic resistance Rn of the N-type substrate. When the voltage drop across the parasitic resistance Rn of the N-type substrate reaches 0.6-0.7V, the PNP parasitic transistor will turn on. When the PNP parasitic transistor is turned on, its emitter current Ie flows through the parasitic resistance Rp of the P-type substrate, further increasing the voltage drop across the parasitic resistance. This, in turn, further increases the conduction level of the NPN parasitic transistor. The disturbance current Ip causes CMOS latch-up. Once latch-up is triggered, the NPN and PNP parasitic transistors form a positive feedback loop, perpetuating the CMOS latch-up effect. The low-resistance path formed by latch-up leads to a continuous high current, which may reach tens or even hundreds of times the current density during normal operation. This high current generates a large amount of heat in a short time, causing the chip to burn out and even triggering a cascading failure of the entire circuit system.

[0023] Figure 3 This is a schematic diagram of the internal structure of an IGBT provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of an IGBT topology provided in an embodiment of the present invention. Figure 3 and Figure 4 It can be seen that there are internal components of IGBT devices that are related to... Figure 2 Similar to the topology in the IGBT, the IGBT device is a monolithic Bi-MOS transistor formed by Darlington connection of a PNP transistor and an N-type MOSFET. Therefore, when a positive voltage is applied between the gate (G) and emitter (E) to turn on the MOSFET, a low resistance is connected between the base and collector of the PNP transistor, thus keeping the PNP transistor in the on state. Subsequently, when the voltage between the gate (G) and emitter (E) is zero or negative, the MOSFET is in the off state, the base current of the PNP transistor is cut off, and the IGBT can be turned off.

[0024] If a large current is applied, a significant voltage drop will occur across the resistor connected to the base of the NPN transistor. This voltage drop is the voltage drop between the base and emitter of the NPN transistor. If the voltage drop reaches 0.6-0.7V, the NPN transistor will conduct. When both the NPN and PNP transistors are conducting, latch-up will be triggered, potentially leading to overpower damage to the IGBT.

[0025] Figure 5This is a schematic diagram of an IGBT latch-up test circuit provided in an embodiment of the present invention. This embodiment is applicable to scenarios where latch-up effects of semiconductor devices are tested, such as IGBTs. Figure 5 As shown, the IGBT latch-up test circuit of this embodiment includes a control circuit 1, a test current generation module 2, a switching module 3, and a first current sampling module 4.

[0026] The first output terminal of control circuit 1 is connected to the control terminal of IGBT 5 under test, and is used to output a first drive signal P1. IGBT 5 under test is turned on or off according to the first drive signal P1. The second output terminal of control circuit 1 is connected to the control terminal of test current generation module 2, and is used to output a second drive signal P2 to test current generation module 2. The power supply terminal of test current generation module 2 is connected to a first power supply voltage V1. Test current generation module 2 is connected to IGBT 5 under test, and is used to generate a test current to the first terminal of IGBT 5 under test according to the second drive signal P2. The third output terminal of control circuit 1 is connected to the control terminal of switch module 3, and is used to output a third drive signal P3 to switch module 3. The power supply terminal of switch module 3 is connected to a second power supply voltage V2. Switch module 3 is connected to IGBT 5 under test, and is used to turn on or off according to the third drive signal P3, and when on, it connects the second power supply voltage V2 to the first terminal of IGBT 5 under test. The first current sampling module 4 is connected to the second terminal of the IGBT 5 under test. The first current sampling module 4 is used to sample the current of the IGBT 5 under test and outputs a first current sampling signal I1 to the first input terminal of the control circuit 1. The control circuit 1 is used to determine whether the IGBT 5 under test is latched based on the first current sampling signal I1.

[0027] In this embodiment of the invention, the control circuit 1 can output a first driving signal P1, a second driving signal P2, and a third driving signal P3 according to preset rules. The preset rules may include a basis for setting the signal types and output timing of the first driving signal P1, the second driving signal P2, and the third driving signal P3. For example, the second driving signal P2 can be a PWM signal, and the first driving signal P1 and the third driving signal P3 can be high-level signals or low-level signals. The control circuit 1 first outputs the first driving signal P1, then the second driving signal P2, and finally the third driving signal P3; or the control circuit 1 simultaneously outputs the first driving signal P1, the second driving signal P2, and the third driving signal P3. The signal types and output timing can be set according to specific test requirements, and this embodiment of the invention does not limit this.

[0028] The IGBT 5 under test can be an N-channel IGBT. The control terminal of the IGBT 5 under test can be the gate of the IGBT 5, the first terminal of the IGBT 5 under test can be the collector of the IGBT 5, and the second terminal of the IGBT 5 under test can be the emitter of the IGBT 5. For example, the IGBT 5 under test is turned on when the first drive signal P1 is a high-level signal and turned off when the first drive signal P1 is a low-level signal.

[0029] The test current generation module 2 generates a test current and applies it to the first terminal of the IGBT 5 under test, providing a disturbance to the IGBT 5. This disturbance activates the PNP transistor inside the IGBT 5. A sufficiently large disturbance and / or a sufficiently long disturbance duration will trigger latch-up in the IGBT 5. The magnitude and duration of the test current are adjustable so that the IGBT 5 can trigger latch-up when the test current reaches the target test current. The target test current can be the magnitude of the test current that causes latch-up in the IGBT 5. For example, the power supply terminal of the test current generation module 2 is connected to a first power supply voltage V1, which can be 24V. By adjusting the duty cycle of the second drive signal P2, the test current generation module 2 can output an adjustable test current, and / or, by controlling the output time of the second drive signal P2, the test current generation module 2 can output a test current with an adjustable duration. Alternatively, the test current generation module 2 can stop outputting the test current by adjusting the duty cycle of the second drive signal P2.

[0030] The switching module 3 controls whether the first terminal of the IGBT 5 under test is connected to the second power supply voltage V2. The second power supply voltage V2 can provide freewheeling current for the IGBT 5 under test. For example, the power supply terminal of the switching module 3 is connected to the second power supply voltage V2. The second power supply voltage V2 can be 12V. The switching module 3 is turned on when the third drive signal P3 is high, connecting the first terminal of the IGBT 5 under test to the second power supply voltage V2; it is turned off when the third drive signal P3 is low, disconnecting the first terminal of the IGBT 5 under test from the second power supply voltage V2.

[0031] The first current sampling module 4 samples the current flowing through the IGBT5 under test and outputs a first current sampling signal I1 to the control circuit 1. When the IGBT5 under test is turned off, if latch-up does not occur, almost no current flows through it. If latch-up occurs, the first and second terminals of the IGBT5 under test are short-circuited, and the current flowing through it will be very large. The control circuit 1 can determine whether the IGBT5 under test has triggered latch-up based on whether the first current sampling signal I1 exceeds a preset threshold. The preset threshold can be set with reference to the performance parameters of the IGBT5 under test. For example, the preset threshold is 2-3 times the current of the IGBT5 under test during normal operation. For instance, if the first current sampling signal I1 is lower than the preset threshold, and the IGBT5 has not triggered latch-up, the control circuit 1 controls the test current generation module 2 to increase the output test current or extend the duration of the test current until the IGBT5 under test triggers latch-up.

[0032] The test current generated by test current generation module 2 provides an external disturbance condition for triggering the latch-up of the IGBT5 under test. Typically, the test current is relatively large to activate the PNP transistor inside the IGBT5, thereby triggering the parasitic thyristor and causing the IGBT5 to latch up. However, on the one hand, if an excessively large test current is continuously applied to the IGBT5 while it is conducting, it can cause avalanche breakdown of the PNP transistor inside the IGBT5, leading to the conduction of the parasitic thyristor and damaging the IGBT5. On the other hand, if the test current generation module 2 stops outputting the test current to the IGBT5 after it has been controlling the current generation module 2, the current on the IGBT5 will disappear. Even if the test current is sufficient to trigger the latch-up of the IGBT5, the latch-up will disappear with the current and cannot be detected. Therefore, after the test current generated by the test current generation module 2 provides a disturbance condition to the IGBT 5 under test, it provides freewheeling current to the IGBT 5 through the second power supply voltage. The second power supply voltage V2 is less than the first power supply voltage V1, which ensures that the latch-up of the IGBT 5 under test can be detected without damaging it. Since the switching module 3 requires time to turn on, to prevent the IGBT 5 from interrupting its current supply midway, the switching module 3 needs to be turned on before the test current generation module 2 stops outputting current. Optionally, the second power supply voltage V2 can be provided by a buck circuit. However, the buck circuit has relatively low power, and the current it provides is insufficient to damage the IGBT 5 under test.

[0033] Taking the example of IGBT 5 being turned on when the first drive signal P1 is high, and switch module 3 being turned on when the third drive signal P3 is high. Specifically, control circuit 1 outputs the first drive signal P1 from its first output terminal to the control terminal of IGBT 5. The first drive signal P1 can be a high-level signal, and IGBT 5 is turned on under the drive of the high-level signal. Subsequently, control circuit 1 outputs the second drive signal P2 from its second output terminal to the control terminal of test current generation module 2. Test current generation module 2 outputs test current to the first terminal of IGBT 5 from its output terminal. The magnitude of the test current can be adjusted by setting the duty cycle of the second drive signal P2, and the duration of the output of the second drive signal P2 can be controlled to adjust the duration of the test current. Next, control circuit 1 outputs the third drive signal P3 from its third output terminal to the control terminal of switch module 3. The third drive signal P3 can be a high-level signal, and switch module 3 is turned on under the drive of the high-level signal, connecting the second power supply voltage V2 to the first terminal of IGBT 5, and providing freewheeling current to IGBT 5 through the second power supply voltage V2. Next, control circuit 1 outputs a second drive signal P2 from its second output terminal to the control terminal of test current generation module 2, causing test current generation module 2 to stop outputting test current. Then, control circuit 1 outputs a first drive signal P1 from its first output terminal to the control terminal of the IGBT 5 under test. The first drive signal P1 can be a low-level signal, turning off the IGBT 5. The first current sampling module 4 samples the current of the IGBT 5 under test and outputs a first current sampling signal I1 to the first input terminal of control circuit 1. Control circuit 1 can determine whether the IGBT under test has triggered latch-up based on whether the first current sampling signal I1 exceeds a preset threshold. If the first current sampling signal I1 is lower than the preset threshold, latch-up is not triggered, and the control circuit increases the test current and / or the duration of the test current until the first current sampling signal I1 is greater than or equal to the preset threshold, triggering latch-up. After latch-up is triggered, control circuit 1 records the test current and latch-up current corresponding to the trigger latch-up and provides a latch-up notification.

[0034] According to the technical solution of this embodiment of the invention, a test current generation module generates a test current to the first terminal of the IGBT under test based on a second drive signal, providing a disturbance condition for the IGBT under test. After a first time interval, a switching module is turned on, connecting a second power supply voltage to the first terminal of the IGBT under test, providing a freewheeling current to the IGBT under test through the second power supply voltage. The current of the IGBT under test is sampled by a first current sampling module, and the control circuit determines whether the IGBT under test is latched based on the first current sampling signal. If not triggered, the magnitude and / or duration of the test current can be precisely controlled until the first current sampling signal I1 is greater than or equal to a preset threshold, triggering latch-up. In summary, the test current magnitude and duration for latch-up testing in this embodiment of the invention are adjustable, and after the test current generation module provides the test current, a freewheeling current is provided to the IGBT under test through the second power supply voltage. This ensures that latch-up of the IGBT under test can be detected without damaging the IGBT under test, improving the reliability of the latch-up test circuit.

[0035] Based on the above embodiments, Figure 6 A schematic diagram of another IGBT latch-up test circuit provided in an embodiment of the present invention is shown below. Figure 6 As shown, the IGBT latch-up test circuit of this embodiment of the invention also includes a second current sampling module 6.

[0036] The second current sampling module 6 is connected between the output terminal of the test current generation module 2 and the first terminal of the IGBT 5 under test. It is used to sample the test current and feed back the second current sampling signal I2 to the second input terminal of the control circuit 1.

[0037] The second current sampling module 6 can sample the test current output by the test current generation module 2. The second current sampling signal I2 is a feedback signal of the test current, which helps the control circuit 1 to adjust the duty cycle and output time of the output second drive signal P2 by using the second current sampling signal I2 and whether the IGBT 5 under test is triggered to latch up.

[0038] Specifically, control circuit 1 acquires a second current sampling signal I2 through the second current sampling module 6, and acquires a first current sampling signal I1 corresponding to the IGBT5 under test under the action of the test current corresponding to the second current sampling signal I2. It then determines whether latch-up is triggered based on the first current sampling signal I1. If not triggered, the second drive signal P2 is further adjusted based on the current second current sampling signal I2. By setting the second current sampling module 6, it is possible to avoid adjusting the duty cycle and / or output time of the second drive signal P2 to be too large or too small. If it is too large, the latch-up current error when judging the latch-up of the IGBT5 under test will be large; if it is too small, the debugging test for latch-up will increase, resulting in low efficiency.

[0039] Figure 7 A circuit structure diagram of an IGBT latch-up test circuit provided in an embodiment of the present invention is shown below. Figure 7 As shown, in some embodiments, the test current generating module 2 includes: a first transistor Q1, a first resistor R1, and a second resistor R2.

[0040] The first end of the first resistor R1 serves as the control terminal of the test current generation module 2, and the second end of the first resistor R1 is connected to the control terminal of the first transistor Q1. The first end of the first transistor Q1 serves as the power supply terminal of the test current generation module 2, and the second end of the first transistor Q1 serves as the output terminal of the test current generation module 2. The second resistor R2 is connected between the control terminal and the second end of the first transistor Q1.

[0041] Optionally, the first transistor Q1 includes a MOSFET, and the second drive signal P2 includes a PWM signal; the MOSFET is used to output a test current according to the second drive signal P2 and the first power supply voltage V1.

[0042] In this circuit, the first transistor Q1 can be an N-type MOSFET. The control terminal of the first transistor Q1 can be the gate of the N-type MOSFET, the first terminal of the first transistor Q1 can be the drain of the N-type MOSFET, and the second terminal of the first transistor Q1 can be the source of the N-type MOSFET. A first resistor R1 is connected between the second output terminal of the control circuit 1 and the control terminal of the first transistor Q1 for current limiting. A second resistor R2 is connected between the control terminal of the first transistor Q1 and the second terminal of the first transistor Q1.

[0043] The second drive signal P2 can be a PWM signal with a frequency higher than a frequency threshold. The frequency threshold can be the frequency value that causes the current output by the first transistor Q1 to change, and can be set according to the characteristic parameters of the first transistor Q1. That is, if the frequency of the PWM signal is too low, the first transistor Q1 will be briefly turned off, resulting in discontinuous output current and failing to provide the test current to trigger the latch. The turn-on and turn-off of the first transistor Q1 is a variable process; it does not directly saturate and turn on with a high-level signal. By setting the frequency of the second drive signal P2, which is higher than the frequency threshold, the first transistor Q1 can be kept between saturation conduction and turn-off, and the test current output by the first transistor Q1 can change accordingly. Furthermore, by setting the duty cycle of the second drive signal P2, the test current can be made to change with the duty cycle of the second drive signal P2 when powered by the first power supply voltage V1.

[0044] Continue to refer to Figure 7 In some embodiments, the switching module 3 includes a second transistor Q2, a third resistor R3, and a fourth resistor R4.

[0045] The first end of the third resistor R3 serves as the control terminal of the switching module 3. The second end of the third resistor R3 is connected to the control terminal of the second transistor Q2. The first end of the second transistor Q2 serves as the power supply terminal of the switching module 3. The second end of the second transistor Q2 is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the first end of the IGBT 5 under test.

[0046] In this design, the second transistor Q2 can be an NPN transistor. The control terminal of the second transistor Q2 can be the base of the NPN transistor, the first terminal of the second transistor Q2 can be the collector of the NPN transistor, and the second terminal of the second transistor Q2 can be the emitter of the NPN transistor. For example, when the third drive signal P3 is high, the second transistor Q2 is turned on, and the switching module 3 is turned on; when the third drive signal P3 is low, the second transistor Q2 is turned off, and the switching module 3 is turned off.

[0047] The third resistor R3 is connected between the third output terminal of the control circuit 1 and the control terminal of the second transistor Q2, and is used to prevent the third drive signal P3 from being too large and damaging the second transistor Q2; the fourth resistor R4 is connected between the second power supply voltage V2 and the first terminal of the IGBT 5 under test, and is used to prevent the current generated when the second transistor Q2 is turned on and the second power supply voltage V2 is connected to the IGBT 5 under test from being too large and damaging the IGBT 5 under test.

[0048] By setting the second transistor Q2, the connection between the second power supply voltage V2 and the first terminal of the IGBT5 under test can be quickly and sensitively controlled under the control of the third drive signal P3. This allows for faster provision of freewheeling current to the IGBT5 under test through the second power supply voltage V2, thereby improving the accuracy of latch-up testing.

[0049] Optionally, the IGBT latch-up test circuit also includes an energy storage capacitor E, with the positive terminal of the energy storage capacitor E connected to the first terminal of the second transistor Q2, and the negative terminal of the energy storage capacitor E grounded.

[0050] Continue to refer to Figure 7 In some embodiments, the first current sampling module 4 includes a first sampling resistor RS1 and a first current sampling unit. The first terminal of the first sampling resistor RS1 is connected to the second terminal of the IGBT5 under test, and the second terminal of the first sampling resistor RS1 is grounded. The first input terminal of the first current sampling unit is connected to the first terminal of the first sampling resistor RS1, and the second input terminal of the first current sampling unit is connected to the second terminal of the first sampling resistor RS1. The first current sampling unit is used to obtain the current of the IGBT5 under test according to the voltage across the first sampling resistor RS1, and outputs a first current sampling signal I1 to the first input terminal of the control circuit 1.

[0051] The second current sampling module 6 includes a second sampling resistor RS2 and a second current sampling unit. The first end of the second sampling resistor RS2 is connected to the output terminal of the test current generation module 2, and the second end of the second sampling resistor RS2 is connected to the first terminal of the IGBT 5 under test. The first input terminal of the second current sampling unit is connected to the first end of the second sampling resistor RS2, and the second input terminal of the second current sampling unit is connected to the second end of the second sampling resistor RS2. The second current sampling unit is used to obtain the test current based on the voltage across RS2 of the second sampling resistor and output the second current sampling signal I2 to the second input terminal of the control circuit 1.

[0052] The first current sampling unit may include a first current sampling chip U1, a fifth resistor R5, and a first capacitor C1. VE+ represents the first input terminal of the first current sampling chip U1, VE- represents the second input terminal of the first current sampling chip U1, VCC represents the power supply terminal of the first current sampling chip U1, GND represents the ground terminal of the first current sampling chip U1, and VOUT represents the output terminal of the first current sampling chip U1. The first input terminal of the first current sampling chip U1 is the first input terminal of the first current sampling unit, and the second input terminal of the first current sampling chip U1 is the second input terminal of the first current sampling unit. The power supply terminal of the first current sampling chip U1 is connected to a third power supply voltage, such as a 3.3V DC voltage. The ground terminal of the first current sampling chip U1 is grounded. The output terminal of the first current sampling chip U1 is connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is grounded. The second terminal of the fifth resistor R5 is the output terminal of the first current sampling unit. The first current sampling chip U1 acquires the differential signal across the first sampling resistor RS1. After processing by the first current sampling chip U1, the first current sampling signal I1 is output at the second end of the fifth resistor R5.

[0053] The second current sampling unit may include a second current sampling chip U2, a sixth resistor R6, and a second capacitor C2. VE+ represents the first input terminal of the second current sampling chip U2, VE- represents the second input terminal of the second current sampling chip U2, VCC represents the power supply terminal of the second current sampling chip U2, GND represents the ground terminal of the second current sampling chip U2, and VOUT represents the output terminal of the second current sampling chip U2. The first input terminal of the second current sampling chip U2 is the first input terminal of the second current sampling unit, and the second input terminal of the second current sampling chip U2 is the second input terminal of the second current sampling unit. The power supply terminal of the second current sampling chip U2 is connected to a third power supply voltage, such as a 3.3V DC voltage. The ground terminal of the second current sampling chip U2 is grounded. The output terminal of the second current sampling chip U2 is connected to the first terminal of the sixth resistor R6, and the second terminal of the sixth resistor R6 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is grounded. The second terminal of the sixth resistor R6 is the output terminal of the second current sampling unit. The second current sampling chip U2 acquires the differential signal across the second sampling resistor RS2. After processing by the second current sampling chip U2, the second current sampling signal I2 is output at the second end of the sixth resistor R6.

[0054] It is understood that the first current sampling chip U1 and the second current sampling chip U1 can be the same type of current sampling chip, such as ZXCT1051E5TA. The first current sampling unit can also sample the current of the IGBT5 under test through other circuits, and the second current sampling unit can also sample the test current through other circuits. The specific circuit structure of the first current sampling unit and the second current sampling unit is not specifically limited in this embodiment of the invention.

[0055] In some embodiments, the seventh resistor R7 is connected between the first output terminal of the control circuit 1 and the control terminal of the IGBT 5 under test for current limiting. The eighth resistor R8 is connected between the control terminal and the second terminal of the IGBT 5 under test for voltage regulation.

[0056] Specifically, when switch module 3 is turned on, the current generated by the second power supply voltage V2 flows through the second transistor Q2, the fourth resistor R4, the IGBT 5 under test, and the first sampling resistor RS1. After the IGBT 5 under test is turned off, if latch-up does not occur, almost no current flows through the IGBT 5. If latch-up occurs, the first and second terminals of the IGBT 5 are short-circuited, and the current flowing through the IGBT 5 is close to or larger than before the IGBT 5 was turned off. The current flowing through the IGBT 5 before it is turned off is the freewheeling current provided by the second power supply voltage V2 for the IGBT 5. Whether the IGBT 5 has triggered latch-up can be determined by the first current sampling signal I1. If the first current sampling signal I1 is greater than or equal to a preset threshold, latch-up is triggered. The freewheeling current I provided by the second power supply voltage V2 for the IGBT 5 under test can be: Where V2 can be the voltage value of the second power supply voltage. It could be the collector-emitter voltage drop of the second transistor Q2. R4 can be the collector-emitter voltage drop of the IGBT5 under test, R4 can be the resistance value of the fourth resistor, and RS1 can be the resistance value of the first sampling resistor RS1.

[0057] Understandably, the degree of difference between the first current sampling signal I1 and the freewheeling current I can also be used to determine whether the IGBT5 under test has triggered latch-up. The degree of difference can be the deviation between the first current sampling signal I1 and the freewheeling current, and can be calculated using at least one of the absolute value, variance, or squared difference of the difference between the first current sampling signal I1 and the freewheeling current. A smaller degree of difference between the first current sampling signal I1 and the freewheeling current I indicates that the IGBT5 under test has latched up.

[0058] Continue to refer to Figure 7 In some embodiments, the control circuit 1 includes a control module 11, a first drive module 12, a second drive module 13, and a third drive module 14.

[0059] The first drive module 12 is connected to the control module 11, and its output terminal serves as the first output terminal of the control circuit 1. The first drive module 12 generates a first drive signal P1 based on the first control signal output by the control module 11 and outputs it to the control terminal of the IGBT 5 under test. The second drive module 13 is connected to the control module 11, and its output terminal serves as the second output terminal of the control circuit 1. The second drive module 13 generates a second drive signal P2 based on the second control signal output by the control module 11 and outputs it to the control terminal of the test current generation module 2. The third drive module 14 is connected to the control module 11, and its output terminal serves as the third output terminal of the control circuit 1. The third drive module 14 generates a third drive signal P3 based on the third control signal output by the control module 11 and outputs it to the control terminal of the switching module 3.

[0060] The first input terminal of the control module 11 serves as the first input terminal of the control circuit 1, and is used to receive the first current sampling signal I1. The second input terminal of the control module 11 serves as the second input terminal of the control circuit 1, and is used to receive the second current sampling signal I2.

[0061] The first driving module 12 may include a first optocoupler OC1, a ninth resistor R9, and a tenth resistor R10. The first end of the ninth resistor R9 is connected to the first output terminal PB3 of the control module 11, and the second end of the ninth resistor R9 is connected to the input terminal of the first optocoupler OC1, whose output terminal is the output terminal of the first driving module 12. The first ends of the tenth resistor R10 and the seventh resistor R7 are both connected to the output terminal of the first optocoupler OC1, and the second end of the tenth resistor R10 is connected to a second power supply voltage, which can be 12V. For example, the control module 11 outputs a first control signal from its first output terminal to the input terminal of the first optocoupler OC1. The first optocoupler OC1 generates a first driving signal P1 based on the first control signal, and the driving capability of the first driving signal P1 is greater than that of the first control signal.

[0062] The second driving module 13 may include a second optocoupler OC2, an eleventh resistor R11, and a twelfth resistor R12. The first end of the eleventh resistor R11 is connected to the second output terminal PB5 of the control module 11, and the second end of the eleventh resistor R11 is connected to the input terminal of the second optocoupler OC2. The output terminal of the second optocoupler OC2 is the output terminal of the second driving module 13. The first ends of the twelfth resistor R12 and the first end of the first resistor R1 are both connected to the output terminal of the second optocoupler OC2, and the second end of the twelfth resistor R12 is connected to a second power supply voltage, which can be 12V. For example, the control module 11 outputs a second control signal from its second output terminal to the input terminal of the second optocoupler OC2. The second optocoupler OC2 generates a second driving signal P2 based on the second control signal, and the driving capability of the second driving signal P2 is greater than that of the second control signal.

[0063] The third driving module 14 may include a third optocoupler OC3, a thirteenth resistor R13, and a fourteenth resistor R14. The first end of the thirteenth resistor R13 is connected to the third output terminal PB4 of the control module 11, and the second end of the thirteenth resistor R13 is connected to the input terminal of the third optocoupler OC3. The output terminal of the third optocoupler OC3 is the output terminal of the third driving module 14. The first ends of the fourteenth resistor R14 and the third resistor R3 are both connected to the output terminal of the third optocoupler OC3, and the second end of the fourteenth resistor R14 is connected to a second power supply voltage, which can be 12V. For example, the control module 11 outputs a third control signal from its third output terminal to the input terminal of the third optocoupler OC3. The third optocoupler OC3 generates a third driving signal P3 based on the third control signal, and the driving capability of the third driving signal P3 is greater than that of the third control signal.

[0064] The output terminal of the first current sampling module 4 is connected to the first input terminal PB1 of the control module 11, and the output terminal of the second current sampling module 6 is connected to the second input terminal PB0 of the control module 11.

[0065] It is understandable that the first drive module 12, the second drive module 13, and the third drive module 14 can also be constructed using other drive circuits.

[0066] In some embodiments, the IGBT latch-up test circuit further includes a power supply module for supplying power to the IGBT latch-up test circuit. The power supply module includes a first power conversion unit and a second power conversion unit. The power supply module can be connected to a first power supply voltage, which can be 24V. The first power conversion unit converts the first power supply voltage to a second power supply voltage, which can be 12V. The second power conversion unit can convert the second power supply voltage to a third power supply voltage, which can be 3.3V. The first power conversion unit can include at least one of a buck converter, a boost converter, and an LDO circuit, and the second power conversion unit can include an LDO circuit.

[0067] In some embodiments, the control circuit further includes some peripheral circuits, such as a button circuit, which can set the type and output timing of the first drive signal, the second drive signal and the third drive signal through the buttons.

[0068] In summary, the IGBT latch-up test circuits in the embodiments of the present invention are all built with low-cost components and chips, and the IGBT latch-up test circuits are simple and low-cost.

[0069] Figure 8 A flowchart of an IGBT latch-up test method provided in an embodiment of the present invention is shown below. Figure 8 As shown, this embodiment of the invention provides an IGBT latch-up test method, applicable to the IGBT latch-up test circuit of any embodiment of the invention. The IGBT latch-up test method includes: S101, the control circuit outputs a first drive signal from the first output terminal to the control terminal of the IGBT under test, and controls the IGBT under test to turn on according to the first drive signal.

[0070] S102, the control circuit outputs a second drive signal at the second output terminal to the control terminal of the test current generation module, and controls the test current generation module to generate a test current according to the second drive signal.

[0071] S103. After the first time interval, the control circuit outputs a third drive signal to the switch module at the third output terminal. The control switch module is turned on according to the third drive signal, so that the second power supply voltage is connected to the first terminal of the IGBT under test.

[0072] By controlling the switching module to turn on after a certain interval, the test current acting on the IGBT under test can be sustained for a period of time, providing a disturbance condition for the IGBT. For example, the first interval can be 0.5 seconds, and this interval can be set according to actual conditions.

[0073] S104. After the second time interval, control the test current generation module to stop outputting current and control the IGBT under test to disconnect.

[0074] By controlling the test current generation module to stop outputting the test current after a second time interval, it can be ensured that the switching module has been turned on and that the second power supply voltage has provided freewheeling current to the IGBT under test, thus preventing the IGBT from experiencing a current interruption midway. The second time interval can be 100 microseconds, and can be set according to actual conditions.

[0075] Understandably, the turn-on time of the switching module cannot be too long, that is, the second time cannot be too large. If it is too large, the switch module will turn on too long in advance, the energy storage capacitor will discharge for too long, and the current provided by the second power supply voltage will be too large.

[0076] S105. Control the first current sampling module to sample the current of the IGBT under test.

[0077] S106. If the first current sampling signal is greater than or equal to the preset threshold, it is determined that the IGBT under test has latched up; if the first current sampling signal is less than the preset threshold, the magnitude and duration of the test current are adjusted until the IGBT under test latches up.

[0078] Optional adjustments to the magnitude and duration of the test current include: The magnitude of the test current is adjusted by adjusting the duty cycle of the second drive signal, and the duration of the test current is adjusted by adjusting the output time of the second drive signal.

[0079] Figure 9 A flowchart of another IGBT latch-up test method provided in an embodiment of the present invention is shown below. Figure 9 As shown, the IGBT latch-up test method includes: S201, the control circuit outputs a first drive signal from the first output terminal to the control terminal of the IGBT under test, and controls the IGBT under test to turn on according to the first drive signal.

[0080] S202, the control circuit outputs a second drive signal at the second output terminal to the control terminal of the test current generation module, controls the second current sampling module to sample the test current, and controls the duty cycle of the second drive signal through a PID algorithm to adjust the magnitude of the test current.

[0081] By controlling the second drive signal through a PID algorithm, the magnitude of the test current can be increased at an appropriate speed, avoiding excessive or insufficient test current and improving the accuracy and efficiency of latch-up testing.

[0082] The process includes controlling the duty cycle of the second drive signal using a PID algorithm to adjust the magnitude of the test current, followed by determining whether the test current exceeds a current threshold. The current threshold is the maximum test current value that the test current generation module can output. If it is exceeded, the latch-up test ends.

[0083] S203. After the first time interval, the control circuit outputs a third drive signal to the switch module at the third output terminal. The control switch module is turned on according to the third drive signal, so that the second power supply voltage is connected to the first terminal of the IGBT under test.

[0084] S204. After the second time interval, control the test current generation module to stop outputting current and control the IGBT under test to disconnect.

[0085] S205. Control the first current sampling module to sample the current of the IGBT under test.

[0086] S206. The first current sampling signal is greater than or equal to a preset threshold; if yes, then execute S207; otherwise, then execute S202.

[0087] S207. Determine that the IGBT under test has latched up.

[0088] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0089] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for testing IGBT latch-up, characterized in that, This invention relates to an IGBT latch-up test circuit, which includes a control circuit, a test current generation module, a switching module, and a first current sampling module. The first output terminal of the control circuit is connected to the control terminal of the IGBT under test (GBT), and is used to output a first drive signal. The IGBT under test is turned on or off according to the first drive signal. The second output terminal of the control circuit is connected to the control terminal of the test current generation module, and is used to output a second drive signal to the test current generation module. The power supply terminal of the test current generation module is connected to a first power supply voltage. The test current generation module is connected to the IGBT under test. The test current generation module is used to generate a test current to the first terminal of the IGBT under test according to the second drive signal. The third output terminal of the control circuit is connected to the control terminal of the switching module and is used to output a third drive signal to the switching module. The power supply terminal of the switching module is connected to a second power supply voltage. The switching module is connected to the IGBT under test. The switching module is used to turn on or off according to the third drive signal, and when it is on, it connects the second power supply voltage to the first terminal of the IGBT under test. The first current sampling module is connected to the second terminal of the IGBT under test. The first current sampling module is used to sample the current of the IGBT under test and output a first current sampling signal to the first input terminal of the control circuit. The control circuit is used to determine whether the IGBT under test is latched based on the first current sampling signal. The method includes: The control circuit outputs a first drive signal from the first output terminal to the control terminal of the IGBT under test, and controls the IGBT under test to turn on according to the first drive signal. The control circuit outputs a second drive signal from the second output terminal to the control terminal of the test current generation module, and controls the test current generation module to generate a test current according to the second drive signal. After a first time interval, the control circuit outputs a third drive signal to the switching module at the third output terminal, and controls the switching module to turn on according to the third drive signal, so that the second power supply voltage is connected to the first terminal of the IGBT under test. After a second time interval, the test current generation module is controlled to stop outputting current, and the IGBT under test is controlled to disconnect. The first current sampling module is controlled to sample the current of the IGBT under test; If the first current sampling signal is greater than or equal to a preset threshold, it is determined that the IGBT under test has latched up; if the first current sampling signal is less than the preset threshold, the magnitude and duration of the test current are adjusted until the IGBT under test latches up.

2. The IGBT latch-up test method according to claim 1, characterized in that, The adjustment of the magnitude and duration of the test current includes: The magnitude of the test current is adjusted by adjusting the duty cycle of the second drive signal, and the duration of the test current is adjusted by adjusting the output time of the second drive signal.

3. The IGBT latch-up test method according to claim 1, characterized in that, The step of controlling the test current generation module to generate the test current according to the second drive signal includes: The second current sampling module is controlled to sample the test current, and the duty cycle of the second drive signal is controlled by a PID algorithm to adjust the magnitude of the test current.

4. The IGBT latch-up test method according to claim 1, characterized in that, The IGBT latch-up test circuit also includes a second current sampling module; The second current sampling module is connected between the output terminal of the test current generation module and the first terminal of the IGBT under test, and is used to sample the test current and feed back the second current sampling signal to the second input terminal of the control circuit.

5. The IGBT latch-up test method according to claim 1, characterized in that, The test current generation module includes: a first transistor, a first resistor, and a second resistor; The first end of the first resistor serves as the control terminal of the test current generating module, and the second end of the first resistor is connected to the control terminal of the first transistor; the first end of the first transistor serves as the power supply terminal of the test current generating module, and the second end of the first transistor serves as the output terminal of the test current generating module; the second resistor is connected between the control terminal of the first transistor and the second end of the first transistor.

6. The IGBT latch-up test method according to claim 5, characterized in that, The first transistor includes a MOSFET, and the second drive signal includes a PWM signal; the MOSFET is used to output a test current according to the second drive signal and the first power supply voltage.

7. The IGBT latch-up test method according to claim 1, characterized in that, The switching module includes a second transistor, a third resistor, and a fourth resistor; The first end of the third resistor serves as the control terminal of the switching module, the second end of the third resistor is connected to the control terminal of the second transistor, the first end of the second transistor serves as the power supply terminal of the switching module, the second end of the second transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the first end of the IGBT under test.

8. The IGBT latch-up test method according to claim 3 or 4, characterized in that, The first current sampling module includes a first sampling resistor and a first current sampling unit; The first end of the first sampling resistor is connected to the second end of the IGBT under test, and the second end of the first sampling resistor is grounded. The first input terminal of the first current sampling unit is connected to the first terminal of the first sampling resistor, and the second input terminal of the first current sampling unit is connected to the second terminal of the first sampling resistor. The first current sampling unit is used to obtain the current of the IGBT under test according to the voltage across the first sampling resistor, and output a first current sampling signal to the first input terminal of the control circuit. The second current sampling module includes a second sampling resistor and a second current sampling unit; The first end of the second sampling resistor is connected to the output end of the test current generation module, and the second end of the second sampling resistor is connected to the first end of the IGBT under test. The first input terminal of the second current sampling unit is connected to the first terminal of the second sampling resistor, and the second input terminal of the second current sampling unit is connected to the second terminal of the second sampling resistor. The second current sampling unit is used to obtain the test current based on the voltage across the second sampling resistor and output a second current sampling signal to the second input terminal of the control circuit.

9. The IGBT latch-up test method according to claim 8, characterized in that, The control circuit includes a control module, a first drive module, a second drive module, and a third drive module; The first driving module is connected to the control module, and the output terminal of the first driving module serves as the first output terminal of the control circuit. The first driving module is used to generate a first driving signal according to the first control signal output by the control module, and output it to the control terminal of the IGBT under test. The second drive module is connected to the control module, and the output terminal of the second drive module serves as the second output terminal of the control circuit. The second drive module is used to generate a second drive signal according to the second control signal output by the control module, and output it to the control terminal of the test current generation module. The third drive module is connected to the control module, and the output terminal of the third drive module serves as the third output terminal of the control circuit. The third drive module is used to generate a third drive signal based on the third control signal output by the control module and output it to the control terminal of the switch module. The first input terminal of the control module serves as the first input terminal of the control circuit and is used to receive the first current sampling signal; the second input terminal of the control module serves as the second input terminal of the control circuit and is used to receive the second current sampling signal.

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