A topology reconfigurable boundary scan interconnect fault detection system, method, platform and storage medium for an ICT fixture

Abstract

The application discloses a topology reconfiguration type boundary scan interconnection fault detection system, method, platform and storage medium for an ICT fixture; the scheme introduces the boundary scan technology through two groups of loopback load boards with different topologies, unifies open circuit, short circuit and misplacement faults of the ICT fixture into logical abnormalities that can be solved in the digital domain, positions the open circuit endpoints by using driving and receiving combined with two topology changes, positions the short circuit position by using bit-by-bit scanning combined with two topology comparisons, and captures the unexpected short circuit caused by misplacement by using the JTAG chip IO pin, so that the misplacement and open circuit faults can be distinguished and accurately positioned without actually powering on the to-be-tested board. Meanwhile, the analog measurement is changed into pure digital testing, the complex circuit interference is avoided, the fault detection machine can be designed in a universal manner, the load board can be reused as an aging or stress test board, the debugging cost and troubleshooting time are reduced, and the trial production efficiency and delivery quality are improved.

Description

Technical Field

[0001] This invention belongs to the field of online testing technology for electronic circuits, specifically relating to a topology reconfiguration boundary scan interconnect fault detection system, method, platform, and storage medium for ICT fixtures. Background Technology

[0002] In-Circuit Test (ICT) is a widely used electrical testing method in the manufacturing process of printed circuit board assemblies (PCBAs). ICT test equipment establishes an electrical connection between a fixture and test pads on the device under test (DUT) to measure electrical parameters and detect faults in the components on the board.

[0003] In ICT test systems, the fixture is a key component for establishing the electrical connection between the test bench and the board under test (DUT). The bottom of the fixture is an interface board with metal contacts that correspond one-to-one with the test resource array on the ICT test bench surface. When the fixture is placed into the ICT test bench, the metal contacts on the bottom of the interface board are tightly pressed against the interface array, introducing the test resources into the fixture's internal cavity. At the top of the interface board, solid pins that mate with the metal contacts are connected via wire (or welding) to the solid heads of the pin insertion points on the upper and lower mold structure plates. Test probes are inserted into the hollow heads of the pin insertion points on the upper and lower mold structure plates, and the test probes are ultimately connected to the pad points on the DUT one by one. Therefore, a complete electrical path exists between the test resource pins of the ICT test bench and the pad points on the DUT, consisting of interface board contacts, wire, solid pins, and test probes.

[0004] In the above path, a failure at any stage can lead to ICT test failure. Common failure types include open circuit failure, short circuit failure, and misalignment failure. An open circuit failure is caused by a broken wire, poor probe contact, or other reasons that break the electrical path. A short circuit failure is caused by accidental overlap between adjacent wires or solder bridging, resulting in a short circuit between paths. A misalignment failure is caused by incorrect wiring during winding, such as swapping the bottom contacts of the fixture corresponding to any two test probes on the board under test. This type of failure is particularly common in manual winding operations and is the most difficult to troubleshoot because its symptoms are similar to open circuits and short circuits.

[0005] For open circuit and short circuit faults, there are already corresponding detection methods in the existing technology. For open circuit faults, the resistance between the pins of the fixture resources can be detected by simulating the board under test with a short-circuit board (metal plate), and the open circuit can be determined based on the resistance value; for short circuit faults, the current in the path can be detected by simulating the board under test with an empty board (insulating board), and the short circuit can be determined based on the resistance value.

[0006] However, neither of the above two methods can effectively detect misalignment faults. The essence of a misalignment fault is that the mapping relationship between the contacts on the bottom interface board of the fixture and the pad points on the board under test is disordered, but the electrical continuity of each path itself is not disrupted: there is neither an open circuit nor a short circuit. Therefore, tests on both the empty board and the short-circuited board will show as passed, while the actual winding mapping relationship is incorrect.

[0007] Currently, misalignment faults can only be detected after the actual board under test (DUT) is powered on, using an ICT testing machine running a test script. Due to the complexity of the actual DUT circuitry, engineers must manually adjust isolation points, set delay times, consider the measurability of resistors, capacitors, and analog circuits, and troubleshoot parasitic impedance and poor contact (false open circuits) caused by the fixture itself. The difficulty of troubleshooting increases dramatically, especially when actual engineering problems are intertwined with fixture malfunctions. During the trial production phase of the DUT, repeated fixture refinement is often required, frequently wasting significant time on open / short circuits or misalignment issues, severely impacting trial production efficiency and product quality.

[0008] Therefore, in view of the above-mentioned technical problems and defects, there is an urgent need to design and develop a topology reconfiguration-based boundary scan interconnect fault detection system, method, platform and storage medium for ICT fixtures. Summary of the Invention

[0009] To overcome the shortcomings and difficulties of the existing technology, the present invention aims to provide a topology-reconfigurable boundary scan interconnect fault detection system, method, platform and storage medium for ICT fixtures. By introducing boundary scan technology and constructing a topology-reconfigurable test link, the invention achieves comprehensive detection and accurate location of open circuit, short circuit and misalignment faults in the internal winding path of the ICT fixture without relying on the complex circuit of the actual board under test.

[0010] The first objective of this invention is to provide a topology-reconfigurable boundary scan interconnect fault detection system for ICT fixtures; the second objective of this invention is to provide a topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures; the third objective of this invention is to provide a topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures; and the fourth objective of this invention is to provide a computer-readable storage medium.

[0011] The first objective of this invention is achieved as follows: the ICT fixture has bottom interface contacts for interfacing with external test resources, and the system includes an error detection machine with signal output terminals on its tabletop that correspond one-to-one with the bottom interface contacts; wherein the signal output terminals are used to introduce the electrical properties of the bottom interface contacts into the error detection machine.

[0012] A boundary scan link is set inside the error detection machine and includes multiple cascaded boundary scan chips; wherein, the test terminal of each boundary scan chip is electrically connected to the corresponding signal output terminal and is used to form a digital scan path from the bottom interface contact to the test terminal.

[0013] A first topology load board and a second topology load board are used to selectively and sequentially electricalally interface with the probe end of the ICT fixture during testing; wherein, the first topology load board is provided with a first pad group shorted according to a first mapping relationship; the second topology load board is provided with a second pad group shorted according to a second mapping relationship; the first mapping relationship and the second mapping relationship are mutually offset;

[0014] The boundary scan master controller is connected to the boundary scan link for communication; wherein the boundary scan master controller is used to load interconnect test vectors and collect digital response signals to the test end in response to the first state when the first topology load board is connected and the second state when the second topology load board is connected, respectively, and calculate and locate the interconnection fault of the ICT fixture based on the difference between the two collected digital response signals.

[0015] The second objective of the present invention is achieved by applying the method to the system, the method comprising the steps of:

[0016] The first topology load board is electrically connected to the probe end of the ICT fixture, and the first pad group forms a first signal loopback topology according to the first mapping relationship;

[0017] The boundary scan master controller controls the boundary scan link to load the first interconnect test vector, drives the test terminal to output the first logic signal, and collects the first digital response signal of the test terminal under the first signal loopback topology;

[0018] The first topology load board is replaced with the second topology load board and electrically connected to the probe end. The second pad group forms a second signal loopback topology according to the second mapping relationship.

[0019] The boundary scan master controller controls the boundary scan link to load the second interconnect test vector, drives the test terminal to output the second logic signal, and collects the second digital response signal of the test terminal under the second signal loopback topology;

[0020] The first digital response signal and the second digital response signal are logically compared, and the interconnection fault of the ICT fixture is located based on the migration characteristics of the abnormal signal nodes in the comparison results.

[0021] The third objective of this invention is achieved as follows: It includes a processor, a memory, and a topology-reconfigurable boundary scan interconnect (BSE) fault detection platform control program for an ICT fixture; wherein the processor executes the BSE fault detection platform control program for an ICT fixture, the BSE fault detection platform control program for an ICT fixture is stored in the memory, and the BSE fault detection platform control program for an ICT fixture implements the BSE fault detection method for an ICT fixture.

[0022] The fourth objective of this invention is achieved as follows: the computer-readable storage medium stores a control program for a topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures, and the control program for the topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures implements the topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures.

[0023] This invention introduces boundary scanning technology and constructs two sets of loopback load boards with different topologies. It unifies the three types of faults—open circuit, short circuit, and misalignment—in the internal winding path of the ICT fixture into precisely solvable logical anomalies in the digital domain. It utilizes unidirectional transmission from the driver receiver combined with two topology changes to achieve precise location of the open circuit endpoint, and employs a bit-by-bit scanning algorithm combined with two topology comparisons to achieve precise location of the short circuit. In particular, it leverages the self-transmitting and self-receiving characteristics of the JTAG protocol chip's I / O pins to capture unexpected short circuit effects between driver terminals caused by misalignment. This allows for the accurate differentiation and distinction between misalignment faults and simple open circuit faults without requiring the actual board under test to be powered on. The system also transforms the fault detection process, which originally relied on analog signal measurement and complex engineering debugging, into a purely digital interconnection test. This avoids interference factors caused by the actual resistance, capacitance, and measurable conditions of the analog circuits on the board under test, thus increasing testing speed and reducing testing complexity. In addition, the fault detection machine can be made into a universal device. It only requires redesigning the wiring of two passive topology load boards for different boards under test to adapt to different fixtures. Moreover, the load board can be reused as an aging test board or a stress test board in a non-short-circuit state. This reduces the manpower and time costs of fixture debugging while realizing the multi-functional reuse of test fixtures, thereby improving trial production efficiency and shipment quality. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the system framework for interfacing an ICT fixture with an error detection machine, according to an embodiment of the topology reconfiguration-based boundary scan interconnect fault detection system for ICT fixtures of the present invention.

[0026] Figure 2 This is a schematic diagram of the interconnection framework between the DUT board 1 and the tested resource end of the ICT fixture, as an embodiment of the topology reconfiguration boundary scan interconnection fault detection system for ICT fixtures according to the present invention.

[0027] Figure 3 This is a schematic diagram of the interconnection framework between the DUT board 2 and the tested resource end of the ICT fixture, as an embodiment of the topology reconfiguration boundary scan interconnection fault detection system for ICT fixtures according to the present invention.

[0028] Figure 4 This is a schematic diagram of the framework of a topology reconfiguration-based boundary scan interconnect fault detection system for ICT fixtures according to the present invention;

[0029] Figure 5 This is a schematic diagram of the process steps of a topology reconfiguration-based boundary scan interconnect fault detection method for ICT fixtures according to the present invention.

[0030] Figure 6 This is a schematic diagram of a topology reconfiguration-based boundary scan interconnect fault detection platform architecture for ICT fixtures according to the present invention;

[0031] Figure 7 This is a schematic diagram of a computer-readable storage medium architecture in one embodiment of the present invention. Detailed Implementation

[0032] To facilitate a clearer understanding of the objectives, technical solutions, and advantages of this invention, the invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of this invention from the content disclosed in this specification.

[0033] This invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of this invention.

[0034] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0035] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Secondly, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0036] Preferably, the topology reconfiguration-based boundary scan interconnect fault detection method for ICT fixtures of the present invention is applied in one or more terminals or servers. The terminal is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0037] The terminal can be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal can interact with the customer via a keyboard, mouse, remote control, touchpad, or voice control device.

[0038] This invention provides a topology-reconfigurable boundary scan interconnect fault detection system, method, platform, and storage medium for ICT fixtures.

[0039] like Figure 5 The diagram shown is a flowchart of a topology reconfiguration-based boundary scan interconnect fault detection method for ICT fixtures provided in an embodiment of the present invention.

[0040] In this embodiment, the topology reconfiguration-based boundary scan interconnect fault detection method for ICT fixtures can be applied to terminals or fixed terminals with display functions. The terminals are not limited to personal computers, smartphones, tablets, desktop computers or all-in-one computers with cameras, etc.

[0041] The topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures can also be applied to a hardware environment consisting of a terminal and a server connected to the terminal via a network. The network includes, but is not limited to, a wide area network (WAN), a metropolitan area network (MAN), or a local area network (LAN). The topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures in this embodiment can be executed by the server, by the terminal, or by both the server and the terminal.

[0042] For example, for a terminal requiring topology-reconfigurable boundary scan interconnect (BSE) fault detection for ICT fixtures, the BSE fault detection function provided by the method of this invention can be directly integrated onto the terminal, or a client for implementing the method of this invention can be installed. Alternatively, the method provided by this invention can also run on servers or other devices in the form of a Software Development Kit (SDK), providing an interface for the BSE fault detection function for ICT fixtures. Terminals or other devices can then implement the BSE fault detection function for ICT fixtures through the provided interface. The invention will be further described below with reference to the accompanying drawings.

[0043] like Figures 1-4 As shown, the present invention provides a topology reconfiguration-based boundary scan interconnect fault detection system for ICT fixtures. The ICT fixture has bottom interface contacts for interfacing with external test resources. The system includes a fault detection machine with signal output terminals on its tabletop that correspond one-to-one with the bottom interface contacts. The signal output terminals are used to introduce the electrical properties of the bottom interface contacts into the fault detection machine.

[0044] A boundary scan link is set inside the error detection machine and includes multiple cascaded boundary scan chips; wherein, the test terminal of each boundary scan chip is electrically connected to the corresponding signal output terminal and is used to form a digital scan path from the bottom interface contact to the test terminal.

[0045] A first topology load board and a second topology load board are used to selectively and sequentially electricalally interface with the probe end of the ICT fixture during testing; wherein, the first topology load board is provided with a first pad group shorted according to a first mapping relationship; the second topology load board is provided with a second pad group shorted according to a second mapping relationship; the first mapping relationship and the second mapping relationship are mutually offset;

[0046] The boundary scan master controller is connected to the boundary scan link for communication; wherein the boundary scan master controller is used to load interconnect test vectors and collect digital response signals to the test end in response to the first state when the first topology load board is connected and the second state when the second topology load board is connected, respectively, and calculate and locate the interconnection fault of the ICT fixture based on the difference between the two collected digital response signals.

[0047] The signal output terminal is an elastic conductor disposed within the error detection machine; wherein, one end of the elastic conductor extends out of the platform for pressing and contacting the bottom interface contact, and the other end is connected to the test terminal of the boundary scan chip.

[0048] The test terminal of the boundary scan chip is configured as a bidirectional input / output pin with self-transmission and self-reception function, and each pin has a built-in pull-up element to maintain a high level when there is no external drive.

[0049] The first mapping relationship is to short-circuit the pads with adjacent serial numbers in the first pad group; the second mapping relationship is to short-circuit the pads with serial numbers that differ by a preset positive integer in the second pad group.

[0050] Specifically, in this embodiment of the invention, to achieve the goal of comprehensive detection of open circuit, short circuit, and misalignment faults in the ICT fixture, boundary scan technology is introduced, and a testable connection based on pure interconnection of JTAG protocol chip IO pins is constructed. The ICT fixture can be tightly pressed with the ICT machine interface array through the metal contacts at the bottom of the interface board. Only a fault detection machine that is 1:1 adapted to the pin resources of the ICT tabletop needs to be designed. This invention is called a boundary scan ICT fault detection machine (hereinafter referred to as fault detection machine). The metal contact resources at the bottom of the ICT fixture interface board are introduced into the fault detection machine, and a testable connection based on pure interconnection of JTAG protocol chip pins is realized inside the fault detection machine.

[0051] like Figure 1 As shown, the error detection machine platform is the same as the ICT test machine platform. When the ICT fixture is placed on the error detection machine platform, the metal contacts p1 to p9...pm on the bottom of the ICT fixture interface board are introduced 1:1 onto the solid pins on the bottom of the error detection machine platform. By winding wire around each solid pin, the other end of the wire can be gathered and assigned to the connector. The connector is then connected to the boundary scan test cards 1 to 3...n (referred to as BS test cards, which contain JTAG protocol chips). This connects the metal contact resource pins on the bottom of the ICT fixture interface board to the signal IO pins of the BS test cards. The BS test cards 1 to 3...n are connected in a daisy chain via the JTAG bus, finally converging to the boundary scan controller, and finally connected to the UI via the local area network.

[0052] TP1 to TP9...TPm are test probes that interface with the DUT pad points. Considering that the test probes are isolated from each other, there is no signal loop between them. In order to achieve the testing purpose, it is necessary to design the test probes to connect to the IO pins of the JTAG protocol chip.

[0053] To achieve this design, the present invention introduces a simulated DUT board and considers placing a JTAG protocol chip inside the simulated DUT board. This design requires consideration of selection, surface mount process, power supply to the chip at the DUT end, and surface mount interference issues. The design is complex and has a long cycle. This method is feasible for testing customized ICT fixtures but is not user-friendly.

[0054] The metal contact resources at the bottom of the ICT fixture interface board are connected to the JTAG protocol chip's IO pins. In the field of boundary scan, the IO pins with self-transmitting and self-receiving capabilities are INOUT pins. For ordinary JTAG protocol chips, such as ARM, CPLD, FPGA, etc., their IO pins are basically INOUT pins. In addition, all IO pins of the JTAG protocol chip are weakly pulled up by default, keeping them in the default high-level 1 state, providing a feasible foundation for the implementation of boundary scan technology in the ICT fixture.

[0055] Based on the above embodiments, in another embodiment of the present invention, such as Figure 2 As shown, to simplify the design and reduce costs, the present invention simulates the design of connecting the pad point of the DUT to the JTAG protocol chip I / O, and adopts the following technical solution, which combines... Figure 1 and Figure 2 Comprehensive analysis;

[0056] Based on the actual DUT netlist and coordinate file, extract the actual pad point names, quantities, and location information, such as... Figure 2 As shown, the number of pad points is m. Since the pad point positions, numbers, and names are different for different DUTs, this invention highlights the core and simplifies the actual DUT pad point names to pd1 to pdm. m can represent any number, and pd1 to pdm represent the pad points that are flexibly distributed in the actual DUT locations.

[0057] A pre-designed simulated DUT board 1 (i.e., the first topology load board) is placed at the DUT end. The pad points pd1 to pdm of the simulated DUT board 1 are identical in name, quantity, and position to the actual DUT pad points. And just like the actual DUT, the pd1 to pdm of the simulated DUT board 1 are completely connected to the test probes TP1 to TPm at the DUT end.

[0058] The loopback design of the simulated DUT board 1 is as follows: On the simulated DUT board 1, pad points pd1 and pd2, pd3 and pd4 are shorted, and so on, until pd7 and pd8 are shorted. Since 9 is an odd number, pd9 is not shorted. Extending to pdm, when m is an even number, pad points pd(m-1) and pdm are shorted. When m is an odd number, pad points pd(m-2) and pd(m-1) are shorted. pdm is isolated and not shorted. The above realizes the loopback shorting of the internal test probes TP1 and TP2, TP3 and TP4, ... of the ICT fixture, thereby realizing the loopback shorting of the solid pin points P1 and P2, P3 and P4, ... of the upper and lower mold structures of the ICT fixture, and thus realizing the loopback shorting of the metal contact resources p1 and P2, P3 and P4, ... of the bottom of the interface board of the ICT fixture.

[0059] Based on the test of the simulated DUT board 1, the specific implementation steps are as follows:

[0060] Step 1: Place the simulated DUT board 1 into the ICT fixture. After the pad points of the simulated DUT board 1 are pressed against the test probes, place the ICT fixture onto the error detection machine table and power it on.

[0061] Step 2: Perform the first open-circuit fault test on the ICT fixture. The test method is as follows:

[0062] By controlling the JTAG daisy chain, the pins of the JTAG protocol chips corresponding to the odd-numbered contact resources p1, p3, p5, p7, p9... at the bottom of the fixture are driven low (0). All even-numbered contact resources p2, p4, p6, p8... corresponding to the I / O pins of the JTAG protocol chips receive low-level (0) drives from p1, p3, p5, p7... respectively. If all pins receive low-level (valid) (0), it indicates that there is no open-circuit fault between the pairs of loopback contacts p1 and p2, p3 and p4, p5 and p6, p7 and p8... on the bottom interface board of the ICT fixture. Otherwise, an open-circuit fault exists. Figure 1 and Figure 2 If an open circuit fault occurs at p1, p2 will not receive a valid low level 0 and can only receive the default high level 1, indicating that there is an open circuit between p1 and p2. However, for the open circuit fault of p1 in the figure, this test cannot effectively locate whether it is an open circuit fault of p1 or p2. In addition, p9 is an odd number, and the open circuit of its path cannot be tested at present. Extending to, when m is an odd number, pm is implemented according to this method. pm combined with the open circuit test of simulated DUT board 1 cannot achieve the same result. When m is an even number, the path of m participates in the loopback of simulated DUT board 1, which does not need to be discussed.

[0063] Step 3: Perform the first short-circuit fault test and the first misalignment fault test on the ICT fixture.

[0064] The test method for short-circuit faults is as follows:

[0065] By controlling the daisy chain of the BS chip, and following a certain algorithm, theoretically, it is only necessary to ensure that, under the same driving data, any two contacts p1, p3, p5, p7, p9... can always find staggered driving level data (0 and 1) between them.

[0066] This invention uses a zero-step algorithm for driving. Table 1 shows the zero-step algorithm list. The odd-numbered contacts p1, p3, p5, p7, p9... are driven one by one according to the zero-step algorithm to output the corresponding level data. The pins of the JTAG chip corresponding to p2, p4, p6, p8,... receive the level data of each drive output in sequence. If the received level data is the same as the expected drive output level data, it indicates that there is no short circuit fault between p1 and p2, p3 and p4, p5 and p6, p7 and p8, p9... the last isolated contact (which may exist, depending on whether m is odd or even) and the other pairs of contacts.

[0067] If there is no open circuit fault in the path of p1, but a short circuit fault exists between p2 and p3, then after the second and first drive level data are sent, the JTAG chip pins corresponding to p4 and p2 will receive 0 respectively, which is not the expected value of 1. This indicates that there is a short circuit fault between p1 and p2 and between p3 and p4. It is not possible to effectively locate whether the short circuit fault occurs between p1 and p3 or p4, or between p2 and p3 or p4. If there is an open circuit fault in the path of p1, and there is a short circuit fault between p2 and p3, after the second drive data is sent, the JTAG chip pin corresponding to p2 will receive 0, which is not the expected value of 1. This indicates that there is a short circuit fault between p2 and p3 or p4. It is not possible to effectively locate whether the short circuit fault occurs between p2 and p3 or p4.

[0068] When m is odd, although the contact pm is isolated and does not form a loop relationship with other contacts, pm should still participate in the zero-running algorithm. As long as a related fault occurs, it can be located, just like the judgment method of other drive output contacts.

[0069] In addition, the misalignment fault detection method is as follows:

[0070] When the test probes pd6 and pd7 on the DUT are located, due to human error in wiring, the contacts p6 and p7 on the bottom interface board of the fixture are incorrectly connected to the test probe positions pd7 and pd6, respectively. If only the above short-circuit test is performed, the fault cannot be effectively located. The analysis is as follows:

[0071] After the third 0 transmission from the JTAG chip I / O located at p5, the JTAG chip I / O located at p6 did not receive a valid low level 0, and instead received a high level 1. After the fourth 0 transmission from the JTAG chip I / O located at p7, the JTAG chip I / O located at p8 also did not receive a valid low level 0, and instead received a high level 1. Although the JTAG chip I / O located at p6 and p8 received the fault, the JTAG chip I / O located at p5 and p7, as drivers, could not bring out the fault. Therefore, it was impossible to locate the misalignment fault caused by the JTAG chip I / O located at p5 and p7 as drivers.

[0072] To effectively locate misalignment faults, a zero-stepping algorithm is employed. Besides controlling the JTAG daisy chain to execute the zero-stepping algorithm, making the JTAG chip I / O pins of contacts p1, p3, p5, p7, p9... drive the operation, all JTAG chip I / O pins of contacts p1, p3, p5, p7, p9... are INOUT pins, performing self-transmission and self-reception. This also ensures that the loopback path of the simulated DUT board 1 will not simultaneously drive 0 and 1, improving test safety. The specific method is as follows:

[0073] Based on the fault scenario, after the third 0 transmission from the JTAG chip I / O located at p5, the JTAG chip I / O located at p6, which loops back with p5, received a high level 1, which is not expected. After the fourth 0 transmission from the JTAG chip I / O located at p7, the JTAG chip I / O located at p8 also received a high level 1, which is also not expected. Although the JTAG chip I / Os located at p6 and p8 received fault signals, it cannot be concluded that the fault was caused by the JTAG chip I / Os located at p5 and p7. Therefore, the misalignment fault cannot be effectively located. To effectively locate the misalignment fault, further testing is required based on this information.

[0074] Misalignment testing and short-circuit testing can be performed simultaneously. The specific methods for effectively locating misalignment faults are as follows:

[0075] If the JTAG chip I / O of p5 and p7 not only acts as the driver but also performs self-transmission and self-reception, the problem can be effectively solved. The misalignment fault will cause a short circuit between p5 and p7. At this time, after the JTAG chip I / O of p5 and p7 is driven according to the 1-step algorithm, it performs self-transmission and self-reception. That is, after the JTAG chip I / O of p5 and p7 sends the 3rd and 4th data, it receives two low-level 0s. The fault is in line with the expectation of the 0-step algorithm. Combined with the loopback connection between p5 and p6 and p7 and p8 through the simulated DUT board 1, the faults of p5, p6, p7 and p8 are closely associated together.

[0076] In summary, after the 3rd and 4th data entries, the JTAG chip I / O pins of p6 and p8 received all 1s, which was not as expected. Furthermore, after the 3rd and 4th data entries, the JTAG chip I / O pins of p5 and p7 received the same low level 0 twice. At this point, a misalignment fault was effectively located among p5, p6, p7, and p8.

[0077] Table 1: Algorithm for Moving to 0

[0078] project p1 p3 p5 p7 p9 ... pm 1st Transaction 0 1 1 1 1 1 1 2nd stroke 1 0 1 1 1 1 1 The third stroke 1 1 0 1 1 1 1 4th stroke 1 1 1 0 1 1 1 5th stroke 1 1 1 1 0 1 1 The... 1 1 1 1 1 0 1 The mth stroke 1 1 1 1 1 1 0

[0079] In another embodiment of the present invention, such as Figure 3 As shown, combined with Figures 1 to 2 After testing the simulated DUT board 1, some faults may not have been detected or effectively located. Testing the simulated DUT board 2 (i.e., the second topology load board) will provide comprehensive coverage and effective location of these faults. The overall technical solution will combine... Figures 1 to 3 Comprehensive analysis;

[0080] Similarly combined Figure 2 and Figure 3 As shown, the positions, number, and names of the pad points on DUT board 2 and board 1 are the same, so they will not be repeated here.

[0081] The loopback design for simulated DUT board 2 is as follows: The difference between the loopback design of simulated DUT board 2 and simulated DUT board 1 is that the pad points are misaligned by one position, and the loopback path is re-established. On simulated DUT board 2, pad points pd2 and pd3, pd3 and pd4, and so on, up to pd8 and pd9. pd1 is not involved in the short circuit. Since 9 is an odd number, pd9 is involved in the short circuit, extending to pdm. When m is an even number, pad point pd(m-2) is finally shorted. And pd(m-1), pdm does not participate in the short circuit. When m is odd, the pad points pd(m-1) and pd(m) are shorted last; thus realizing the loopback short circuit of the internal test probes TP2 and TP3, TP4 and TP5, ... of the ICT fixture, thus realizing the loopback short circuit of the solid pin points P2 and P2, P3 and P4, ... of the upper and lower mold structures of the ICT fixture, thus realizing the loopback short circuit of the metal contact resources p1 and p3, p4 and p5, ... of the bottom of the interface board of the ICT fixture.

[0082] The specific implementation steps, based on the test of the simulated DUT board 2, are as follows:

[0083] Step 1: After the simulated DUT board 1 is tested, remove it from the fixture and put in the simulated DUT board 2. After the pad point of the simulated DUT board 2 is pressed with the test probe, place the ICT fixture on the error detection machine table and power it on.

[0084] Step 2: Perform a second open-circuit fault test on the ICT fixture. The test method is as follows:

[0085] Similarly, drive the JTAG protocol chip pins corresponding to the odd-numbered contact resources p1, p3, p5, p7, p9... at the bottom of the fixture to a low level (0). For all even-numbered contact resources p2, p4, p6, p8..., the corresponding JTAG protocol chip IO pins should receive a low level (0) driven by p3, p5, p7, p9... respectively. If all receive a low level (valid level), it indicates that there is no open circuit fault between the loopback contacts p2 and p3, p4 and p5, p6 and p7, p8 and p9... on the bottom interface board of the ICT fixture. Otherwise, an open circuit fault exists. As shown in the figure, the open circuit fault corresponding to position p1 cannot be detected by only considering DUT board 2; a comprehensive analysis of DUT board 1 is required as follows:

[0086] Based on the previous test of simulated DUT board 1, an open circuit fault was detected between p1 and p2, but it was not possible to effectively locate whether the open circuit fault was in p1 or p2. By combining simulated test board 2, p2 and p3 were re-formed into a loopback path, and it was found that there was no open circuit between p2 and p3. Therefore, the open circuit fault was located to p1. After the fault was located, the path of p1 was investigated and repaired. 9 is an odd number, and the path of p9 can be used to loop back and test for open circuit faults. The test of simulated DUT board 2 was placed, and the analysis of the open circuit fault location of p9 was the same as that of p1, except that the loopback paths were distributed on simulated DUT board 1 and board 2 respectively. However, p9 is more special than p1 because both open circuit and misalignment faults occur at the same time. The paths of p8 and p9 were investigated. If the paths are not open circuits, it means that the fault is not caused by an open circuit fault.

[0087] Step 3: Perform the second short-circuit fault test and the second misalignment fault test on the ICT fixture. The short-circuit fault test method is as follows: Similarly, execute the zero-running algorithm in Table 1, and drive the odd-numbered contacts p1, p3, p5, p7, p9... one by one according to the zero-running algorithm to output the corresponding data level. The corresponding JTAG chip pins p2, p4, p6, p8,... receive the level data of each drive output in sequence. If the received level data is the same as the expected drive output level data, it indicates that there is no short-circuit fault between the first and last isolated contacts (which may exist, depending on whether m is odd or even) of p1, p2 and p3, p4 and p5, p6 and p7, p8 and p9... and between other pairs of contacts.

[0088] A short circuit fault exists between p2 and p3, which is affected by the loopback of DUT board 2. If only the test results simulating DUT board 2 are considered, the fault cannot be detected. Therefore, a comprehensive analysis is needed, combining the test results simulating DUT board 1 as follows:

[0089] Based on the results of the two tests, it was found that there was a short circuit fault between p2 and p3 and p4, but it was not clear whether the short circuit fault was between p2 and p3 or p4, so the problem could not be effectively located. Based on the results of the two tests, it was found that there was no short circuit fault between p2 and p3 and between p4 and p5. Based on the results of the two tests, it can be determined that there is no short circuit fault between p2 and p4, and the short circuit fault is located between p2 and p3. After the fault is located, the short circuit path between p2 and p3 is investigated and repaired.

[0090] In the loopback path of the simulated DUT board 2, although contact p1 is isolated and does not form a loopback relationship with other contacts, p1 should still participate in the zero-run algorithm drive. The method is the same as the judgment method of other drive output contacts. As long as an associated fault occurs, it can be located.

[0091] The misalignment fault test method is as follows: In the loopback path of the simulated DUT board 2, the DUT end test probes pd7 and pd6 are designed to loop back. The misalignment fault problem at the corresponding contact pd6 and pd7 will not be detected. However, when analyzing the simulated DUT board 1, the fault can be effectively located. The misalignment fault analysis method of the simulated DUT board 2 is the same as the analysis method of the simulated DUT board 1. It is a misalignment fault test with complementary effects. The combination of the two tests achieves comprehensive misalignment detection.

[0092] Combination Figure 2 and Figure 3 As shown, the path where the p9 contact is located is represented by a dashed line to indicate that the path where the odd number is located may or may not exist, depending on whether m is odd or even. However, the implementation of this invention is compatible in any case.

[0093] The present invention simulates DUT board 1 and board 2, providing two loopback scenarios. The two loopback tests complement each other. DUT board 1 and board 2 are placed at the DUT end of the ICT fixture and tested separately. This can effectively locate open, short, and miswiring faults in the ICT test fixture from all aspects.

[0094] This invention ensures that the simulated DUT board 1 and board 2 are implemented separately, while taking into account the consistency of the execution algorithm. The only difference is the difference in the expected value of the pins. Based on the connection of the two simulated DUTs, two different expected values ​​can be obtained respectively, which supports the testing of this invention.

[0095] The boundary scanning ICT error detection machine of the present invention can be made into a fixed and universal error detection machine. Later, depending on the different DUTs, matching simulated DUT boards 1 and 2 bare boards can be designed to realize the machine.

[0096] This invention uses only two types of bare boards, looping back from the original pad points. The design is simple and cost-effective. Combining the testing of these two types of bare boards, the overall solution can effectively locate open circuits, short circuits, and misalignment faults in ICT fixtures.

[0097] This invention simplifies fault testing of ICT fixtures by introducing boundary scan technology and using JTAG daisy chain to transform the original analog test into a purely interconnected digital test. The test speed is fast and solves the problem that existing ICT fixtures cannot effectively locate misalignment faults.

[0098] The present invention provides simulated DUT plates 1 and 2 designed for specific DUTs. These plates can be designed to have the same positioning holes, size, and thickness as the actual DUTs. The simulated DUT plates 1 and 2 can not only be used for testing the scheme of the present invention, but also as aging test plates and stress test plates. In particular, the advantages of using bare plates as stress plates are self-evident.

[0099] To achieve the above objectives, the present invention also provides a topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures, such as... Figure 5 As shown, the method is applied to the system, and the method includes the following steps:

[0100] S01. Electrically connect the first topology load board to the probe end of the ICT fixture, and form a first signal loopback topology according to the first mapping relationship;

[0101] S02. The boundary scan master controller controls the boundary scan link to load the first interconnect test vector, drives the test terminal to output the first logic signal, and collects the first digital response signal of the test terminal under the first signal loopback topology.

[0102] S03. Replace the first topology load board with the second topology load board and electrically connect it to the probe end. The second pad group forms a second signal loopback topology according to the second mapping relationship.

[0103] S04. The boundary scan master controller controls the boundary scan link to load the second interconnect test vector, drives the test terminal to output the second logic signal, and collects the second digital response signal of the test terminal under the second signal loopback topology;

[0104] S05. Perform a logical comparison between the first digital response signal and the second digital response signal, and locate the interconnection fault of the ICT fixture based on the migration characteristics of the abnormal signal nodes in the comparison result.

[0105] In the embodiments of the present invention, the functional modules involved in the topology reconfiguration boundary scan interconnection fault detection for ICT fixtures have been described in detail above and will not be repeated here.

[0106] To achieve the above objectives, the present invention also provides a topology reconfiguration-based boundary scan interconnect fault detection platform for ICT fixtures, such as... Figure 6 As shown, the system includes a processor, a memory, and a control program for a topology-reconfigurable boundary scan interconnect (BSE) fault detection platform for an ICT fixture. The processor executes the control program, which is stored in the memory. The control program implements the steps of the topology-reconfigurable BSE fault detection method for the ICT fixture. The specific details of these steps have been described above and will not be repeated here.

[0107] In this embodiment of the invention, the built-in processor of the topology reconfigurable boundary scan interconnect fault detection platform for ICT fixtures can be composed of integrated circuits. For example, it can be composed of a single packaged integrated circuit, or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor connects various components using various interfaces and lines, and executes programs or units stored in memory, as well as calling data stored in memory, to perform various functions of topology reconfigurable boundary scan interconnect fault detection for ICT fixtures and process data.

[0108] The memory is used to store program code and various data. It is installed in the topology reconfiguration boundary scan interconnect fault detection platform for ICT fixtures and enables high-speed, automatic access to programs or data during operation. The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0109] To achieve the above objectives, the present invention also provides a computer-readable storage medium, such as... Figure 7 As shown, the computer-readable storage medium stores a control program for a topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures. The control program for the topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures implements the steps of the topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures. The specific details of the steps have been described above and will not be repeated here.

[0110] In the description of embodiments of the present invention, it should be noted that any process or method description in the flowcharts or otherwise described herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0112] This invention introduces boundary scanning technology and constructs two sets of loopback load boards with different topologies. It unifies the three types of faults—open circuit, short circuit, and misalignment—in the internal winding path of the ICT fixture into precisely solvable logical anomalies in the digital domain. It utilizes unidirectional transmission from the driver receiver combined with two topology changes to achieve precise location of the open circuit endpoint, and employs a bit-by-bit scanning algorithm combined with two topology comparisons to achieve precise location of the short circuit. In particular, it leverages the self-transmitting and self-receiving characteristics of the JTAG protocol chip's I / O pins to capture unexpected short circuit effects between driver terminals caused by misalignment. This allows for the accurate differentiation and distinction between misalignment faults and simple open circuit faults without requiring the actual board under test to be powered on. The system also transforms the fault detection process, which originally relied on analog signal measurement and complex engineering debugging, into a purely digital interconnection test. This avoids interference factors caused by the actual resistance, capacitance, and measurable conditions of the analog circuits on the board under test, thus increasing testing speed and reducing testing complexity. In addition, the fault detection machine can be made into a universal device. It only requires redesigning the wiring of two passive topology load boards for different boards under test to adapt to different fixtures. Moreover, the load board can be reused as an aging test board or a stress test board in a non-short-circuit state. This reduces the manpower and time costs of fixture debugging while realizing the multi-functional reuse of test fixtures, thereby improving trial production efficiency and shipment quality.

[0113] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A topology-reconfigurable boundary scan interconnect fault detection system for an ICT fixture, the ICT fixture having bottom interface contacts for interfacing with external test resources, characterized in that, The system includes an error detection machine with signal output terminals on its platform that are pressed together with the bottom interface contacts one by one; wherein, the signal output terminals are used to introduce the electrical properties of the bottom interface contacts into the error detection machine. A boundary scan link is set inside the error detection machine and includes multiple cascaded boundary scan chips; wherein, the test terminal of each boundary scan chip is electrically connected to the corresponding signal output terminal and is used to form a digital scan path from the bottom interface contact to the test terminal. A first topology load board and a second topology load board are used to selectively and sequentially electricalally interface with the probe end of the ICT fixture during testing; wherein, the first topology load board is provided with a first pad group shorted according to a first mapping relationship; the second topology load board is provided with a second pad group shorted according to a second mapping relationship; the first mapping relationship and the second mapping relationship are mutually offset; The boundary scan master controller is connected to the boundary scan link for communication; wherein the boundary scan master controller is used to load interconnect test vectors and collect digital response signals to the test end in response to the first state when the first topology load board is connected and the second state when the second topology load board is connected, respectively, and calculate and locate the interconnection fault of the ICT fixture based on the difference between the two collected digital response signals.

2. The topology reconfiguration-based boundary scan interconnect fault detection system for ICT fixtures according to claim 1, characterized in that, The signal output terminal is an elastic conductor disposed within the error detection machine; wherein, one end of the elastic conductor extends out of the platform for pressing and contacting the bottom interface contact, and the other end is connected to the test terminal of the boundary scan chip.

3. A topology-reconfigurable boundary scan interconnect fault detection system for ICT fixtures according to claim 1 or 2, characterized in that, The test terminal of the boundary scan chip is configured as a bidirectional input / output pin with self-transmission and self-reception function, and each pin has a built-in pull-up element to maintain a high level when there is no external drive. The first mapping relationship is to short-circuit the pads with adjacent serial numbers in the first pad group; the second mapping relationship is to short-circuit the pads with serial numbers that differ by a preset positive integer in the second pad group.

4. A method for topology reconfiguration-based boundary scan interconnect fault detection for ICT fixtures, wherein the method is applied to the system described in any one of claims 1 to 3, characterized in that, The method includes: The first topology load board is electrically connected to the probe end of the ICT fixture, and the first pad group forms a first signal loopback topology according to the first mapping relationship; The boundary scan master controller controls the boundary scan link to load the first interconnect test vector, drives the test terminal to output the first logic signal, and collects the first digital response signal of the test terminal under the first signal loopback topology; The first topology load board is replaced with the second topology load board and electrically connected to the probe end. The second pad group forms a second signal loopback topology according to the second mapping relationship. The boundary scan master controller controls the boundary scan link to load the second interconnect test vector, drives the test terminal to output the second logic signal, and collects the second digital response signal of the test terminal under the second signal loopback topology; The first digital response signal and the second digital response signal are logically compared, and the interconnection fault of the ICT fixture is located based on the migration characteristics of the abnormal signal nodes in the comparison results.

5. The method for topology reconfiguration-based boundary scan interconnect fault detection for ICT fixtures according to claim 4, characterized in that, The interconnection faults include open circuit faults, short circuit faults, and misalignment faults; The step of logically comparing the first digital response signal with the second digital response signal and locating the interconnection fault of the ICT fixture based on the migration characteristics of the abnormal signal nodes in the comparison result further includes the following steps: If both the first digital response signal and the second digital response signal indicate an anomaly in the same signal transmission path, then based on the difference in attribution of the receiving node in the path according to the first mapping relationship and the second mapping relationship, the anomaly is defined as an open-circuit fault or a misalignment fault.

6. The method for topology reconfiguration-based boundary scan interconnect fault detection for ICT fixtures according to claim 4, characterized in that, When loading the first interconnect test vector or the second interconnect test vector, the preset driving node in the test terminal is driven to output the test level specified by the current scan position, and the actual level of the preset receiving node in the test terminal is read. If the actual voltage level does not match the test voltage level, then the corresponding path is marked as having an open circuit anomaly. By combining the migration of the open-circuit fault corresponding path in the two tests under the first mapping relationship and the second mapping relationship, the specific endpoint of the open-circuit fault can be located.

7. A method for topology reconfiguration-based boundary scan interconnect fault detection for ICT fixtures according to claim 4 or 6, characterized in that, Both the first interconnect test vector and the second interconnect test vector are bit-by-bit test level scanning sequences; wherein, at each scan bit, the current bit node in the preset driving node outputs the first test level, and the remaining nodes output the second test level; When loading the bit-by-bit test level scanning sequence, each preset driving node is controlled to perform self-transmission and self-reception while outputting a level; if the self-transmission and self-reception level of the preset driving node does not match the currently output first test level or second test level, or the readback level of the preset receiving node does not match the current output level of the preset driving node, then the corresponding node combination is marked as having a short circuit or misalignment anomaly.

8. The method for topology reconfiguration-based boundary scan interconnect fault detection for ICT fixtures according to claim 7, characterized in that, For the marked short circuit or misalignment anomaly, if the associated node in the node combination is offset in position under the first signal loopback topology and the second signal loopback topology, the fault type is located as misalignment fault, and a misalignment path indication is output according to the direction and amount of the offset. Both the first topology load board and the second topology load board are passive printed circuit boards; wherein, the outline, positioning structure and pad layout of the first topology load board and the second topology load board are adapted to the probe end of the test fixture. The non-short-circuit pads of the first and second topology load boards also serve as components of stress test boards or aging test boards.

9. A topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures, characterized in that, The system includes a processor, a memory, and a topology-reconfigurable boundary scan interconnect (BSE) fault detection platform control program for an ICT fixture. The processor executes the BSE fault detection platform control program for an ICT fixture, which is stored in the memory. The BSE fault detection platform control program for an ICT fixture implements the BSE fault detection method for an ICT fixture as described in any one of claims 4 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a control program for a topology-reconfigurable boundary scan interconnect fault detection platform for ICT fixtures, which implements the topology-reconfigurable boundary scan interconnect fault detection method for ICT fixtures as described in any one of claims 4 to 8.

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