A circuit testing method, apparatus, device and medium

Abstract

The application discloses a circuit test method, device, equipment and medium in the computer technology field. According to the test case exclusive to each measured module in the measured circuit, and with a plurality of interrupt signals of fixed timing, the automatic configuration of the registers of each measured module is completed, which can avoid the problems of manual configuration errors and timing disorder, and improve the accuracy and consistency of register configuration. After the test of each measured module is completed, the test comparison information corresponding to each measured module is recorded according to the matching comparison mode of each measured module, and a test report including the test comparison information is generated. Thus, the accuracy of the test comparison information is improved by adapting to the test judgment requirements of different modules, and the test period is effectively shortened, so that the circuit test efficiency and test accuracy can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a circuit testing method, apparatus, device, and medium. Background Technology

[0002] In the research and development of integrated circuits (such as FPGAs), verification testing is a crucial step in ensuring their functional correctness, stability, and reliability. Integrated circuits are typically complex, with diverse test case formats required for each functional module. Manual register configuration is also necessary, leading to a large workload and a high risk of errors, thus impacting testing efficiency and accuracy.

[0003] Therefore, how to improve the efficiency and accuracy of circuit testing is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a circuit testing method, apparatus, device and medium to improve circuit testing efficiency and accuracy.

[0005] In a first aspect, this application provides a circuit testing method, including: Obtain the test cases corresponding to each module under test in the circuit under test; For each module under test, the registers of the corresponding module under test are automatically configured according to the test cases corresponding to the module under test, using multiple interrupt signals with fixed timing. After each module under test is tested, the test comparison information corresponding to each module under test is recorded according to the comparison method matched by each module under test. Generate a test report that includes test comparison information.

[0006] Preferably, before automatically configuring the registers of the corresponding module under test, the method further includes: The pre-set scripts are used to convert the test cases corresponding to each module under test into the target format.

[0007] Preferably, according to the test cases corresponding to the module under test, the registers of the corresponding module under test are automatically configured using multiple interrupt signals with fixed timing, including: Determine the correspondence between multiple interrupt signals and multiple registers in the corresponding module under test; According to a fixed timing sequence and correspondence, the corresponding configuration parameters are read from the test cases corresponding to the module under test, and the configuration parameters are written into the corresponding registers.

[0008] Preferably, the test comparison information corresponding to each tested module is recorded according to the comparison method matched for each tested module, including: Query the comparison methods for each module under test; According to the comparison method found, the actual test data and expected data of the corresponding module under test are compared, and the test comparison information is recorded.

[0009] Preferably, the comparison method corresponding to any module under test includes at least one or a combination of the following: bitmask comparison, tolerance interval comparison, and byte-by-byte comparison.

[0010] Preferably, a test report including test comparison information is generated, including: Determine the test description information for the circuit under test; the test description information includes at least one or a combination of the following: project name, model, number of test cases, pass rate, and test time; Generate a test report that includes test description information and test comparison information.

[0011] Preferably, after generating the test report including test comparison information, the method further includes: The test report is sent to the preset management terminal so that the preset management terminal can analyze the test report.

[0012] Secondly, this application provides a circuit testing apparatus, comprising: The acquisition module is used to acquire the test cases corresponding to each module under test in the circuit under test. The configuration module is used to automatically configure the registers of each module under test according to the test cases corresponding to the module under test, using multiple interrupt signals with fixed timing. The comparison module is used to record the test comparison information corresponding to each test module according to the comparison method matched by each test module after the test is completed. The generation module is used to generate test reports that include test comparison information.

[0013] Thirdly, this application provides an electronic device, comprising: Memory, used to store computer programs; A processor is used to execute the computer program to implement the aforementioned disclosed circuit testing method.

[0014] Fourthly, this application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned disclosed circuit testing method.

[0015] Fifthly, this application provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed circuit testing method.

[0016] As can be seen from the above scheme, this application provides a circuit testing method, including: obtaining test cases corresponding to each module under test in the circuit under test; for each module under test, automatically configuring the registers of the corresponding module under test according to the test cases corresponding to the corresponding module under test, using multiple interrupt signals with fixed timing; after the testing of each module under test is completed, recording the test comparison information corresponding to each module under test according to the comparison method matched by each module under test; and generating a test report including the test comparison information.

[0017] Therefore, the beneficial effects of this application are as follows: It automatically configures the registers of each module under test according to its own specific test cases and multiple interrupt signals with fixed timing, thereby avoiding errors and timing discrepancies caused by manual configuration and improving the accuracy and consistency of register configuration. After each module under test is tested, the test comparison information corresponding to each module is recorded according to the comparison method matched to each module, and a test report including the test comparison information is generated. This overcomes the shortcomings of a uniform comparison method, adapts to the test judgment requirements of different modules to improve the accuracy of test comparison information, and thus improves the accuracy of the test report. This solution can improve the efficiency and accuracy of register configuration, ensure the timing of configuration and the accuracy of test results, and effectively shorten the test cycle, reduce test costs and error rates, thus improving circuit testing efficiency and accuracy.

[0018] Correspondingly, the circuit testing device, equipment, medium, and program product provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 This is a flowchart of a circuit testing method disclosed in this application; Figure 2 This is a schematic diagram of a circuit test architecture disclosed in this application; Figure 3 This is a schematic diagram of a circuit testing device disclosed in this application; Figure 4 This is a schematic diagram of an electronic device disclosed in this application; Figure 5 A server architecture diagram provided for this application; Figure 6A terminal structure diagram provided for this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other instances obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Currently, in the research and development process of integrated circuits (such as FPGAs), verification testing is a crucial step in ensuring their functional correctness, stability, and reliability. Integrated circuits are typically complex, with diverse test case formats required for each functional module. Manual register configuration is also necessary, leading to a large workload and a high risk of errors, impacting testing efficiency and accuracy. Therefore, this application provides a circuit testing scheme that improves register configuration efficiency and accuracy, ensures configuration timing and test result accuracy, effectively shortens the testing cycle, and reduces testing costs and error rates, thus improving circuit testing efficiency and accuracy.

[0023] See Figure 1 As shown in the figure, this application discloses a circuit testing method, including: S101. Obtain the test cases corresponding to each module under test in the circuit under test.

[0024] In this embodiment, the circuit under test can be an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like. Generally, the circuit under test can be divided into multiple functional modules according to its operational logic; these functional modules are the various modules under test. Different modules under test can have parallel, serial, or other logical operation relationships. For example, if the output data of module A is the input data of module B, then there is a serial logical operation relationship between module A and module B. Similarly, if the output data of module A and the output data of module B are both input data of module C, then there is a parallel logical operation relationship between module A and module B, a serial logical operation relationship between module A and module C, and a serial logical operation relationship between module B and module C. Of course, different modules under test may not have any relationship; whether or not there is a relationship between different modules under test does not affect the implementation of this embodiment.

[0025] Since different modules under test may correspond to different test cases, in order to avoid inconsistent test case formats, this embodiment uses a preset script to convert the test cases corresponding to each module under test into the target format before automatically configuring the registers of the corresponding modules under test. This achieves standardized processing of test case formats, provides standardized input for subsequent register configuration, eliminates configuration obstacles caused by differences in test case formats, ensures the compatibility and smoothness of the register configuration process, and thus improves the reliability and execution efficiency of automated testing.

[0026] S102. For each module under test, according to the test cases corresponding to the module under test, the registers of the corresponding module under test are automatically configured using multiple interrupt signals with fixed timing.

[0027] This embodiment can set four interrupt signals in a fixed sequence within one second, and assign each of these four interrupt signals a corresponding register type. This results in multiple interrupt signals with a fixed timing sequence and the correspondence between each interrupt signal and register type. In one implementation, according to the test cases corresponding to the module under test, the registers of the corresponding module under test are automatically configured using multiple interrupt signals with a fixed timing sequence. This includes: determining the correspondence between multiple interrupt signals and multiple registers in the corresponding module under test; reading the corresponding configuration parameters from the test cases corresponding to the module under test according to the fixed timing sequence and correspondence, and writing the configuration parameters into the corresponding registers. This method, by clearly defining the one-to-one correspondence between interrupt signals and registers, and in conjunction with fixed timing, avoids signal conflicts and timing errors during register configuration, ensuring that each register obtains accurate configuration parameters at the correct time. This automated configuration method improves the standardization and stability of the testing process, reduces configuration errors caused by timing mismatches or ambiguous correspondences, thereby enhancing the reliability and execution efficiency of circuit testing.

[0028] S103. After each module under test has been tested, record the test comparison information corresponding to each module under test according to the comparison method matched by each module under test.

[0029] This embodiment can pre-record the comparison methods matched for each type of module under test, and then query them when needed. The actual test data of the corresponding module is compared with the expected data according to the queried comparison method, and the corresponding test comparison information is recorded. In one implementation, the test comparison information corresponding to each module under test is recorded according to the comparison methods matched for each module under test. This includes: querying the comparison methods matched for each module under test; comparing the actual test data of the corresponding module under test with the expected data according to the queried comparison method, and recording the test comparison information. This method, by dynamically querying the comparison methods specific to each module, can flexibly adapt to the differentiated comparison needs of different modules, without the need for a unified and fixed comparison rule. This improves the adaptability of the test comparison, ensures that each module uses the most suitable comparison logic, thereby improving the accuracy of the comparison results and the reliability of the test information.

[0030] In one implementation, the comparison method corresponding to any module under test includes at least one or a combination of the following: bitmask comparison, tolerance range comparison, and byte-by-byte comparison. This provides multiple optional comparison strategies and allows for flexible selection of a single method or a combination of multiple methods for different modules under test. Bitmask comparison can ignore the influence of irrelevant bits, tolerance range comparison can adapt to deviations allowed by analog quantities or precision, and byte-by-byte comparison is suitable for strict data integrity verification. By combining these comparison methods as needed, diverse test scenario requirements can be met, thereby improving comparison accuracy and the adaptability of test cases.

[0031] S104. Generate a test report including test comparison information.

[0032] To ensure the comprehensiveness and accuracy of the test report, this embodiment first determines the test description information of the circuit under test. This information includes at least one or a combination of the following: project name, model, number of test cases, pass rate, and test time. Then, the test description information is combined with previously recorded test comparison information to generate a complete test report. Therefore, in one implementation, generating a test report including test comparison information includes: determining the test description information of the circuit under test; the test description information includes at least one or a combination of the following: project name, model, number of test cases, pass rate, and test time; generating a test report including both the test description information and the test comparison information. In other words, the test report not only includes the comparison results of each module but also overall project overview information, making the report more comprehensive and structured. The statistical descriptions such as pass rate and number of test cases allow testers to quickly understand the overall test progress and pass / fail status, enabling them to assess test quality without analyzing each comparison piece of information. This improves the readability and management efficiency of the test results and facilitates subsequent archiving, traceability, and analysis.

[0033] In one implementation, after generating a test report including test comparison information, the process further includes sending the test report to a preset management terminal for analysis. Thus, after generating the test report, sending it to the preset management terminal allows for analysis, establishing a data transmission channel between the test system and the remote management platform, and automatically completing report submission. If multiple test nodes exist, the management terminal can centrally collect reports from each node, enabling unified analysis of test results for multiple circuits under test. This facilitates batch evaluation of test quality, identification of common problems, and tracking of test progress, thereby improving the data analysis efficiency of test management.

[0034] Based on the test report, the overall test status can be quickly determined according to the test case pass rate, distinguishing between three test results: full pass, partial failure, and full failure, thus initially narrowing down the scope of the fault. Further refined analysis is then conducted on individual test cases, combining byte-by-byte precise comparison, bitmask comparison, and tolerance range comparison with suitable scenarios to check for anomalies in the comparison of discrete register data, valid mask bits, and IQ floating-point sampled data, accurately locating bit positions, time domain positions, and data deviation issues. Simultaneously, timing and configuration analysis is performed using logs to investigate issues such as interrupt timing coordination anomalies, code stream parsing errors, and register configuration offsets. Through the aforementioned analysis, faults can be categorized into three types: first, test link anomalies with no fixed pattern, which can further confirm whether they are caused by communication link, version mismatch, or timeout configuration issues; second, configuration parsing anomalies with errors at fixed locations, which can further confirm whether they originate from test case conversion, address mapping, or configuration operation errors; and third, logic anomalies with continuous errors at fixed points, which can further confirm whether they are core design defects such as hardware logic or sampling timing. This provides a valid basis for optimizing the circuit under test.

[0035] As can be seen, this embodiment automates module-level configuration by acquiring test cases for each module under test and automatically completing register configuration using multiple interrupt signals with fixed timing. After testing, corresponding test comparison information is recorded according to the matching comparison method of each module, and a test report containing this information is finally generated. This ensures the timing accuracy and consistency of register configuration, while the automated configuration and comparison information recording significantly improves testing efficiency and reduces manual intervention. The generated test report centrally presents the comparison results of each module, facilitating rapid problem location and thus improving the reliability and repeatability of circuit testing.

[0036] The following describes an FPGA testing system using FPGA as an example. The system includes a test case conversion module, a hardware storage module, a test tool configuration module, a DSP software data reading module, a DSP software data comparison module, a DSP software test result marking module, and a test report generation module. Each module operates independently yet works collaboratively to complete the automated verification testing of the FPGA. The architecture of the test tools and DSP software is as follows: Figure 2 As shown.

[0037] The test case conversion module, developed using the Python scripting language, receives test cases generated during the algorithm design phase and can uniformly convert various file formats such as decimal, binary, CSV, and JSON into a target format (e.g., hexadecimal). Specifically, through preset format conversion rules, it converts core information such as configuration parameters and expected result data within the test cases into a hexadecimal code stream recognizable by the FPGA hardware, providing a standardized data foundation for subsequent hardware loading and test configuration. For example, each module under test in the FPGA corresponds to its own test case, which records register values, test vectors, the identifier of the module to be tested, and configures the storage address of the test vectors. Based on this, register values ​​can be mapped to the corresponding registers within the module, and the storage address of the corresponding test vector can be automatically indexed.

[0038] In one example, the test case header structure of the hexadecimal code stream has a total length of 8 bytes, used to identify the core attributes of the test case. The first 4 bytes contain multi-dimensional bit identification information, specifically a 4-bit global module identifier, a 6-bit cell search submodule identifier, a 10-bit downlink receiving submodule identifier, and a 4-bit uplink transmitting submodule identifier. The last 4 bytes contain 1 byte of test subframe number information and 3 bytes of uplink transmitted data length information. FPGA register configuration parameters and expected test return results are stored immediately following the test case header structure. Based on the corresponding test module identified in the header structure, targeted parsing and invocation can be performed, achieving precise matching between test data and test modules. Test cases can define fields such as the module to be tested, the test milliseconds, the registers to be tested, and the length of the result.

[0039] The FPGA hardware has an internal hardware storage module, which can be an independent non-volatile storage unit. It can be Double Data Rate (DDR), Block Random Access Memory (BRAM), Flash memory, or external Static Random Access Memory (SRAM). The module address space is preset to a fixed storage address range, for example 0x0000_0000-0x0000_FFFF, which is used to store the hexadecimal code stream output by the test case conversion module. This fixed address range can be flexibly adjusted through the FPGA configuration file to adapt to different hardware storage capacities and storage layout requirements.

[0040] The test tool configuration module runs on a host computer or embedded processor terminal. It can establish a stable data connection with the FPGA hardware through various communication interfaces such as PCIe, Ethernet, and UART. It can complete the version burning of the FPGA hardware program and DSP software program, and accurately download binary files carrying hexadecimal code stream information to a predefined fixed address in the FPGA hardware storage module, completing the hardware loading of test data. This module also achieves automated configuration with timing coordination based on interrupts. Specifically, it achieves precise timing coordination through multiple types of interrupts between the DSP software and the FPGA (such as configuration completion interrupt, timer interrupt, and processing completion interrupt). Upon receiving a specific interrupt signal, it automatically executes register configuration. During configuration, it employs atomic read-modify-write operations and a real-time readback verification mechanism to ensure that the written value is consistent with the expectation. If it fails, it automatically retryes until the configuration is successful or an exception is reported, thereby avoiding the inefficiency and error risks of manual configuration and ensuring the accuracy and consistency of the configuration. As can be seen, the DSP software and FPGA hardware achieve precise timing coordination through multiple types of interrupt signals. The interrupt can be a post-interrupt triggered after the hardware processing is completed, or a timed interrupt triggered by a preset time node. The DSP software can respond to the corresponding type of interrupt signal according to the job requirements of different test modules, and the interrupt triggering conditions and response timing can be flexibly configured through test cases to adapt to the timing requirements of multiple test scenarios.

[0041] The DSP software data reading module is used to start running after the test tool completes the software and hardware version burning and test data download. This module first completes the initialization configuration of the operating platform, UART communication, interrupt mechanism, and other operating environment components. Then, it reads and parses the hexadecimal code stream from a fixed address in the FPGA hardware storage module, extracting the test configuration parameters and the test content to be compared. Next, it completes the initialization configuration of the FPGA clock and register default parameters. After the FPGA completes hardware initialization and triggers an interrupt signal, the module completes the parameter configuration of the FPGA's internal registers step by step according to the preset timing logic.

[0042] The DSP software data comparison module receives test data from the FPGA in real time through a dedicated data interface between the DSP and the FPGA. This includes status codes, configuration confirmation values, register return values, and baseband and intermediate frequency signal sampling data. For multiple sets of comparison results in the test process, the module can automatically compare the actual FPGA operation results with the expected test case results based on the timing-corresponding return data. The module defaults to a byte-by-byte precise comparison mode, but the comparison method can be flexibly configured according to actual test requirements. If the comparison results of all test points are consistent, the corresponding test case is considered to have passed. If any comparison anomaly exists, the module automatically records key information such as the time domain location, actual value, and expected value of the abnormal data, providing data support for subsequent problem localization and fault diagnosis. It can also achieve multi-level, high-precision automatic data comparison: compare the actual data fed back by the FPGA (register return value, IQ data, etc.) with the expected results in the test case, and support three modes: bit mask comparison (can mask irrelevant bits), tolerance range comparison (suitable for analog signals and floating-point data), and byte-by-byte precise comparison; after comparison, it accurately locates the erroneous bit or specific data field, and records the time domain location, actual value, and expected value of the anomaly, which greatly improves the comparison efficiency and problem location accuracy.

[0043] The DSP software test result marking module is based on the pre-defined standardized test result data structure of each test function module. It can classify and categorize the channel type and data reporting type of the sub-module and update the test result flag bit in real time. After a single test case is executed, the module writes the completion flag into the test completion flag address preset by the test tool, and at the same time moves the complete test result structure to the predefined storage address of the FPGA for the host computer test tool to read, parse and statistically analyze.

[0044] After the test data is downloaded, the test tool report generation module continuously polls and monitors the test completion flag. When a valid completion flag is detected, the module reads all test result data from the predefined storage address and automatically generates a complete test report based on the preset standardized report template. If the test completion flag is not detected within the preset timeout threshold, the corresponding test case is directly determined to have failed, and a test timeout exception is marked in the report. The generated test report includes core content such as test project name, FPGA model, total number of test cases, number of passed tests, test pass rate, detailed information on abnormal test cases, and test start and end times, enabling standardized archiving and full-process traceability of test results.

[0045] This embodiment supports verification requirements for different algorithm types (communication baseband, radar signals, image processing, etc.), different FPGA models, and multiple communication interfaces (PCIe, Ethernet, UART), which can reduce the complexity and cost of verification testing.

[0046] Accordingly, a testing process includes: Step 1: Algorithm designers compile and generate test case files containing test configuration parameters and expected result data, and input the test case files into the architecture's test case conversion module.

[0047] Step 2: The test case conversion module uses a built-in script tool to complete the format conversion and data validity verification of the test cases, generating a standardized hexadecimal code stream; the test tool configuration module downloads and stores the generated hexadecimal code stream to a fixed address range of the FPGA hardware storage module through the communication interface.

[0048] Step 3: The DSP software data reading module reads the hexadecimal code stream from the fixed address of the FPGA hardware storage module, completes data parsing according to the preset data structure and communication protocol, accurately extracts the test configuration parameters and expected result data, and completes local storage.

[0049] Step 4: After the FPGA hardware completes the initialization configuration, it reports an interrupt signal to the DSP software. After receiving the interrupt signal, the DSP software data reading module writes the parsed test configuration parameters into the FPGA internal register according to the timing node corresponding to the interrupt, thus completing the hardware configuration before the test.

[0050] Step 5: The FPGA executes the corresponding test process according to the register configuration parameters and reports an interrupt signal at a preset fixed timing node; after receiving the interrupt signal, the DSP software data reading module reads the actual test data such as the register return value and IQ data fed back by the FPGA, and transmits the data to the DSP software data comparison module.

[0051] Step 6: The DSP software data comparison module completes the comparison and verification between the actual test data and the expected result data, updates the pass / fail status of the test result structure according to the comparison results, and sets the test case execution end flag.

[0052] Step 7: The test tool report generation module summarizes the test process logs, data comparison results, anomaly information, and other data, and automatically generates a standardized test report to complete the FPGA verification test process for a single set of test cases.

[0053] As can be seen, this embodiment, through modular architecture design and full-process automation, achieves intelligent conversion of test cases, automated configuration of interrupt timing, multi-level high-precision data comparison, standardized report generation, and multi-scenario compatibility. It effectively solves the technical problems of traditional FPGA verification testing, such as excessive manual operation, poor adaptability, low test accuracy, difficulty in result traceability, and high test cost. It realizes full-process automation of FPGA verification testing, significantly improving test efficiency and accuracy. At the same time, through configurable and modular design, it is compatible with multiple algorithms, multiple hardware, and multiple interface test scenarios, and has strong versatility and scalability. It can effectively reduce the manpower and time costs of FPGA R&D testing, standardize test processes and test results, and provide efficient, accurate, and standardized technical support for the verification testing of various FPGA hardware algorithm modules, adapting to the industrial, batch, and iterative FPGA R&D testing needs.

[0054] The following describes a circuit testing device provided by an embodiment of this application. The circuit testing device described below can be referred to in conjunction with other embodiments described herein.

[0055] See Figure 3 As shown in the figure, this application discloses a circuit testing device, including: The acquisition module 301 is used to acquire the test cases corresponding to each module under test in the circuit under test. Configuration module 302 is used to automatically configure the registers of each module under test according to the test cases corresponding to the module under test, using multiple interrupt signals with fixed timing. The comparison module 303 is used to record the test comparison information corresponding to each test module according to the comparison method matched by each test module after the test is completed. Module 304 is used to generate a test report that includes test comparison information.

[0056] In one implementation, it further includes: The conversion module is used to automatically convert the test cases corresponding to each module under test into the target format using a preset script before configuring the registers of the corresponding module under test.

[0057] In one implementation, the configuration module is specifically used for: Determine the correspondence between multiple interrupt signals and multiple registers in the corresponding module under test; According to a fixed timing sequence and correspondence, the corresponding configuration parameters are read from the test cases corresponding to the module under test, and the configuration parameters are written into the corresponding registers.

[0058] In one implementation, the comparison module is specifically used for: Query the comparison methods for each module under test; According to the comparison method found, the actual test data and expected data of the corresponding module under test are compared, and the test comparison information is recorded.

[0059] In one implementation, the comparison method corresponding to any module under test includes at least one or a combination of the following: bitmask comparison, tolerance interval comparison, and byte-by-byte comparison.

[0060] In one implementation, the generation module is specifically used for: Determine the test description information for the circuit under test; the test description information includes at least one or a combination of the following: project name, model, number of test cases, pass rate, and test time; Generate a test report that includes test description information and test comparison information.

[0061] In one implementation, it further includes: The sending module generates a test report including test comparison information and then sends the test report to a preset management terminal so that the preset management terminal can analyze the test report.

[0062] For more detailed information on the working process of each module and unit in this embodiment, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0063] As can be seen, this embodiment provides a circuit testing device that can improve the efficiency and accuracy of register configuration, ensure the timing of configuration and the accuracy of test results, and effectively shorten the test cycle, reduce test costs and error rates, thereby improving circuit testing efficiency and accuracy.

[0064] The following describes an electronic device provided by an embodiment of this application. The electronic device described below can be referred to in conjunction with other embodiments described herein.

[0065] See Figure 4 As shown in the figure, an embodiment of this application discloses an electronic device, including: Memory 401 is used to store computer programs; Processor 402 is configured to execute the computer program to implement the method disclosed in any of the above embodiments.

[0066] Furthermore, embodiments of this application also provide an electronic device. The aforementioned electronic device can be, for example,... Figure 5 The server shown can also be as follows: Figure 6 The terminal shown. Figure 5 and Figure 6 These are all diagrams illustrating the structure of an electronic device according to an exemplary embodiment. The content in the diagrams should not be considered as any limitation on the scope of this application.

[0067] Figure 5 This is a schematic diagram of a server provided in an embodiment of this application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory stores a computer program, which is loaded and executed by the processor to implement the relevant steps in the circuit testing disclosed in any of the foregoing embodiments.

[0068] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0069] In addition, the memory, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system, computer programs and data, etc., and the storage method can be temporary storage or permanent storage.

[0070] The operating system manages and controls the various hardware devices and computer programs on the server to enable the processor to perform operations and processes on the data in the memory. It can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs capable of performing the circuit testing methods disclosed in any of the foregoing embodiments, the computer programs may further include computer programs capable of performing other specific tasks. The data may include application update information and application developer information.

[0071] Figure 6 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. The terminal may include, but is not limited to, a smartphone, tablet computer, laptop computer, or desktop computer.

[0072] Typically, the terminal in this embodiment includes a processor and a memory.

[0073] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor can be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and coprocessors. The main processor, also known as the CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which handles computational operations related to machine learning.

[0074] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory is used to store at least the following computer program, which, after being loaded and executed by the processor, is capable of implementing the relevant steps in the circuit testing method executed on the terminal side as disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory may also include operating systems and data, and the storage method may be temporary or permanent storage. The operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, application update information.

[0075] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0076] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the terminal and may include more or fewer components than illustrated.

[0077] The following describes a non-volatile storage medium provided in an embodiment of this application. The non-volatile storage medium described below can be referred to in conjunction with other embodiments described herein.

[0078] A non-volatile storage medium is provided for storing a computer program, wherein the computer program, when executed by a processor, implements the circuit testing method disclosed in the foregoing embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier of resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored thereon include an operating system, computer programs, and data, and the storage method can be temporary storage or permanent storage.

[0079] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.

[0080] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed circuit testing method.

[0081] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0082] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of non-volatile storage medium known in the art.

[0084] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A circuit testing method, characterized in that, include: Obtain the test cases corresponding to each module under test in the circuit under test; For each module under test, the registers of the corresponding module under test are automatically configured according to the test cases corresponding to the module under test, using multiple interrupt signals with fixed timing. After each tested module is completed, the test comparison information corresponding to each tested module is recorded according to the comparison method matched by each tested module. Generate a test report that includes the test comparison information.

2. The method according to claim 1, characterized in that, Before automatically configuring the registers of the corresponding module under test, the following steps are also included: The test cases corresponding to each module under test are converted into the target format using a preset script.

3. The method according to claim 1, characterized in that, Based on the test cases corresponding to the module under test, the registers of the corresponding module under test are automatically configured using multiple interrupt signals with fixed timing, including: Determine the correspondence between the multiple interrupt signals and the multiple registers in the corresponding tested module; According to the fixed timing and the corresponding relationship, the corresponding configuration parameters are read from the test cases corresponding to the module under test, and the configuration parameters are written into the corresponding registers.

4. The method according to claim 1, characterized in that, Record the test comparison information corresponding to each tested module according to the comparison method matched for each module, including: Query the matching comparison method for each of the tested modules; The actual and expected data of the corresponding module under test are compared according to the comparison method found in the query, and the test comparison information is recorded.

5. The method according to claim 4, characterized in that, The comparison method corresponding to any module under test includes at least one or a combination of the following: bitmask comparison, tolerance interval comparison, and byte-by-byte comparison.

6. The method according to claim 1, characterized in that, Generate a test report including the test comparison information, including: Determine the test description information of the circuit under test; the test description information includes at least one or a combination of the following: project name, model, number of test cases, pass rate, and test time; Generate a test report that includes the test description information and the test comparison information.

7. The method according to any one of claims 1-6, characterized in that, After generating the test report including the test comparison information, it also includes: The test report is sent to a preset management terminal so that the preset management terminal can analyze the test report.

8. A circuit testing device, characterized in that, include: The acquisition module is used to acquire the test cases corresponding to each module under test in the circuit under test. The configuration module is used to automatically configure the registers of each module under test according to the test cases corresponding to the module under test, using multiple interrupt signals with a fixed timing. The comparison module is used to record the test comparison information corresponding to each test module according to the comparison method matched by each test module after the test is completed; The generation module is used to generate a test report that includes the test comparison information.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in any one of claims 1 to 7.

10. A non-volatile storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 1 to 7.

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