Battery simulation circuit and battery simulation device

Abstract

The embodiment of the application discloses a battery simulation circuit and a battery simulation device. The battery simulation circuit comprises a voltage conversion module, a voltage regulation module, a voltage output module and a feedback regulation module, the voltage conversion module is used for outputting a bus voltage; the voltage regulation module is used for regulating a driving signal; the voltage output module is used for generating an output voltage; and the feedback regulation module is used for controlling the voltage output module to regulate the output voltage. The application forms a double-loop feedback architecture by synchronously controlling the voltage regulation module and the feedback regulation module through a single instruction voltage, realizes adaptive adjustment of the bus voltage and the output voltage following the instruction voltage, so that the bus voltage is no longer a fixed voltage, thereby providing a basis for reducing the overall power consumption of the battery simulation circuit, avoiding excessive power loss of the voltage output module caused by excessive voltage difference between the bus voltage and the output voltage in the related art, and greatly reducing the power consumption of the battery simulation circuit.

Description

Technical Field

[0001] This application relates to the field of battery simulation technology, specifically to a battery simulation circuit and a battery simulation device. Background Technology

[0002] In the field of battery testing, the battery total voltage simulator, as a core device for battery pack performance testing, must meet the requirements of a 12V input condition and achieve a wide-range constant voltage output of 5V-60V, while also simulating an external 300mA charging and discharging current of the battery. Battery total voltage simulators are widely used in scenarios such as whole-system testing of new energy battery packs and compatibility verification of charging and discharging equipment. The battery total voltage simulators provided by related technologies mainly adopt a single-stage voltage regulation architecture, using a boost circuit to output a fixed high voltage, and then using a linear voltage regulator circuit to regulate the fixed high voltage to obtain the user's desired output voltage. When the difference between the output voltage and the fixed high voltage is large, the linear voltage regulator circuit needs to bear a large power consumption, resulting in high power consumption for the single-stage voltage regulation architecture. Summary of the Invention

[0003] One objective of this application is to provide a battery simulation circuit and a battery simulation device to improve the high power consumption of related technologies.

[0004] In a first aspect, embodiments of this application provide a battery simulation circuit, including a voltage conversion module, a voltage regulation module, a voltage output module, and a feedback regulation module. The voltage conversion module is configured to acquire a drive signal and perform a voltage conversion operation on a preset input voltage based on the drive signal to obtain a bus voltage. The voltage regulation module is electrically connected to the voltage conversion module and is configured to receive a command voltage and adjust the drive signal based on the command voltage and the bus voltage fed back by the voltage conversion module to adjust the bus voltage output by the voltage conversion module. The voltage output module is electrically connected to the voltage conversion module and is configured to generate an output voltage. The feedback regulation module is electrically connected to the voltage output module and is configured to receive the command voltage and transmit a first error signal to the voltage output module based on the command voltage and the output voltage fed back by the voltage output module, so that the voltage output module adjusts the output voltage of the voltage output module under the drive of the bus voltage based on the first error signal.

[0005] In a second aspect, embodiments of this application provide a battery simulation device, comprising: a controller and a battery simulation circuit, wherein the controller is configured to output a command voltage according to a preset digital-to-analog instruction; and a voltage regulation module and a feedback regulation module of the battery simulation circuit are electrically connected to the controller.

[0006] The technical advantages of the battery simulation circuit provided in this application are as follows: This application embodiment uses a dual-loop feedback architecture formed by a single command voltage synchronous control voltage regulation module and a feedback regulation module to achieve adaptive adjustment of the bus voltage following the command voltage, so that the bus voltage is no longer a fixed voltage. At the same time, the output voltage also adaptively adjusts with the command voltage. This provides a basis for reducing the overall power consumption of the battery simulation circuit and avoids the excessive power loss of the voltage output module caused by the large voltage difference between the bus voltage and the output voltage in related technologies. This can greatly reduce the power loss of the battery simulation circuit, thereby eliminating the need to install various heat sinks, saving hardware costs and ensuring the miniaturization of the battery simulation circuit. Attached Figure Description

[0007] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0008] Figure 1 A schematic diagram of the circuit structure of a battery simulation circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 3 A schematic diagram of the specific circuit structure of the feedback regulation module and voltage output module provided in the embodiments of this application; Figure 4 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 5 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 6 This is a schematic diagram of the specific circuit structure of the error generation circuit provided in the embodiments of this application; Figure 7 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 8 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 9 This is a schematic diagram of the specific circuit structure of the voltage control circuit provided in the embodiments of this application; Figure 10 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 11 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 12 A schematic diagram of the circuit structure of a battery simulation circuit provided in another embodiment of this application; Figure 13 This is a schematic diagram of the specific circuit structure of the voltage conversion module provided in the embodiments of this application; Figure 14 This is a schematic diagram of the circuit structure of a battery simulation device provided in an embodiment of this application. Detailed Implementation

[0009] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0010] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. Furthermore, technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0011] In the process of implementing the embodiments of this application, the inventors discovered the following related technologies: 1) A combined solution using a boost circuit and an LDO (Low Dropout Regulator) circuit.

[0012] The boost circuit converts the 12V output voltage of the switching power supply to a bus voltage slightly higher than 60V. This bus voltage is then linearly stepped down by the LDO circuit to obtain the desired target voltage, and the output current is based on the target voltage. The target voltage can be any value between 5V and 60V.

[0013] The disadvantage of this combined approach is that, while it meets the functional requirements of battery simulation, it typically operates at a fixed output power, such as 18W, with a bus voltage of 60V and an output current of 300mA. When the target voltage required by the user is lower, such as a 5V target voltage from the LDO circuit, the LDO circuit needs to step down the 60V bus voltage to achieve the 5V target voltage. This means the LDO circuit needs to handle a power loss of 16.5W, where 16.5W = (60V - 5V) * 0.3A. This power loss is usually dissipated as heat, so the combined approach requires a large heatsink and fan for auxiliary cooling. This not only increases power consumption but also raises the hardware cost and size of the resulting battery simulation device.

[0014] In addition, it is rare to find LDO circuits on the market that can support a target voltage of 60V. Furthermore, it is necessary to simultaneously meet the requirements of voltage adjustment from 5V to 60V and output current of 300mA. LDO circuits that meet the above requirements are scarce on the market, and if there are LDO circuits that meet the above requirements, their cost is also very high.

[0015] 2) A combined scheme using a boost circuit and a microprocessor-based PWM (Pulse Width Modulation) control method.

[0016] This combined solution includes a boost circuit, a microprocessor, an analog-to-digital converter (ADC), and a voltage output circuit. The boost circuit converts the 12V output voltage from the switching power supply into a bus voltage slightly higher than 60V. The microprocessor outputs a PWM-type drive signal to the voltage output circuit to control its output voltage. The ADC samples this voltage and feeds it back to the microprocessor. The microprocessor adjusts the drive signal based on a preset control algorithm to regulate the voltage output from the voltage output circuit to the target voltage for output.

[0017] The output voltage response speed of this combined scheme is limited by the sampling frequency of the analog-to-digital converter (ADC), software delay, and PWM update mechanism, resulting in a lag in output voltage regulation. Furthermore, to suppress noise, this combined scheme typically performs digital filtering on the voltage sampled by the ADC, which introduces additional delay and phase lag, further limiting the output voltage regulation speed. Additionally, the limited resolution of the microprocessor means that for small voltage errors (e.g., 20mV), multiple switching cycles are required to accumulate sufficient duty cycle adjustment, also causing delay. Therefore, this combined scheme still needs improvement in output voltage regulation speed.

[0018] 3) A combined solution using a boost circuit and a digital-to-analog converter.

[0019] This combined solution includes a boost circuit, a microprocessor, a digital-to-analog converter (DAC), an operational amplifier (op-amp) circuit, and a voltage output circuit. The boost circuit converts the 12V output from the switching power supply to a bus voltage slightly higher than 60V. The microprocessor controls the DAC to output the corresponding voltage. This DAC output voltage is applied to the op-amp circuit, controlling it to generate a corresponding drive signal. This drive signal is transmitted to the voltage output circuit to control its output voltage. The output voltage of the voltage output circuit provides feedback to the op-amp circuit, which continuously adjusts the drive signal to ensure the output voltage reaches the target voltage. This approach shares a similar drawback with the first approach: because the bus voltage is fixed, the voltage output circuit must handle a 16.5W power loss.

[0020] In view of this, the embodiments of this application utilize a dual-loop feedback architecture formed by a single command voltage synchronous control voltage regulation module and a feedback regulation module to achieve adaptive adjustment of the bus voltage following the command voltage, so that the bus voltage is no longer a fixed voltage. This provides a basis for reducing the overall power consumption of the battery simulation circuit. At the same time, the output voltage also adaptively adjusts with the command voltage. After both the voltage regulation module and the feedback regulation module enter a steady state, the bus voltage is greater than or equal to the output voltage, and the voltage difference between the bus voltage and the output voltage is less than or equal to a preset floating threshold. Therefore, the voltage difference is locked within a very small range. While ensuring that the bus voltage and output voltage can respond and adjust quickly, it avoids the excessive power loss of the voltage output module caused by the excessive voltage difference between the bus voltage and the output voltage in related technologies. This can significantly reduce the power loss of the battery simulation circuit, thereby eliminating the need for additional heat sinks, saving hardware costs and ensuring the miniaturization of the battery simulation circuit.

[0021] The following embodiment of this application provides a battery simulation circuit. Please refer to... Figure 1 The battery simulation circuit 100 includes a voltage conversion module 200, a voltage regulation module 300, a voltage output module 400, and a feedback regulation module 500. The voltage regulation module 300 is electrically connected to the voltage conversion module 200, the voltage output module 400 is electrically connected to the voltage conversion module 200, and the feedback regulation module 500 is electrically connected to the voltage output module 400.

[0022] The voltage conversion module 200 is configured to acquire a drive signal and perform a voltage conversion operation on a preset input voltage based on the drive signal to obtain the bus voltage. The voltage conversion module 200 can be a boost circuit, a buck circuit, or a hybrid boost-buck circuit. Correspondingly, the voltage conversion operation includes a boost operation or a buck operation; the voltage conversion module 200 performs a boost operation or a buck operation on the preset input voltage based on the drive signal to obtain the bus voltage.

[0023] The drive signal is a PWM signal that drives the voltage conversion module 200 to generate the corresponding voltage. The bus voltage is the voltage output by the voltage conversion module 200. In steady state, the bus voltage output by the voltage conversion module 200 reaches the voltage expected by the user. For example, if the input voltage is 12V, the voltage conversion module 200 is a boost circuit. The voltage conversion module 200 performs a boost operation on the 12V input voltage based on the drive signal. When the voltage conversion module 200 enters steady state, the bus voltage output by the voltage conversion module 200 is slightly higher than 30V, for example, the bus voltage is 31.4V.

[0024] The duty cycle of the drive signal is positively correlated with the bus voltage; that is, the larger the duty cycle of the drive signal, the larger the bus voltage, and the smaller the duty cycle of the drive signal, the smaller the bus voltage. For example, the bus voltage output by the voltage conversion module 200 based on a drive signal with a 90% duty cycle is greater than the bus voltage output based on a drive signal with a 50% duty cycle.

[0025] It is understood that after the voltage conversion module 200 performs a boost operation on the input voltage based on a drive signal with any duty cycle, the resulting bus voltage can be mapped to any voltage within a specified voltage range. For example, if the input voltage is 12V, the voltage conversion module 200 performs a boost operation based on a drive signal with any duty cycle, and the resulting bus voltage is any voltage within the specified voltage range of 12V-60V.

[0026] The voltage regulation module 300 is configured to receive a command voltage and, based on the command voltage and the bus voltage fed back by the voltage conversion module 200, adjust the drive signal to adjust the bus voltage output by the voltage conversion module 200.

[0027] The command voltage is output by the controller 600 according to preset digital-to-analog commands. The controller 600 integrates a digital-to-analog converter (DAC). The DAC commands encapsulate voltage parameters corresponding to the command voltage. The controller 600 parses the voltage parameters corresponding to the command voltage from the DAC commands and controls the DAC to output the command voltage according to the voltage parameters. For example, if the voltage parameter is 3.3V, the controller 600 controls the DAC to output an analog 3.3V command voltage according to the digital 3.3V voltage parameter.

[0028] There are various ways to generate analog-to-digital (A / D) commands. In some embodiments, A / D commands are transmitted from the user to the controller 600 via a host computer. For example, the user operates the host computer to transmit the A / D commands to the controller 600. In other embodiments, A / D commands are generated by the controller 600 upon detecting a trigger condition. For example, the controller 600 executes a preset algorithm step, and when the controller 600 executes the step corresponding to the trigger condition, the controller 600 automatically issues the A / D commands.

[0029] The command voltage and the bus voltage output by the voltage conversion module 200 in steady state are anchored together, and the command voltage and the output voltage output by the voltage output module 400 in steady state are also anchored together. For example, when the command voltage is 3.3V, the bus voltage output by the voltage conversion module 200 in steady state is 31.4V, and the output voltage output by the voltage output module 400 in steady state is 30V. When the command voltage is 1.8V, the bus voltage output by the voltage conversion module 200 in steady state is 21.4V, and the output voltage output by the voltage output module 400 in steady state is 20V.

[0030] The magnitude and precision of the command voltage are strongly correlated with the resolution of the digital-to-analog converter (DAC). For example, for a 12-bit DAC with a resolution of 25mV, the precision of the command voltage can be extended to the thousandths, meaning the DAC can output at least 0.025V. For instance, the command voltage could be 0.05V, 0.15V, 2.75V, or 2.775V, etc.

[0031] Because the command voltage is anchored to the bus voltage output by the voltage conversion module 200 in steady state, and the command voltage is anchored to the output voltage output by the voltage output module 400 in steady state, the accuracy of the command voltage is related to the accuracy of the bus voltage, and the accuracy of the command voltage is related to the accuracy of the output voltage. The smaller the command voltage, the more finely granular the bus voltage that the voltage conversion module 200 can output, such as 15.12V. At the same time, the voltage output module 400 can also output a more finely granular bus voltage, such as 16.52V. This enables the battery simulation circuit 100 to simulate and output a high-precision output voltage, meeting the requirements of battery simulation scenarios with high voltage accuracy.

[0032] The voltage output module 400 is configured to generate an output voltage. This output voltage is directly transmitted to the subsequent load to drive the load.

[0033] The feedback adjustment module 500 is configured to receive the command voltage and, based on the command voltage and the output voltage fed back by the voltage output module 400, transmit a first error signal to the voltage output module 400 so that the voltage output module 400 adjusts the output voltage of the voltage output module 400 under the drive of the bus voltage based on the first error signal.

[0034] The first error signal is used to reflect the deviation between the target output voltage anchored by the command voltage and the current output voltage fed back by the voltage output module 400. The feedback adjustment module 500 needs to transmit the first error signal to the voltage output module 400 so that the voltage output module 400 adjusts its output voltage based on the first error signal and driven by the bus voltage. Finally, the output voltage of the voltage output module 400 converges to the target output voltage anchored by the command voltage. For example, if the final output voltage anchored by the command voltage is 30V, and the initial output voltage of the voltage output module 400 is 28V, after multiple error feedback iterations, the output voltage of the voltage output module 400 finally converges to 30V, and the 30V output voltage is the target output voltage.

[0035] This embodiment of the application uses a dual-loop feedback architecture formed by a single command voltage synchronous control voltage regulation module 300 and a feedback regulation module 500 to achieve adaptive adjustment of the bus voltage following the command voltage, so that the bus voltage is no longer a fixed voltage. This provides a basis for reducing the overall power consumption of the battery analog circuit. At the same time, the output voltage also adaptively adjusts following the command voltage.

[0036] After both the voltage regulation module 300 and the feedback regulation module 500 have entered a steady state, the bus voltage output by the voltage conversion module 200 is greater than the output voltage output by the voltage output module 400, and the voltage difference between the bus voltage and the output voltage is less than or equal to the preset floating threshold.

[0037] Steady state refers to a state where both the voltage regulation module 300 and the feedback regulation module 500 reach equilibrium. Specifically, the voltage regulation module 300 controls the voltage conversion module 200 to output a bus voltage that ultimately reaches the target bus voltage anchored to the command voltage, and the feedback regulation module 500 controls the voltage output module 400 to output a voltage that ultimately reaches the target output voltage anchored to the command voltage. The target bus voltage is the voltage output by the voltage conversion module 200 in steady state, and the target output voltage is the voltage output by the voltage output module 400 in steady state. For example, according to design requirements, when the command voltage is 3.3V, the voltage conversion module 200 needs to output a bus voltage of 31.4V, and the voltage output module 400 needs to output an output voltage of 30V. Here, the 31.4V bus voltage is the target bus voltage, and the 30V output voltage is the target output voltage.

[0038] The voltage output module 400 generates the output voltage under the drive of the bus voltage. Considering the power loss factor, under steady state, the bus voltage output by the voltage conversion module 200 needs to be greater than the output voltage output by the voltage output module 400.

[0039] The preset floating threshold is the maximum allowable voltage difference between the bus voltage and the output voltage under steady state. In other words, under steady state, the output voltage of the voltage output module 400 is only slightly less than the bus voltage output by the voltage conversion module 200.

[0040] The preset floating threshold is customized by the designer based on engineering experience. In some embodiments, the preset floating threshold is equal to the sum of the voltage drops of the two diodes. In other embodiments, the preset floating threshold is 2.0V or 2.5V, etc. For example, if the diode voltage drop is 0.7V and the preset floating threshold is 1.4V, that is, in steady state, the voltage difference between the bus voltage and the output voltage is less than or equal to 1.4V. If the battery simulation circuit 100 maintains a constant output current of 300mA (i.e., 0.3A), then, in this embodiment, the power consumption of the battery simulation circuit 100 is locked within 0.42W, 0.42W = 0.3A * 1.4V.

[0041] To demonstrate the advantages of the battery simulation circuit 100 provided in this application embodiment, a comparison is made with the first combined solution mentioned above, as explained below: In the first joint scheme, since the bus voltage of 60V is applied to the LDO circuit as a fixed voltage, when the LDO circuit only needs to output a 5V output voltage, the LDO circuit needs to bear a power loss of 16.5W.

[0042] In this embodiment, when the voltage output module 400 needs to output a 5V output voltage, the command voltage is 0.55V according to the design requirements. Based on the 0.55V command voltage and the bus voltage fed back by the voltage conversion module 200, the voltage regulation module 300 adjusts the drive signal to adjust the bus voltage output by the voltage conversion module 200. Finally, under steady state, the bus voltage output by the voltage conversion module 200 is 31.4V.

[0043] Simultaneously, the feedback adjustment module 500 transmits a first error signal to the voltage output module 400 based on the command voltage and the output voltage fed back from the voltage output module 400. This causes the voltage output module 400 to adjust its output voltage based on the first error signal and driven by the bus voltage. Ultimately, in steady state, the output voltage of the voltage output module 400 is 30V. During this period, the power consumption of the voltage output module 400 is locked within 0.42W.

[0044] Under the same output voltage of 5V and current of 0.3A, the first combined solution requires a power loss of 16.5W, while the embodiment of this application only requires a power loss of 0.42W. The power loss of the two solutions differs by a factor of 39. It can be seen that the embodiment of this application locks the voltage difference within a very small range. While ensuring that the bus voltage and output voltage can be quickly adjusted, it avoids the voltage output module from bearing excessive power loss due to the large voltage difference between the bus voltage and the output voltage in related technologies. This can greatly reduce the power loss of the battery simulation circuit 100, thereby eliminating the need to install various heat sinks, saving hardware costs and ensuring the miniaturization of the battery simulation circuit 100.

[0045] Please see Figure 2 The feedback adjustment module 500 includes a first voltage divider circuit 51 and a first error amplifier circuit 52. The first voltage divider circuit 51 is electrically connected to the voltage output module 400. A command voltage is applied to the non-inverting input terminal of the first error amplifier circuit 52, the inverting input terminal of the first error amplifier circuit 52 is electrically connected to the first voltage divider circuit 51, and the output terminal of the first error amplifier circuit 52 is electrically connected to the voltage output module 400.

[0046] The first voltage divider circuit 51 is configured to divide the output voltage fed back by the voltage output module 400 according to a preset voltage division ratio to obtain the first voltage divider.

[0047] The first error amplifier circuit 52 is configured to generate a first error signal based on the command voltage and a first voltage divider, wherein the output voltage fed back by the voltage output module 400 is negatively correlated with the first error signal. The first error amplifier circuit 52 can be a single-supply error amplifier, wherein the input power supply of the single-supply error amplifier can be 12V, and the output voltage of the first error amplifier circuit 52 is greater than 0V and less than 12V, i.e., 0V < first error signal < 12V. The expression for the output voltage of the first error amplifier circuit 52 is:

[0048] in, The output voltage of the first error amplifier circuit 52 (i.e., the first error signal) is... This is the bias voltage set inside the first error amplifier circuit 52. Command voltage, This is the first voltage divider. This is the amplification factor of the first error amplifier circuit 52.

[0049] The first voltage divider is affected by the feedback output voltage. Let the first voltage divider be the independent variable and the first error signal be the dependent variable. Rearranging the above equation, we have:

[0050] From the above formula, we can see that the first partial pressure It is negatively correlated with the first error signal, due to the first voltage divider. The first error signal is positively correlated with the output voltage fed back by the voltage output module 400; therefore, it is negatively correlated with the output voltage fed back by the voltage output module 400. The smaller the output voltage fed back by the voltage output module 400, the larger the first error signal; conversely, the larger the output voltage fed back by the voltage output module 400, the smaller the first error signal.

[0051] As shown above, mapping the above formula to a two-dimensional coordinate system x0y, the function in the formula is a monotonically decreasing function in the first quadrant, and the intersection coordinates of this monotonically decreasing function with the x-axis are... The coordinates of the intersection with the y-axis are .

[0052] When the current output voltage equals the target output voltage (i.e., the command voltage equals the first voltage divider), the voltage value of the first error signal equals the bias voltage. When the current output voltage is less than the target output voltage, i.e., the command voltage is greater than the first voltage divider, the voltage value of the first error signal is within the voltage range. The voltage range changes, and the larger the current output voltage, the greater the first error signal within the voltage range. The smaller the value within the range, the smaller the current output voltage, and the better the first error signal is within the voltage range. The larger the value of the inner element, the better.

[0053] When the current output voltage is greater than the target output voltage, i.e., the command voltage is less than the first voltage divider, the voltage value of the first error signal is within the voltage range. The voltage range changes, and the larger the current output voltage, the greater the first error signal within the voltage range. The smaller the value within the range, the smaller the current output voltage, and the better the first error signal is within the voltage range. The larger the value of the inner value, the more likely the current output voltage will converge to the target output voltage after multiple voltage iterations.

[0054] For example, if the target output voltage is 40V, the current output voltage is 35V. The current output voltage is fed back to the first voltage divider circuit 51, which performs voltage division according to a preset voltage division ratio to obtain the first voltage division for the first boost operation. The first error amplifier circuit 52 generates a first error signal for the first boost operation based on the command voltage and the first voltage division for the first boost operation. The voltage output module 400 increases the output voltage based on the first error signal for the first boost operation; for example, the output voltage after the first increase is 38V. After multiple voltage iterations and adjustments, the output voltage fed back by the voltage output module 400 gradually converges to 40V.

[0055] For another example, if the target output voltage is 40V, the current output voltage is 45V. The current output voltage is fed back to the first voltage divider circuit 51, which performs voltage division according to a preset voltage division ratio to obtain the first voltage division for the first step-down operation. The first error amplifier circuit 52 generates a first error signal for the first step-down operation based on the command voltage and the first voltage division for the first step-down operation. The voltage output module 400 reduces the output voltage based on the first error signal for the first step-down operation, for example, the reduced output voltage is 42V. After multiple voltage iterations and adjustments, the output voltage fed back by the voltage output module 400 gradually converges to 40V.

[0056] Following this pattern, after multiple voltage iterations and adjustments, the output voltage fed back by the voltage output module 400 will eventually reach a stable state. At this point, the output voltage fed back by the voltage output module 400 will be divided by the first voltage divider circuit 51 according to the preset voltage division ratio, resulting in a voltage difference of 0 between the first voltage divider and the command voltage. This will ultimately ensure that the output voltage of the voltage output module 400 remains at the target output voltage.

[0057] In this embodiment, the higher output voltage fed back by the voltage output module 400 is reduced to a first voltage close to the command voltage by the first voltage divider circuit 51, so as to accelerate the convergence speed of the output voltage of the voltage output module 400 to the target output voltage. The error between the command voltage and the first voltage is characterized in the form of a first error signal by the first error amplifier circuit 52. The first error signal enables the voltage output module 400 to adjust the output voltage, thereby realizing accurate and fast automatic tracking of the output voltage to the command voltage.

[0058] Please see Figure 3 The first voltage divider circuit 51 includes a first resistor R1 and a second resistor R2. The first error amplifier circuit 52 includes a third resistor R3 and a first error amplifier U1. The first end of the first resistor R1 is applied with the output voltage fed back by the voltage output module 400. The second end of the first resistor R1 and the first end of the second resistor R2 are both electrically connected to the inverting input terminal of the first error amplifier U1. The first end of the third resistor R3 is applied with a command voltage. The second end of the third resistor R3 is electrically connected to the non-inverting input terminal of the first error amplifier U1. The output terminal of the first error amplifier U1 is electrically connected to the voltage output module 400.

[0059] The first resistor R1 and the second resistor R2 are configured to divide the output voltage fed back by the voltage output module 400 according to a preset voltage division ratio to obtain the first voltage division, and transmit the first voltage division to the inverting input terminal of the first error amplifier U1. The command voltage is transmitted to the non-inverting input terminal of the first error amplifier U1 through the third resistor R3.

[0060] The working principle of the feedback regulation module 500 is as follows: Output voltage The voltage is divided by the first resistor R1 and the second resistor R2, resulting in a first voltage at the inverting input of the first error amplifier U1. Among them, the first pressure division With output voltage The mathematical relationship is as follows: , This is the preset voltage distribution ratio.

[0061] Command voltage The voltage is transmitted through the third resistor R3 to the non-inverting input of the first error amplifier U1, which is based on the command voltage. and the first pressure division A first error signal is generated. The first error signal is transmitted to the voltage output module 400, and the voltage output module 400 adjusts its output voltage under the drive of the bus voltage.

[0062] After multiple voltage iterations and adjustments, the command voltage... With the first pressure division Equal, that is: When the output voltage fed back by the voltage output module 400 is in a stable state, the output voltage of the voltage output module 400 is the target output voltage.

[0063] Please see Figure 4 The voltage regulation module 300 includes an error generation circuit 31 and a voltage control circuit 32. The error generation circuit 31 is electrically connected to the voltage conversion module 200, and the voltage control circuit 32 is electrically connected to both the error generation circuit 31 and the voltage conversion module 200.

[0064] Error generation circuit 31 is configured to generate a second error signal based on the command voltage and the bus output voltage fed back from voltage conversion module 200. Voltage control circuit 32 is configured to adjust the drive signal based on the second error signal to adjust the bus voltage output by voltage conversion module 200.

[0065] The second error signal is used to reflect the deviation between the target bus voltage anchored by the command voltage and the bus voltage currently fed back by the voltage output module 400. The error generation circuit 31 needs to transmit the second error signal to the voltage control circuit 32 so that the voltage control circuit 32 adjusts the drive signal based on the second error signal, so that the bus voltage output by the voltage conversion module 200 converges to the target bus voltage anchored by the command voltage. For example, the target bus voltage anchored by the command voltage is 31.4V, and the bus voltage initially output by the voltage conversion module 200 is 30V. After multiple error feedback iterations, the bus voltage output by the voltage conversion module 200 finally converges to 31.4V, and the 31.4V bus voltage is the target bus voltage.

[0066] It is understood that in the embodiments of this application, a single command voltage is synchronously transmitted to the voltage regulation module 300 and the feedback regulation module 500 respectively. On the one hand, for the voltage regulation module 300, the command voltage can cause the voltage regulation module 300 to control the voltage conversion module 200 to output the target bus voltage in a steady state. On the other hand, for the feedback regulation module 500, the command voltage can cause the feedback regulation module 500 to control the voltage output module 400 to output the target output voltage in a steady state. Therefore, the same command voltage can control different circuits to output different voltages in a steady state.

[0067] The second error signal is positively correlated with the duty cycle of the drive signal. The larger the second error signal, the larger the duty cycle of the drive signal. The voltage control circuit 32 outputs a drive signal with a larger duty cycle to the voltage conversion module 200, causing the voltage conversion module 200 to increase the bus voltage. For example, if the target bus voltage is 41.4V and the current bus voltage is 35V, since the current bus voltage of 35V is less than the target bus voltage of 40V, the second error signal of this first boost operation can prompt the voltage control circuit 32 to increase the duty cycle of the drive signal, causing the voltage conversion module 200 to increase the current bus voltage, for example, to 38V. After multiple voltage iterations and adjustments, the bus voltage fed back by the voltage conversion module 200 gradually converges to 41.4V.

[0068] Similarly, the smaller the second error signal, the smaller the duty cycle of the drive signal. The voltage control circuit 32 outputs a drive signal with a smaller duty cycle to the voltage conversion module 200, causing the voltage conversion module 200 to reduce the bus voltage. For example, if the target bus voltage is 41.4V and the current bus voltage is 45V, since the current bus voltage of 45V is greater than the target bus voltage of 41.4V, the second error signal of this first voltage reduction operation can prompt the voltage control circuit 32 to reduce the duty cycle of the drive signal, causing the voltage conversion module 200 to reduce the current bus voltage, for example, to 43V. After multiple voltage iterations and adjustments, the bus voltage fed back by the voltage conversion module 200 gradually converges to 41.4V.

[0069] Similarly, after multiple voltage iterations and adjustments, the bus voltage output by the voltage conversion module 200 will be in a stable state and will converge to the target bus voltage.

[0070] Please see Figure 5 The error generation circuit 31 includes a level shifting circuit 311, a second voltage divider circuit 312, and a second error amplifier circuit 313. The level shifting circuit 311 is electrically connected to the voltage conversion module 200, the second voltage divider circuit 312 is electrically connected to the level shifting circuit 311, a command voltage is applied to the non-inverting input of the second error amplifier circuit 313, the inverting input of the second error amplifier circuit 313 is electrically connected to the second voltage divider circuit 312, and the output of the second error amplifier circuit 313 is electrically connected to the voltage control circuit 32.

[0071] The level shifting circuit 311 is configured to perform level shifting processing on the bus voltage fed back by the voltage conversion module 200 according to a preset floating threshold to obtain a reference voltage. Level shifting processing refers to shifting the bus voltage fed back by the voltage conversion module 200 downwards according to the preset floating threshold. For example, if the preset floating threshold is 1.4V and the bus voltage fed back by the voltage conversion module 200 is 31.4V, the level shifting circuit 311 shifts the bus voltage fed back by the voltage conversion module 200 downwards according to the preset floating threshold of 1.4V to obtain a reference voltage of 30V.

[0072] The second voltage divider circuit 312 is configured to divide the reference voltage according to a preset voltage division ratio to obtain a second voltage. After both the voltage regulation module 300 and the feedback regulation module 500 enter a steady state, the second voltage is consistent with the first voltage.

[0073] In the feedback adjustment module 500, the first voltage divider circuit 51 also needs to divide the output voltage fed back by the voltage output module 400 according to a preset voltage division ratio to obtain the first voltage. In the error generation circuit 31, the second voltage divider circuit 312 also needs to divide the reference voltage according to the same preset voltage division ratio. When both the voltage adjustment module 300 and the feedback adjustment module 500 enter a steady state, the first voltage output by the first voltage divider circuit 51 is consistent with the second voltage output by the second voltage divider circuit 312, and both the first voltage and the second voltage are equal to the command voltage. This process has the following logical relationship, as shown below: Reference voltage ,in, The bus voltage fed back by the voltage conversion module 200 For reference voltage, This is a preset floating threshold.

[0074] Second pressure ,in, This is the second partial voltage. This is the preset voltage distribution ratio.

[0075] First pressure division ,in, This is the first voltage divider. This is the output voltage.

[0076] After both the voltage regulation module 300 and the feedback regulation module 500 reach a steady state, the command voltage... ,Right now: As can be seen from the formula, under steady state, the bus voltage output by the voltage conversion module 200 is only slightly greater than the output voltage output by the voltage output module 400 than the preset floating threshold, which is 1.4V. Therefore, the bus voltage output by the voltage conversion module 200 can be considered to be slightly greater than the output voltage output by the voltage output module 400. This can lock the power consumption of the battery simulation circuit provided in this application embodiment within a small power range.

[0077] The second error amplifier circuit 313 is configured to generate a second error signal based on the command voltage and the second voltage divider. The second error amplifier circuit 313 can be a single-supply error amplifier, wherein the input power supply of the single-supply error amplifier can be 12V, and the output voltage of the second error amplifier circuit 313 is greater than 0V and less than 12V, i.e., 0V < second error signal < 12V. The expression for the output voltage of the second error amplifier circuit 313 is:

[0078] From the above formula, it can be seen that the second partial pressure It is negatively correlated with the second error signal, due to the second voltage divider. The second error signal is positively correlated with the bus voltage fed back by the voltage conversion module 200; therefore, it is negatively correlated with the bus voltage fed back by the voltage conversion module 200. The smaller the bus voltage fed back by the voltage conversion module 200, the larger the second error signal; conversely, the larger the bus voltage fed back by the voltage conversion module 200, the smaller the second error signal.

[0079] As shown above, mapping the above formula to a two-dimensional coordinate system x0y, the function in the formula is a monotonically decreasing function in the first quadrant, and the intersection coordinates of this monotonically decreasing function with the x-axis are... The coordinates of the intersection with the y-axis are .

[0080] When the current bus voltage equals the target bus voltage, i.e., the command voltage equals the second voltage divider, the voltage value of the second error signal equals the bias voltage. When the current bus voltage is less than the target bus voltage, i.e., the command voltage is greater than the second voltage divider, the voltage value of the second error signal is within the voltage range. The voltage changes within a certain range, where the higher the current bus voltage, the greater the second error signal becomes within that voltage range. The smaller the value within the range, the smaller the current bus voltage, and the better the second error signal is within the voltage range. The larger the value of the inner element, the better.

[0081] When the current bus voltage is greater than the target bus voltage, i.e., the command voltage is less than the second voltage divider, the voltage value of the second error signal is within the voltage range. The voltage changes within a certain range, where the higher the current bus voltage, the greater the second error signal becomes within that voltage range. The smaller the value within the range, the smaller the current bus voltage, and the better the second error signal is within the voltage range. The larger the value of the inner value, the more likely the current bus voltage will converge to the target bus voltage after multiple voltage iterations.

[0082] The second error signal is positively correlated with the bus voltage fed back by the voltage conversion module 200. The larger the second error signal, the larger the bus voltage fed back by the voltage conversion module 200; conversely, the smaller the second error signal, the smaller the bus voltage fed back by the voltage conversion module 200.

[0083] The larger the second error signal, the larger the duty cycle of the drive signal. The voltage control circuit 32 outputs a drive signal with a larger duty cycle to the voltage conversion module 200, causing the voltage conversion module 200 to increase the bus voltage. For example, if the target bus voltage is 41.4V and the current bus voltage is 35V, since the current bus voltage of 35V is less than the target bus voltage of 40V, the second error signal output by the second error amplifier circuit 313 is relatively large. The second error signal can prompt the voltage control circuit 32 to increase the duty cycle of the drive signal, causing the voltage conversion module 200 to increase the current bus voltage, for example, to 38V. After multiple voltage iterations, the current bus voltage will gradually converge to the target bus voltage of 41.4V.

[0084] The smaller the second error signal, the smaller the duty cycle of the drive signal. The voltage control circuit 32 outputs a drive signal with a smaller duty cycle to the voltage conversion module 200, causing the voltage conversion module 200 to reduce the bus voltage. For example, if the target bus voltage is 41.4V and the current bus voltage is 45V, since the current bus voltage of 45V is greater than the target bus voltage of 41.4V, the second error signal output by the second error amplifier circuit 313 is relatively small. This second error signal can prompt the voltage control circuit 32 to reduce the duty cycle of the drive signal, causing the voltage conversion module 200 to reduce the current bus voltage, for example, to 43V. After multiple voltage iterations, the current bus voltage will gradually converge to the target bus voltage of 41.4V.

[0085] In this embodiment, the bus voltage fed back by the voltage conversion module 200 is level-shifted according to a preset floating threshold by the level shifting circuit 311. This lays the foundation for ensuring that the bus voltage output by the voltage conversion module 200 in steady state is only greater than the output voltage output by the voltage output module 400 than the preset floating threshold. The reference voltage is divided by the second voltage divider circuit 312 using the same preset voltage division ratio as the first voltage divider circuit 51, which helps to ensure that the obtained second voltage division is consistent with the first voltage division in steady state. The command voltage is compared with the second voltage division by the second error amplifier circuit 313. The obtained second error signal can prompt the voltage control circuit 32 to adjust the duty cycle of the drive signal so as to drive the voltage conversion module 200 to adjust the bus voltage. Finally, it can ensure that the bus voltage output by the voltage conversion module 200 gradually converges to the target bus voltage in steady state.

[0086] In some embodiments, the level shifting circuit 311 can be a Zener diode, and the Zener diode's regulated voltage value is a preset floating threshold. For example, the Zener diode's regulated voltage value is 2V, and the preset floating threshold is 2V.

[0087] In other embodiments, please refer to Figure 6 The level shifting circuit 311 includes a first diode D1 and a second diode D2. The second voltage divider circuit 312 includes a fourth resistor R4 and a fifth resistor R5. The second error amplifier circuit 313 includes a sixth resistor R6 and a second error amplifier U2. The positive terminal of the first diode D1 is applied with a bus voltage Vs. The negative terminal of the first diode D1 is electrically connected to the positive terminal of the second diode D2. The negative terminal of the second diode D2 is electrically connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is electrically connected to the first terminal of the fifth resistor R5 and the inverting input terminal of the second error amplifier U2. The second terminal of the fifth resistor R5 is grounded. The first terminal of the sixth resistor R6 is applied with a command voltage. The second terminal of the sixth resistor R6 is electrically connected to the non-inverting input terminal of the second error amplifier U2.

[0088] The first diode D1 and the second diode D2 are configured to perform level shifting processing on the bus voltage fed back by the voltage conversion module 200 according to a preset floating threshold to obtain a reference voltage.

[0089] The fourth resistor R4 and the fifth resistor R5 are configured to divide the reference voltage according to a preset voltage division ratio to obtain a second voltage, and the second voltage is transmitted to the inverting input of the second error amplifier U2. The command voltage is transmitted to the non-inverting input of the second error amplifier U2 through the sixth resistor R6.

[0090] The working principle of the error generation circuit 31 is as follows: The bus voltage Vs fed back by the voltage conversion module 200 is applied to the positive terminal of the first diode D1. After level shifting by the first diode D1 and the second diode D2, the bus voltage Vs becomes a reference voltage. This reference voltage is then divided by the fourth resistor R4 and the fifth resistor R5, and a second voltage divider is applied to the inverting input of the second error amplifier U2. The second voltage divider... With bus voltage The mathematical relationship is as follows: , This is the preset voltage division ratio. Combining the mathematical expression for the relationship between the first voltage division and the output voltage, we can see that... .

[0091] The command voltage is applied to the non-inverting input of the second error amplifier U2 through the sixth resistor R6. The second error amplifier U2 compares the command voltage with the second voltage divider to obtain the second error signal.

[0092] The second error amplifier U2 transmits the second error signal to the voltage control circuit 32. The voltage control circuit 32 adjusts the drive signal based on the second error signal to adjust the bus voltage output by the voltage conversion module 200. Under steady state, the bus voltage output by the voltage conversion module 200 will converge to the target bus voltage.

[0093] Please see Figure 7 The voltage control circuit 32 includes a voltage feedback circuit 321 and a boost driver chip 322. The voltage feedback circuit 321 is electrically connected to the error generation circuit 31, and the boost driver chip 322 is electrically connected to both the voltage feedback circuit 321 and the voltage conversion module 200.

[0094] Voltage feedback circuit 321 is configured to generate a target compensation signal based on a second error signal. Boost driver chip 322 is configured to adjust the drive signal based on the target compensation signal to regulate the bus voltage output by voltage conversion module 200. The target compensation signal Vcomp is positively correlated with the duty cycle of the drive signal. A larger target compensation signal Vcomp results in a larger duty cycle of the drive signal output by boost driver chip 322 and a larger bus voltage output by voltage conversion module 200; conversely, a smaller target compensation signal Vcomp results in a smaller duty cycle of the drive signal output by boost driver chip 322 and a smaller bus voltage output by voltage conversion module 200.

[0095] Please see Figure 8The voltage feedback circuit 321 includes a signal amplification circuit 3211, a current injection circuit 3212, and a three-terminal regulator 3213. The signal amplification circuit 3211 is electrically connected to the error generation circuit 31. The current injection circuit 3212 is electrically connected to the signal amplification circuit 3211 at the feedback node FB and is also electrically connected to the voltage conversion module 200. The reference electrode of the three-terminal regulator 3213 is electrically connected to the feedback node FB, the anode of the three-terminal regulator 3213 is grounded, and the cathode of the three-terminal regulator 3213 is electrically connected to the compensation terminal COMP of the boost driver chip 322.

[0096] The signal amplification circuit 3211 is configured to draw current from a preset feedback node FB based on a second error signal to adjust the feedback voltage of the feedback node. The magnitude of the current drawn from the feedback node FB is negatively correlated with the feedback voltage of the feedback node FB; that is, the more current drawn from the feedback node FB, the smaller the feedback voltage of the feedback node FB. The second error signal is also negatively correlated with the feedback voltage; a larger second error signal results in a smaller feedback voltage, and vice versa.

[0097] For example, if the target bus voltage is 41.4V and the current bus voltage is 35V, since the current bus voltage of 35V is less than the target bus voltage of 40V, the second error signal output by the second error amplifier circuit 313 is relatively large. Based on this second error signal, the signal amplifier circuit 3211 draws a larger current from the feedback node FB.

[0098] For another example, if the target bus voltage is 41.4V and the current bus voltage is 45V, since the current bus voltage of 45V is greater than the target bus voltage of 41.4V, the second error signal output by the second error amplifier circuit 313 is relatively small. In contrast, the signal amplifier circuit 3211 draws less current from the feedback node FB based on this second error signal.

[0099] The signal amplification circuit 3211 provided in this application embodiment can respond to changes in the second error signal, dynamically extract current from the feedback node, dynamically adjust the feedback voltage of the feedback node, thereby changing the working state of the three-terminal regulator 3213, so as to adjust the voltage condition of the compensation terminal of the boost drive chip, thereby achieving the purpose of adjusting the duty cycle of the drive signal, and finally causing the bus voltage output by the voltage conversion module 200 to converge to the target bus voltage.

[0100] The current injection circuit 3212 is configured to inject current into the feedback node FB based on the bus voltage fed back from the voltage conversion module 200, thereby adjusting the feedback voltage of the feedback node FB. The magnitude of the current injected into the feedback node FB is positively correlated with the feedback voltage of the feedback node FB; that is, the more current injected into the feedback node FB, the higher the feedback voltage of the feedback node FB. When the bus voltage fed back from the voltage conversion module 200 increases, the current injected into the feedback node FB increases, and the feedback voltage of the feedback node FB can be raised rapidly.

[0101] For example, if the target bus voltage is 41.4V and the current bus voltage is 35V, since the current bus voltage of 35V is less than the target bus voltage of 40V, the second error signal output by the second error amplifier circuit 313 is relatively large. Based on this second error signal, the signal amplifier circuit 3211 draws more current from the feedback node FB. Because the current bus voltage of 35V is low, the current injection circuit 3212 injects less current into the feedback node FB, causing a drop in the feedback voltage of the feedback node FB. Based on the change in the feedback voltage, the three-terminal regulator 3213 controls the boost driver chip 322 to increase the duty cycle of the drive signal in order to raise the current bus voltage to 41.4V.

[0102] For another example, if the target bus voltage is 41.4V and the current bus voltage is 45V, since the current bus voltage of 45V is greater than the target bus voltage of 41.4V, the second error signal output by the second error amplifier circuit 313 is relatively small. Based on this second error signal, the signal amplifier circuit 3211 draws a smaller current from the feedback node FB. Since the current bus voltage of 35V is relatively high, the current injection circuit 3212 injects a larger current into the feedback node FB. Consequently, the feedback voltage of the feedback node FB rises. Based on the change in the feedback voltage, the three-terminal regulator 3213 controls the boost driver chip 322 to reduce the duty cycle of the drive signal in order to reduce the current bus voltage to 41.4V.

[0103] The three-terminal regulator 3213 is configured to respond to a feedback voltage being less than a reference voltage by gradually increasing the on-resistance of the three-terminal regulator, thereby gradually increasing the voltage of the target compensation signal at the compensation terminal COMP of the boost driver chip 322, and thereby increasing the duty cycle of the drive signal based on the gradually increasing target compensation signal.

[0104] The reference voltage is the voltage configured within the three-terminal regulator 3213. When the feedback voltage is lower than the reference voltage, the on-resistance of the three-terminal regulator 3213 gradually increases, tending towards the cutoff state. Influenced by the internal chip architecture of the boost driver chip 322, the voltage of the target compensation signal at the compensation terminal of the boost driver chip 322 gradually increases. When the compensation terminal of the boost driver chip 322 receives the target compensation signal with a gradually increasing voltage, the boost driver chip 322 increases the duty cycle of the drive signal and then transmits the drive signal to the voltage conversion module 200. The voltage conversion module 200 is driven by the high duty cycle drive signal, increasing the bus voltage. The bus voltage is fed back to the error generation circuit 31, which generates a second error signal based on the command voltage and the bus output voltage fed back by the voltage conversion module 200. The voltage control circuit 32 adjusts the drive signal based on the second error signal to adjust the bus voltage output by the voltage conversion module 200. After multiple error feedback iterations, the voltage regulation module 300 enters a steady state, and the bus voltage output by the voltage conversion module 200 finally converges to the target bus voltage.

[0105] The three-terminal regulator 3213 is also configured to gradually reduce the on-resistance of the three-terminal regulator 3213 in response to the feedback voltage being greater than or equal to the reference voltage, so that the voltage of the target compensation signal at the compensation end of the boost driver chip 322 gradually decreases, and the boost driver chip 322 reduces the duty cycle of the drive signal based on the target compensation signal with gradually decreasing voltage.

[0106] When the feedback voltage is greater than or equal to the reference voltage, the on-resistance of the three-terminal regulator 3213 gradually decreases, tending to enter the on state. The three-terminal regulator 3213 pulls down the voltage at the compensation terminal of the boost driver chip 322. Therefore, the compensation terminal of the boost driver chip 322 detects the target compensation signal with a gradually decreasing voltage. When the compensation terminal of the boost driver chip 322 receives the target compensation signal with a gradually decreasing voltage, the boost driver chip 322 reduces the duty cycle of the drive signal. The voltage conversion module 200 is driven by the drive signal with a small duty cycle, reducing the bus voltage. The bus voltage is fed back to the error generation circuit 31, which generates a second error signal based on the command voltage and the bus output voltage fed back by the voltage conversion module 200. The voltage control circuit 32 adjusts the drive signal based on the second error signal to adjust the bus voltage output by the voltage conversion module 200. After multiple error feedback iterations, the voltage adjustment module 300 enters a steady state, and the bus voltage output by the voltage conversion module 200 finally converges to the target bus voltage.

[0107] As mentioned earlier, the second error signal is negatively correlated with the bus voltage and negatively correlated with the feedback voltage of the feedback node. The bus voltage is positively correlated with the feedback voltage of the feedback node. Therefore, when the bus voltage increases, for example, if the target bus voltage is 31.4V and the current bus voltage is 33V, the bus voltage is fed back to the error generation circuit 31, resulting in a smaller second error signal. This smaller second error signal is input to the signal amplification circuit 3211. The signal amplification circuit 3211 can only draw a small current from the feedback node FB. Simultaneously, the current injection circuit 3212 injects a larger current into the feedback node FB based on the larger bus voltage. The feedback node FB experiences both a small current outflow and a large current injection, causing the feedback voltage of the feedback node FB to rise rapidly. When the feedback voltage exceeds the reference voltage, the three-terminal regulator 3213 tends to conduct, and the boost driver chip 322 reduces the duty cycle of the drive signal according to the above mechanism. This causes the voltage conversion module 200 to reduce the bus voltage, for example, reducing the bus voltage to 32V. After multiple voltage iterations, the bus voltage output by the voltage conversion module 200 finally stabilized at 31.4V.

[0108] Similarly, when the bus voltage decreases, for example, if the target bus voltage is 31.4V and the current bus voltage is 30V, the bus voltage is fed back to the error generation circuit 31, resulting in a larger second error signal. This larger second error signal is input to the signal amplification circuit 3211, which draws more current from the feedback node FB. Simultaneously, the current injection circuit 3212 injects less current into the feedback node FB based on the smaller bus voltage. The feedback node FB experiences both a larger current outflow and a smaller current injection, resulting in an overall decrease in the feedback voltage of the feedback node FB. When the feedback voltage is less than the reference voltage, the three-terminal regulator 3213 tends to cut off, and the boost driver chip 322 increases the duty cycle of the drive signal according to the above mechanism. This causes the voltage conversion module 200 to increase the bus voltage, for example, raising it to 31V. After multiple voltage iterations, the bus voltage output by the voltage conversion module 200 finally stabilizes at 31.4V.

[0109] In this embodiment, the feedback voltage of the feedback node is quickly adjusted through the coordinated operation of the signal amplification circuit 3211 and the current injection circuit 3212. This enables the boost driver chip 322 to quickly adjust the duty cycle of the drive signal, ultimately allowing the bus voltage output by the voltage conversion module 200 to quickly converge to the target bus voltage, which is beneficial to improving the voltage simulation efficiency of the battery simulation circuit 100.

[0110] Please see Figure 9The signal amplification circuit 3211 includes a seventh resistor R7, an eighth resistor R8, a first NPN transistor NQ1, and a third diode D3. The current injection circuit 3212 includes a ninth resistor R9 and a tenth resistor R10. A second error signal is applied to the first terminal of the seventh resistor R7. The second terminal of the seventh resistor R7, the first terminal of the eighth resistor R8, and the base of the first NPN transistor NQ1 are electrically connected to the same node. The second terminal of the eighth resistor R8 and the emitter of the first NPN transistor NQ1 are both grounded. The collector of the first NPN transistor NQ1 is electrically connected to the cathode of the third diode D3. The anode of the third diode D3, the first terminal of the ninth resistor R9, and the first terminal of the tenth resistor R10 are electrically connected to the feedback node FB. The second terminal of the ninth resistor R9 is applied with a bus voltage Vs, and the second terminal of the tenth resistor R10 is grounded.

[0111] The first NPN transistor NQ1 is configured to enter the amplification state and, based on the second error signal, draws current from the preset feedback node FB to adjust the feedback voltage of the feedback node FB.

[0112] The ninth resistor R9 and the tenth resistor R10 are configured to inject current into the feedback node FB based on the bus voltage fed back by the voltage conversion module 200, so as to adjust the feedback voltage of the feedback node FB.

[0113] The working principle of voltage feedback circuit 321 is as follows: The first NPN transistor NQ1 is set to amplification mode. The second error signal is transmitted to the base of the first NPN transistor NQ1 through the seventh resistor R7, providing base current to the base of the first NPN transistor NQ1. The first NPN transistor NQ1 amplifies the base current, thereby increasing the current flowing through the collector of the first NPN transistor NQ1. The collector of the first NPN transistor NQ1 is electrically connected to the feedback node FB through the third diode D3. The current flowing out of the feedback node FB through the third diode D3 is equal to the current of the collector of the first NPN transistor NQ1. Therefore, the collector of the first NPN transistor NQ1 can draw current from the feedback node FB. The amount of current drawn by the collector of the first NPN transistor NQ1 from the feedback node FB is positively correlated with the second error signal. That is, the larger the second error signal, the more current the collector of the first NPN transistor NQ1 draws from the feedback node FB, and the smaller the second error signal, the less current the collector of the first NPN transistor NQ1 draws from the feedback node FB.

[0114] like Figure 9As shown, under the premise that the bus voltage Vs fed back by the voltage conversion module 200 remains unchanged, when the current bus voltage is less than the target bus voltage, the second error signal increases, and the collector current of the first NPN transistor NQ1 increases. The more current the collector of the first NPN transistor NQ1 draws from the feedback node FB, the less current is transferred from the feedback node FB to the tenth resistor R10. The feedback voltage of the feedback node FB is equal to the voltage across the tenth resistor R10. When the current flowing through the tenth resistor R10 decreases, the voltage across the tenth resistor R10 decreases, meaning the feedback voltage of the feedback node FB decreases. When the feedback voltage of the feedback node FB is less than the 2.5V reference voltage of the reference terminal of the three-terminal regulator 3213, the three-terminal regulator 3213 tends to be cut off. The compensation terminal COMP of the boost driver chip 322 detects the target compensation signal with gradually increasing voltage, so that the boost driver chip 322 increases the duty cycle of the drive signal based on the target compensation signal with gradually increasing voltage. The voltage conversion module 200 increases the bus voltage Vs based on the drive signal with increased duty cycle.

[0115] Conversely, the increased bus voltage Vs injects more current into the tenth resistor R10 through the ninth resistor R9, causing the feedback voltage of the feedback node FB to increase. If the increased feedback voltage is still less than the reference voltage, the three-terminal regulator 3213 tends to turn off, and the compensation terminal COMP of the boost driver chip 322 continuously detects the target compensation signal with gradually increasing voltage. This causes the boost driver chip 322 to increase the duty cycle of the drive signal based on the target compensation signal with gradually increasing voltage, and the voltage conversion module 200 increases the bus voltage Vs based on the drive signal with increased duty cycle.

[0116] If the increased feedback voltage is greater than or equal to the reference voltage, the three-terminal regulator 3213 tends to turn on. The compensation terminal of the boost driver chip 322 detects the target compensation signal with gradually decreasing voltage, causing the boost driver chip 322 to reduce the duty cycle of the drive signal based on the target compensation signal with gradually decreasing voltage. The voltage conversion module 200 reduces the bus voltage Vs based on the drive signal with reduced duty cycle.

[0117] After multiple voltage iterations and adjustments, the bus voltage output by the voltage conversion module 200 converges to the target bus voltage.

[0118] Similarly, when the current bus voltage is greater than the target bus voltage, the second error signal decreases, and the collector current of the first NPN transistor NQ1 decreases. As the collector of the first NPN transistor NQ1 draws less current from the feedback node FB, the current transferred from the feedback node FB to the tenth resistor R10 relatively increases. The feedback voltage of the feedback node FB is equal to the voltage across the tenth resistor R10. When the current flowing through the tenth resistor R10 increases, the voltage across the tenth resistor R10 increases, meaning the feedback voltage of the feedback node FB increases. When the feedback voltage of the feedback node FB is greater than the 2.5V reference voltage of the three-terminal regulator 3213, the three-terminal regulator 3213 tends to conduct. The compensation terminal of the boost driver chip 322 detects the gradually decreasing target compensation signal, causing the boost driver chip 322 to reduce the duty cycle of the drive signal based on the gradually decreasing target compensation signal. The voltage conversion module 200 then reduces the bus voltage Vs based on the reduced duty cycle drive signal.

[0119] If the reduced feedback voltage is still less than the reference voltage, the three-terminal regulator 3213 tends to turn on, and the compensation terminal COMP of the boost driver chip 322 continuously detects the target compensation signal with gradually decreasing voltage. This causes the boost driver chip 322 to reduce the duty cycle of the drive signal based on the target compensation signal with gradually decreasing voltage. The voltage conversion module 200 continues to reduce the bus voltage Vs based on the drive signal with reduced duty cycle.

[0120] If the reduced feedback voltage is less than the reference voltage, the three-terminal regulator 3213 tends to turn off. The compensation terminal COMP of the boost driver chip 322 detects the target compensation signal with gradually increasing voltage, causing the boost driver chip 322 to increase the duty cycle of the drive signal based on the target compensation signal with gradually increasing voltage. The voltage conversion module 200 increases the bus voltage Vs based on the drive signal with increased duty cycle.

[0121] After multiple voltage iterations and adjustments, the bus voltage output by the voltage conversion module 200 converges to the target bus voltage.

[0122] Please see Figure 10 The voltage output module 400 includes an amplification unit 41 and a voltage output unit 42. The amplification unit 41 is electrically connected to the feedback adjustment module 500 and the voltage conversion module 200, respectively, and the voltage output unit 42 is electrically connected to the amplification unit 41.

[0123] Amplification unit 41 is configured to perform current amplification operation based on a first error signal and driven by the bus voltage to obtain the target current. The first error signal is positively correlated with the target current; when the first error signal increases, the target current increases, and when the first error signal decreases, the target current decreases.

[0124] The voltage output unit 42 is configured to generate an output voltage based on the target current.

[0125] The amplification unit 41 provided in this embodiment uses the bus voltage as the driving source to perform current amplification operation on the first error signal, which can convert the weak first error signal into a large current drive of the power level. Finally, the target current is converted into an output voltage through the voltage output unit 42 for output, thereby realizing high-gain voltage output.

[0126] Please see Figure 11 The amplification unit 41 includes a first amplification subunit 411, a second amplification subunit 412, and a third amplification subunit 413. The first amplification subunit 411 is electrically connected to the feedback adjustment module 500, the second amplification subunit 412 is electrically connected to the first amplification subunit 411 and the voltage conversion module 200, and the third amplification subunit 413 is electrically connected to the second amplification subunit 412 and the voltage conversion module 200, respectively.

[0127] The first amplification subunit 411 is configured to perform a first-stage current amplification operation based on a first error signal to obtain a first amplified current. The second amplification subunit 412 is configured to perform a second-stage current amplification operation on the first amplified current under the drive of the bus voltage to obtain a second amplified current. The third amplification subunit 413 is configured to perform a third-stage current amplification operation on the second amplified current under the drive of the bus voltage to obtain a target current.

[0128] The embodiments of this application employ a multi-stage current amplification architecture consisting of a first amplification subunit 411, a second amplification subunit 412, and a third amplification subunit 413, which achieves high-gain current amplification from a microampere-level first error signal to a power output of hundreds of milliamperes, thereby meeting the needs of battery simulation.

[0129] Please continue reading. Figure 3The first amplification subunit 411 includes an eleventh resistor R11, a twelfth resistor R12, and a second NPN transistor NQ2. The second amplification subunit 412 includes a thirteenth resistor R13 and a first PNP transistor PQ1. The third amplification subunit 413 includes a fourteenth resistor R14 and a third NPN transistor NQ3. A first error signal is applied to the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11, the first terminal of the twelfth resistor R12, and the base of the second NPN transistor NQ2 are electrically connected to the same node. The second terminal of the twelfth resistor R12 and the base of the second NPN transistor NQ2 are also connected to the same node. The emitters of transistors 2 and 3 are all grounded. The collector of the second NPN transistor NQ2 is electrically connected to the first terminal of the thirteenth resistor R13, and the second terminal of the thirteenth resistor R13 is electrically connected to the base of the first PNP transistor PQ1. The emitter of the first PNP transistor PQ1 and the collector of the third NPN transistor NQ3 are both subject to a bus voltage Vs. The collector of the first PNP transistor PQ1 is electrically connected to the first terminal of the fourteenth resistor R14, and the second terminal of the fourteenth resistor R14 is electrically connected to the base of the third NPN transistor NQ3. The emitter of the third NPN transistor NQ3 is electrically connected to the voltage output unit 42. All three transistors—the second NPN transistor NQ2, the first PNP transistor PQ1, and the third NPN transistor NQ3—are configured to enter amplification mode.

[0130] The working principle of the amplification unit 41 is as follows: The second NPN transistor NQ2, the first PNP transistor PQ1, and the third NPN transistor NQ3 are all operating in amplification mode.

[0131] The first error signal injects base current into the second NPN transistor NQ2 through the eleventh resistor R11. The expression for this base current is: ,in, This is the first error signal. This represents the base current of the second NPN transistor NQ2. The on-state voltage drop is typically 0.7V.

[0132] Since the second NPN transistor NQ2 is operating in amplification mode, the collector current of the second NPN transistor NQ2 is: ,in, This is the collector current (i.e., the first amplification current) of the second NPN transistor NQ2. This is the amplification factor of the second NPN transistor NQ2.

[0133] The collector of the second NPN transistor NQ2 is electrically connected to the base of the first PNP transistor PQ1 through the thirteenth resistor R13. Therefore, the current at the collector of the second NPN transistor NQ2 is equal to the current at the base of the first PNP transistor PQ1.

[0134] Since the first PNP transistor PQ1 is operating in amplification mode, the collector current of the first PNP transistor PQ1 is: ,in, This is the collector current (i.e., the second amplification current) of the first PNP transistor PQ1. This is the amplification factor of the first PNP transistor, PQ1.

[0135] The collector current of the first PNP transistor PQ1 flows through the fourteenth resistor R14 and then through the base of the third NPN transistor NQ3. Therefore, the base current of the third NPN transistor NQ3 is: ,in, This is the base current of the third NPN transistor NQ3.

[0136] Since the third NPN transistor NQ3 is operating in amplification mode, the emitter current of the third NPN transistor NQ3 is: ; in, This refers to the emitter current (i.e., the target current) of the third NPN transistor NQ3. This represents the amplification factor of the third NPN transistor NQ3. From the above formula, it can be seen that the emitter current of the third NPN transistor NQ3 is related to the first error signal. They are positively correlated.

[0137] It is understandable that the bus voltage Vs has the following function in the amplification unit 41: the bus voltage Vs can set the operating point of the second NPN transistor NQ2, the first PNP transistor PQ1, and the third NPN transistor NQ3, so that the second NPN transistor NQ2, the first PNP transistor PQ1, and the third NPN transistor NQ3 all enter the amplification state. For example, for the second NPN transistor NQ2 to enter the amplification state, the collector voltage of the second NPN transistor NQ2 must be high enough. This collector voltage is controlled by the bus voltage Vs. For instance, the collector voltage of the second NPN transistor NQ2 is equal to the bus voltage Vs minus the forward voltage drop of the first PNP transistor PQ1, and then minus the voltage across the thirteenth resistor R13. If the collector voltage of the second NPN transistor NQ2 is less than its base voltage, then the second NPN transistor NQ2 enters saturation, not the amplification state. Therefore, the bus voltage Vs provides the voltage condition for the second NPN transistor NQ2 to enter the amplification state.

[0138] For example, in order for the third NPN transistor NQ3 to enter the amplification state, the collector voltage of the third NPN transistor NQ3 must be high enough. This process is consistent with the process described above, and will not be repeated here.

[0139] Overall, the bus voltage Vs provides the voltage condition for the second NPN transistor NQ2, the first PNP transistor PQ1, and the third NPN transistor NQ3 to enter the amplification state. Without the bus voltage Vs, it is impossible to guarantee that the weak first error signal can be converted into a power-level bus current.

[0140] Please see Figure 12 The voltage output unit 42 includes a first switching circuit 421, a third voltage divider circuit 422, and a second switching circuit 423. The first switching circuit 421 is electrically connected to the amplification unit 41 at a preset first node N1; the third voltage divider circuit 422 is electrically connected to the amplification unit 41 at the preset first node N1, and is also electrically connected to the first switching circuit 421 at a preset second node N2; the second switching circuit 423 is electrically connected to the third voltage divider circuit 422.

[0141] The second switching circuit 423 is configured to enter the target switching state in response to the target enable signal, so that the target current output by the amplification unit 41 passes through the third voltage divider circuit 422, and the voltage generated by the third voltage divider circuit 422 at the second node N2 triggers the first switching circuit 421 to enter the target switching state, and the voltage generated at the first node N1 is output as an output voltage through the conducting first switching circuit 421.

[0142] The target enable signal is a signal that can trigger the second switching circuit 423 to enter the target switching state. The target enable signal can be either high or low. The target enable signal can be sent by the controller. The target switching state is a switching state that enables the flow of the target current. The target switching state can be either on or off, and the target switching state depends on the switching type of the second switching circuit 423.

[0143] Please continue reading. Figure 3The first switching circuit 421 includes a first PMOS transistor PM1, the third voltage divider circuit 422 includes a fifteenth resistor R15 and a sixteenth resistor R16, and the second switching circuit 423 includes a seventeenth resistor R17, an eighteenth resistor R18, and a fourth NPN transistor NQ4. The source of the first PMOS transistor PM1 and the first terminal of the fifteenth resistor R15 are both electrically connected to the first node N1. The drain of the first PMOS transistor PM1 is configured to transmit the output voltage. The second terminal of the fifteenth resistor R15 and the sixteenth resistor R16 are connected to the first node N1. The first terminal of R16 and the gate of the first PMOS transistor PM1 are both electrically connected to the second node N2. The second terminal of the sixteenth resistor R16 is electrically connected to the collector of the fourth NPN transistor NQ4. The base of the fourth NPN transistor NQ4 is electrically connected to the first terminal of the seventeenth resistor R17 and the first terminal of the eighteenth resistor R18 on the same node. The second terminal of the seventeenth resistor R17 is given a target enable signal. The second terminal of the eighteenth resistor R18 and the emitter of the fourth NPN transistor NQ4 are both grounded.

[0144] The first PMOS transistor PM1 is configured to enter the on-state in response to a voltage generated at the second node N2 exceeding the on-state voltage drop of the first PMOS transistor PM1, wherein the target switch state is the on-state. The fourth NPN transistor NQ4 is configured to enter the saturation on-state in response to a target enable signal.

[0145] The working principle of voltage output unit 42 is as follows: The controller transmits a high-level target enable signal to the fourth NPN transistor NQ4 through the seventeenth resistor R17, causing NQ4 to enter saturation conduction. The target current output by the third NPN transistor NQ3 is transmitted to ground through the fifteenth resistor R15, the sixteenth resistor R16, and the third NPN transistor NQ3. This causes the fifteenth resistor R15, the sixteenth resistor R16, and the third NPN transistor NQ3 to generate voltage dividers at the first node N1 and the second node N2, respectively. The voltage divider at the second node N2 controls the first PMOS transistor PM1 to enter linear conduction, at which point PM1 can be considered a switch. The voltage divider at the first node N1 serves as the output voltage, which is output through the conducting first PMOS transistor PM1.

[0146] Please see Figure 13The voltage conversion module 200 includes a first capacitor C1, a first inductor L1, a first NMOS transistor NM1, a nineteenth resistor R19, a fourth diode D4, and a second capacitor C2. Input voltages are applied to the first terminals of both the first capacitor C1 and the first inductor L1. The second terminal of the first capacitor C1 is grounded. The second terminal of the first inductor L1 is electrically connected to the drain of the first NMOS transistor NM1 and the anode of the fourth diode D4, respectively. The cathode of the fourth diode D4 is electrically connected to the first terminal of the second capacitor C2, configured to transmit the output voltage. The second terminal of the second capacitor C2 is grounded. The source of the first NMOS transistor NM1 is electrically connected to the first terminal of the nineteenth resistor R19, and the second terminal of the nineteenth resistor R19 is grounded. The gate of the first NMOS transistor NM1 is electrically connected to the drive terminal of the voltage regulation module 300. The voltage across the nineteenth resistor R19 is transmitted to the boost driver chip 322 via node BST_C for processing by the boost driver chip 322.

[0147] The working principle of the voltage conversion module 200 is as follows: The voltage conversion module 200 operates in boost mode. Specifically, the drive terminal of the voltage regulation module 300 outputs a drive signal corresponding to the duty cycle, which acts on the gate of the first NMOS transistor NM1. When the high-level portion of the drive signal acts on the gate of the first NMOS transistor NM1, NM1 enters the conducting state, and the 12V input voltage charges the first inductor L1. When the low-level portion of the drive signal acts on the gate of the first NMOS transistor NM1, NM1 enters the cutoff state, and the first inductor L1 discharges. The electromotive force of the first inductor L1 is added in series with the 12V input voltage to obtain the bus voltage, which is then output.

[0148] As another aspect of this application, this application provides a battery simulation device. Please refer to... Figure 14 The battery simulation device 140 includes a controller 600 and a battery simulation circuit 100. The voltage regulation module 300 and feedback regulation module 500 of the battery simulation circuit 100 are electrically connected to the controller 600. The controller 600 is configured to output a command voltage according to preset digital-to-analog commands. The battery simulation circuit 100 generates output voltage and current based on the command voltage.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A battery simulation circuit, characterized in that, include: The voltage conversion module is configured to acquire a drive signal and perform a voltage conversion operation on a preset input voltage based on the drive signal to obtain the bus voltage; A voltage regulation module, electrically connected to the voltage conversion module, is configured to receive a command voltage and, based on the command voltage and the bus voltage fed back by the voltage conversion module, adjust the drive signal to adjust the bus voltage output by the voltage conversion module. A voltage output module, electrically connected to the voltage conversion module, is configured to generate an output voltage; The feedback adjustment module, electrically connected to the voltage output module, is configured to receive the command voltage and, based on the command voltage and the output voltage fed back by the voltage output module, transmit a first error signal to the voltage output module, so that the voltage output module adjusts the output voltage of the voltage output module under the drive of the bus voltage based on the first error signal.

2. The battery simulation circuit according to claim 1, characterized in that, After both the voltage regulation module and the feedback regulation module have entered a steady state, the bus voltage output by the voltage conversion module is greater than the output voltage output by the voltage output module, and the voltage difference between the bus voltage and the output voltage is less than or equal to a preset floating threshold.

3. The battery simulation circuit according to claim 2, characterized in that, The duty cycle of the drive signal is positively correlated with the bus voltage; and / or, The preset floating threshold is equal to the sum of the voltage drops of the two diodes.

4. The battery simulation circuit according to claim 1, characterized in that, The feedback adjustment module includes: The first voltage divider circuit is electrically connected to the voltage output module and is configured to divide the output voltage fed back by the voltage output module according to a preset voltage division ratio to obtain the first voltage divider. A first error amplifier circuit is configured to generate a first error signal based on the command voltage and the first voltage divider circuit, wherein the output voltage fed back by the voltage output module is negatively correlated with the first error signal.

5. The battery simulation circuit according to claim 4, characterized in that, The first voltage divider circuit includes a first resistor and a second resistor. The first error amplifier circuit includes a third resistor and a first error amplifier. The first terminal of the first resistor is applied with the output voltage fed back by the voltage output module. The second terminal of the first resistor and the first terminal of the second resistor are both electrically connected to the inverting input terminal of the first error amplifier. The first terminal of the third resistor is applied with the command voltage. The second terminal of the third resistor is electrically connected to the non-inverting input terminal of the first error amplifier. The output terminal of the first error amplifier is electrically connected to the voltage output module. The first resistor and the second resistor are configured to divide the output voltage fed back by the voltage output module according to a preset voltage division ratio to obtain a first voltage division, and the first voltage division is transmitted to the inverting input terminal of the first error amplifier. The command voltage is transmitted to the non-inverting input terminal of the first error amplifier through the third resistor.

6. The battery simulation circuit according to claim 4, characterized in that, The voltage regulation module includes: An error generation circuit, electrically connected to the voltage conversion module, is configured to generate a second error signal based on the command voltage and the bus voltage fed back by the voltage conversion module. The voltage control circuit, which is electrically connected to the error generation circuit and the voltage conversion module respectively, is configured to adjust the drive signal based on the second error signal to adjust the bus voltage output by the voltage conversion module.

7. The battery simulation circuit according to claim 6, characterized in that, The error generation circuit includes: A level shifting circuit, electrically connected to the voltage conversion module, is configured to perform level shifting processing on the bus voltage fed back by the voltage conversion module according to a preset floating threshold to obtain a reference voltage; The second voltage divider circuit is electrically connected to the level shifting circuit and is configured to divide the reference voltage according to a preset voltage division ratio to obtain the second voltage. The second voltage is consistent with the first voltage after the voltage regulation module and the feedback regulation module have both entered a steady state. The second error amplifier circuit has the command voltage applied to its non-inverting input terminal, the inverting input terminal electrically connected to the second voltage divider circuit, and the output terminal electrically connected to the voltage control circuit. The second error amplifier circuit is configured to generate a second error signal based on the command voltage and the second voltage divider circuit.

8. The battery simulation circuit according to claim 7, characterized in that, The level shifting circuit includes a first diode and a second diode; the second voltage divider circuit includes a fourth resistor and a fifth resistor; the second error amplifier circuit includes a sixth resistor and a second error amplifier; the positive terminal of the first diode is applied with the bus voltage; the negative terminal of the first diode is electrically connected to the positive terminal of the second diode; the negative terminal of the second diode is electrically connected to the first end of the fourth resistor; the second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the inverting input terminal of the second error amplifier; the second end of the fifth resistor is grounded; the first end of the sixth resistor is applied with the command voltage; and the second end of the sixth resistor is electrically connected to the non-inverting input terminal of the second error amplifier. The first diode and the second diode are configured to perform level shifting processing on the bus voltage fed back by the voltage conversion module according to a preset floating threshold to obtain a reference voltage; The fourth resistor and the fifth resistor are configured to divide the reference voltage according to a preset voltage division ratio to obtain a second voltage, and the second voltage is transmitted to the inverting input of the second error amplifier. The command voltage is transmitted to the non-inverting input of the second error amplifier through the sixth resistor.

9. The battery simulation circuit according to claim 6, characterized in that, The voltage control circuit includes: A voltage feedback circuit, electrically connected to the error generation circuit, is configured to generate a target compensation signal based on the second error signal; The boost drive chip is electrically connected to the voltage feedback circuit and the voltage conversion module, respectively, and is configured to adjust the drive signal based on the target compensation signal to adjust the bus voltage output by the voltage conversion module.

10. The battery simulation circuit according to claim 9, characterized in that, The voltage feedback circuit includes: A signal amplification circuit, electrically connected to the error generation circuit, is configured to draw current from a preset feedback node based on the second error signal to adjust the feedback voltage of the feedback node. A current injection circuit, electrically connected to the signal amplification circuit and also electrically connected to the voltage conversion module at the feedback node, is configured to inject current into the feedback node based on the bus voltage fed back by the voltage conversion module, so as to adjust the feedback voltage of the feedback node. A three-terminal voltage regulator, wherein the reference electrode of the three-terminal voltage regulator is electrically connected to the feedback node, the anode of the three-terminal voltage regulator is grounded, and the cathode of the three-terminal voltage regulator is electrically connected to the compensation terminal of the boost driver chip. The three-terminal voltage regulator is configured to, in response to the feedback voltage being less than the reference voltage, gradually increase the on-resistance of the three-terminal voltage regulator, thereby gradually increasing the voltage of the target compensation signal at the compensation terminal of the boost driver chip, and thus increasing the duty cycle of the drive signal based on the gradually increasing target compensation signal; or, in response to the feedback voltage being greater than or equal to the reference voltage, gradually decrease the on-resistance of the three-terminal voltage regulator, thereby gradually decreasing the voltage of the target compensation signal at the compensation terminal of the boost driver chip, and thus decreasing the duty cycle of the drive signal based on the gradually decreasing target compensation signal.

11. The battery simulation circuit according to claim 10, characterized in that, The signal amplification circuit includes a seventh resistor, an eighth resistor, a first NPN transistor, and a third diode. The current injection circuit includes a ninth resistor and a tenth resistor. The second error signal is applied to the first terminal of the seventh resistor. The second terminal of the seventh resistor, the first terminal of the eighth resistor, and the base of the first NPN transistor are electrically connected to the same node. The second terminal of the eighth resistor and the emitter of the first NPN transistor are both grounded. The collector of the first NPN transistor is electrically connected to the negative terminal of the third diode. The positive terminal of the third diode, the first terminal of the ninth resistor, and the first terminal of the tenth resistor are electrically connected to the feedback node. The bus voltage is applied to the second terminal of the ninth resistor, and the second terminal of the tenth resistor is grounded. The first NPN transistor is configured to enter an amplification state and, based on the second error signal, draws current from a preset feedback node to adjust the feedback voltage of the feedback node. The ninth resistor and the tenth resistor are configured to inject current into the feedback node based on the bus voltage fed back by the voltage conversion module, so as to adjust the feedback voltage of the feedback node.

12. The battery simulation circuit according to any one of claims 1 to 11, characterized in that, The voltage output module includes: The amplification unit, which is electrically connected to the feedback adjustment module and the voltage conversion module respectively, is configured to perform a current amplification operation based on the first error signal and driven by the bus voltage to obtain the target current; A voltage output unit, electrically connected to the amplification unit, is configured to generate an output voltage based on the target current.

13. The battery simulation circuit according to claim 12, characterized in that, The amplification unit includes: The first amplification subunit is electrically connected to the feedback adjustment module and is configured to perform a first-stage current amplification operation based on the first error signal to obtain a first amplified current. The second amplification subunit is electrically connected to the first amplification subunit and the voltage conversion module, respectively, and is configured to perform a second-stage current amplification operation on the first amplified current under the drive of the bus voltage to obtain a second amplified current; The third amplification subunit is electrically connected to the second amplification subunit and the voltage conversion module, respectively, and is configured to perform a third-stage current amplification operation on the second amplified current under the drive of the bus voltage to obtain the target current.

14. The battery simulation circuit according to claim 13, characterized in that, The first amplification subunit includes an eleventh resistor, a twelfth resistor, and a second NPN transistor; the second amplification subunit includes a thirteenth resistor and a first PNP transistor; the third amplification subunit includes a fourteenth resistor and a third NPN transistor; the first terminal of the eleventh resistor is applied with the first error signal; the second terminal of the eleventh resistor, the first terminal of the twelfth resistor, and the base of the second NPN transistor are electrically connected to the same node; the second terminal of the twelfth resistor and the emitter of the second NPN transistor are both grounded; the collector of the second NPN transistor is electrically connected to the first terminal of the thirteenth resistor; the second terminal of the thirteenth resistor is electrically connected to the base of the first PNP transistor; the emitter of the first PNP transistor and the collector of the third NPN transistor are both applied with the bus voltage; the collector of the first PNP transistor is electrically connected to the first terminal of the fourteenth resistor; the second terminal of the fourteenth resistor is electrically connected to the base of the third NPN transistor; and the emitter of the third NPN transistor is electrically connected to the voltage output unit. The second NPN transistor, the first PNP transistor, and the third NPN transistor are all configured to enter the amplification state.

15. The battery simulation circuit according to claim 12, characterized in that, The voltage output unit includes: The first switching circuit is electrically connected to the amplification unit at a preset first node; The third voltage divider circuit is electrically connected to the amplification unit at a preset first node, and is also electrically connected to the first switching circuit at a preset second node. The second switching circuit, electrically connected to the third voltage divider circuit, is configured to enter a target switching state in response to a target enable signal, so that the target current output by the amplification unit passes through the third voltage divider circuit, causing the voltage generated by the third voltage divider circuit at the second node to trigger the first switching circuit to enter the target switching state, and the voltage generated at the first node is output as the output voltage through the conducting first switching circuit.

16. The battery simulation circuit according to claim 15, characterized in that, The first switching circuit includes a first PMOS transistor, the third voltage divider circuit includes a fifteenth resistor and a sixteenth resistor, and the second switching circuit includes a seventeenth resistor, an eighteenth resistor, and a fourth NPN transistor. The source of the first PMOS transistor and the first terminal of the fifteenth resistor are both electrically connected to the first node. The drain of the first PMOS transistor is configured to transmit the output voltage. The second terminal of the fifteenth resistor, the first terminal of the sixteenth resistor, and the gate of the first PMOS transistor are all electrically connected to the second node. The second terminal of the sixteenth resistor is electrically connected to the collector of the fourth NPN transistor. The base of the fourth NPN transistor, the first terminal of the seventeenth resistor, and the first terminal of the eighteenth resistor are all electrically connected to the same node. A target enable signal is applied to the second terminal of the seventeenth resistor. The second terminal of the eighteenth resistor and the emitter of the fourth NPN transistor are both grounded. The first PMOS transistor is configured to enter the on state in response to the voltage generated by the second node being greater than the on-state voltage drop of the first PMOS transistor, wherein the target switch state is the on state; The fourth NPN transistor is configured to enter a saturated conduction state in response to the target enable signal.

17. A battery simulation device, characterized in that, include: The controller is configured to output a command voltage according to preset digital-to-analog instructions; The battery simulation circuit according to any one of claims 1 to 16, wherein the voltage regulation module and the feedback regulation module of the battery simulation circuit are respectively electrically connected to the controller.

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