A standard cell test circuit

Abstract

The application discloses a standard unit test circuit, relates to the technical field of integrated circuit design, and saves chip area and cost, improves the accuracy of leakage current test results, and reduces power consumption. The test circuit comprises a voltage adjusting circuit, a first controllable switch, a current-voltage conversion circuit, n switch networks, n auxiliary units and n second controllable switches, and n is greater than or equal to 2; a third end of the i th switch network is connected with a power supply end of the i th auxiliary unit and is connected with a power supply end of the i th test unit through the i th second controllable switch; i = 1, 2, 3, …, n; the voltage adjusting circuit has a monitoring end, a power supply end, a feedback input end and an output end; the power supply end of the voltage adjusting circuit is connected with a power supply through the first controllable switch, the output end is connected with second ends of the n switch networks, and the feedback input end is connected with first ends of the n switch networks; and the monitoring end is connected with an input end of the current-voltage conversion circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a standard unit test circuit. Background Technology

[0002] Standard cells, as fundamental building blocks in circuit design, encompass a range of basic logic and functional units such as inverters, NAND gates, and registers. Through specific combinational logic and connection methods, these cells can be used to construct circuits with complex logical operations and efficient data processing capabilities. This construction method is extremely common in integrated circuit design, especially in the field of ASIC (Application-Specific Integrated Circuit) design.

[0003] The performance of standard cells directly affects the realization of the logic functions and overall performance of a chip (the physical implementation of an integrated circuit). With the continuous advancement of semiconductor process technology, manufacturers establish corresponding standard cell libraries for different process nodes. These libraries, as core resources for integrated circuit design, are crucial for ensuring the efficiency and reliability of the design. However, the process of developing a new standard cell library into mass production requires multiple rigorous tape-out verification and testing stages. This process aims to comprehensively verify whether the logic functions of the standard cells are accurate and error-free, whether the performance indicators meet the design requirements, and simultaneously verify the production level of the process line.

[0004] The performance of a standard cell is typically evaluated from three aspects: speed, area, and power consumption. The power consumption of a standard cell is divided into static power consumption and dynamic power consumption. Dynamic power consumption refers to the power consumed by the standard cell during normal operation, and its magnitude is usually large. Static power consumption refers to the power consumed by the standard cell in standby or idle states, mainly caused by leakage current. Although its magnitude is relatively small, at advanced process nodes, as leakage current increases, the proportion of static power consumption increases significantly and cannot be ignored. Evaluating static power consumption can lay a solid foundation for subsequent integrated circuit design.

[0005] Traditional standard cell test circuits generally employ a separate testing strategy, which involves building independent test circuits for specific test content, such as test circuits for logic function verification and leakage current test circuits when the standard cell is in standby or idle state. However, implementing this separate testing strategy undoubtedly increases the overall chip area and manufacturing cost.

[0006] In advanced process nodes, the leakage current of a standard cell may be as low as the picoampere (pA) level. If the leakage current is directly led to the PAD (pad, which is the interface between the chip and the outside world) and measured, the current is easily interfered with by external circuits and produces large errors. In order to improve the tiny leakage current to a testable level, the traditional standard cell test circuit will adopt the method of connecting multiple standard cells of the same specification in parallel. However, this method often requires a large number of standard cells of the same specification in parallel to reach the current level that external current measuring instruments can recognize, which inevitably occupies a large chip area, and the larger current will also bring more power loss.

[0007] It is evident that traditional standard cell test circuits face several problems: the discrete test strategy increases chip area and cost; when a tiny leakage current signal is directly led to the PAD for measurement, it is susceptible to interference from external circuits, leading to inaccurate test results; and the parallel connection of a large number of standard cells of the same specifications to measure tiny leakage current further occupies a larger chip area and brings more power consumption. Summary of the Invention

[0008] In view of the above problems, this application provides a standard unit test circuit to save chip area and cost, improve the accuracy of leakage current test results, and reduce power consumption. The specific solution is as follows:

[0009] This application provides a standard unit test circuit, including: a voltage adjustment circuit, a first controllable switch, a current-to-voltage conversion circuit, n switch networks, n auxiliary units, and n second controllable switches, where n≥2;

[0010] The internal components of the i-th switch network are responsible for establishing a three-terminal interconnected electrical connection or keeping the three terminals disconnected, according to the controller's instructions; i = 1, 2, 3, ..., n;

[0011] The internal components of the i-th auxiliary unit are responsible for establishing or de-connecting the power supply terminal P4 and the ground terminal of the i-th auxiliary unit according to the instructions of the controller.

[0012] The third terminal P3 of the i-th switch network is connected to the power supply terminal P4 of the i-th auxiliary unit, and is connected to the power supply terminal P5 of the i-th test unit via the i-th second controllable switch.

[0013] The voltage regulation circuit has a monitoring terminal P6, a power supply terminal P7, a feedback input terminal P8, and an output terminal P9. Its power supply terminal P7 is connected to the power supply VDD via a first controllable switch. Its output terminal P9 is simultaneously connected to the second terminal P2 of n switching networks, and its feedback input terminal P8 is simultaneously connected to the first terminal P1 of n switching networks. When the first controllable switch is closed, and the output terminal P9 of the voltage regulation circuit and the feedback input terminal P8 are electrically connected through the i-th switching network, the voltage regulation circuit controls its own monitoring terminal P6 to establish an electrical connection with the output terminal P9, and adjusts the signal of the output terminal P9 according to the signal of the feedback input terminal P8, so as to maintain the voltage difference between the third terminal P3 of the i-th switching network and the power supply VDD within a preset error range.

[0014] The i-th test unit is composed of one or more standard units of the same specification connected in parallel; the logic signal output terminal of the i-th test unit serves as the logic function test port OUT2 of the i-th test unit; the monitoring terminal P6 of the voltage adjustment circuit is connected to the input terminal of the current-to-voltage conversion circuit, and the output terminal of the current-to-voltage conversion circuit serves as the leakage current test port OUT1 shared by n test units.

[0015] In one possible implementation, the voltage regulation circuit includes an operational amplifier OP and a power transistor MN0; the non-inverting input of the operational amplifier OP is connected to the power supply terminal P7 of the voltage regulation circuit; the inverting input of the operational amplifier OP is connected to the feedback input terminal P8 of the voltage regulation circuit; the output of the operational amplifier OP is connected to the control terminal of the power transistor MN0; the current input of the power transistor MN0 is connected to the monitoring terminal P6 of the voltage regulation circuit; and the current output of the power transistor MN0 is connected to the output terminal P9 of the voltage regulation circuit.

[0016] In one possible implementation, each switching network includes a switch MN1 and a switch MN2; the current input terminal of the i-th switch MN1 is connected to the first terminal P1 of the i-th switching network, and the current input terminal of the i-th switch MN2 is connected to the second terminal P2 of the i-th switching network; the current output terminals of the i-th switch MN1 and the i-th switch MN2 are both connected to the third terminal P3 of the i-th switching network.

[0017] In one possible implementation, each auxiliary unit includes a transistor MN3;

[0018] The current input terminal of the i-th transistor MN3 is connected to the power supply terminal of the i-th auxiliary unit; the current output terminal of the i-th transistor MN3 is connected to the ground terminal of the i-th auxiliary unit.

[0019] In one possible implementation, each auxiliary unit also includes: a current source I a and transistor MN6; the i-th current source Ia The output terminal of the i-th transistor MN6, the current input terminal of the i-th transistor MN6, the control terminal of the i-th transistor MN6, and the control terminal of the i-th transistor MN3 are connected to one point; the current output terminal of the i-th transistor MN6 is grounded.

[0020] In one possible implementation, n second controllable switches are omitted, and the third terminal P3 of the i-th switch network is directly connected to the power supply terminal P5 of the i-th test unit.

[0021] In one possible implementation, the standard unit test circuit further includes: n pull-down units;

[0022] The internal components of the i-th pull-down unit are responsible for pulling down the voltage of the power supply terminal P5 of the i-th test unit to ground potential or keeping it in a non-pull-down state according to the instructions of the controller.

[0023] In one possible implementation, each pull-down unit includes a switch MN5; the power input terminal of the i-th switch MN5 is connected to the power supply terminal P5 of the i-th test unit, and the power output terminal of the i-th switch MN5 is grounded.

[0024] In one possible implementation, the standard unit test circuit further includes: a decoder; the output of the decoder is connected to the control terminal of an n-switch network; and the input of the decoder is connected to the controller.

[0025] In one possible implementation, the standard unit test circuit further includes: a data selector;

[0026] The input terminal of the data selector is connected to the logic signal output terminal of n test units, and the output terminal of the data selector serves as the logic function test port OUT3 shared by the n test units.

[0027] By employing the above technical solution, the standard unit test circuit provided in this application can achieve leakage current testing and logic function testing of different test units by switching different switch networks. Specifically: when the first controllable switch is closed, the three terminals of the i-th switch network are connected, the power supply terminal of the i-th auxiliary unit is grounded through the conductive path inside the i-th auxiliary unit, the i-th second controllable switch is closed, and the i-th test unit is in standby or idle state, the test current I... out The current flowing from the monitoring terminal to the output terminal of the voltage adjustment circuit is equal to the sum of the current I3 (the current flowing through the i-th auxiliary unit) and the leakage current of the i-th test unit; then the i-th second controllable switch is disconnected, at which point the test current I... out It equals the current I3; therefore, by obtaining the test current I from the two tests before and after, outBy subtracting the values, the leakage current of the i-th test unit can be obtained. Furthermore, with the first controllable switch closed, the power supply terminal of the i-th auxiliary unit grounded through a conductive path within the i-th auxiliary unit, the three terminals of the i-th switch network connected, and the i-th second controllable switch closed, the i-th test unit is controlled to operate normally. By observing the voltage signal at the OUT2 terminal, the logic function test of the i-th test unit can be achieved. Therefore, this application integrates leakage current testing and logic function testing, saving chip area and cost compared to traditional separate testing strategies. Moreover, the test current I... out The magnitude is relatively large, and it will be converted into a voltage signal that is easier to measure accurately through a current-to-voltage conversion circuit. This not only improves the accuracy of leakage current testing, but also avoids the need to connect multiple standard units of the same specification in parallel to amplify the leakage current, thereby reducing power consumption and further saving chip area. Attached Figure Description

[0028] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0029] Figure 1 A schematic diagram of a standard unit test circuit provided in this application;

[0030] Figure 2 A schematic diagram of yet another standard unit test circuit provided in this application;

[0031] Figure 3 A schematic diagram of another standard unit test circuit provided in this application. Detailed Implementation

[0032] This application provides a standard cell test circuit. This test circuit achieves high integration by reusing test resources and optimizing test logic. Specifically, it integrates leakage current testing and logic function testing, and can meet the testing requirements of standard cells of different specifications in a time-sharing manner, saving chip area and cost. Furthermore, by converting the test current into other more easily measurable signal forms, this test circuit overcomes the challenges of small leakage current magnitude, high measurement difficulty, and susceptibility to interference, thus improving the accuracy of leakage current test results.

[0033] The following detailed description, with reference to the accompanying drawings, describes a standard unit test circuit provided in an embodiment of this application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in this application are equally applicable to similar technical problems.

[0034] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0035] See Figure 1 The present application provides a standard unit test circuit, including: a voltage adjustment circuit 1, a first controllable switch 2, a current-to-voltage conversion circuit 3, n switch networks 4, n auxiliary units 5, and n second controllable switches 6, where n≥2;

[0036] The internal components of the i-th switch network 4 are responsible for establishing a three-terminal interconnected electrical connection or keeping the three terminals disconnected, according to the controller's instructions; i = 1, 2, 3, ..., n;

[0037] The internal components of the i-th auxiliary unit 5 are responsible for establishing or de-connecting the power supply terminal P4 and the ground terminal of the i-th auxiliary unit 5 according to the instructions of the controller.

[0038] The third terminal P3 of the i-th switch network 4 is connected to the power terminal P4 of the i-th auxiliary unit 5, and is connected to the power terminal P5 of the i-th test unit via the i-th second controllable switch 6.

[0039] The voltage adjustment circuit 1 has a monitoring terminal P6, a power supply terminal P7, a feedback input terminal P8, and an output terminal P9. Its power supply terminal P7 is connected to the power supply VDD via a first controllable switch 2. Its output terminal P9 is simultaneously connected to the second terminal P2 of n switch networks 4, and its feedback input terminal P8 is simultaneously connected to the first terminal P1 of n switch networks 4. When the first controllable switch 2 is closed, and the output terminal P9 of the voltage adjustment circuit 1 and the feedback input terminal P8 are electrically connected through the i-th switch network 4, the voltage adjustment circuit 1 controls its own monitoring terminal P6 to establish an electrical connection with its output terminal P9, and adjusts the signal of the output terminal P9 according to the signal of the feedback input terminal P8, so as to maintain the voltage difference between the third terminal P3 of the i-th switch network 4 and the power supply VDD within a preset error range.

[0040] The i-th test unit is composed of one or more standard units of the same specification connected in parallel; the logic signal output terminal of the i-th test unit serves as the logic function test port OUT2 of the i-th test unit; the monitoring terminal P6 of the voltage adjustment circuit 1 is connected to the input terminal of the current-to-voltage conversion circuit 3, and the output terminal of the current-to-voltage conversion circuit 3 serves as the leakage current test port OUT1 shared by n test units.

[0041] The i-th switch network 4, the i-th auxiliary unit 5, the i-th second controllable switch 6, and the i-th test unit constitute the i-th test branch (the first terminal P1 and the second terminal P2 of the i-th switch network 4 are the two ends of the i-th test branch). By switching different switch networks 6, leakage current testing and logic function testing of different test units can be achieved. The working principle of this embodiment will be described in detail below, taking one of the test branches as an example:

[0042] Because the leakage current of a standard cell is relatively small, directly connecting it to the PAD for measurement may be subject to interference from external circuits, leading to significant deviations in the leakage current test results. Furthermore, the small leakage current makes direct measurement difficult. To address these issues, this embodiment introduces a current-to-voltage conversion circuit 3 into the standard cell test circuit. Specifically, the test current is led to the input terminal of the current-to-voltage conversion circuit 3, which converts the small input current signal into a larger voltage signal. The output terminal of the current-to-voltage conversion circuit 3 serves as the final leakage current test port OUT1. The converted voltage signal is stronger than the original current signal, making it easier to measure and identify. By introducing the current-to-voltage conversion circuit 3, not only is the accuracy of the leakage current test improved, but the need to connect multiple standard cells of the same specification in parallel to amplify the leakage current is also avoided, thus saving chip area and reducing power consumption. Of course, if chip area allows, a few standard cells of the same specification can also be connected in parallel to amplify the leakage current. One or a few standard cells of the same specification connected in parallel form a test unit, with different specifications of the standard cells in different test units.

[0043] However, the current-to-voltage conversion circuit 3 will generate a certain voltage drop, causing the power supply voltage of the test unit to be significantly lower than the theoretical power supply voltage VDD (VDD represents both the power supply and the voltage of the power supply), which in turn leads to deviations in the leakage current test and logic function test results of the test unit. Therefore, this application embodiment also introduces a voltage adjustment circuit 1, which uses the voltage adjustment circuit and the switching network 4 to construct a voltage negative feedback system to stabilize the power supply voltage of the test unit at VDD. Specifically, when the first controllable switch 2 is closed, and the first terminal P1, the second terminal P2, and the third terminal P3 of the switch network 4 are electrically connected, the output terminal P9 of the voltage adjustment circuit 1 is electrically connected to the feedback input terminal P8 through the switch network 4. At this time, the voltage adjustment circuit 1 will control its own monitoring terminal P6 to establish an electrical connection with the output terminal P9, and adjust the signal of the output terminal P9 according to the signal of the feedback input terminal P8, so that the voltage of the third terminal P3 of the switch network 4 is basically stable at VDD. Then, when the second controllable switch 6 is closed, ignoring the conduction voltage drop on the second controllable switch 6, the voltage of the power supply terminal P5 of the test unit is basically stable at VDD.

[0044] For ease of description, the current in the electrical connection path formed between the first terminal P1 and the third terminal P3 of the switching network is denoted as I1; the current in the electrical connection path formed between the second terminal P2 and the third terminal P3 of the switching network is denoted as I2; the current in the electrical connection path formed between the power supply terminal P4 and the ground terminal of auxiliary unit 5 is denoted as I3; the current in the electrical connection path formed between the power supply terminal P5 and the ground terminal of the test unit is denoted as I4; and the current in the electrical connection path formed between the monitoring terminal P6 and the output terminal P9 of voltage adjustment circuit 1 is denoted as I... out .

[0045] With the voltage at the third terminal P3 of the switching network 4 basically stable at VDD, this embodiment of the application performs leakage current testing and logic function testing on the same test unit in a time-sharing manner. The specific test process is as follows:

[0046] 1) Leakage current test

[0047] First, the first controllable switch 2 is closed, establishing an interconnected electrical connection between the first terminal P1, the second terminal P2, and the third terminal P3 of the controllable network 4. An electrical connection is also established between the power supply terminal P4 of the auxiliary unit 5 and the ground terminal. The second controllable switch 6 is closed, and the test unit is placed in standby or idle mode. At this time: although current exists in the voltage negative feedback loop, this current primarily transmits voltage information through the voltage negative feedback loop, rather than flowing directly from the output terminal P9 of the voltage adjustment circuit 1 to the feedback input terminal P8. Therefore, the current I1 is approximately zero. After the current flows in from the monitoring terminal P6 of the voltage adjustment circuit 1, it sequentially passes through the output terminal P9 of the voltage adjustment circuit 1, the second terminal P2 of the switch network, and the third terminal P3 of the switch network. Then, it splits into two paths: one path flows through the power supply terminal P4 of the auxiliary unit 5 to the ground terminal, and the other path flows through the second controllable switch 6 and the power supply terminal P5 of the test unit to the ground terminal. Therefore, the current I1 is approximately zero. out =I2 = I3 + I4. Since the test unit is in standby or idle state at this time, the current I4 is the leakage current of the test unit.

[0048] Then, the second controllable switch 6 is opened. At this time, the current I1 is still basically zero, but the current I2 changes from flowing in two separate paths to flowing only in one path, that is, the current I... out =I2=I3.

[0049] Before and after disconnecting the second controllable switch 6, the current I... out The sizes are denoted as I. out1 I out2 Then the leakage current of the test unit I4 = I out1 -I out2 Assume the test unit consists of M D It consists of standard units of the same specifications connected in parallel, and the leakage current of each standard unit is I. D Then the leakage current of the test unit is M. D ×I D The leakage current I of a single standard cell D =(I out1 -I out2 ) / M D It can be seen that the current I before and after the second controllable switch 6 is disconnected is measured. out The test current I obtained in the two tests was... out By subtracting the values, the leakage current of the test unit can be obtained.

[0050] Figure 2 In this context, A represents the input signal of the test unit. By controlling the input signal A, the test unit can be in different states (standby state or idle state), and the leakage current of the test unit in different states can be measured.

[0051] It should be noted that the embodiments of this application do not directly measure the leakage current of the test unit because the leakage current of the test unit is small and difficult to measure; moreover, although the leakage current of the test unit can be made to reach the current level that can be recognized by an external current measuring instrument by connecting a large number of standard units in parallel in the test unit, this inevitably occupies a large chip area, so it is also not advisable. The embodiments of this application measure I separately out1 I out2 Then, the leakage current I of the test unit is obtained by subtraction. out1 and I out2 Relatively large, easier to measure accurately, and with a larger negative feedback current (I) compared to the leakage current. out1 and I out2 To a certain extent, it can ensure the normal operation of the voltage regulation circuit 1, help to establish stable negative feedback, better suppress interference and nonlinear distortion in the circuit, and improve the accuracy of leakage current testing.

[0052] Of course, when the leakage current of the test unit is large, the second controllable switch 6 can also be disconnected from the circuit and the leakage current of the test unit can be measured directly.

[0053] 2) Logical Function Testing

[0054] After the first controllable switch 2 is closed, establishing an interconnected electrical connection between the first terminal P1, the second terminal P2, and the third terminal P3 of the controllable switch network 4, establishing an electrical connection between the power supply terminal P4 of the auxiliary unit 5 and the ground terminal, and closing the second controllable switch 6, and after the test unit is operating normally, current flows into the voltage adjustment circuit 1 from the monitoring terminal P6, then sequentially through the output terminal P9 of the voltage adjustment circuit 1, the second terminal P2 of the controllable switch network, and the third terminal P3 of the controllable switch network. The current then splits into two paths: one path flows through the power supply terminal P4 of the auxiliary unit 5 to the ground terminal, and the other path flows through the second controllable switch 6 and the power supply terminal P5 of the test unit to the ground terminal. At this time, the current flowing into the monitoring terminal P6 of the voltage adjustment circuit 1 is relatively large, sufficient to ensure the normal operation of the voltage adjustment circuit 1 and establish stable negative feedback. Therefore, by controlling the input signal A of the test unit and observing the voltage signal at the logic function test port OUT2, the logic function of the test unit can be tested. The test unit may have multiple input signals; in this case, input signal A represents one set of input signals.

[0055] Based on the above analysis of the working principle, it can be seen that for any test branch, when the first controllable switch 2 is closed, the three terminals of the switch network 4 are connected, the power supply terminal P4 of the auxiliary unit 5 is grounded through the conductive path inside the auxiliary unit 5, the second controllable switch 6 is closed, and the test unit is in standby or idle state, the test current I... outThe current I3 is equal to the sum of the current I3 and the leakage current of the test unit; then the second controllable switch 6 is disconnected, at which point the test current I... out It equals the current I3; therefore, by obtaining the test current I from the two tests before and after, out The leakage current of the test unit can be obtained by subtracting the values. Furthermore, for any test branch, with the first controllable switch 2 closed, the power supply terminal P4 of the auxiliary unit 5 grounded through the internal conductive path of the auxiliary unit 5, the three terminals of the switch network 4 connected, and the second controllable switch 6 closed, the test unit is controlled to operate normally. By observing the voltage signal at the OUT2 terminal, the logic function test of the test unit can be achieved. It is evident that this embodiment integrates leakage current testing and logic function testing, saving chip area and cost compared to the traditional separate testing strategy. Moreover, the test current I... out The current-to-voltage conversion circuit 3 converts the current into a voltage signal that is easier to measure accurately. This not only improves the accuracy of leakage current testing, but also avoids the need to connect multiple standard units of the same specifications in parallel to amplify the leakage current, thereby reducing power consumption and further saving chip area.

[0056] In one possible implementation, see Figure 2 Each switch network 4 in any of the above embodiments includes a switch MN1 and a switch MN2; the current input terminal of the i-th switch MN1 is connected to the first terminal P1 of the i-th switch network 4, and the current input terminal of the i-th switch MN2 is connected to the second terminal P2 of the i-th switch network 4; the current output terminals of the i-th switch MN1 and the i-th switch MN2 are both connected to the third terminal P3 of the i-th switch network 4.

[0057] Specifically, the control terminals of both switches MN1 and MN2 are connected to the controller to perform turn-on and turn-off actions under the control of the controller. When both switches MN1 and MN2 are on, an interconnected electrical connection is established between the first terminal P1, the second terminal P2, and the third terminal P3 of the i-th switch network 4. When both switches MN1 and MN2 are off, a disconnected electrical connection is established between the first terminal P1, the second terminal P2, and the third terminal P3 of the i-th switch network 4. Switches MN1 and MN2 are, for example, both N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). When the switch is an N-type MOSFET, its power input terminal is the drain of the N-type MOSFET, its power output terminal is the source of the N-type MOSFET, and its control terminal is the gate of the N-type MOSFET.

[0058] In one possible implementation, see still Figure 2 Each auxiliary unit 5 in any of the above embodiments includes a transistor MN3; the current input terminal of the i-th transistor MN3 is connected to the power supply terminal of the i-th auxiliary unit 5; the current output terminal of the i-th transistor MN3 is connected to the ground terminal of the i-th auxiliary unit 5.

[0059] Specifically, the control terminal of the i-th transistor MN3 is connected to the controller to perform turn-on and turn-off actions under the control of the controller. When the i-th transistor MN3 is turned on, an electrical connection is established between the power supply terminal P4 of the i-th auxiliary unit 5 and the ground terminal. When the i-th transistor MN3 is turned off, the electrical connection between the power supply terminal P4 of the i-th auxiliary unit 5 and the ground terminal is broken. The i-th transistor MN3 is, for example, an N-type MOSFET.

[0060] In one possible implementation, see still Figure 2 In any of the above embodiments, the voltage adjustment circuit 1 includes an operational amplifier OP and a power transistor MN0. The non-inverting input of the operational amplifier OP is connected to the power supply terminal P7 of the voltage adjustment circuit 1; the inverting input of the operational amplifier OP is connected to the feedback input terminal P8 of the voltage adjustment circuit 1; the output of the operational amplifier OP is connected to the control terminal of the power transistor MN0; the current input of the power transistor MN0 is connected to the monitoring terminal P6 of the voltage adjustment circuit 1; and the current output of the power transistor MN0 is connected to the output terminal P9 of the voltage adjustment circuit 1. The power transistor MN0 is, for example, an N-type MOSFET.

[0061] In any of the above embodiments, the second controllable switch 6 includes, for example, a switching transistor MN4, which is, for example, an N-type MOSFET. In any of the above embodiments, the first controllable switch 2 includes, for example, a switching transistor MP1, which is, for example, a P-type MOSFET. When the switching transistor is a P-type MOSFET, its power input terminal is the source of the P-type MOSFET, its power output terminal is the drain of the P-type MOSFET, and its control terminal is the gate of the P-type MOSFET.

[0062] Below, on Figure 2 The test process for performing leakage current testing and logic function testing on the test unit in a time-sharing manner, as shown in the diagram, is described in detail below:

[0063] 1) Leakage current test

[0064] First, control switches MP1, MN1, MN2, MN3, and MN4 are turned on, and the test unit is controlled to be in standby or idle state. At this time, since the voltage Vp at the non-inverting input of operational amplifier OP is initially higher than its voltage Vn at its inverting input, according to the basic operating principle of operational amplifier OP, operational amplifier OP will output a high-level signal. The amplitude of this high-level signal is higher than the turn-on voltage of power transistor MN0, thus turning on power transistor MN0. After power transistor MN0 is turned on, the output of operational amplifier OP is connected to its inverting input through a feedback network. Operational amplifier OP has a sufficiently high open-loop gain, which allows the loop to form deep negative feedback.

[0065] When an operational amplifier (OP) is in deep negative feedback mode, it exhibits "virtual short" and "virtual open" characteristics. "Virtual short" means the voltage at the non-inverting and inverting input terminals of the OP is nearly equal; "virtual open" means the input current at the non-inverting and inverting input terminals is approximately zero (because the OP has a high input impedance, the input current at both terminals is approximately zero). These two characteristics work together to allow the OP to automatically adjust its output voltage based on the input signal and feedback network parameters, maintaining the output voltage around a specific value closely related to the input signal and feedback network, thus ensuring relative stability of the output state.

[0066] The currents flowing through switching transistors MN1, MN2, MN3, MN4, and MN0 are I1, I2, I3, I4, and I, respectively. out .

[0067] Based on the "virtual short" characteristic of the operational amplifier (OP), we know that Vn = Vp = VDD. Based on the "virtual open" characteristic of the OP, the current I1 is approximately zero, so the potential Ve at point E (the third terminal P3 of the switching network) is approximately equal to Vn. Ignoring the on-state voltage drop of the switching transistor MN4, the potential Vf at point F (the power supply terminal P5 of the test unit) is approximately equal to Ve. Therefore, the potential Vf at point F is approximately equal to VDD, meaning the power supply voltage of the test unit is approximately equal to VDD.

[0068] Because the power transistor MN0 is turned on, I out =I2. Since the current I1 is approximately zero, the current I2 = I3 + I4. Therefore, I... out =I2=I3+I4. Since the test unit is in standby or idle state and the power supply voltage of the test unit is approximately equal to VDD, the current I4 can be regarded as the leakage current of the test unit. Therefore, the measured current I output from the first output terminal OUT1 is... outThis is the sum of current I3 and leakage current of the test unit.

[0069] Next, control switch MN4 is turned off (switches MN1, MN2, MN3, and the test unit remain in the state before switch MN4 was turned off). At this time, operational amplifier OP is still in a deep negative feedback state, current I1 is still basically zero, and the potential at point E, Ve, is still approximately equal to Vn. However, current I2 changes from flowing in two paths to flowing only in one path, i.e., I... out =I2=I3.

[0070] Before and after the switching transistor MN4 is turned off, the measured current output from the first output terminal OUT1 is recorded as I. out1 I out2 Then the leakage current of the test unit is I. out1 -I out2 Assume the test unit consists of M D It consists of three identical standard units connected in parallel, with each standard unit having a leakage current of I. D Then the leakage current of the test unit is M. D ×I D The leakage current I of a single standard cell D =(I out1 -I out2 ) / M D .

[0071] 2) Logical Function Testing

[0072] The test unit operates normally, controlling the conduction of transistors MN1, MN2, MN3, and MN4. At this time, according to the "virtual short" characteristic of the operational amplifier OP, Vn = Vp = VDD. According to the "virtual open" characteristic of the operational amplifier OP, the current I1 is approximately zero, so the potential at point E, Ve, is approximately equal to Vn. Ignoring the on-state voltage drop of transistor MN4, the potential at point F, Vf, is approximately equal to Ve. Therefore, the potential at point F, Vf, is approximately equal to VDD, meaning the power supply voltage of the test unit is VDD. By controlling the input signal A of the test unit and observing the voltage signal at the second output terminal OUT2, the logic function of the test unit can be tested.

[0073] like Figure 3 As shown, each auxiliary unit 5 may also include: a current source I a and transistor MN6; the i-th current source I a The output terminal of the i-th transistor MN6, the current input terminal of the i-th transistor MN6, the control terminal of the i-th transistor MN6, and the control terminal of the i-th transistor MN3 are connected to one point; the current output terminal of the i-th transistor MN6 is grounded.

[0074] Specifically, during leakage current testing, for any test branch, the control test unit is in standby or idle state, and switches MN1, MN2, MN3, MN4, and MN6 are turned on. At this time, transistors MN3 and MN6 form a current mirror structure, and the current flowing through transistor MN6 is a known quantity I. a The current flowing through transistor MN3 is I3. The dimensions of transistors MN3 and MN6 are known. Assume the current mirror factor is N. a Then I3 = I a / N a .

[0075] The main difference between this embodiment and the previous embodiments lies in the value of the current I3. For other aspects of the principle analysis, please refer to the working principle analysis in the previous embodiments for understanding. I3 = I a / N a Since its value is known and controllable, the second controllable switch 6 is kept on, and the test current I is tested only once. out The leakage current of the standard unit can be obtained by subtraction. Therefore, the second controllable switch 6 can be omitted, and the third terminal P3 of the switch network 4 can be directly connected to the power supply terminal P5 of the test unit.

[0076] Of course, if the user has I a If the calibration value is questionable, the test current I can also be measured twice, similar to the previous embodiment. out Then, the leakage current of the standard cell is obtained by subtraction.

[0077] In one possible implementation, any of the standard unit test circuits provided above may further include: n pull-down units; the internal components of the i-th pull-down unit are responsible for working according to the controller's instructions to pull down the voltage of the power supply terminal (P5) of the i-th test unit to ground potential, or to keep it in a non-pull-down state.

[0078] Specifically, when a test unit is in the test state, the other test branches are not turned on due to the presence of the switching network. The presence of the pull-down unit can pull down the potential of the power supply terminal of the test power supply in the other test branches, thus preventing the voltage node of the test unit from being left floating for a long time when it is not selected.

[0079] See also Figure 2 or Figure 3 Each pull-down unit includes a switch MN5. The power input terminal of the i-th switch MN5 is connected to the power supply terminal (P5) of the i-th test unit, and the power output terminal of the i-th switch MN5 is grounded.

[0080] See also Figure 2 or Figure 3The standard unit test circuit provided above may further include: a decoder; the output terminal of the decoder is connected to the control terminal S of an n-switch network. i The input terminal of the decoder is connected to the controller; the input ports of the decoder are D1 to D2. m The output ports are S1 to S2. n , m < n.

[0081] Specifically, a decoder is a circuit that converts input binary code into a set of output signals. This conversion allows a smaller binary input to control more output lines, thereby reducing the number of control pins required.

[0082] See also Figure 2 or Figure 3 The standard unit test circuit provided above may further include: a data selector MUX; the input terminal of the data selector is connected to the logic signal output terminal Y of n test units. i The output of the data selector serves as the logic function test port OUT3 shared by n test units.

[0083] Specifically, a data selector can select one signal from multiple input signals and output it to a single output terminal. In this embodiment, the data selector is used to select a signal from the logic signal output terminals of n test units and then send it to the logic function test port OUT3 shared by the n test units. A significant advantage of this method is that it can reduce the number of ports required, thereby simplifying the wiring and management of the test system.

[0084] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of this application. Therefore, the embodiments of this application are not to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A standard unit test circuit, characterized in that, include: The circuit consists of a voltage regulation circuit (1), a first controllable switch (2), a current-to-voltage conversion circuit (3), n switch networks (4), n auxiliary units (5), and n second controllable switches (6), where n ≥ 2. The internal components of the i-th switch network (4) are responsible for establishing a three-terminal interconnected electrical connection or keeping the three terminals disconnected from each other, according to the controller's instructions; i = 1, 2, 3, ..., n; The internal components of the i-th auxiliary unit (5) are responsible for establishing or de-connecting the power supply terminal (P4) and the ground terminal of the i-th auxiliary unit (5) according to the instructions of the controller. The third terminal (P3) of the i-th switch network (4) is connected to the power supply terminal (P4) of the i-th auxiliary unit (5), and is connected to the power supply terminal (P5) of the i-th test unit via the i-th second controllable switch (6). The voltage adjustment circuit (1) has a monitoring terminal (P6), a power supply terminal (P7), a feedback input terminal (P8), and an output terminal (P9). Its power supply terminal (P7) is connected to the power supply (VDD) via a first controllable switch (2). Its output terminal (P9) is simultaneously connected to the second terminal (P2) of n switch networks (4), and its feedback input terminal (P8) is simultaneously connected to the first terminal (P1) of n switch networks (4). When the first controllable switch (2) is closed, and the output terminal (P9) of the voltage adjustment circuit (1) and the feedback input terminal (P8) are electrically connected via the i-th switch network (4), the voltage adjustment circuit (1) controls its own monitoring terminal (P6) to establish an electrical connection with the output terminal (P9), and adjusts the signal of the output terminal (P9) according to the signal of the feedback input terminal (P8) to maintain the voltage difference between the third terminal (P3) of the i-th switch network (4) and the power supply (VDD) within a preset error range. The i-th test unit is composed of one or more standard units of the same specification connected in parallel; the logic signal output terminal of the i-th test unit serves as the logic function test port (OUT2) of the i-th test unit; the monitoring terminal (P6) of the voltage adjustment circuit (1) is connected to the input terminal of the current-voltage conversion circuit (3), and the output terminal of the current-voltage conversion circuit (3) serves as the leakage current test port (OUT1) shared by n test units.

2. The standard unit test circuit according to claim 1, characterized in that, The voltage adjustment circuit (1) includes an operational amplifier (OP) and a power transistor MN0; the non-inverting input terminal of the operational amplifier (OP) is connected to the power supply terminal (P7) of the voltage adjustment circuit (1); the inverting input terminal of the operational amplifier (OP) is connected to the feedback input terminal (P8) of the voltage adjustment circuit (1); the output terminal of the operational amplifier (OP) is connected to the control terminal of the power transistor MN0, the current input terminal of the power transistor MN0 is connected to the monitoring terminal (P6) of the voltage adjustment circuit (1), and the current output terminal of the power transistor MN0 is connected to the output terminal (P9) of the voltage adjustment circuit (1).

3. The standard unit test circuit according to claim 1, characterized in that, Each switching network (4) includes a switch MN1 and a switch MN2; the current input terminal of the i-th switch MN1 is connected to the first terminal (P1) of the i-th switching network (4), and the current input terminal of the i-th switch MN2 is connected to the second terminal (P2) of the i-th switching network (4); the current output terminals of the i-th switch MN1 and the i-th switch MN2 are both connected to the third terminal (P3) of the i-th switching network (4).

4. The standard unit test circuit according to claim 1, characterized in that, Each auxiliary unit (5) includes a transistor MN3; The current input terminal of the i-th transistor MN3 is connected to the power supply terminal of the i-th auxiliary unit (5); the current output terminal of the i-th transistor MN3 is connected to the ground terminal of the i-th auxiliary unit (5).

5. The standard unit test circuit according to claim 4, characterized in that, Each auxiliary unit (5) further comprises a current source (I a ) and a transistor MN6; the output of the i-th current source (I a ), the current input of the i-th transistor MN6, the control terminal of the i-th transistor MN6 and the control terminal of the i-th transistor MN3 are connected to a common point; the current output of the i-th transistor MN6 is connected to ground.

6. The standard unit test circuit according to claim 5, characterized in that, The n second controllable switches (6) are omitted, and the third terminal (P3) of the i-th switch network (4) is directly connected to the power supply terminal (P5) of the i-th test unit.

7. The standard unit test circuit according to claim 1, characterized in that, The standard unit test circuit also includes: n pull-down units; The internal components of the i-th pull-down unit are responsible for pulling down the voltage of the power supply terminal (P5) of the i-th test unit to ground potential or keeping it in a non-pull-down state according to the instructions of the controller.

8. The standard unit test circuit according to claim 7, characterized in that, Each pull-down unit includes a switching transistor MN5; the power input terminal of the i-th switching transistor MN5 is connected to the power supply terminal (P5) of the i-th test unit, and the power output terminal of the i-th switching transistor MN5 is grounded.

9. The standard unit test circuit according to any one of claims 1 to 8, characterized in that, The standard unit test circuit further includes: a decoder; the output of the decoder is connected to the control terminal of n switch networks (4); the input of the decoder is connected to the controller.

10. The standard unit test circuit according to any one of claims 1 to 8, characterized in that, The standard unit test circuit also includes: a data selector; The input terminal of the data selector is connected to the logic signal output terminal of n test units, and the output terminal of the data selector serves as the logic function test port (OUT3) shared by the n test units.

Images