A fluxgate detection circuit and method based on homodyne coherent digital down conversion

Abstract

The application discloses a kind of based on homologous coherent digital down conversion fluxgate detection circuit and method, it is related to weak magnetic detection technical field, its technical solution key points include fluxgate probe, excitation drive module, program-controlled analog amplification module, analog-digital conversion module and digital logic processing unit;The digital logic processing unit is used to generate the excitation control signal of fluxgate, the excitation control signal is transmitted to the excitation drive module to drive the fluxgate probe, after being converted into discrete sampling sequence by analog-digital conversion module, input to the digital logic processing unit;Phase calibration operation based on inverse digital rotation matrix is carried out to baseband in-phase component and quadrature component, and the measured magnetic field intensity is solved using the calibration in-phase component and the calibration parameter matched with current gain level, the effect is to realize the high flexibility of hardware reconfiguration-free and adaptive measurement capability.

Description

Technical Field

[0001] This invention relates to the field of weak magnetic field detection technology, and more specifically, to a fluxgate detection circuit and method based on coherent digital downconversion. Background Technology

[0002] A fluxgate magnetometer is a sensor that utilizes the periodic saturation characteristics of soft magnetic materials to detect weak magnetic fields. In an even-harmonic fluxgate magnetometer system, the external magnetic field disrupts the symmetry of the magnetization process of the magnetic core, causing a second harmonic component related to the measured magnetic field to appear in the output signal of the induction coil. Therefore, the amplitude and phase of the second harmonic signal can be used to characterize the magnitude and direction of the external magnetic field.

[0003] Traditional fluxgate magnetometer detection circuits typically employ analog frequency-selective amplifiers and analog phase-sensitive demodulators to extract the second harmonic component. In this purely analog architecture, the center frequency of the analog frequency-selective circuit is easily affected by manufacturing variations in physical components such as resistors and capacitors, as well as temperature drift, leading to extremely complex hardware debugging. Simultaneously, the analog phase-sensitive demodulator itself suffers from unavoidable phase drift, multiplier nonlinearity errors, DC offset, and temperature drift. Furthermore, when the system's excitation frequency changes, the entire analog filtering and demodulation circuit requires hardware reconstruction or re-tuning, lacking frequency adaptive configuration capabilities. In multi-channel or multi-axis fluxgate magnetometer systems, the component dispersion between each analog demodulation channel also results in poor channel consistency. The lengthy analog hardware links increase the overall system size and power consumption, and also increase the number of accumulated error sources within the system, limiting the resolution of extremely weak magnetic field detection. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a fluxgate detection circuit and method based on coherent digital downconversion.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A fluxgate detection circuit based on coherent digital downconversion includes a fluxgate probe, an excitation drive module, a programmable analog amplifier module, an analog-to-digital converter module, and a digital logic processing unit.

[0007] The digital logic processing unit is used to generate an excitation control signal for the fluxgate and transmit the excitation control signal to the excitation drive module to drive the fluxgate probe.

[0008] The output signal of the fluxgate probe's induction coil is conditioned by the programmable analog amplification module and then input to the analog-to-digital conversion module. After being converted into a discrete sampling sequence by the analog-to-digital conversion module, it is input to the digital logic processing unit.

[0009] The digital logic processing unit generates a second harmonic digital reference signal that is from the same source as the excitation control signal based on the same internal digital time base.

[0010] The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain a digital mixing signal; the digital mixing signal is then subjected to digital low-pass filtering and decimation processing to obtain the baseband in-phase component and the orthogonal component;

[0011] A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

[0012] Preferably, the digital logic processing unit is internally configured with an N-bit wide phase accumulator, which operates according to a set excitation frequency. Internal clock frequency Generate excitation frequency control word The calculation formula is: ;

[0013] The excitation phase generated by the digital logic processing unit Reference phase with the second harmonic digital reference signal Satisfying the homology coherence relation: ;

[0014] in, This is a programmable digital phase calibration value; the digital logic processing unit automatically generates it as an excitation frequency control word. Twice the second harmonic reference control word = 2 This is to achieve synchronous following of the second harmonic reference frequency when the excitation frequency changes.

[0015] Preferably, the digital logic processing unit is based on the reference phase. Generate mutually orthogonal in-phase reference signals Orthogonal reference signal The discrete sampling sequence The in-phase and quadrature digital mixer signals are obtained by multiplying the two reference signals respectively. After digital low-pass filtering and decimation, the in-phase component of the baseband is output. Orthogonal components The mathematical models for both are as follows:

[0016] ;

[0017] ;

[0018] in, This is the current gain of the programmable analog amplifier module. The equivalent gain of the analog-to-digital conversion module. This represents the second harmonic amplitude output by the fluxgate probe. The equivalent phase offset introduced by the hardware link.

[0019] Preferably, the digital logic processing unit is equipped with a phase calibration module, which utilizes the programmable digital phase calibration value. Construct an inverse digital rotation matrix for the in-phase components. Orthogonal components The expression for performing a two-dimensional coordinate axis rotation transformation is:

[0020] .

[0021] Preferably, the digital logic processing unit integrates an absolute peak detection module and a dual-threshold hysteresis comparator, wherein the absolute peak detection module monitors the discrete sampling sequence in real time. absolute peak The dual-threshold hysteresis comparator will determine the absolute peak value. Compared with the preset high and low safety thresholds, the output gain level switching command is sent to the programmable analog amplifier module to adaptively adjust the physical gain level m.

[0022] Preferably, the digital logic processing unit has a built-in non-volatile calibration lookup table that stores the zero-point offset parameters of the corresponding physical gain level m as the index address. With proportional calibration coefficient The digital logic processing unit utilizes the calibrated in-phase components. The estimated value of the measured magnetic field is calculated using the following formula:

[0023] ;

[0024] The lookup table completes addressing updates within the same clock cycle, ensuring the continuity of magnetic field output during gain switching.

[0025] Preferably, the digital logic processing unit is a field-programmable gate array (FPGA), which internally contains a common time base module, an excitation phase generation module, a second harmonic digital reference generation module, an orthogonal digital downconversion module, a digital low-pass filter and decimation module, a phase calibration module, and a magnetic field calculation module.

[0026] Preferably, the programmable analog amplifier module adopts an integrated programmable gain amplifier chip, a voltage-controlled variable gain amplifier, or a programmable gain conditioning circuit composed of an operational amplifier and a switching resistor network controlled via digital I / O pins.

[0027] The analog-to-digital conversion module uses successive approximation, pipeline, or oversampling sigma delta type analog-to-digital conversion chips.

[0028] Preferably, it also includes a digital interface output module;

[0029] The digital logic processing unit frames the calculated digital magnetic field data according to the protocol and then transmits it to the external host computer through the digital interface output module.

[0030] The digital interface output module includes an Ethernet physical layer PHY chip, a serial peripheral interface bus driver, a universal asynchronous transceiver physical layer chip, or a universal parallel bus interface.

[0031] A fluxgate detection method based on coherent digital downconversion includes the following steps:

[0032] Generates the excitation control signal for the fluxgate;

[0033] A second harmonic digital reference signal, which is of the same origin as the excitation control signal, is generated based on the same internal digital time base.

[0034] The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain a digital mixing signal; the digital mixing signal is then subjected to digital low-pass filtering and decimation processing to obtain the baseband in-phase component and the orthogonal component;

[0035] A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention generates the excitation signal and the second harmonic reference signal from the same internal digital time base, establishing an absolute and invariant digital coherence relationship between them. This fundamentally eliminates the physical phase drift distortion problem caused by environmental temperature drift or aging of passive components in traditional analog phase-sensitive demodulation architectures. Utilizing the strict mapping relationship of digital phase, when the system dynamically changes the excitation frequency, the underlying second harmonic reference frequency and control word can automatically track and match with absolute zero delay, completely eliminating the cumbersome process of resoldering and tuning the frequency selection network required by traditional analog circuits during frequency conversion. By using an inverse digital rotation matrix to perform two-dimensional coordinate axis correction in a purely mathematical dimension, the complex hardware phase alignment operation is transformed into high-precision digital calculation, overcoming the amplitude attenuation caused by physical link delay. Combined with a multi-level seamless lookup table compensation mechanism of programmable analog amplification, the high-precision dynamic measurement range of the sensor is expanded while ensuring extremely high resolution. It can adaptively configure and lock updates with microsecond-level absolute zero delay, achieving high flexibility and adaptive measurement capabilities without hardware reconfiguration. Attached Figure Description

[0038] Figure 1 This is an overall block diagram of a fluxgate detection circuit based on coherent digital downconversion provided in an embodiment of the present invention;

[0039] Figure 2 This is a flowchart of digital downconversion processing and phase calibration provided in an embodiment of the present invention;

[0040] Figure 3 This is a block diagram of the programmable gain adaptive and seamless lookup table compensation logic provided in an embodiment of the present invention;

[0041] Figure 4 The underlying adaptive frequency conversion and dynamic full-follow logic diagram provided for embodiments of the present invention. Detailed Implementation

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0044] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0045] Reference Figures 1-4 As shown.

[0046] The embodiments further illustrate the fluxgate detection circuit and method based on coherent digital downconversion proposed in this invention.

[0047] A fluxgate detection circuit based on coherent digital downconversion includes a fluxgate probe, an excitation drive module, a programmable analog amplifier module, an analog-to-digital converter module, and a digital logic processing unit.

[0048] The digital logic processing unit is used to generate the excitation control signal for the fluxgate and transmits the excitation control signal to the excitation drive module to drive the fluxgate probe.

[0049] The output signal of the fluxgate probe's induction coil is conditioned by the programmable analog amplification module and then input to the analog-to-digital conversion module. After being converted into a discrete sampling sequence by the analog-to-digital conversion module, it is input to the digital logic processing unit.

[0050] The digital logic processing unit generates a second harmonic digital reference signal that originates from the same internal digital time base as the excitation control signal;

[0051] The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain the digital mixing signal; the digital mixing signal is then subjected to digital low-pass filtering and decimation to obtain the baseband in-phase component and the orthogonal component;

[0052] A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

[0053] The field-programmable gate array (FPGA) digital processing module uses its unique internal system clock source to simultaneously constrain and drive the excitation phase generation module and the second harmonic digital reference generation module.

[0054] The digital logic processing unit is internally equipped with an N-bit wide phase accumulator, which operates according to a set excitation frequency. Internal clock frequency Generate excitation frequency control word The calculation formula is: ;

[0055] The phase accumulator operates at an internal clock frequency. As the reference timing for operation, the frequency control word will be excited in each clock cycle. The process involves continuous accumulation, with the accumulated result corresponding to a phase value, thereby generating an excitation phase sequence. The entire phase generation chain shares the same internal clock and N-bit wide phase accumulator architecture. The generation processes of the excitation phase and the second harmonic reference phase are completely synchronized. The two phase frequencies are distinguished only by different accumulation step values, and the set excitation frequency is modified accordingly. After that, the excitation frequency control word Synchronous updates ensure that the second harmonic frequency step value changes adaptively and synchronously, without requiring any changes to the hardware circuitry. This guarantees the phase co-location stability of the excitation signal and the demodulation reference signal from the source of phase generation, eliminating frequency drift and phase shift problems caused by discrete analog oscillator circuits.

[0056] To maintain a strict coherent demodulation relationship, the operational architecture automatically adjusts the control word of the second harmonic digital reference generation module according to the mathematical relationship of second harmonics. Scaling set to 2 This synchronously generates the second harmonic digital demodulation reference phase. .

[0057] Excitation phase generated by digital logic processing unit Reference phase with the second harmonic digital reference signal Satisfying the homology coherence relation: ;

[0058] in, This is a programmable digital phase calibration value; the digital logic processing unit automatically generates it as the excitation frequency control word. Twice the second harmonic reference control word = 2 This is to achieve synchronous following of the second harmonic reference frequency when the excitation frequency changes.

[0059] Generate the excitation phase for the digital logic processing unit. The reference phase corresponding to the second harmonic digital reference signal. This is a programmable digital phase calibration value, which can be adjusted digitally to compensate for inherent phase deviations introduced by the hardware link. The digital logic processing unit is based on the excitation frequency control word. Automatically generate a second harmonic reference control word with a value twice that of the second harmonic. Second harmonic reference control word The frequency is then adjusted synchronously and adaptively to achieve double harmonic synchronization of the second harmonic reference frequency with respect to the excitation frequency. The coherence of the two phases is ensured throughout the process by relying on the same digital time base. No additional independent oscillation hardware is required to maintain the frequency matching relationship between the excitation signal and the demodulation reference signal.

[0060] The digital logic processing unit is based on the reference phase. Generate mutually orthogonal in-phase reference signals Orthogonal reference signal The input discrete modulus to sample sequence The signals are then subjected to time-domain digital multiplication and mixing with the two orthogonal reference signals mentioned above. Based on the product-to-difference principle of trigonometric identities, the resulting in-phase and quadrature digital mixed signal streams contain low-frequency baseband components and high-frequency mixing components at twice the reference frequency. This data stream enters a cascaded digital low-pass filter and decimation module. Through a multi-stage decimation structure composed of an integral comb filter and a finite-length unit impulse response filter, the discrete sampled sequence is decimated. The in-phase and quadrature digital mixer signals are obtained by multiplying the two reference signals respectively. After digital low-pass filtering and decimation, the in-phase component of the baseband is output. Orthogonal components The mathematical models for both are as follows:

[0061] ;

[0062] ;

[0063] in, This is the current gain of the programmable analog amplifier module. The equivalent gain of the analog-to-digital conversion module. This represents the second harmonic amplitude output by the fluxgate probe. The equivalent phase offset introduced by the hardware link.

[0064] The phase deviation generated by the hardware link splits the second harmonic amplitude carrying magnetic field information into two baseband components, I and Q. The I component carries the result of multiplying the amplitude by the cosine of the phase deviation, while the Q component carries the result of multiplying the amplitude by the sine of the phase deviation. Both components completely retain the second harmonic amplitude information corresponding to the measured magnetic field and the phase offset information brought by the hardware, providing raw baseband data for digital phase calibration and magnetic field numerical calculation.

[0065] The digital logic processing unit is equipped with a phase calibration module to address the equivalent phase deviation that is unavoidably introduced in the hardware link. The phase calibration module utilizes programmable digital phase calibration values. Construct an inverse digital rotation matrix for in-phase components. Orthogonal components The expression for performing a two-dimensional coordinate axis rotation transformation is:

[0066] .

[0067] Configuration via computation during the calibration phase = After performing the above rotation transformation, the pseudo signal energy in the orthogonal traffic channel Forced to cancel out and approach zero, all effective characteristic energies reflecting the true magnetic field strength are completely transferred and concentrated into the calibrated in-phase component. middle.

[0068] According to programmable digital phase calibration Construct the corresponding inverse digital rotation matrix to convert the in-phase component obtained from the previous digital downconversion operation. Orthogonal components As the original data to be transformed, a two-dimensional coordinate axis rotation transformation operation is performed. The entire transformation operation is calculated using matrix operation expressions. The left side of the matrix expression represents the calibrated in-phase component after phase calibration. Orthogonal components of calibration The vectors formed by the matrix expression are represented by the matrix in the middle. The inverse digital rotation matrix, composed of the cosine and sine values, has a vector on the right side of its expression consisting of the original in-phase and quadrature components without phase calibration. Matrix multiplication is used to perform a two-dimensional coordinate rotation, thereby offsetting the equivalent phase deviation introduced by the hardware link and consolidating the effective magnetic field information originally dispersed in the two components into the calibrated matrix. The channel completes the phase deviation compensation process in the digital domain.

[0069] The digital logic processing unit integrates an absolute peak detection module and a dual-threshold hysteresis comparator. The absolute peak detection module monitors the discrete sampling sequence in real time. absolute peak The dual-threshold hysteresis comparator will determine the absolute peak value. Compared with the preset high and low safety thresholds, the output gain level switching command is sent to the programmable analog amplifier module to adaptively adjust the physical gain level m.

[0070] When absolute peak When the gain level exceeds the set high safety threshold, the gain level state machine immediately responds and sends a switching command to the next level through the external digital control bus to reduce the physical gain level m of the programmable analog amplifier module; conversely, if the signal is weak and touches the set low safety threshold, the physical gain level m is adaptively increased.

[0071] To ensure the absolute continuity and linearity of the digital magnetic field output when switching physical gain levels, the system internally constructs a non-volatile calibration lookup table. The digital logic processing unit has a built-in non-volatile calibration lookup table, which stores the zero-point offset parameters of the corresponding physical gain level m as the index address. With proportional calibration coefficient The digital logic processing unit utilizes the calibrated in-phase component. The estimated value of the measured magnetic field is calculated using the following formula:

[0072] ;

[0073] The lookup table completes the addressing update within the same clock cycle, ensuring the continuity of the magnetic field output during gain switching.

[0074] Because phase calibration and gain lookup table compensation operate independently and in parallel within the pure digital mathematical matrix dimension, the system can perfectly isolate hardware shocks and output smooth, continuous, and phase-error-free digital magnetic field data even when abrupt changes occur in the physical circuit. Finally, the calculated digital magnetic field data is framed and packaged by the protocol framing module and transmitted at high speed to an external host computer through the digital interface output module.

[0075] The digital logic processing unit is a field-programmable gate array, which internally contains a common-source time base module, an excitation phase generation module, a second harmonic digital reference generation module, an orthogonal digital downconversion module, a digital low-pass filter and decimation module, a phase calibration module, and a magnetic field calculation module.

[0076] The entire digital signal processing flow uses a common time base module to provide a unified reference timing. The common time base module outputs a unified clock signal, which is supplied to both the excitation phase generation module and the second harmonic digital reference generation module. The excitation phase generation module calculates and generates the excitation phase required to drive the fluxgate probe. The second harmonic digital reference generation module synchronously generates a demodulation reference phase that maintains a second harmonic coherence with the excitation phase based on the common time base. The probe's sensed signal is converted from analog to digital and then sent to the quadrature digital down-conversion module. The quadrature digital down-conversion module uses the quadrature reference signals output from the two phase generation modules to perform digital mixing. The mixed data is then sent to the digital low-pass filter and decimation module. The filtering and decimation module filters out high-frequency noise and reduces the sampling rate, outputting the separated in-phase and quadrature components. The two components are synchronously sent to the phase calibration module, which performs a two-dimensional coordinate rotation transformation through an inverse digital rotation matrix to compensate for the phase deviation caused by the hardware link and collect the effective magnetic field signal. The calibrated component after phase calibration is finally sent to the magnetic field calculation module, which calculates and outputs the measured magnetic field value by combining the pre-calibrated gain and zero-point parameters. All signal generation, demodulation, filtering, phase compensation, and magnetic field calculation processes are completed within the same field-programmable gate array, eliminating the phase and frequency drift problems caused by discrete analog devices.

[0077] The programmable analog amplifier module uses an integrated programmable gain amplifier chip, a voltage-controlled variable gain amplifier, or a programmable gain conditioning circuit composed of an operational amplifier and a switching resistor network controlled by digital I / O pins. Its internal amplification gain level is dynamically switched by an external digital control bus, thereby realizing voltage gain conditioning and impedance matching of weak signals in the first stage of the analog domain.

[0078] The integrated programmable gain amplifier chip enables signal amplification level switching; the voltage-controlled variable gain amplifier continuously adjusts the gain value through input control voltage; and the operational amplifier combined with a switched resistor network forms a complete programmable gain conditioning circuit. The digital logic processing unit outputs control signals through digital I / O pins to switch the resistance values ​​connected inside the switched resistor network, thereby changing the closed-loop amplification factor of the operational amplifier and achieving programmable gain level switching. All three architectures receive control commands from the digital logic processing unit and adjust the current amplification gain according to the amplitude requirements of the detected signal. This amplifies the small-amplitude second harmonic signal output by the fluxgate probe to a voltage range suitable for the input range of the analog-to-digital converter module. The amplified analog signal is directly sent to the analog-to-digital converter module for sampling, and the currently effective gain value of the module is simultaneously sent to the digital logic processing unit for gain compensation calculations in the subsequent magnetic field solution process.

[0079] The analog-to-digital conversion module uses successive approximation, pipeline, or oversampling sigma delta type analog-to-digital conversion chips.

[0080] The analog-to-digital converter (ADC) module can use any one of three types of ADC chips: successive approximation, pipelined, or oversampling sigma delta. The module receives the analog voltage signal output from the programmable analog amplifier module and, according to the chip's corresponding ADC architecture, converts the continuously changing analog second harmonic voltage signal into a discrete digital sampling sequence. During the conversion process, the chip has a fixed equivalent gain, which participates in the calculation and derivation of the digital down-conversion component. After the conversion, the digital sampling data is synchronously transmitted to the quadrature digital down-conversion module in the digital logic processing unit to provide the original digital sampling data for digital domain demodulation. Different types of ADC chips only differ in their internal signal conversion implementation architecture; their overall function is to convert analog signals into digital sampling sequences and output them.

[0081] It also includes a digital interface output module;

[0082] The digital logic processing unit frames the calculated digital magnetic field data according to the protocol and then transmits it to the external host computer through the digital interface output module.

[0083] The digital interface output module includes an Ethernet physical layer PHY chip, a serial peripheral interface bus driver, a universal asynchronous transceiver physical layer chip, or a universal parallel bus interface, which are used to realize high-speed, low-latency transmission of digital magnetic field data to an external host computer or control terminal.

[0084] After the digital logic processing unit completes the numerical calculation of the measured magnetic field, it obtains the corresponding digitized magnetic field data. The unit then performs a framing operation on this digitized magnetic field data according to a preset communication protocol, completing the data frame encapsulation process. The encapsulated data frame is sent to the digital interface output module, which transmits the magnetic field data to an external host computer for data reception and retrieval. The digital interface output module can be implemented in various hardware forms. It can use an Ethernet physical layer PHY chip to build a network port transmission link, a serial peripheral interface bus driver to build a serial communication link, a universal asynchronous transceiver physical layer chip to build a serial port transmission link, or a universal parallel bus interface to build a parallel data transmission link. Each hardware device corresponds only to a different communication transmission method and can carry the framed magnetic field data, completing the data interaction and transmission between the digital logic processing unit and the external host computer.

[0085] A fluxgate detection method based on coherent digital downconversion includes the following steps:

[0086] Generates the excitation control signal for the fluxgate;

[0087] The second harmonic digital reference signal is generated based on the same internal digital time base and the excitation control signal is of the same origin.

[0088] The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain the digital mixing signal; the digital mixing signal is then subjected to digital low-pass filtering and decimation to obtain the baseband in-phase component and the orthogonal component;

[0089] A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fluxgate detection circuit based on coherent digital down-conversion, characterized in that, It includes a fluxgate probe, an excitation drive module, a programmable analog amplifier module, an analog-to-digital converter module, and a digital logic processing unit; The digital logic processing unit is used to generate an excitation control signal for the fluxgate and transmit the excitation control signal to the excitation drive module to drive the fluxgate probe. The output signal of the fluxgate probe's induction coil is conditioned by the programmable analog amplification module and then input to the analog-to-digital conversion module. After being converted into a discrete sampling sequence by the analog-to-digital conversion module, it is input to the digital logic processing unit. The digital logic processing unit generates a second harmonic digital reference signal that is from the same source as the excitation control signal based on the same internal digital time base. The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain the digital mixing signal; Digital low-pass filtering and decimation are performed on the digital mixing signal to obtain the baseband in-phase and quadrature components; A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

2. The fluxgate detection circuit based on coherent digital down-conversion according to claim 1, characterized in that, The digital logic processing unit is internally configured with an N-bit wide phase accumulator, which operates according to a set excitation frequency. Internal clock frequency Generate excitation frequency control word The calculation formula is: ; The excitation phase generated by the digital logic processing unit Reference phase with the second harmonic digital reference signal Satisfying the homology coherence relation: ; in, This is a programmable digital phase calibration value; the digital logic processing unit automatically generates it as an excitation frequency control word. Twice the second harmonic reference control word = 2 This is to achieve synchronous following of the second harmonic reference frequency when the excitation frequency changes.

3. The fluxgate detection circuit based on coherent digital down-conversion according to claim 2, characterized in that, The digital logic processing unit is based on the reference phase. Generate mutually orthogonal in-phase reference signals Orthogonal reference signal The discrete sampling sequence The in-phase and quadrature digital mixer signals are obtained by multiplying the two reference signals respectively. After digital low-pass filtering and decimation, the in-phase component of the baseband is output. Orthogonal components The mathematical models for both are as follows: ； ； in, This is the current gain of the programmable analog amplifier module. The equivalent gain of the analog-to-digital conversion module. This represents the second harmonic amplitude output by the fluxgate probe. The equivalent phase offset introduced by the hardware link.

4. The fluxgate detection circuit based on coherent digital down-conversion according to claim 3, characterized in that, The digital logic processing unit is equipped with a phase calibration module, which utilizes the programmable digital phase calibration value. Construct an inverse digital rotation matrix for the in-phase components. Orthogonal components The expression for performing a two-dimensional coordinate axis rotation transformation is: 。 5. A fluxgate detection circuit based on coherent digital down-conversion according to claim 4, characterized in that, The digital logic processing unit integrates an absolute peak detection module and a dual-threshold hysteresis comparator. The absolute peak detection module monitors the discrete sampling sequence in real time. absolute peak The dual-threshold hysteresis comparator will determine the absolute peak value. Compared with the preset high and low safety thresholds, the output gain level switching command is sent to the programmable analog amplifier module to adaptively adjust the physical gain level m.

6. A fluxgate detection circuit based on coherent digital down-conversion according to claim 5, characterized in that, The digital logic processing unit has a built-in non-volatile calibration lookup table that stores the zero-point offset parameters of the corresponding physical gain level m as the index address. With proportional calibration coefficient ; The digital logic processing unit utilizes the calibrated in-phase component. The estimated value of the measured magnetic field is calculated using the following formula: ； The lookup table completes addressing updates within the same clock cycle, ensuring the continuity of magnetic field output during gain switching.

7. A fluxgate detection circuit based on coherent digital down-conversion according to claim 6, characterized in that, The digital logic processing unit is a field-programmable gate array, which internally contains a common-source time base module, an excitation phase generation module, a second harmonic digital reference generation module, an orthogonal digital downconversion module, a digital low-pass filter and decimation module, a phase calibration module, and a magnetic field calculation module.

8. A fluxgate detection circuit based on coherent digital down-conversion according to claim 7, characterized in that, The programmable analog amplifier module adopts an integrated programmable gain amplifier chip, a voltage-controlled variable gain amplifier, or a programmable gain conditioning circuit composed of an operational amplifier and a switched resistor network controlled by digital I / O pins. The analog-to-digital conversion module uses successive approximation, pipeline, or oversampling sigma delta type analog-to-digital conversion chips.

9. A fluxgate detection circuit based on coherent digital down-conversion according to claim 8, characterized in that, It also includes a digital interface output module; The digital logic processing unit frames the calculated digital magnetic field data according to the protocol and then transmits it to the external host computer through the digital interface output module. The digital interface output module includes an Ethernet physical layer PHY chip, a serial peripheral interface bus driver, a universal asynchronous transceiver physical layer chip, or a universal parallel bus interface.

10. A fluxgate detection method based on coherent digital downconversion, applied to a fluxgate detection circuit based on coherent digital downconversion as described in any one of claims 1-9, characterized in that, Includes the following steps: Generates the excitation control signal for the fluxgate; A second harmonic digital reference signal, which is of the same origin as the excitation control signal, is generated based on the same internal digital time base. The discrete sampling sequence is multiplied by the orthogonal reference signal generated based on the second harmonic digital reference signal to obtain the digital mixing signal; Digital low-pass filtering and decimation are performed on the digital mixing signal to obtain the baseband in-phase and quadrature components; A phase calibration operation based on an inverse digital rotation matrix is ​​performed on the baseband in-phase and quadrature components, and the measured magnetic field strength is calculated using the calibration parameters matched with the current gain level of the calibrated in-phase component.

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