A multi-channel electronics data processing method for cosmic muon imaging

Abstract

The application discloses a kind of multichannel electronics data processing methods for cosmic muon imaging, its steps include: the multichannel muon signal of front-end acquisition is converted into multichannel parallel data stream;Each data stream of parallel is divided into two branches, the first branch enters signal peak finding unit and is detected, when detecting muon pulse event, output a Trigger signal and send to delay unit;Second branch enters delay unit and delays a fixed time to input data;When delay unit receives Trigger signal, the data of delayed output is integrated in the set integration time window, and the energy of muon pulse signal is obtained;According to the pulse width of muon pulse, the fixed time and integration time window are determined.The application significantly reduces data transmission, greatly saves transmission bandwidth, and completely solves the data transmission and storage bottleneck of large-area imaging system from the source.

Description

Technical Field

[0001] This invention belongs to the field of cosmic ray muon imaging and relates to a multi-channel electronic data processing method for cosmic ray muon imaging. Background Technology

[0002] Cosmic ray muons are secondary particles produced by the interaction of high-energy primary cosmic rays with the atmosphere. With their extremely strong penetrating power and scattering characteristics that are sensitive to high atomic number (High-Z) materials, muon imaging technology has shown great application potential in fields such as large-scale industrial structure inspection, nuclear material monitoring, and geological exploration.

[0003] A typical cosmic ray muon imaging system usually consists of two (or more) layers of position-sensitive detectors (such as a combination of plastic scintillators and photomultiplier tubes). The basic physical process is as follows: when a beam of cosmic ray muons penetrates the system, it almost simultaneously excites photons in both layers of detectors, converting them into weak analog electrical pulse signals. These analog signals then enter the electronics system, are amplified by front-end circuitry, and are continuously digitized by a multi-channel high-speed analog-to-digital converter (ADC). The sampled digital signals are sent to an FPGA for high-speed logic processing. The FPGA extracts the charge information (reflecting energy) and precise timing information of the effective pulses, packages this data, and sends it to a host computer. The host computer software then uses these paired charge and timing information pairs to reconstruct the spatial trajectory of the muons using a specific coincidence algorithm, thereby achieving internal imaging of the object under test. The basic data flow of the entire system is as follows: Figure 1 As shown.

[0004] With the development of large-area muon imaging technology, the number of detector channels is constantly increasing. In practical electronic systems, multi-channel ADCs perform continuous sampling without dead time at a fixed sampling rate, generating a large amount of raw waveform data. If this large amount of raw waveform data is directly transmitted to a computer (host computer), it will not only greatly exceed the transmission bandwidth of the hardware interface, but also impose a heavy computational load on the host computer's storage and software processing.

[0005] Therefore, in modern muon imaging electronics systems, a crucial core task of the FPGA is real-time signal extraction. Since no physical events occur at the detector for most of the sampling time, the FPGA needs to accurately and in real-time identify the effective pulse signals induced by muon penetration within the continuous data stream, and extract the two core physical quantities necessary for the host computer to reconstruct the track: Time information (time stamp): used by the host computer to determine the coincidence of the upper and lower layer detectors to confirm whether these signals come from the same muon track. Charge information (energy): The energy level of the signal is obtained by integrating the pulse waveform, which is used to eliminate low-energy background noise interference and verify the validity of muon events.

[0006] However, processing hundreds of channels of continuous waveforms simultaneously in real time within a single FPGA is no easy task. Existing data processing solutions often face problems such as insufficiently compact pipeline design, large logic resource consumption, or data buffer overflow and packet loss at high-speed sampling when dealing with multi-channel concurrent signals. Summary of the Invention

[0007] To address the problems existing in the prior art, the present invention aims to provide a multi-channel electronic data processing method for cosmic ray muon imaging. This method can automatically complete the threshold triggering of effective signals, the integral accumulation of charge, and the marking of global timestamps in a continuous digital waveform stream with extremely simple logic and extremely high resource utilization. It also efficiently packages and outputs this key information to the host computer in a specific format, thereby completely solving the problems of massive data transmission bottlenecks and multi-channel parallel processing.

[0008] The technical solution of this invention is as follows: A multi-channel electronics data processing method for cosmic ray muon imaging, comprising the following steps: Convert the multi-channel muon signals acquired at the front end into multi-channel parallel data streams; Each parallel data stream is divided into two branches. The first branch enters the signal peak finding unit for detection. When a muon pulse event is detected, a trigger signal is output and sent to the delay unit. The second branch enters the delay unit to delay the input data by a fixed time. When the delay unit receives the trigger signal, it integrates the delayed output data within the set integration time window to obtain the energy of the muon pulse signal; the fixed time and integration time window are determined according to the pulse width of the muon pulse.

[0009] Preferably, the fixed time is the time elapsed from the start of the muon pulse to the determination that a muon pulse event has occurred and the generation of a trigger signal.

[0010] Preferably, the parallel multi-channel data stream is divided into several groups of parallel data streams; when any one of the data streams in a group of parallel data streams generates a trigger signal, it is synchronously sent to each parallel delay unit in that group of parallel data streams for integration, and the signal values ​​higher than the set integration threshold are summed as the energy of the corresponding muon pulse signal.

[0011] Preferably, multiple parallel data streams corresponding to the same detector array are treated as a group of parallel data streams.

[0012] Preferably, when reading the integral of each parallel delay unit in the parallel data stream, the corresponding global timestamp and channel number are concatenated to it.

[0013] Preferably, the signal peak finding unit sets a threshold higher than the baseline noise level; when the waveform amplitude of the input signal is detected to rise above the threshold, and the waveform is subsequently detected to be at a falling edge, a muon pulse event is determined to have occurred and a trigger signal is output.

[0014] Preferably, the delay unit utilizes the internal storage resources of the FPGA to delay the input data by a fixed time.

[0015] Preferably, the analog signal output after amplifying and filtering the multi-channel muon signals acquired at the front end is converted into a high-speed serial data stream. Then, the serial data stream is converted into multiple low-speed parallel data streams after serial-to-parallel conversion and data bit alignment.

[0016] The advantages of this invention are as follows: 1. Significantly reduces data transmission volume and greatly saves transmission bandwidth: "Energy + timestamp" information is directly extracted and packaged at the FPGA bottom layer, replacing the traditional massive ADC full waveform transmission, and completely solving the data transmission and storage bottleneck of large-area imaging systems from the source.

[0017] 2. Achieve lossless and high-precision physical feature extraction: The "peak finding + delay" dual-path architecture accurately aligns the trigger point with the waveform start point, completely eliminating energy loss caused by waveform front truncation; the "32-channel group synchronous integration" mechanism accurately preserves the induced charge of adjacent channels. Attached Figure Description

[0018] Figure 1 This is a basic data flow diagram of the system.

[0019] Figure 2 This is a flowchart of the method of the present invention.

[0020] Figure 3 This is a block diagram of the internal logic processing of 128-channel electronics based on FPGA.

[0021] Figure 4 This is a schematic diagram of the peak finding and delay unit logic. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] like Figure 1 As shown, an optional embodiment of the present invention provides a multi-channel electronics data processing method for cosmic ray muon imaging, the steps of which include: Convert the multi-channel muon signals acquired at the front end into multi-channel parallel data streams; Each parallel data stream is divided into two branches. The first branch enters the signal peak finding unit for detection. When a muon pulse event is detected, a trigger signal is output and sent to the signal delay unit. The second branch enters the delay unit to delay the input data by a fixed time. When the delay unit receives the trigger signal, it integrates the delayed output data within the set integration time window to obtain the energy of the muon pulse signal; the fixed time and integration time window are determined according to the pulse width of the muon pulse.

[0024] One embodiment of this invention uses an FPGA as its core. The FPGA receives a single system clock from an external programmable clock chip and internally generates four highly synchronized sampling clocks to drive four highly integrated ADCs. Simultaneously, the FPGA receives high-speed serial data output from the ADCs, decodes it using alignment logic, and restores it to 128 channels of time-aligned parallel data. Based on this, the invention designs a baseline subtraction and multi-channel coincidence triggering algorithm within the FPGA to filter and extract the true muon penetration event waveform from massive amounts of continuous sampling data in real time. This accurately obtains the charge and time information of the detector output signal and directly discards invalid background noise, effectively solving the network bandwidth congestion problem during massive data transmission in large-scale arrays.

[0025] In this embodiment, the 128 signals are divided into 4 groups (32 channels per group) according to the physical array. Each group independently performs peak finding and delay processing to generate a trigger flag signal, thereby obtaining a unified integration start flag signal for the 32 channels and achieving synchronous integration of the entire array. By monitoring the status flags of the energy FIFOs of the 4 groups (32 channels each), once an event is detected in a certain group, the read / write control logic sequentially reads the data (including energy and timestamp) of the 32 channels in that group over 32 consecutive clock cycles to obtain a complete muon ray incident event.

[0026] In this embodiment, the FPGA, as the core device, achieves the following by developing underlying high-concurrency logic algorithm functions: 1) Serial-to-parallel conversion and data bit alignment of 128-channel front-end high-speed serial ADC signals; 2) Accurate detection of 128 pulse signals based on peak finding and waveform delay dual-path coordination; 3) Unified determination of the integration starting point marker for 32-channel (single detector array) units; 4) Merging and transmitting 128:1 energy data and global timestamps.

[0027] like Figure 3 The diagram shows the internal logic processing block diagram of a 128-channel FPGA-based electronics system. This FPGA internal logic processing architecture achieves efficient extraction and transmission from high-speed raw waveforms to muon signals, specifically including the following collaborative processing modules: 1. Serial-to-Parallel Conversion Module (Channel 1-Channel 128): After amplification and filtering, the 128 muon signals from the front end are output as analog signals. These signals are then converted into high-speed serial data streams by four 32-channel ADCs on the 128-channel electronics board. The serial-to-parallel conversion is then performed internally within the FPGA, aligning the data bits and converting them into stable 128-channel low-speed parallel data streams. The four 32-channel ADCs constitute the 128-channel electronics board, performing serial-to-parallel conversions from Channel 1 to Channel 128. Each ADC performs serial-to-parallel conversion for 32 channels.

[0028] 2. Signal Peak Finding and Signal Delay: After serial-to-parallel conversion, each waveform data stream is divided into two independent branches. The first data stream enters the signal peak finding unit, and the second data stream enters the signal delay unit.

[0029] The logic for signal peak finding is as follows: like Figure 4 As shown in the waveform diagram above, the peak finding unit performs real-time amplitude monitoring of the input digital waveform. First, an internal threshold higher than the baseline noise level is set. When the waveform amplitude is detected to rise above this threshold, and subsequently a falling edge is detected, the system recognizes this as a genuine muon pulse event and immediately outputs a "Trigger signal" to the delay unit to begin integration. Since this process, from the pulse's actual physical starting point to crossing the threshold and finally completing the peak finding, inevitably consumes a certain number of clock cycles in the digital circuit.

[0030] The logic of the delay unit is as follows: To compensate for the time consumed in peak finding and judgment, the original data waveform is buffered in a signal delay unit for equal length. For example... Figure 4As shown in the waveform diagram below, the delay unit utilizes the FPGA's internal storage resources (such as a shift register chain) to delay the input raw digital waveform by a fixed time (i.e., the time elapsed from the start of the muon pulse to the generation of the trigger signal when the muon pulse event is determined). After the delay, the actual start point of the waveform from the delay unit below is precisely aligned with the "Trigger signal" generated by the peak-finding unit above on the time axis. At this point, the "Trigger signal" also serves as the "integration start flag," allowing subsequent integration of the signal waveform within a set "integration time" window, thereby achieving energy extraction of the muon pulse signal.

[0031] 3. Signal integration: such as Figure 3 As shown in the dashed box, the 128 channels of this invention physically correspond to four muon detector arrays (i.e., one array corresponds to 32 channels). To obtain the complete space charge distribution, the system employs a "group synchronous integration" mechanism. Taking detector array 1 (channels 1-32) as an example: this group has a shared "integration control logic". As long as the peak-finding unit of any of these 32 channels detects a muon signal and generates a trigger signal, the "integration control logic" will synchronously send an "integration start flag" to all 32 "signal integration modules" in the group. Subsequently, the 32 integration modules will synchronously integrate their respective delayed signal waveforms within the set "integration time" window, thereby realizing the energy extraction of the muon pulse signal.

[0032] 4. Energy FIFO Group Synchronization Cache Module: After integration, these 32 channels will synchronously cache the extracted integrated energy into their respective 32 energy FIFOs. Although for a single muon event, only about 4 channels typically generate significant main pulse signals, the system also saves the integrated values ​​of the remaining untriggered channels. This is to fully preserve the weak induced charge and baseline reference value around the particle impact point, thus providing data support for the host computer to perform sub-millimeter-level position interpolation using the "center of gravity method." The triggering and caching logic for the remaining channel arrays (Ch33-64, Ch65-96, Ch97-128) is similar. Typically, if the first channel has a signal, the energy of the first channel and the energy of the second channel are added together (adjacent channels are related, 1 and 2, 3 and 4). (31 and 32); there should also be two other channels with signals, such as 7 and 8; thus, the integrals of channels 1, 2, 7, and 8 are added together as the energy of the muon event. A muon event typically deposits energy in four channels of a detector, so as long as the signal of any channel exceeds the threshold, it is integrated, and then the associated channels are also integrated; thus, two channels have integral values. There should also be another channel that exceeds the threshold, which is also integrated, and the associated channels are also integrated; the centroid method for calculating position actually uses these four channels and is unrelated to other channels; the energy value is also the sum of these four channels.

[0033] 5. 128:1 FIFO Read / Write Control Logic: A single muon event may hit a single detector array (generating integration within one 32-channel array) or penetrate multiple arrays (generating integration within multiple 32-channel arrays). Therefore, the logic of this module is to independently monitor the FIFO status of the four 32-channel arrays. If buffered data is detected in the FIFO of one of the 32-channel arrays, the state machine will sequentially read the energy integration values ​​of those 32 FIFOs over 32 clock cycles. Crucially, while reading and outputting each energy integration data point, the control logic precisely appends the corresponding global timestamp and channel number to the hardware data bit width. The same logic applies to the other three 32-channel arrays.

[0034] 6. Network Transmission Module: The network transmission module packages the data read from the FIFO and sends it to the computer. Therefore, the data packet received by the computer is the charge information generated by a muon event.

[0035] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-channel electronics data processing method for cosmic ray muon imaging, comprising the following steps: Convert the multi-channel muon signals acquired at the front end into multi-channel parallel data streams; Each parallel data stream is divided into two branches. The first branch enters the signal peak finding unit for detection. When a muon pulse event is detected, a trigger signal is output and sent to the delay unit. The second branch enters the delay unit to delay the input data by a fixed time. When the delay unit receives the trigger signal, it integrates the delayed output data within the set integration time window to obtain the energy of the muon pulse signal; the fixed time and integration time window are determined according to the pulse width of the muon pulse.

2. The method according to claim 1, characterized in that, The fixed time is the time elapsed from the start of the muon pulse to the determination that a muon pulse event has occurred, generating a trigger signal.

3. The method according to claim 1, characterized in that, The parallel multi-channel data stream is divided into several groups of parallel data streams. When any one of the data streams in a group of parallel data streams generates a trigger signal, it is synchronously sent to each parallel delay unit in that group of parallel data streams for integration. The signal values ​​that are higher than the set integration threshold are summed as the energy of the corresponding muon pulse signal.

4. The method according to claim 3, characterized in that, Multiple parallel data streams corresponding to the same detector array are treated as a set of parallel data streams.

5. The method according to claim 3, characterized in that, When reading the integral of each parallel delay unit in the parallel data stream, append the corresponding global timestamp and channel number to it.

6. The method according to claim 1, characterized in that, The signal peak finding unit sets a threshold higher than the baseline noise level; when the waveform amplitude of the input signal is detected to rise above the threshold, and the waveform is subsequently detected to be at a falling edge, a muon pulse event is determined to have occurred and a trigger signal is output.

7. The method according to claim 1, characterized in that, The delay unit utilizes the FPGA's internal storage resources to delay the input data by a fixed time.

8. The method according to claim 1, characterized in that, The analog signals from the multi-channel muon signals acquired at the front end are amplified and filtered, and then converted into high-speed serial data streams. The serial data streams are then converted into multiple low-speed parallel data streams after serial-to-parallel conversion and data bit alignment.

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