Display panel binding structure and display panel

Abstract

The application discloses a display panel binding structure and a display panel. The display panel binding structure comprises a substrate, an upper surface of the substrate is provided with a binding pad, a chip on film is arranged above the substrate, a solder resist layer is arranged in the chip on film, a panel binding gold finger is arranged on a lower surface of the chip on film and corresponds to a position of the binding pad, a conductive connection layer is arranged between the substrate and the chip on film and is used for electrically connecting the binding pad and the panel binding gold finger, and a buffer layer is at least partially arranged between the substrate and the chip on film, the buffer layer and the conductive connection layer are arranged in the same layer and are spaced from each other, and the hardness of the buffer layer is smaller than that of the solder resist layer. The buffer layer forms a buffer force, effectively reduces the contact stress between the solder resist layer and the chip on film in a bending working condition, avoids adverse defects such as peeling of the chip on film and fracture of a pin, and greatly improves the bending stress resistance and use reliability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel bonding structure and a display panel. Background Technology

[0002] Currently, LCD TV panel manufacturers typically use either DRD (dual-rate driving) or TRD (triple-rate driving) technology to drive display panels. DRD technology can double the driving speed, allowing one driver chip to perform the work of two. Similarly, TRD technology can triple the driving speed, allowing one driver chip to perform the work of three.

[0003] Figure 1 This is a comparative example diagram showing the implementation of panel driving using the original driver panel technology and the DRD driver panel technology; by Figure 1 It can be seen that by replacing the original driver panel technology with DRD driver panel technology, the display panel can be replaced from the original 12 driver chips to 6 driver chips. Figure 2 This is a comparison example of panel driving using the original driver panel technology and the TRD driver panel technology; by Figure 2 It is known that by replacing the original driver panel technology with DRD (Dual Rendering) driver panel technology, the display panel can be reduced from using 6 driver chips to using only 2. Therefore, using DRD and TRD driver panel technologies can reduce the number of driver chips, thereby lowering the manufacturing cost of the LCD panel. However, due to the reduced number of COF (Chip On Film) chips, the average force on each COF chip increases, making it more susceptible to COF peeling and COF lead breakage when subjected to external tension, ultimately leading to display abnormalities. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a display panel bonding structure and a display panel to solve the problem that the force on a single COF in the display panel is increased due to the current upgrade of the driving panel technology, which makes it easy for COF to peel off and COF lead wires to break when subjected to external pulling.

[0005] The first aspect of this application provides a display panel bonding structure, including: A substrate, wherein bonding pads are provided on the upper surface of the substrate; A flip-chip film is stacked on top of the substrate. A solder resist layer is disposed inside the flip-chip film, and panel bonding gold fingers are disposed on the lower surface of the flip-chip film corresponding to the bonding pads. A conductive connection layer is disposed between the substrate and the flip-chip film for electrically connecting the bonding pads to the gold fingers of the panel bonding pads; A buffer layer, at least partially located between the substrate and the flip-chip film, is disposed in the same layer as the conductive connection layer and spaced apart from each other, and the hardness of the buffer layer is less than that of the solder resist layer.

[0006] This application adds a buffer layer with a hardness lower than that of the solder resist layer between the substrate and the flip-chip film. When the display panel is bent, a buffer force can be formed between the two, which can effectively alleviate the peeling of the flip-chip film during the bending process and the cutting effect of the solder resist layer on the root of the pin, thus preventing the pin from breaking.

[0007] In some embodiments of this application, the flip-chip film further includes a substrate, a conductive circuit disposed on the lower surface of the substrate, a solder resist layer covering a portion of the conductive circuit, and a buffer layer disposed on the lower surface of the solder resist layer.

[0008] This application places a buffer layer on the lower surface of the solder resist layer. During the bending process of the display panel, it creates a buffer between the substrate and the solder resist layer, effectively reducing the mechanical stress between the solder resist layer and the substrate during bending and preventing the flip-chip film from peeling off. Furthermore, the buffer layer's support for the solder resist layer also reduces the shearing force exerted by the solder resist layer on the pin roots during panel bending, effectively preventing pin breakage and failure. Simultaneously, since this application only places the buffer layer on the lower surface of the solder resist layer, it does not obstruct the lead terminals, fundamentally avoiding the risk of short circuits.

[0009] In some embodiments of this application, the first end of the buffer layer is flush with the edge of the substrate, and the first end is the end of the buffer layer near the edge of the substrate.

[0010] This application sets the end of the buffer layer near the substrate edge to be flush with or extend beyond the substrate edge, so that the solder mask layer will not come into contact with or be squeezed against the substrate edge when the display panel is bent in any state, thereby avoiding the stress generated by the contact between the two, eliminating the shearing and cutting effect of the solder mask layer on the root of the pin, and effectively preventing the pin from breaking and failing.

[0011] In some embodiments of this application, the buffer layer has a covering structure that covers the edge of the substrate. The covering structure is formed by the buffer layer and an extension portion. The extension portion is formed by the first end of the buffer layer extending downward along the side of the substrate. The first end is the end of the buffer layer near the edge of the substrate.

[0012] This application provides full-coverage protection for the substrate edges, which are prone to contact stress with the solder resist layer, by adding a buffer layer and an extension. This ensures that the solder resist layer never contacts the substrate edges under various bending conditions, eliminating contact stress generation at the source and removing the shearing force exerted by the solder resist layer on the pin roots, effectively preventing pin breakage and failure. Simultaneously, the extension's structural design improves the synchronization of mechanical deformation between the flip-chip film and the substrate during display panel bending, further optimizing the overall bending adaptability, significantly enhancing structural bending reliability, and extending the product's actual service life.

[0013] In some embodiments of this application, the spacing between the conductive connection layer and the buffer layer is greater than 1 mm.

[0014] In this embodiment, the spacing between the conductive connection layer and the buffer layer is set to be greater than 1 mm, which can effectively avoid the buffer layer from having an adverse effect on the conductivity of the conductive connection layer.

[0015] In some embodiments of this application, the material of the buffer layer is insulating resin.

[0016] This application uses insulating resin as the material for the buffer layer, which can effectively alleviate the force between the substrate and the solder mask layer.

[0017] In some embodiments of this application, the flip-chip film adopts a double-layer wiring structure.

[0018] This application adopts a double-layer wiring structure design for flip-chip films, which can reduce the torsional force generated when subjected to external forces and the tensile force caused by the difference in stacking height, effectively reducing the risk of peeling and breakage.

[0019] In some embodiments of this application, the flip-chip film is further provided with flip-chip film bonding gold fingers, and either the panel bonding gold fingers and / or the flip-chip film bonding gold fingers satisfy any of the following parameters: the surface roughness is 0.1μm~1.8μm, the maximum corrugation height of the surface is 0.05μm~0.7μm, or the peak-valley height of the surface is 0.05μm~1.5μm.

[0020] This application optimizes the parameters of the panel bonding gold fingers and the flip-chip bonding gold fingers as described above, effectively increasing the physical contact area between the panel bonding gold fingers and the conductive connection layer, and between the flip-chip bonding gold fingers and the insulating layer, further preventing the flip-chip film from peeling off, and avoiding defects such as flip-chip film pin breakage.

[0021] In some embodiments of this application, the flip-chip film includes a substrate with a thickness of 15 μm to 50 μm.

[0022] By setting the substrate thickness as described above, this application can significantly improve the substrate stiffness, effectively reduce the peeling stress caused by deformation, and thus reduce the risk of peeling between the flip-chip film and related structures.

[0023] A second aspect of this application provides a display panel including the aforementioned display panel bonding structure.

[0024] This application adopts the above-mentioned display panel bonding structure, which can effectively avoid the peeling of the flip-chip film during bending, and at the same time alleviate the cutting effect of the solder mask layer on the root of the pin during bending, thus preventing the pin from breaking.

[0025] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects: The display panel bonding structure of this embodiment adds a buffer layer with a hardness lower than that of the solder resist layer between the substrate and the flip-chip film. When the display panel is bent, the buffer layer can form a buffering force between the two, effectively reducing the contact stress between the solder resist layer and the flip-chip film under bending conditions, avoiding defects such as flip-chip film peeling and pin breakage, and significantly improving the bending resistance and reliability of the display panel.

[0026] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a comparison diagram showing the implementation of panel driving using the original driver panel technology and the DRD driver panel technology.

[0029] Figure 2 This is a comparison diagram of panel driving technology using the original driver panel technology and the TRD driver panel technology.

[0030] Figure 3 The diagram shows a flip-chip thin film structure with a single-layer wiring structure.

[0031] Figure 4 The diagram shown is a structural schematic of the display panel binding structure described in an embodiment of this application.

[0032] Figure 5 This is a schematic diagram of another structure of the display panel binding structure described in the embodiments of this application.

[0033] Figure 6 The diagram shown is another structural schematic of the display panel binding structure described in the embodiments of this application.

[0034] Figure 7 This is a schematic diagram of another structure of the display panel binding structure described in the embodiments of this application.

[0035] Figure 8 The diagram shows a flip-chip thin film structure with a double-layer wiring structure.

[0036] Figure 9 The diagram shows the output circuit connection of a flip-chip thin film with a double-layer wiring structure.

[0037] Figure 10 The diagram shows the output circuit connection of a flip-chip thin film using a single-layer wiring structure.

[0038] Figure 11 The diagram shown is a structural schematic of the display panel described in an embodiment of this application.

[0039] Figure 12 The diagram shown is a structural schematic of the display device described in an embodiment of this application.

[0040] Specific element symbols: 1-substrate, 11-bonding pad, 2-chip flip film, 21-substrate, 22-wire circuit, 221-top wire circuit, 222-bottom wire circuit, 23-solder mask, 231-top solder mask, 232-bottom solder mask, 24-panel bonding gold finger, 25-chip flip film bonding gold finger, 26-gold bump, 27-epoxy resin adhesive, 28-driver chip, 29-spacer, 3-conductive connection layer, 4-buffer layer, 5-chip flip film output circuit, 6-extension, 7-display panel bonding structure, 8-display panel. Detailed Implementation

[0041] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0042] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0044] Both DRD and TRD panel driving technologies can be optimized to drive more pixels with fewer driver chips, effectively simplifying the driver architecture and reducing hardware costs. Taking a 1024×600 resolution display panel as an example, it needs to drive 1024 groups of RGB (Red, Green, Blue) pixels along the X-axis, totaling 3072 sub-pixels. Using traditional driving schemes, following the logic of one channel corresponding to one sub-pixel, a driver chip with 3072 channels is required, with each sub-pixel driven by an independent channel. If DRD panel driving technology is introduced, time-division multiplexing is achieved through upgraded driving speeds, allowing a single channel to drive two sub-pixels simultaneously. Therefore, only a 1536-channel driver chip is needed to meet the overall system driving requirements. Furthermore, with TRD panel driving technology, the drive multiplexing capability is further enhanced, requiring only a 1024-channel driver chip to drive all sub-pixels.

[0045] Therefore, most LCD TV panel manufacturers currently use DRD (dual-rated riving) or TRD (triple-rated riving) technology to drive display panels. When the number of channels in the chip is fixed, using DRD and TRD panel driving technologies can reduce the number of COFs compared to the original panel driving technology. However, this also increases the stress on each COF when the display panel is subjected to external forces, making it more prone to COF peeling and COF lead breakage, ultimately affecting the display effect.

[0046] Based on this, this application improves the display panel bonding structure and display panel in the related technology.

[0047] Figure 4 As shown, the display panel bonding structure 7 of this embodiment includes a substrate 1 and a flip-chip film 2. Specifically, the substrate 1 can be a glass substrate, a polyimide flexible substrate, or other types of substrates. Bonding pads 11 are provided on the upper surface of the substrate 1. The bonding pads 11 provided on the substrate 1 are mainly used to provide precise docking points when the components achieve electrical conduction, so as to ensure stable signal transmission.

[0048] Typically, the flip-chip film 2 in a display panel adopts a single-layer wiring structure. Unless otherwise specified in the following embodiments, the flip-chip film 2 refers to a flip-chip film with a single-layer wiring structure. (Reference) Figure 3 As shown, the single-layer flip-chip film 2 typically includes a substrate 21, a conductive circuit 22 disposed on the lower surface of the substrate 21, and a solder mask layer 23 covering part of the conductive circuit 22. A driver chip 28 is attached to the underside of the flip-chip film 2 and is bonded to the conductive circuit 22 via gold bumps 26 on its surface. The driver chip 28 is encapsulated and protected by epoxy resin adhesive 27. The two ends of the conductive circuit 22 are exposed to form panel bonding gold fingers 24 and flip-chip film bonding gold fingers 25, respectively. The panel bonding gold fingers 24 are used to achieve bonding with the display panel, and the flip-chip film bonding gold fingers 25 are used to achieve bonding with the motherboard.

[0049] A flip-chip film 2 is disposed on top of a substrate 1, and panel bonding fingers 24 are disposed on the lower surface of the flip-chip film 2, corresponding to the positions of bonding pads 11 on the substrate 1. A conductive connection layer 3 is disposed between the substrate 1 and the flip-chip film 2, which is used to achieve electrical connection between the bonding pads 11 and the panel bonding fingers 24. Specifically, the conductive connection layer 3 can be anisotropic conductive film (ACF), or other types of conductive connection layers.

[0050] Simultaneously, a buffer layer 4 is also provided on the same layer as the conductive connection layer 3. The buffer layer 4 is spaced apart from the conductive connection layer 3, effectively ensuring that the contact area between the conductive connection layer 3 and the gold fingers 24 bonded to the panel is not affected, while maintaining the conductivity stability of the conductive connection layer 3 and preventing short circuits. Furthermore, the hardness of the buffer layer 4 should be lower than that of the solder resist layer 23 inside the flip-chip film 2. This design can effectively improve the mechanical compatibility between the substrate 1 and the flip-chip film 2 during the bending process of the display panel, and alleviate the mechanical stress between them. Moreover, when placing the buffer layer 4, it should be placed near the edge of the substrate. This structure can optimize the deformation state of both from the edge, thereby effectively alleviating the mechanical stress between the substrate 1 and the flip-chip film 2.

[0051] In the process of setting the buffer layer 4, although the buffer layer 4 is set in the same layer as the conductive connection layer 3, the buffer layer 4 does not necessarily have to be completely set between the substrate 1 and the flip-chip film 2. The buffer layer 4 can be set at least partially between the substrate 1 and the flip-chip film 2. This setting can ensure that there is at least a partial buffer layer 4 between the substrate 1 and the flip-chip film 2, so as to effectively improve the mechanical stress between the substrate 1 and the flip-chip film 2 during the bending process of the display panel.

[0052] Since the flip-chip film 2 includes a substrate 21, a conductive circuit 22 disposed on the lower surface of the substrate 21, and a solder mask layer 23 covering part of the conductive circuit 22, the two ends of the conductive circuit 22 are exposed from the solder mask layer 23 to form panel bonding gold fingers 24 and flip-chip film bonding gold fingers 25, respectively. The panel bonding gold fingers 24 are electrically connected to the bonding pads 11 of the substrate 1 through the conductive connection layer 3. Therefore, the buffer layer 4 can be disposed on the lower surface of the solder mask layer 23 and the lower surface of the flip-chip film bonding gold fingers 25, or it can be disposed simultaneously in both locations. However, if the buffer layer 4 is disposed on the lower surface of the flip-chip film bonding gold fingers 25, it is easy to cause a short circuit in the bonding area. Therefore, to avoid this problem, refer to... Figure 4 As shown, in one embodiment of this application, the buffer layer 4 is completely disposed on the lower surface of the solder resist layer 23.

[0053] Specifically, the buffer layer 4 is completely disposed on the lower surface of the solder resist layer 23. During the bending process of the display panel, a buffering force is formed between the substrate 1 and the solder resist layer 23, effectively alleviating the mechanical stress generated between the solder resist layer 23 and the substrate 1 due to bending, and preventing the peeling of the flip-chip film 2. At the same time, under the support of the buffer layer 4, the shearing and cutting effect of the solder resist layer 23 on the root of the pins is weakened during the bending state of the panel, avoiding the problem of pin breakage and failure. Furthermore, since this application only places the buffer layer 4 on the lower surface of the solder resist layer 23, it can also effectively avoid short circuit problems caused by the buffer layer 4 covering the lead end.

[0054] Normally, the bonding pads 11 and the flip-chip film 2 are electrically connected and fixed to the panel gold fingers only by the conductive connection layer 3. No filling or isolation structures are provided in the remaining areas. Therefore, the area near the edge of the substrate within the bonding area is mostly suspended and unused. Furthermore, the edge of the substrate usually corresponds to the position of the solder resist layer 23 in the flip-chip film 2. When the display panel is bent, the edge of the substrate easily comes into direct contact and is squeezed against the solder resist layer 23. During bending, the edge of the substrate will create significant concentrated stress on the solder resist layer 23, which can easily cause the flip-chip film 2 to peel off or even lead to pin breakage and failure. To solve the above problems, in one embodiment of this application, the first end of the buffer layer 4 is at least flush with the edge of the substrate. The first end is the end of the buffer layer closest to the edge of the substrate.

[0055] Furthermore, the first end of the buffer layer 4 can be flush with the edge of the substrate, or the first end of the buffer layer 4 can extend beyond the edge of the substrate. Figure 5 This diagram illustrates a structure in which the first end of the buffer layer is flush with the edge of the substrate in the display panel bonding structure of an embodiment of this application. Figure 6This diagram illustrates a structural embodiment of the display panel bonding structure in which the first end of the buffer layer extends beyond the edge of the substrate. When the first end of the buffer layer 4 is flush with or extends beyond the edge of the substrate, the solder mask 23 will not come into contact with or be pressed against the edge of the substrate in any bending state of the display panel. This avoids the compressive stress generated by the contact between the two, eliminates the shearing and cutting effect of the solder mask 23 on the root of the pin, and effectively prevents the pin from breaking and failing.

[0056] refer to Figure 7 As shown, to more effectively solve the problem of large concentrated stress on the solder resist layer 23 due to direct contact and compression between the substrate edge and the solder resist layer 23 during bending, in one embodiment of this application, in addition to the first end of the buffer layer 4 being flush with the substrate edge, or the first end of the buffer layer 4 extending beyond the substrate edge, an extension portion 6 can also be provided on the outer side of the substrate edge corresponding to the solder resist layer 23. Furthermore, this extension portion 6 is formed by the first end of the buffer layer 4 extending downward along the side of the substrate 1, and the formed extension portion 6 cooperates with the buffer layer 4 to form a covering structure covering the corresponding substrate edge.

[0057] This encapsulation structure completely isolates the solder resist layer 23 from the substrate edge, ensuring that the solder resist layer 23 will never come into contact with or be pressed against the substrate edge under any bending state of the display panel. This eliminates the problem of peeling off the flip-chip film 2 caused by contact and pressing between the solder resist layer 23 and the substrate edge. At the same time, it eliminates the shear stress of the solder resist layer 23 on the root of the pins, greatly avoiding the risk of pin breakage and failure. In addition, the extension 6 can also improve the mechanical linkage synchronization between the flip-chip film 2 and the substrate 1 during the bending process of the display panel, further optimizing the overall bending adaptability and significantly improving the structural bending stability and service life.

[0058] In this application embodiment, the first end of the buffer layer 4 is flush with the edge of the substrate, or the first end of the buffer layer 4 is extended beyond the edge of the substrate. The buffer layer 4 may also include other reasonable structures, and this application does not impose any fixed limitations on them.

[0059] In one embodiment of this application, the spacing 29 between the conductive connection layer 3 and the buffer layer 4 can be set to be greater than 1 mm.

[0060] This spacing 29 effectively isolates the material, filling components, and deformation stress of the buffer layer 4 from interfering with the conductive pathways inside the conductive connection layer 3. It prevents the buffer layer 4 from being damaged by compression, material penetration, or thermal fusion, thus avoiding problems such as interruption of conductive pathways, increased contact resistance, and decreased conductivity uniformity. From a spatial layout perspective, it avoids various adverse effects of the buffer layer 4 on the conductivity of the conductive connection layer 3, ensuring that the conductive connection layer 3 has stable, excellent, and continuously reliable conductive transmission performance. At the same time, it can also reduce the mechanical stress generated by the mutual compression between the two layers, further improving the overall structural assembly stability and long-term reliability.

[0061] In one embodiment of this application, the buffer layer 4 can be made of an insulating resin material. To ensure that the hardness of the buffer layer 4 is lower than that of the solder resist layer 23 inside the flip-chip film 2, a liquid curing molding process can be used to mold the buffer layer 4 onto the lower surface of the solder resist layer 23 of the flip-chip film 2 or the upper surface of the substrate 1. This molding method can precisely control the mechanical hardness of the buffer layer 4 after curing, so that it meets the hardness matching requirements. It can achieve electrical isolation protection by relying on the insulating resin, and can also play a role in stress buffering and shock absorption by virtue of its lower hardness. This effectively alleviates mechanical extrusion and deformation impact during assembly and use, and reduces the risk of pin bending and breakage and film peeling of the flip-chip film 2.

[0062] In any of the above embodiments, the buffer layer 4 coating process is completed after the liquid crystal cell assembly process and before the flip-chip film bonding process. This allows for the early formation of the buffer insulation structure, which avoids the impact of the front-end cell assembly process on the material properties of the buffer layer 4 and ensures the smooth progress of the subsequent flip-chip film 2 bonding operation, guaranteeing that the mechanical and insulation performance of the bonding structure meets the standards.

[0063] In one embodiment of this application, the flip-chip film 2 in the display panel bonding structure 7 adopts a double-layer wiring structure, and the double-layer flip-chip film 2 has two layers of conductive circuits. (See reference...) Figure 8As shown, the flip-chip film 2 with a double-layer wiring structure typically includes a substrate 21, a top-layer conductive circuit 221 disposed on the upper surface of the substrate 21, and a bottom-layer conductive circuit 222 disposed on the lower surface of the substrate 21. The top-layer conductive circuit 221 and the bottom-layer conductive circuit 222 are electrically connected through holes in the substrate 21. A top-layer solder mask 231 covering a portion of the top-layer conductive circuit 221 is deposited on the upper surface, and a bottom-layer solder mask 232 covering a portion of the bottom-layer conductive circuit 222 is deposited on the lower surface. One end of the top-layer conductive circuit 221 is exposed to form a flip-chip bonding gold finger 25, and one end of the bottom-layer conductive circuit 222 is exposed to form a panel bonding gold finger 24. The flip-chip bonding gold finger 25 and the panel bonding gold finger 24 are located on opposite sides of the flip-chip film 2. The panel bonding gold finger 24 is used to achieve a bonding connection with the display panel, and the flip-chip bonding gold finger 25 is used to achieve a bonding connection with the motherboard. The double-layer flip-chip film 2 also includes a driver chip 28, which is upside down disposed on the upper side of the flip-chip film 2. It is connected to the top layer wire circuit 221 by gold bumps 26 on its surface, and the driver chip 28 is encapsulated and protected by epoxy resin 27.

[0064] In this embodiment, the buffer layer 4 in the display panel bonding structure 7 can be disposed between the bottom solder mask layer 232 and the substrate 1. The other structural limitations and functions of the buffer layer 4 are the same as those in the above-described embodiment of the display panel bonding structure 7, and no further restrictions will be imposed on it here.

[0065] Combination Figure 9 and Figure 10 As shown (bonding pads not shown), this embodiment significantly improves the mechanical reliability of the flip-chip output circuit 5 by employing a double-layer trace structure for the flip-chip film 2. This reduces torsional stress under external forces and alleviates tensile stress caused by differences in the stacking height of different components, effectively preventing problems such as flip-chip film 2 peeling and pin breakage. Furthermore, this structure allows the driver chip 28 to be placed outside the display module without additional protection, achieving a smaller bending radius and thinner overall thickness, providing greater freedom in the structural design of the terminal product.

[0066] By improving the surface condition of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25 of the flip-chip film 2, and appropriately increasing the surface roughness of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25, the physical contact area between the panel bonding gold fingers 24 and the conductive connection layer 3, and between the flip-chip bonding gold fingers 25 and the insulating layer, can be enhanced. Surface roughness can be adjusted through professional roughness control technology, with the increase in roughness mainly achieved through surface treatment processes.

[0067] In one embodiment of this application, the surface roughness of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25 can be increased by forming an alloy roughening particle layer. Specifically, since copper foil is the most basic core substrate of the gold fingers, a copper-cobalt-nickel alloy roughening particle layer can be deposited on the surface of the copper foil to achieve the purpose of increasing the surface roughness of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25.

[0068] The specific quantification parameters for the coarsening particle layer of the copper-cobalt-nickel alloy can be set as follows: Deposition amount control: 5~12mg of copper, 6~13mg of cobalt, and 5~12mg of nickel are deposited per square decimeter of copper foil.

[0069] Alloy ratio optimization: When the cobalt content is 1.2~2.2 mg / dm² / mg of copper and the nickel content is 1.0~2.0 mg / dm² / mg of copper, the "undercut" phenomenon can be suppressed, preventing the decrease in adhesion in the subsequent tin plating process.

[0070] The micro-uneven structure formed by this alloy roughening layer can significantly increase the physical contact area and mechanical locking force between the panel bonding gold fingers 24 and the conductive connection layer 3, as well as between the flip-chip bonding gold fingers 25 and the insulating layer.

[0071] In one embodiment of this application, the surface roughness of the panel bonding gold fingers 24 and the flip-chip film bonding gold fingers 25 can also be improved by adjusting the surface roughness parameters of the control panel bonding gold fingers 24 and the flip-chip film bonding gold fingers 25. When the flip-chip film 2 is made of copper foil, it is necessary to consider the surface roughness, light transmittance, and fine circuit processing performance. Therefore, the parameters of the panel bonding gold fingers 24 and / or the flip-chip film bonding gold fingers 25 on the flip-chip film 2 can be limited to meet at least one of the following parameter conditions: bonding surface roughness 0.1μm~1.8μm, maximum corrugation height of bonding surface 0.05μm~0.7μm, peak-valley height of bonding surface 0.05μm~1.5μm, and copper foil surface 85° gloss Gs not less than 100.

[0072] Among them, the surface roughness parameter setting is used to control the ten-point average roughness of the bonding interface between the panel bonding gold finger 24 and the conductive connection layer 3, and between the flip-chip bonding gold finger 25 and the insulating layer. The reasonable control range is 0.1μm~1.8μm.

[0073] The gloss index setting is used to control the 85° gloss Gs of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25 to 100 or above; this parameter can ensure that the substrate 21 has excellent light transmittance after etching, which meets the optical positioning requirements in the assembly of the driver chip 28.

[0074] The waviness parameter setting is used to control the bonding surfaces of the panel bonding gold fingers 24 and the conductive connection layer 3, and the flip-chip bonding gold fingers 25 and the insulating layer, so that the maximum waviness height is controlled within the range of 0.05μm~0.7μm and the peak-valley height is controlled within the range of 0.05μm~1.5μm.

[0075] This embodiment optimizes the parameters of the panel bonding gold fingers 24 and the flip-chip bonding gold fingers 25 as described above, which can effectively increase the physical contact area between the panel bonding gold fingers 24 and the conductive connection layer 3, and between the flip-chip bonding gold fingers 25 and the insulating layer. This can effectively prevent the flip-chip film 2 from peeling off and avoid various process defects such as the breakage of the flip-chip film 2 pins.

[0076] This embodiment can also improve the overall stiffness of the flip-chip film 2 by increasing its substrate thickness, thereby reducing the peel stress caused by display panel deformation. In one embodiment of this application, the substrate thickness is conventionally set to 15μm~40μm; however, to enhance stiffness, adapt to high curvature conditions, or meet high mechanical reliability requirements, the substrate thickness can be increased to 15μm~50μm to improve the product's peel and breakage resistance.

[0077] The display panel bonding structure 7 of this application constructs a key protection mechanism by adding a buffer layer 4 with a hardness lower than that of the solder resist layer between the substrate 1 and the flip-chip film 2. When the display panel is bent, the buffer layer 4 can form an effective buffer between the substrate 1 and the flip-chip film 2, precisely reducing the contact stress between the solder resist layer and the flip-chip film 2 under bending conditions, fundamentally avoiding core defects such as peeling of the flip-chip film 2 and lead breakage, and significantly improving the bending resistance and reliability of the display panel. Furthermore, by completely placing the buffer layer 4 on the lower surface of the solder resist layer, a targeted buffer is formed between the substrate 1 and the solder resist layer, effectively alleviating the mechanical stress generated when they are bent, further consolidating the anti-peeling effect of the flip-chip film 2; at the same time, the buffer layer 4 supports the solder resist layer 23, preventing the leads from breaking due to bending stress. Since the buffer layer 4 does not cover the lead ends, the risk of short circuit can be completely eliminated, achieving dual protection and safety.

[0078] Based on this, the first end of the buffer layer 4 is set to be at least flush with the edge of the substrate, forming a substrate edge covering structure with the extension 6, so that the solder mask layer and the substrate edge are completely isolated. This design ensures that the two will not come into contact or be squeezed when the display panel is bent arbitrarily, fundamentally eliminating the problem of peeling off the flip-chip film 2 caused by this, while eliminating the shear stress of the solder mask layer on the root of the pin, further reducing the risk of pin breakage. In addition, the extension 6 can also improve the mechanical linkage synchronization between the flip-chip film 2 and the substrate 1, optimize the overall bending adaptability, and significantly extend the service life of the structure.

[0079] Further, refer to Figure 11As shown, in order to better implement the display panel binding structure 7 in any of the above embodiments, based on the above display panel binding structure 7, this application embodiment also provides a display panel 8, which includes the display panel binding structure 7 as described above.

[0080] Further, refer to Figure 12 As shown, in order to better implement the display panel 8 in any of the above embodiments, based on the display panel 8 described above, this application embodiment also provides a display device 9, which includes the display panel 8 as described above.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0082] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0083] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0084] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0085] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display panel bonding structure, characterized in that, include: A substrate, wherein bonding pads are provided on the upper surface of the substrate; A flip-chip film is stacked on top of the substrate. A solder resist layer is disposed inside the flip-chip film, and panel bonding gold fingers are disposed on the lower surface of the flip-chip film corresponding to the bonding pads. A conductive connection layer is disposed between the substrate and the flip-chip film for electrically connecting the bonding pads to the gold fingers of the panel bonding pads; A buffer layer, at least partially located between the substrate and the flip-chip film, is disposed in the same layer as the conductive connection layer and spaced apart from each other, and the hardness of the buffer layer is less than that of the solder resist layer.

2. The display panel bonding structure according to claim 1, characterized in that, The flip-chip film also includes a substrate, a conductive circuit disposed on the lower surface of the substrate, a solder resist layer covering a portion of the conductive circuit, and a buffer layer disposed on the lower surface of the solder resist layer.

3. The display panel bonding structure according to claim 2, characterized in that, The first end of the buffer layer is flush with the edge of the substrate, and the first end is the end of the buffer layer near the edge of the substrate.

4. The display panel bonding structure according to claim 2, characterized in that, The buffer layer has a covering structure that covers the edge of the substrate. The covering structure is formed by the buffer layer and an extension portion. The extension portion is formed by the first end of the buffer layer extending downward along the side of the substrate. The first end is the end of the buffer layer near the edge of the substrate.

5. The display panel bonding structure according to any one of claims 1 to 4, characterized in that, The spacing between the conductive connection layer and the buffer layer is greater than 1 mm.

6. The display panel bonding structure according to any one of claims 1 to 4, characterized in that, The material of the buffer layer is insulating resin.

7. The display panel bonding structure according to any one of claims 1 to 4, characterized in that, The flip-chip film adopts a double-layer wiring structure.

8. The display panel bonding structure according to any one of claims 1 to 4, characterized in that, The flip-chip film is further provided with flip-chip film bonding gold fingers, and the panel bonding gold fingers and / or the flip-chip film bonding gold fingers satisfy any of the following parameters: the surface roughness is 0.1μm~1.8μm, the maximum corrugation height of the surface is 0.05μm~0.7μm, and the peak-valley height of the surface is 0.05μm~1.5μm.

9. The display panel bonding structure according to any one of claims 1 to 4, characterized in that, The flip-chip film includes a substrate with a thickness of 15 μm to 50 μm.

10. A display panel, characterized in that, The display panel bonding structure includes any one of claims 1 to 9.

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