A test structure and method for monitoring process uniformity in an active region

Abstract

The application provides a test structure and a test method for testing process uniformity of an active region. In the test structure, a first test unit includes a first active region and a first gate electrode. The first active region is subjected to a light-doped drain ion implantation process. The first gate electrode has two preset offset directions relative to the first active region. Along each preset offset direction, at least two first test units with different offset amounts are arranged. The first active region is connected to a test on one side along the offset direction of the first gate electrode. A second test unit includes a second active region and a second gate electrode. The second active region is subjected to a light-doped drain ion implantation process and is subjected to a process to be monitored. The second gate electrode has two preset offset directions relative to the second active region. Along each preset offset direction, at least two second test units with different offset amounts are arranged. The second active region is connected to a test on one side along the offset direction of the second gate electrode. Through the application, the uniformity of the process to be monitored of the active region can be quickly judged.

Description

Technical Field

[0001] This application belongs to the field of semiconductor design and manufacturing technology, and in particular relates to a test structure and test method for monitoring the process uniformity of active regions. Background Technology

[0002] With the continuous development of semiconductor technology, device feature sizes are constantly shrinking, and the requirements for controlling the uniformity of active region processes are becoming increasingly stringent. The uniformity of active region processes directly determines the electrical performance and yield of devices. Poor process uniformity will significantly affect the consistency of device performance, and in severe cases, may even lead to device failure.

[0003] Currently, the process uniformity of active areas is mainly monitored using two methods: real-time measurement on the production line and cross-sectional analysis. Real-time measurement on the production line mostly uses optical detection methods, which have significant limitations: factors such as blurred alignment marks and large differences in the height of adjacent layers can cause the optimal focal length deviation to exceed the allowable range of the machine, resulting in measurement failure. At the same time, this method can only achieve process monitoring at the current station, with limited timeliness, and cannot track changes in the process uniformity of active areas introduced by subsequent processes such as CMP (chemical mechanical polishing) and heat treatment. Although cross-sectional analysis can accurately obtain process parameters of different areas of the finished product, it suffers from problems such as cumbersome operation, long detection cycle, and high cost, making it difficult to meet the needs of large-scale, high-efficiency process monitoring.

[0004] Electrical testing, with its advantages of simple operation, high efficiency, and ability to monitor large areas, has been widely used in the detection of various performance parameters of semiconductors. It can also intuitively reflect the true electrical response of semiconductor device parameters after multiple processes are completed, and related technology research and application continue to deepen.

[0005] Therefore, there is an urgent need to design a new type of electrical testing structure to make up for the technical shortcomings of existing optical measurement and slicing analysis, so as to achieve accurate and efficient monitoring of the process uniformity of the active region and provide reliable support for semiconductor process optimization and yield improvement. Summary of the Invention

[0006] To address all or part of the problems in the prior art, this application provides a test structure and test method for monitoring the process uniformity of the active region, so as to achieve accurate and efficient monitoring of the process uniformity of the active region by measuring the electrical error of the gate overlay in the active region.

[0007] To achieve the above objectives, the first aspect of this application provides a test structure for monitoring the process uniformity of the active region, comprising N first test units and N second test units, where N ≥ 4 and is an integer, wherein... The first test unit includes a first active region and a first gate disposed on the first active region. The first active region is lightly doped by drain ion implantation. The first gate has two preset offset directions relative to the first active region. At least two first test units with different offsets are disposed along each preset offset direction. The first active region is connected to the test unit on one side along the offset direction of the first gate. The second test unit includes a second active region and a second gate disposed on the second active region. The second active region is lightly doped by drain ion implantation and a monitoring process is performed on the second active region. The second gate has two preset offset directions relative to the second active region, and at least two second test units with different offsets are disposed along each preset offset direction. The second active region is connected to the test unit on one side along the offset direction of the second gate.

[0008] In some embodiments, the process to be monitored is a source / drain heavy doping process or a metal silicide process.

[0009] In some embodiments, the N first test units include n1 first structures and n2 second structures, wherein the first gate in the n1 first structures is offset relative to the first active region along a first direction, and the first gate in the n2 second structures is offset relative to the first active region along a second direction, where n1≥2, n2≥2, and n1+n2=N; The N second test units include n3 third structures and n4 fourth structures. In the n3 third structures, the second gate is offset relative to the second active region along a first direction, and in the n4 fourth structures, the second gate is offset relative to the second active region along a second direction. n3≥2, n4≥2, and n3+n4=N.

[0010] In some embodiments, in the first test unit, when the offset is negative, the first gate is offset relative to the first active region along a first direction, and the first active region is connected for testing along one side of the first gate in the first direction; when the offset is positive, the first gate is offset relative to the first active region along a second direction, and the first active region is connected for testing along one side of the first gate in the second direction. In the second test unit, when the offset is negative, the second gate is offset relative to the second active region along a first direction, and the second active region is connected to the test along one side of the second gate along the first direction; when the offset is positive, the second gate is offset relative to the second active region along a second direction, and the second active region is connected to the test along one side of the second gate along the second direction.

[0011] In some embodiments, in the first test unit, at least two first gates are disposed on the first active region, and in the second test unit, at least two second gates are disposed on the second active region, wherein the number of first gates is the same as the number of second gates.

[0012] In some embodiments, the first active region is provided with one or two pins at the beginning and end perpendicular to the preset offset direction on one side along the first gate offset direction, for performing two-terminal resistance testing or four-terminal Kelvin testing on the first active region. The second active region has one or two pins at the beginning and end perpendicular to the preset offset direction on one side along the second gate offset direction, for performing two-terminal resistance testing or four-terminal Kelvin testing on the second active region.

[0013] The second aspect of this application provides a test method for monitoring the process uniformity of the active region, implemented using the test structure described in the first aspect above, comprising the following steps: Obtain the resistance parameters of the first active region of N first test units measured at different offsets, and use the offset and the corresponding resistance parameters as a set of reference data to obtain N sets of first reference data. Obtain the resistance parameters of the second active region measured by N second test units at different offsets, and use the offset and the corresponding resistance parameters as a set of reference data to obtain N sets of second reference data; Data fitting is performed based on N sets of the first reference data and N sets of the second reference data respectively, so as to obtain the overlay error value of the first test unit and the overlay error value of the second test unit according to the data fitting results; Based on the comparison results of the overlay error values ​​of the first test unit and the second test unit, the uniformity of the process to be monitored is determined.

[0014] In some embodiments, the data fitting process based on N sets of the first reference data to obtain the overlay error value of the first test unit according to the data fitting result includes: In a Cartesian coordinate system, for the first test unit, N sets of the first reference data are denoted as coordinate points (Xm, Rxm) and (Xn, Rxn), where 2≤m≤n1, 2≤n≤n2, where Xm represents the offset of the first gate relative to the first active region along the first direction, Xn represents the offset of the first gate relative to the first active region along the second direction, Rxm represents the resistance of the region of the first active region along the first direction of the first gate when the first gate is offset relative to the first active region along the first direction, and Rxn represents the resistance of the region of the first active region along the second direction of the first gate when the first gate is offset relative to the first active region along the second direction. Based on the coordinate points of the first reference data, two fitted lines are obtained by linear fitting. The resistance symmetry point of the first active region is determined based on the two fitted straight lines, and the resistance symmetry point is used as the overlay error value of the first test unit.

[0015] In some embodiments, determining the resistance symmetry point of the first active region based on the two fitted straight lines includes: The offset corresponding to the intersection of the two fitted straight lines is determined as the resistance symmetry point of the first active region.

[0016] In some embodiments, determining the uniformity of the process to be monitored based on the comparison result of the overlay error value of the first test unit and the overlay error value of the second test unit includes: When the overlay error value of the first test unit and the overlay error value of the second test unit are the same, the uniformity of the process to be monitored implemented in the second active region is good. When the overlay error value of the first test unit and the overlay error value of the second test unit are different, the uniformity of the process to be monitored implemented in the second active region is lacking.

[0017] The aforementioned test structure and method for monitoring the uniformity of the active region process includes N first test units and N second test units. By having the first gate with two preset offset directions relative to the first active region, and setting at least two first test units with different offset amounts along each preset offset direction, two sets of first electrical data can be obtained for data fitting. Similarly, by having the second gate with two preset offset directions relative to the second active region, and setting at least two second test units with different offset amounts along each preset offset direction, two sets of second electrical data can be obtained for data fitting. By implementing the process to be monitored in the second active region of the second test unit, and comparing the fitting results of the first and second reference data, the overlay error before and after the implementation of the process to be monitored can be obtained, thereby quickly determining the uniformity of the process to be monitored and providing a basis for process optimization. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a test structure for monitoring the process uniformity of the active region according to an embodiment of this application. 1a and 1b are schematic diagrams of the first test unit along two preset offset directions, and 1c and 1d are schematic diagrams of the second test unit along two preset offset directions.

[0020] Figure 2 A schematic diagram of the first test unit offset along the first direction in a test structure for monitoring the process uniformity of the active region provided in an embodiment of this application (lightly doped drain ion implantation treatment of the first active region).

[0021] Figure 3 a is Figure 2 A schematic diagram of the cross-sectional structure along the AA direction.

[0022] Figure 3 b is Figure 2 A schematic diagram of the cross-sectional structure along the BB direction.

[0023] Figure 4 A schematic diagram of a second test unit offset along a first direction in a test structure for monitoring the process uniformity of the active region provided in an embodiment of this application (the second active region implements source and drain heavy doping process).

[0024] Figure 5 a is Figure 4 A schematic diagram of the cross-sectional structure along the AA direction.

[0025] Figure 5 b is Figure 4 A schematic diagram of the cross-sectional structure along the BB direction.

[0026] Figure 6 A schematic diagram of a second test unit offset along a first direction in a test structure for monitoring the process uniformity of the active region provided in another embodiment of this application (the second active region implements a metal silicide process).

[0027] Figure 7 a is Figure 6 A schematic diagram of the cross-sectional structure along the AA direction.

[0028] Figure 7 b is Figure 6 A schematic diagram of the cross-sectional structure along the BB direction.

[0029] Figure 8 'a' is a graph showing the change in resistance value of the first active region (second active region) with the offset under ideal conditions; Figure 8 b is a schematic diagram showing the actual position of the first gate (second gate) relative to the first active region (second active region) under the same offset amount when the first gate (second gate) is offset along the first direction and the second direction respectively. Figure 9 'a' is a graph showing the change in resistance value of the first active region (second active region) with offset when the overprinting error is positive. Figure 9 b is a schematic diagram showing the actual position of the first gate (second gate) relative to the first active region (second active region) under the same offset amount when the first gate (second gate) is offset along the first direction and the second direction respectively. Figure 10 'a' represents the change in resistance value of the first active region (second active region) with offset when the overprinting error is negative; Figure 10 b is a schematic diagram showing the actual position of the first gate (second gate) relative to the first active region (second active region) under the same offset amount when the first gate (second gate) is offset along the first direction and the second direction, respectively.

[0030] Figure descriptions: 1. Gate interconnect; 2 / 3 / 4 / 5. Active region interconnect; 6a. First gate; 6b. Second gate; 7a. First active region; 7b. Second active region; 8. Metal silicide barrier layer; 9. Contact hole; 10. Substrate; 11. Well region; 12. Lightly doped region; 13. Gate oxide; 14. Metal silicide; 15. Sidewall; 16. Heavily doped region. Detailed Implementation

[0031] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the detailed description of any embodiment below with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this application.

[0032] The active area is the core region for transistor formation. The process uniformity of the active area directly determines the core performance parameters of the transistor, such as device performance consistency, yield control, and circuit compatibility. Active area process uniformity monitoring refers to the process of monitoring the formation process and physical characteristics of the active area (AA) on the chip during semiconductor manufacturing. This ensures that the size, morphology, doping distribution, and alignment accuracy with key layers such as the gate remain consistent within the same wafer and between different wafers, thereby improving electrical performance and yield.

[0033] like Figures 1-5 As shown, this application provides a test structure for monitoring the uniformity of active region fabrication processes. It assesses the impact of active region formation processes on device uniformity by inverting physical overlay (OVL) errors using electrical parameters. Figure 2 , Figure 3 a and Figure 3 As shown in b, this test structure can be integrated into the scribe line or test chip area of ​​a wafer, mainly comprising N first test units, where N ≥ 4 and is an integer, preferably an integer not less than 20. This number setting ensures sufficient sampling points during data fitting to meet the requirements of statistical significance and the accuracy of the fitted curve. The test structure includes a substrate 10, and the first test unit includes a first active region 7a and a first gate 6a disposed on the first active region 7a. A well region 11 is formed on the substrate 10, the first active region 7a is located within the well region 11, a gate oxide 13 is disposed between the first gate 6a and the first active region 7a, and sidewalls 15 may be provided on both sides of the gate 6a.

[0034] To comprehensively monitor the process uniformity of the active region within a two-dimensional plane, the test structure can employ a specific angle offset design. Specifically, the first gate 6a has two preset offset directions relative to the first active region 7a. These two preset offset directions refer to the direction vectors that are manually set during the layout design stage to cause a relative positional offset between the first gate 6a and the first active region 7a. Specifically, the preset offset directions can include a positive and a negative direction along the width direction of the first gate 6a.

[0035] Along each of the preset offset directions, at least two first test units with different offsets are provided to construct different overlay positions. Since the overlay positions of the first gate 6a and the first active region 7a are different in different first test units, the width of the active region along one side of the preset offset direction of the first gate 6a will change, resulting in a difference in the resistance of the active region. By performing electrical tests on at least two first test units in each of the preset offset directions, electrical data for each preset offset direction is captured, and at least two data points are obtained for data fitting. In this embodiment, the first active region 7a is lightly doped to form a lightly doped region 12 through lightly doped drain ion implantation. Exemplarily, N first test units include n1 first structures and n2 second structures (n1≥2, n2≥2 and n1+n2=N). In the n1 first structures, the first gate 6a is offset relative to the first active region 7a along a first direction, and in the n2 second structures, the first gate 6a is offset relative to the first active region 7a along a second direction. The offset includes a zero offset, several positive offsets and several negative offsets that vary relative to the zero offset according to a preset offset step size, wherein the first direction and the second direction are opposite vectors. For example, the offset corresponding to one of the first and second directions is positive, and the offset corresponding to the other is negative. The offset step size M is 1nm-10nm, and can be flexibly adjusted according to the process node and accuracy requirements to meet process needs.

[0036] Specifically, in this example, the first active region 7a is treated with lightly doped drain (LDD) ion implantation to form a lightly doped region 12. Specifically, after the first active region 7a is patterned, the first gate 6a and the first sidewall are used as a mask to perform self-aligned ion implantation on the source and drain regions of the first active region 7a. By controlling the implantation energy and dose, lightly doped regions 12 are formed on both sides of the edge of the first gate 6a.

[0037] During testing, the first gate 6a is connected through the contact hole 8 and the metal layer (gate connection 1). By applying a voltage to the first gate 6a to turn off the channel, the first active regions 7a on both sides of the first gate 6a are isolated, avoiding mutual interference of test results. For each first test unit, the first active region 7a is connected for testing along one side of the offset direction of the first gate 6a. Specifically, when the offset is negative, the first gate 6a is offset relative to the first active region 7a along a first direction, and the first active region 7a is connected for testing along one side of the first gate 6a along the first direction; when the offset is positive, the first gate 6a is offset relative to the first active region 7a along a second direction, and the first active region 7a is connected for testing along one side of the first gate 6a along the second direction.

[0038] Specifically, on one side of the first active region 7a along the offset direction of the first gate 6a, one or two pins (active region lines 2, 3, 4, and 5) are respectively provided at the beginning and end perpendicular to the preset offset direction, for performing two-terminal resistance testing or four-terminal Kelvin testing on the first active region 7a. That is, when the first gate 6a is offset relative to the first active region 7a along the first direction, the offset is negative, and on one side of the first active region 7a along the first direction, one pin is respectively provided at the beginning and end perpendicular to the preset offset direction for performing two-terminal resistance testing; when the first gate 6a is offset relative to the first active region 7a along the second direction, the offset is positive, and on one side of the first active region 7a along the second direction, one pin is respectively provided at the beginning and end perpendicular to the preset offset direction for performing two-terminal resistance testing. In other embodiments, the first active region 7a may be provided with two pins at its head and tail ends perpendicular to the preset offset direction for performing a four-terminal Kelvin test on the first active region 7a. This application does not limit this.

[0039] like Figures 4-7 As shown, in this embodiment, the test structure for monitoring the process uniformity of the active region also includes N second test units (N≥4 and are integers) arranged at intervals from the N first test units. The configuration of the second test units can refer to the first test units in the above embodiment. For the sake of brevity, any part of the configuration of the second test units not mentioned can be referred to the corresponding content in the first test units.

[0040] Specifically, the second test unit includes a second active region 7b and a second gate 6b disposed on the second active region 7b. The second gate 6b has two preset offset directions relative to the second active region 7b, and at least two second test units with different offsets are disposed along each preset offset direction. For example, N second test units include n3 third structures and n4 fourth structures (n3≥2, n4≥2, and n3+n4=N). In the n3 third structures, the second gate 6b is offset relative to the second active region 7b along a first direction, and in the n4 fourth structures, the second gate 6b is offset relative to the second active region 7b along a second direction.

[0041] In this embodiment, the second active region 7b is connected to the test along one side of the offset direction of the second gate 6b. When the offset is negative, the second gate 6b is offset relative to the second active region 7b along a first direction, and the second active region 7b is connected to the test along one side of the first direction of the second gate 6b. When the offset is positive, the second gate 6b is offset relative to the second active region 7b along a second direction, and the second active region 7b is connected to the test along one side of the second direction of the second gate 6b.

[0042] Specifically, on one side of the second active region 7b along the offset direction of the second gate 6b, one or two pins are respectively provided at the beginning and end perpendicular to the preset offset direction for performing two-terminal resistance testing or four-terminal Kelvin testing on the second active region 7b. That is, when the second gate 6b is offset relative to the second active region 7b along the first direction, the offset is negative, and on one side of the second active region 7b along the first direction, one pin is respectively provided at the beginning and end perpendicular to the preset offset direction for performing two-terminal resistance testing; when the second gate 6b is offset relative to the second active region 7b along the second direction, the offset is positive, and on one side of the second active region 7b along the second direction, one pin is respectively provided at the beginning and end perpendicular to the preset offset direction for performing two-terminal resistance testing. In other embodiments, two pins may be provided at the beginning and end of the second source region perpendicular to the preset offset direction for performing a four-terminal Kelvin test on the second active region 7b. This application does not limit this.

[0043] In this embodiment, the second test unit differs from the first test unit in that: In addition to performing lightly doped drain ion implantation on the first active region 7a, the second active region 7b is also subjected to the process to be monitored. The lightly doped drain ion implantation process can be referred to the corresponding description in the first test unit above. The process to be monitored can be a source / drain heavy doping process, a metal silicide process, or other active region processes with uniformity issues.

[0044] The source / drain heavy doping process is a high-energy ion implantation process performed after light doping (LDD) to form a heavily doped region capable of low-resistance ohmic contacts. By implanting high concentrations of phosphorus or arsenic (N-type) or boron (P-type) ions, the series resistance of the source / drain region is significantly reduced, increasing the device drive current. The energy, dosage, annealing conditions, and implantation temperature of the ion implantation all affect the uniformity of the distribution of the source / drain heavy doping ions. When the distribution of source / drain heavy ions is uneven along the channel length and width, the resistance of the active region will vary unevenly with the offset, thus affecting the calculation of overlay error. The salicide process involves reacting a metal (such as cobalt or nickel) with the polysilicon of the source / drain region and gate to form a low-resistance silicide layer. This process can significantly reduce contact resistance and improve device performance. The thickness of the deposited metal, annealing temperature, and substrate cleanliness all affect the uniformity of the salicide growth. The uneven distribution of metal silicide along the length and width of the channel can also affect the uniform change of the active region resistance with the offset, resulting in inaccurate overlay error values. When the metal silicide process is implemented, the second active region is covered with metal silicide 14; conversely, a metal silicide barrier layer 8 is set for test units that do not undergo the metal silicide process.

[0045] The uniformity of the active region process is evaluated by comparing the gate-to-active region overlay error calculated by the first test unit (reference) and the second test unit (process monitoring).

[0046] The aforementioned test structure for monitoring the process uniformity of the active region includes N first test units and N second test units. By having the first gate 6a offset from the first active region 7a in two preset offset directions, and setting at least two first test units with different offset amounts along each preset offset direction, two sets of first reference data can be obtained for data fitting. Similarly, by having the second gate 6b offset from the second active region 7b in two preset offset directions, and setting at least two second test units with different offset amounts along each preset offset direction, two sets of second reference data can be obtained for data fitting. By implementing the process to be monitored on the second active region 7b in the second test unit, and comparing the fitting results of the first and second reference data, the uniformity of the process to be monitored can be quickly determined, providing a basis for process optimization.

[0047] The following is a detailed description through preferred embodiments: In some embodiments, in the first test unit, at least two first gates 6a (m, m≥2) are provided on the first active region 7a, thereby dividing the first active region 7a into m+1 regions. At this time, by applying voltage to multiple first gates 6a to turn off the channel, the first active region 7a is isolated into m+1 regions, and the side regions of the first active region 7a along the offset direction of the first gate 6a can be connected out for testing.

[0048] Similarly, in the second test unit, at least two second gates 6b (m, m≥2) are provided on the second active region 7b, thereby dividing the second active region 7b into m+1 regions. At this time, by applying voltage to multiple second gates 6b to turn off the channel, the second active region 7b is isolated into m+1 regions, and the side region of the second active region 7b along the offset direction of the second gate 6b can be connected for testing.

[0049] It should be noted that in this embodiment, the number of the first gate 6a is the same as the number of the second gate 6b. This configuration allows for the construction of a fully matched control group. In the first and second test units, except for the difference in the "process to be monitored" (such as a heavy source / drain doping process or a metal silicide process), all other physical factors affecting electrical parameters (including the size of the active region, the number of gates, the test area, the number of test units, etc.) remain consistent, thereby ensuring that the final measured electrical differences can be uniquely and accurately attributed to changes in the uniformity of the active region process.

[0050] This application also provides a test method for monitoring the process uniformity of the active region, implemented using the test structure described in any of the above embodiments, including the following steps S101-S104.

[0051] Step S101: Obtain the resistance parameters of the first active region 7a measured by N first test units at different offsets, and use the offsets and corresponding resistance parameters as a set of reference data to obtain N sets of first reference data; Step S102: Obtain the resistance parameters of the second active region 7b measured by N second test units at different offsets, and use the offsets and corresponding resistance parameters as a set of reference data to obtain N sets of second reference data.

[0052] In this embodiment, the test structure for monitoring the process uniformity of the active region includes N first test units and N second test units. The configuration of the first test units and the second test units can be referred to the corresponding descriptions in the above embodiments, which will not be repeated here. The following describes the test process of N first test units: For N first test units, at least two first test units with different offsets are set along each preset offset direction. Electrical data for each preset offset direction is captured by performing electrical tests on at least two first test units in each preset offset direction. During testing, the channel is turned off by applying a voltage to the first gate 6a, thereby isolating the first active regions 7a on both sides of the first gate 6a and avoiding mutual interference of test results.

[0053] For each first test unit, the first active region 7a is connected for testing along one side of the offset direction of the first gate 6a. Specifically, when the offset is negative, the first gate 6a is offset relative to the first active region 7a along a first direction, and the first active region 7a is connected for testing along one side of the first direction of the first gate 6a. At this time, perpendicular to the preset offset direction, one or two pins are respectively provided at the beginning and end of the first active region 7a for performing two-terminal resistance testing or four-terminal Kelvin testing on the first active region 7a. When the offset is positive, the first gate 6a is offset relative to the first active region 7a along a second direction, and the first active region 7a is connected for testing along one side of the second direction of the first gate 6a. At this time, perpendicular to the preset offset direction, one or two pins are respectively provided at the beginning and end of the first active region 7a for performing two-terminal resistance testing or four-terminal Kelvin testing on the first active region 7a. The first and second directions are opposite vectors.

[0054] After obtaining the resistance parameters of the first active region 7a of N first test units at different offsets, the offsets and corresponding resistance parameters are used as a set of reference data to obtain N sets of first reference data. Similarly, referring to the above testing process, the resistance parameters of the second active region 7b of N second test units at different offsets are obtained, and the offsets and corresponding resistance parameters are used as a set of reference data to obtain N sets of second reference data.

[0055] Step S103: Perform data fitting processing based on N sets of the first reference data and N sets of the second reference data respectively, so as to obtain the overlay error value OVL1 of the first test unit and the overlay error value OVL2 of the second test unit according to the data fitting results.

[0056] Specifically, in a Cartesian coordinate system, for the first test unit, N sets of the first reference data are denoted as coordinate points (Xm, Rxm) and (Xn, Rxn), where 2≤m≤n1 and 2≤n≤n2. Here, Xm represents the offset of the first gate 6a relative to the first active region 7a along the first direction, Xn represents the offset of the first gate 6a relative to the first active region 7a along the second direction, Rxm represents the resistance of the region of the first active region 7a along the first direction when the first gate 6a is offset relative to the first active region 7a along the first direction, and Rxn represents the resistance of the region of the first active region 7a along the second direction when the first gate 6a is offset relative to the first active region 7a along the second direction.

[0057] When the active region of the first test unit undergoes lightly doped drain ion implantation, the resistance value obtained is relatively large due to the low concentration of lightly doped drain ions. The first active region 7a is less affected by processes such as lightly doped drain ion implantation / annealing, so the resistance value of the first active region 7a will change uniformly with the offset, reflecting the resistance value of the first active region 7a itself. Thus, the overlay error of the first gate 6a to the first active region 7a can be accurately obtained. In this embodiment, a graph can be plotted based on the coordinate points corresponding to the N sets of the first reference data to obtain the overlay error value OVL1 of the first test unit under two preset offset directions. This overlay error value OVL1 can reflect the overlay error of the first gate 6a to the first active region 7a when the process to be monitored has not been implemented, and can be used as a comparison benchmark for subsequent monitoring.

[0058] Specifically, a resistance-offset relationship diagram can be constructed based on N sets of the first reference data to obtain the overlay error value OVL1 of the first test unit.

[0059] First, linear fitting is performed based on the coordinate points of the first reference data. Since the first direction and the second direction are opposite vector directions, the N sets of first reference data can be divided into two groups according to the offset direction for segmented fitting, resulting in two fitted straight lines. Specifically, at least two sets of data are obtained and linearly fitted based on the offset of the first gate 6a relative to the first active region 7a along the first direction and the corresponding resistance measurement value. This yields the trend of the resistance of the first active region 7a in the first test unit changing with the corresponding offset along the first direction. Similarly, at least two sets of data are obtained and linearly fitted based on the offset of the first gate 6a relative to the first active region 7a along the second direction and the corresponding resistance measurement value. This yields the trend of the resistance of the first active region 7a in the first test unit changing with the corresponding offset along the second direction.

[0060] Then, after obtaining two fitted straight lines, the resistance symmetry point of the first active region 7a is determined based on the two fitted straight lines, and the resistance symmetry point is used as the overlay error value of the first test unit.

[0061] like Figure 8 As shown, generally, in an ideal state without overlay error, when the offset of the first gate 6a relative to the first active region 7a is 0, the physical dimensions of the first active region 7a along the first direction of the first gate 6a and along the second direction of the first gate 6a are the same (width w1=w2). The trends of the two resistance measurements with the offset are symmetrical about the design zero point (0 offset), that is, the offset corresponding to the resistance symmetry point is zero. When overlay error exists, the actual physical positions of the first gate 6a and the first active region 7a deviate from the design positions, causing the center of symmetry of the resistance-offset relationship diagram to shift. At this time, the resistance symmetry point will deviate from zero. Therefore, the resistance symmetry point of the first active region 7a can be determined according to the two fitted lines, and the resistance symmetry point can be used as the overlay error value of the first test unit. For example: Figure 9 As shown, when there is an overlay error M in the second direction between the first gate 6a and the first active region 7a, the active region width (w1) obtained by testing the first active region 7a along the first direction of the first gate 6a (hereinafter referred to as structure 1) is greater than the active region width (w2) obtained by testing the first active region 7a along the second direction of the first gate 6a (hereinafter referred to as structure 2). The resistance value of the first active region 7a measured by structure 1 is smaller (the conductive cross-section becomes larger). Under the same offset, the resistance value measured by structure 1 is also smaller than the resistance value measured by structure 2. The horizontal coordinate value corresponding to the symmetrical point is -M; conversely, if... Figure 10 As shown, when there is an overlay error M in the first direction between the first gate 6a and the first active region 7a, the active region width (w1) measured by structure 1 is smaller than the active region width (w2) measured by structure 2. The resistance measured by structure 1 is larger (the conductive cross-section becomes smaller). Under the same offset, the resistance measured by structure 1 is also larger than the resistance measured by structure 2. The horizontal coordinate value corresponding to the symmetrical point is M.

[0062] Therefore, the resistance symmetry point of the first active region 7a can be determined based on the two fitted straight lines, and the resistance symmetry point can be used as the overlay error value of the first test unit.

[0063] In this application, the offset corresponding to the intersection point of the two fitted straight lines can be determined as the resistance symmetry point of the first active region 7a. The specific method for obtaining the resistance symmetry point is as follows: Since the resistance values ​​of the two regions are equal only when the first gate 6a is at the physical geometric center position relative to the first active region 7a (i.e., the effective structures on both sides are completely symmetrical), equal resistance values ​​correspond to a symmetrical state of the physical structure. For the two fitted straight lines mentioned above, their intersection point has the following physical meaning: In the offset coordinates corresponding to the intersection point, Rxmi = Rxnj; therefore, the X-axis coordinate (offset) corresponding to the intersection point is the resistance symmetry point.

[0064] Similarly, for the second test unit, in a rectangular coordinate system, N sets of the second reference data are denoted as coordinate points (Xi, Rxi) and (Xj, Rxj), 2≤i≤n1, 2≤j≤n2, where Xi represents the offset of the second gate 6b relative to the second active region 7b along the first direction, Xj represents the offset of the second gate 6b relative to the second active region 7b along the second direction, Rxi represents the resistance of the second active region 7b along one side of the second gate 6b in the first direction when the second gate 6b is offset relative to the second active region 7b in the first direction, and Rxj represents the resistance of the second active region 7b along one side of the second gate 6b in the second direction when the second gate 6b is offset relative to the second active region 7b in the second direction. The coordinate points of the second reference data obtained by the test are fitted to obtain two fitted lines / curves. The resistance symmetry point of the second active region 7b is determined according to the two fitted lines / curves, and the resistance symmetry point is used as the overlay error value OVL2 of the second test unit.

[0065] Of course, the relationship between the active region resistance and the overlay error value OVL is not always strictly linear. For example, at different offsets, due to optical proximity correction effects, open / short circuits, etc., the relationship between resistance and offset may exhibit a quadratic curve or more complex nonlinear characteristics. In other embodiments, nonlinear fitting (such as polynomial fitting, Gaussian fitting, etc.) can often more accurately approximate the actual physical process, thereby improving the calculation accuracy of the overlay error. The resistance symmetry point of the active region is determined based on the two fitting curves (at this time, the two fitting curves intersect, and the intersection point is the symmetry point where the resistance is equal). The resistance symmetry point is used as the overlay error value OVL.

[0066] In this embodiment, the overlay error of the gate to the active region is inverted by electrical testing to monitor the process uniformity of the active region. Compared with traditional optical measurement, it not only has the advantages of simple operation, short test cycle and support for wafer-level large-area scanning detection, but also effectively avoids the risk of measurement failure caused by unclear markings or excessive interlayer height difference. This method can comprehensively reflect the actual overlay deviation under the cumulative effect of the active region processing process, thereby more accurately evaluating the process uniformity of the active region.

[0067] Step S104: Based on the comparison result of the overlay error value of the first test unit and the overlay error value of the second test unit, determine the uniformity of the process to be monitored.

[0068] In this embodiment, the overlay error value OVL1 of the first test unit reflects the initial alignment state between the first gate 6a and the active region after the active region undergoes a lightly doped drain implantation process. This value includes the basic deviations accumulated by necessary standard processes such as photolithography alignment error, wafer planarization stress, and deformation caused by conventional thermal processing, and can be used as a reference benchmark.

[0069] The overlay error value OVL2 of the second test unit, based on the same basic process (lightly doped drain implantation process), additionally introduces the active region process to be monitored (such as source / drain heavy doping process, metal silicide process, etc.). Because the inhomogeneity of these active region processes causes uneven changes in the resistance of the active region with gate offset, the actual gate-to-active region OVL value cannot be obtained from the fitted data. Therefore, the uniformity of the process can be judged by comparing OVL1 and OVL2.

[0070] For example, when the second test unit undergoes a heavy source / drain doping process, it is typically necessary to monitor the distribution of heavy ions in the source / drain by slicing combined with EDX (Energy Dispersive X-ray Spectroscopy). This process is complex, time-consuming, and cannot achieve large-area detection. The uniformity of the heavy ion distribution in the source / drain affects the resistance distribution of the second test unit, thereby affecting the overlay error of the gate to the active region calculated from the fitted data. By comparing OVL1 and OVL2, the uniformity of the heavy ion distribution in the source / drain can be quickly determined over a large area. When the second test unit undergoes a metal silicide growth process, the uniformity of the metal silicide growth is typically monitored by slicing and manual measurement. However, since the metal silicide is only a very thin layer, it is difficult to accurately and over a large area determine its uniformity using this method. The uniformity of the metal silicide growth affects the resistance distribution of the second test unit, thereby affecting the overlay error of the gate to the active region calculated from the fitted data. By comparing OVL1 and OVL2, the uniformity of the metal silicide growth can be quickly determined over a large area.

[0071] In this embodiment, if the process to be monitored has good uniformity, the overlay error value should be consistent between the two test structures of the first test unit and the second test unit. Conversely, if there is a significant difference between the two sets of data, it indicates that the active region process has a uniformity defect, which makes the overlay error value OVL2 of the second test unit inaccurate. The test result cannot reflect the actual overlay error value in the second test unit.

[0072] In this embodiment, the process to be monitored is self-verified by comparing the overlay error value OVL1 of the first test unit with the overlay error value OVL2 of the second test unit, thereby determining the uniformity of the process to be monitored.

[0073] Specifically, when the overlay error value of the first test unit and the overlay error value of the second test unit are the same, the uniformity of the process to be monitored implemented in the second active region 7b is good. For example, when the difference between the overlay error value OVL1 of the first test unit and the overlay error value OVL2 of the second test unit is less than 10%, the two results are determined to be the same. Conversely, when the overlay error value of the first test unit and the overlay error value of the second test unit are greater than or equal to 10%, the two results are determined to be different, and the uniformity of the process to be monitored implemented in the second active region 7b is lacking.

[0074] The following examples further illustrate this application.

[0075] Example 1: Firstly, a test structure for monitoring the process uniformity of the active region is provided, comprising two sets of test units: a) 60 first test units, wherein in 30 of the first test units, the first gate 6a is offset relative to the first active region 7a along a first direction, and in the other 30, the first gate 6a is offset relative to the first active region 7a along a second direction, with an offset step M of 2nm. The first active region 7a of each first test unit is treated with lightly doped drain ion implantation; b) 60 second test units, wherein in 30 of the second test units, the second gate 6b is offset relative to the second active region 7b along a first direction, and in the other 30, the second gate 6b is offset relative to the second active region 7b along a second direction, with an offset step M of 2nm. The second active region 7b of each second test unit is treated with both lightly doped drain ion implantation and heavily doped source / drain ion implantation. The resistance of each test unit is measured using a four-terminal Kelvin.

[0076] Then, a graph was plotted with resistance on the Y-axis and offset on the X-axis. Curve fitting was used to obtain the offsets M1 and M2 corresponding to the symmetrical points of the two fitted lines in group a) and group b), respectively. These offsets M1 and M2 represent the overlay error OVL1 of the first gate 6a to the first active region 7a and the overlay error OVL2 of the second gate 6b to the second active region 7b, respectively. OVL1 in group a) is 2.19 nm, and OVL2 in group b) is 2.12 nm. The difference between any two OVL results is less than 10%, therefore OVL1 = OVL2. The overlay error of the first gate 6a to the first active region 7a is 2.19 nm (positive value), and the direction is along the first direction. Compared with the slice data, the measured overlay error of the first gate 6a to the first active region 7a is accurate, and the uniformity of the monitored process is good.

[0077] Example 2: Firstly, a test structure for monitoring the process uniformity of the active region is provided, comprising two sets of test units: a) 60 first test units, wherein in 30 of the first test units, the first gate 6a is offset relative to the first active region 7a along a first direction, and in the other 30, the first gate 6a is offset relative to the first active region 7a along a second direction, with an offset step M of 2nm. The first active region 7a of each first test unit is treated with lightly doped drain ion implantation; b) 60 second test units, wherein in 30 of the second test units, the second gate 6b is offset relative to the second active region 7b along a first direction, and in the other 30, the second gate 6b is offset relative to the second active region 7b along a second direction, with an offset step M of 2nm. The second active region 7b of each second test unit is treated with both lightly doped drain ion implantation and heavily doped source / drain ion implantation. The resistance of each test unit is measured using a four-terminal Kelvin.

[0078] Then, plotting the resistance value on the Y-axis and the offset on the X-axis, the offset M1 corresponding to the symmetrical point of the two fitted lines in group a) and the offset M2 corresponding to the symmetrical point of the two fitted lines in group b) are obtained by curve fitting. The offsets M1 and M2 are the overlay error value OVL1 of the first gate 6a to the first active region 7a and the overlay error value OVL2 of the second gate 6b to the second active region 7b, respectively. OVL1 = 2.17 nm in group a) and OVL2 = 5 nm in group b). The difference between OVL1 and OVL2 is greater than 10%, so it is determined that OVL1 ≠ OVL2. The overlay error of the first gate 6a to the first active region 7a is 2.17 nm (positive value), and the direction is along the first direction. The uniformity of the source and drain heavy doping process is lacking. After slicing and EDX verification, the measured overlay error of the first gate 6a to the first active region 7a is accurate, and the uniformity of the distribution of source and drain heavy doping is indeed poor.

[0079] Example 3: Firstly, a test structure for monitoring the process uniformity of the active region is provided, comprising two sets of test units: a) 60 first test units, wherein in 30 of the first test units, the first gate 6a is offset relative to the first active region 7a along a first direction, and in the other 30, the first gate 6a is offset relative to the first active region 7a along a second direction, with an offset step M of 2nm. The first active region 7a of each first test unit undergoes light doping drain ion implantation treatment; b) 60 second test units, wherein in 30 of the second test units, the second gate 6b is offset relative to the second active region 7b along a first direction, and in the other 30, the second gate 6b is offset relative to the second active region 7b along a second direction, with an offset step M of 2nm. The second active region 7b of each second test unit undergoes light doping drain ion implantation treatment and metal silicide treatment. The resistance value of each test unit is measured using a four-terminal Kelvin test.

[0080] Then, a graph was plotted with resistance on the Y-axis and offset on the X-axis. Through curve fitting, the offsets M1 and M2 corresponding to the symmetrical points of the two fitted lines in group a) and group b) were obtained, respectively. These offsets M1 and M2 are the overlay error values ​​OVL1 of the first gate 6a to the first active region 7a and OVL2 of the second gate 6b to the second active region 7b, respectively. In group a), OVL1 = 2.2 nm, and in group b), OVL3 = 10 nm. The difference between OVL1 and OVL2 is greater than 10%, so OVL1 ≠ OVL3. The overlay error of the first gate 6a to the first active region 7a is 2.2 nm (positive value), and the direction is along the first direction. The uniformity of the metal silicide growth is lacking. After slicing verification, the measured overlay error of the first gate 6a to the first active region 7a is accurate, and the metal silicide growth in the active region is uneven due to the shielding effect of the gate.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A test structure for monitoring the process uniformity of the active region, characterized in that, It includes N first test units and N second test units, where N ≥ 4 and is an integer, where, The first test unit includes a first active region and a first gate disposed on the first active region. The first active region is lightly doped by drain ion implantation. The first gate has two preset offset directions relative to the first active region. At least two first test units with different offsets are disposed along each preset offset direction. The first active region is connected to the test unit on one side along the offset direction of the first gate. The second test unit includes a second active region and a second gate disposed on the second active region. The second active region is lightly doped by drain ion implantation and a monitoring process is performed on the second active region. The second gate has two preset offset directions relative to the second active region, and at least two second test units with different offsets are disposed along each preset offset direction. The second active region is connected to the test unit on one side along the offset direction of the second gate.

2. The test structure for monitoring the process uniformity of the active region according to claim 1, characterized in that, The process to be monitored is a source / drain heavy doping process or a metal silicide process.

3. The test structure for monitoring the process uniformity of the active region according to claim 1, characterized in that, The N first test units include n1 first structures and n2 second structures. In the n1 first structures, the first gate is offset relative to the first active region along a first direction. In the n2 second structures, the first gate is offset relative to the first active region along a second direction. n1≥2, n2≥2 and n1+n2=N. The N second test units include n3 third structures and n4 fourth structures. In the n3 third structures, the second gate is offset relative to the second active region along a first direction, and in the n4 fourth structures, the second gate is offset relative to the second active region along a second direction. n3≥2, n4≥2, and n3+n4=N.

4. The test structure for monitoring the process uniformity of the active region according to claim 1, characterized in that, In the first test unit, when the offset is negative, the first gate is offset relative to the first active region along a first direction, and the first active region is connected to the test along one side of the first gate in the first direction; when the offset is positive, the first gate is offset relative to the first active region along a second direction, and the first active region is connected to the test along one side of the first gate in the second direction. In the second test unit, when the offset is negative, the second gate is offset relative to the second active region along a first direction, and the second active region is connected to the test along one side of the second gate along the first direction; when the offset is positive, the second gate is offset relative to the second active region along a second direction, and the second active region is connected to the test along one side of the second gate along the second direction.

5. The test structure for monitoring the process uniformity of the active region according to claim 1, characterized in that, In the first test unit, at least two first gates are disposed on the first active region, and in the second test unit, at least two second gates are disposed on the second active region, wherein the number of first gates is the same as the number of second gates.

6. The test structure for monitoring the process uniformity of the active region according to claim 1, characterized in that, The first active region has one or two pins at the beginning and end perpendicular to the preset offset direction on one side along the first gate offset direction, for performing two-terminal resistance testing or four-terminal Kelvin testing on the first active region. The second active region has one or two pins at the beginning and end perpendicular to the preset offset direction on one side along the second gate offset direction, for performing two-terminal resistance testing or four-terminal Kelvin testing on the second active region.

7. A test method for monitoring the process uniformity of the active region, implemented using the test structure described in any one of claims 1-6, characterized in that, Includes the following steps: Obtain the resistance parameters of the first active region of N first test units measured at different offsets, and use the offset and the corresponding resistance parameters as a set of reference data to obtain N sets of first reference data. Obtain the resistance parameters of the second active region measured by N second test units at different offsets, and use the offset and the corresponding resistance parameters as a set of reference data to obtain N sets of second reference data; Data fitting is performed based on N sets of the first reference data and N sets of the second reference data respectively, so as to obtain the overlay error value of the first test unit and the overlay error value of the second test unit according to the data fitting results; Based on the comparison results of the overlay error values ​​of the first test unit and the second test unit, the uniformity of the process to be monitored is determined.

8. The test method for monitoring the process uniformity of the active region according to claim 7, characterized in that, The data fitting process based on N sets of the first reference data, to obtain the overlay error value of the first test unit according to the data fitting result, includes: In a Cartesian coordinate system, for the first test unit, N sets of the first reference data are denoted as coordinate points (Xm, Rxm) and (Xn, Rxn), where 2≤m≤n1, 2≤n≤n2, where Xm represents the offset of the first gate relative to the first active region along the first direction, Xn represents the offset of the first gate relative to the first active region along the second direction, Rxm represents the resistance of the region of the first active region along the first direction of the first gate when the first gate is offset relative to the first active region along the first direction, and Rxn represents the resistance of the region of the first active region along the second direction of the first gate when the first gate is offset relative to the first active region along the second direction. Based on the coordinate points of the first reference data, two fitted lines are obtained by linear fitting. The resistance symmetry point of the first active region is determined based on the two fitted straight lines, and the resistance symmetry point is used as the overlay error value of the first test unit.

9. The test method for monitoring the process uniformity of the active region according to claim 8, characterized in that, The step of determining the resistance symmetry point of the first active region based on the two fitted straight lines includes: The offset corresponding to the intersection of the two fitted straight lines is determined as the resistance symmetry point of the first active region.

10. The test method for monitoring the process uniformity of the active region according to claim 7, characterized in that, The determination of the uniformity of the process to be monitored based on the comparison result of the overlay error value of the first test unit and the overlay error value of the second test unit includes: When the overlay error value of the first test unit and the overlay error value of the second test unit are the same, the uniformity of the process to be monitored implemented in the second active region is good. When the overlay error value of the first test unit and the overlay error value of the second test unit are different, the uniformity of the process to be monitored implemented in the second active region is lacking.

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