Method and apparatus for carry chain delay tuning of field programmable gate arrays

Abstract

The application relates to a carry chain delay tuning method and device of a field programmable logic gate array, and belongs to the technical field of time-to-digital conversion. In view of the problem that the large time interval difference of each tap of the carry chain leads to poor linearity of measurement, a delay chain is constructed by cascading multiple-stage carry chain unit stages, the output of the previous stage is simultaneously guided to the first input end with a small delay and the second input end with a large delay of the next stage; calibration measurement is carried out by taking the full second delay path as an initial structure; according to the delay parameter, the input path of the time interval deviation over-limit tap is switched to the first delay path to form a mixed delay chain. The application improves the tap distribution uniformity by dynamically adjusting the path selection parameter and the multi-stage register output selection adjustment, and is mainly applied to a high-precision time-to-digital converter and a measurement test system.

Description

Technical Field

[0001] This invention relates to the field of measurement and testing technology, and specifically to a carry chain delay tuning method and apparatus for a field-programmable gate array with high linearity. Background Technology

[0002] A time-to-digital converter (TDC) is a core circuit that converts analog time interval signals into digital outputs. It has wide applications in chip testing systems, lidar ranging, high-energy physics experiments, medical imaging, and precision timing synchronization. With advancements in integrated circuit technology, implementing TDCs based on field-programmable gate arrays (FPGAs) has become an important technological approach. Compared to application-specific integrated circuit (ASIC) solutions, FPGAs offer advantages such as shorter development cycles, lower costs, and greater reconfigurability, making them widely used in various high-precision time measurement systems.

[0003] Currently, FPGA-based Time Control (TDC) designs mostly employ tapped delay line (TDL) structures. These structures form a fine time scale by cascading numerous logic units (such as carry chains or lookup tables), achieving sub-nanosecond or even picosecond time resolution using a two-stage measurement architecture combining coarse counting and fine interpolation. Inside the FPGA, the core physical carrier of the carry chain is the carry logic unit (such as the CARRY4 primitive in the AMD / Xilinx 7 series). Each carry logic unit contains multiple cascaded carry logic stages and has dedicated input / output ports. Adjacent carry logic units are directly connected via dedicated metal wiring in the vertical direction within the chip, forming a dedicated carry transmission channel with a delay of approximately tens of picoseconds. The path connecting to the data input terminal via a general interconnect matrix has a larger delay, approximately hundreds of picoseconds.

[0004] However, in actual FPGA hardware implementations, due to environmental factors such as semiconductor manufacturing process variations, on-chip voltage fluctuations, and temperature gradients, the propagation delay time of each basic delay unit constituting the delay chain is not entirely consistent. This physical non-ideal characteristic leads to significant differences in the time width of each tap in the delay chain, i.e., nonlinear error. This nonlinear error directly worsens the differential and integral nonlinearities of the delay chain (TDC), causing systematic deviations in the measurement results and severely limiting the overall measurement accuracy and stability of the system.

[0005] Existing tuning methods rely on the delay characteristics of the carry chain and select different carry logic unit output ports (such as CO0-CO3 or O0-O3 ports on CARRY4) for output selection adjustment based on calibration results. This method has the following limitations: First, the signal delays of each output port are not linear, or even monotonic, resulting in poor adjustment accuracy; second, this adjustment method is a local adjustment, and errors caused by excessively long or short delays in a certain stage of the carry chain will accumulate in the measurement results of the next stage of the carry chain, and will not change due to the current adjustment. After accumulating for several stages, the error may exceed the dynamic range of the output selection, making it theoretically impossible to calibrate to the ideal value. Summary of the Invention

[0006] The purpose of this invention is to address the aforementioned problems in the prior art by providing a carry chain delay tuning method and apparatus for field-programmable gate arrays. By constructing a hybrid carry chain structure, the method controls the dynamic switching of each carry chain unit between a short-delay dedicated path and a long-delay general path using path selection parameters. It uses a fully general path as the basic structure, selectively inserts dedicated paths as a coarse adjustment means, and supplements it with multi-level buffer output selection for local fine adjustment, so that the time interval of each tap tends to be uniform.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution: a carry chain delay tuning method for a field-programmable gate array, comprising:

[0008] A delay chain is constructed by cascading multiple carry chain units, where each carry chain unit has a first input terminal and a second input terminal. The output signal of the previous carry chain unit is simultaneously guided to the carry chain delay tuning first input terminal and the carry chain delay tuning second input terminal of the field-programmable gate array (FPGA) of the next carry chain unit. When the signal is transmitted through the carry chain delay tuning first input terminal of the FPGA, it passes through the first delay path with a smaller delay amount. When the signal is transmitted through the carry chain delay tuning second input terminal of the FPGA, it passes through the second delay path with a larger delay amount. The path selection parameter controls the current carry chain unit to select whether to transmit through the carry chain delay tuning first delay path or the carry chain delay tuning second delay path of the FPGA. Using a carry chain delay tuning second delay path where all carry chain units are field-programmable gate arrays as the initial structure, the delay parameters of each tap in the carry chain delay tuning delay chain of the field-programmable gate array are obtained by calibration measurement. Based on the carry chain delay tuning delay parameters of the field-programmable gate array (FPGA), by adjusting the carry chain delay tuning path selection parameters of the FPGA, the input path of the carry chain unit corresponding to the tap with a time interval deviation exceeding the preset range is switched from the second delay path of the carry chain delay tuning of the FPGA to the first delay path of the carry chain delay tuning of the FPGA, so as to form a hybrid delay chain structure including the first delay path and the second delay path.

[0009] Furthermore, it also includes an output selection adjustment step: The output signals of each carry chain unit are captured by the first-level register group and then passed to the second-level register group for buffering. Then, the output selection parameter selects the signal from the output of the second-level register group of the carry chain delay tuning of the field-programmable gate array and outputs it to the third-level register group. The signal in the third-level register group of the carry chain delay tuning of the field-programmable gate array is the tuned tap output.

[0010] Furthermore, the carry chain delay tuning first-level register group of the field-programmable gate array (FPGA) and the corresponding carry chain unit are located in the same basic logic array block; the carry chain delay tuning second-level register group of the FPGA is used to isolate the drive load of the carry chain delay tuning first-level register group of the FPGA; the carry chain delay tuning second-level register group and the carry chain delay tuning third-level register group of the FPGA have no layout position constraints.

[0011] Furthermore, the first delay path of the carry chain delay tuning of the field-programmable gate array is the path through which the carry chain cascaded signal is directly transmitted via dedicated wiring resources inside the chip, and the second delay path of the carry chain delay tuning of the field-programmable gate array is the path through which the signal is transmitted via a general interconnect matrix.

[0012] Furthermore, the carry chain delay tuning of the field-programmable gate array (FPGA) involves switching the input path based on the delay parameter, including a global optimization process: The initial state of the carry chain delay tuning delay chain of the field-programmable gate array is configured such that all carry chain units adopt the second delay path of the carry chain delay tuning of the field-programmable gate array. The first round of measurement and evaluation is conducted to identify carry chain units with adjacent tap intervals greater than the first threshold. By modifying the corresponding path selection parameters, a carry chain unit with a first delay path tuned by a field-programmable gate array is inserted in front of the carry chain unit, and the carry chain structure behind the node is logically shifted backward according to the path selection parameters. A second round of measurement and evaluation is performed to identify carry chain units where the interval between adjacent taps is less than the second threshold. By modifying the corresponding path selection parameters, a carry chain unit with a carry chain delay tuned to the first delay path using a field-programmable gate array is inserted after the carry chain unit.

[0013] Furthermore, the global optimization process for carry chain delay tuning of the field-programmable gate array also includes a dynamic verification step for each tap position: Check the absolute position deviation of each tap sequentially from low to high to see if it is within the preset error tolerance range; If the position deviation of the target tap is lower than the lower limit of the carry chain delay tuning error tolerance range of the field programmable gate array, then a carry chain unit of the first delay path using the carry chain delay tuning of the field programmable gate array is inserted after the carry chain unit corresponding to the target tap. If the position deviation of the target tap is higher than the upper limit of the carry chain delay tuning error tolerance range of the field programmable gate array, then delete the carry chain unit of the first delay path of the carry chain delay tuning field programmable gate array immediately following the carry chain unit corresponding to the target tap. After each adjustment, actual tests are conducted to verify the changes. If the nonlinearity of the measured delay interval is improved, the current modification is retained; otherwise, the current modification is withdrawn.

[0014] Furthermore, it also includes local optimization processes: After completing the global optimization, based on the output of the carry chain unit of the carry chain delay tuning second delay path using field-programmable gate array, the adjustment range of the output selection parameter is set to include the output of the current level carry chain unit and the output of at least one of the carry chain units of the carry chain delay tuning first delay path immediately following it. If the tap position deviation is lower than the preset fifth threshold, the output selection parameter is increased to search in the direction of the next stage output; if the tap position deviation is higher than the preset sixth threshold, the output selection parameter is decreased to search in the direction of the previous stage output. The search proceeds in a single direction until the position deviation of the carry chain delay tuning tap of the field-programmable gate array falls into the preset error range or reaches the adjustment boundary of the carry chain delay tuning output selection parameter of the field-programmable gate array, and then selects the output selection parameter that minimizes the absolute value of the position deviation.

[0015] Furthermore, the steps for carrying chain delay tuning calibration measurement of a field-programmable gate array include: The clock management module inside the field-programmable gate array is configured to phase-shift mode to generate a calibration signal that produces a fixed-time phase shift with each input clock. The carry-chain delay tuning calibration signal of the field-programmable gate array (FPGA) is dynamically switched between the carry-chain delay tuning calibration signal and the external measurement signal by a multiplexer, and the switched signal is input to the beginning of the carry-chain delay tuning delay chain of the FPGA.

[0016] A carry-chain delay tuning device for a field-programmable gate array includes: The hybrid carry chain module is formed by cascading multiple carry chain units. Each carry chain unit has a first input terminal and a second input terminal. The output signal of the previous carry chain unit is simultaneously guided to the carry chain delay tuning first input terminal and the carry chain delay tuning second input terminal of the field-programmable gate array (FPGA) of the next carry chain unit. When the signal is transmitted through the carry chain delay tuning first input terminal of the FPGA, it passes through the first delay path with a smaller delay. When the signal is transmitted through the carry chain delay tuning second input terminal of the FPGA, it passes through the second delay path with a larger delay. Each carry chain unit selects to transmit through the carry chain delay tuning first delay path or the carry chain delay tuning second delay path of the FPGA according to the path selection parameters. The calibration measurement module is used to calibrate and measure each tap in the carry chain delay tuning hybrid carry chain module of the field programmable gate array to obtain the delay parameters of each tap. The path tuning module is used to adjust the carry chain delay tuning path selection parameters of the field-programmable gate array (FPGA) according to the carry chain delay tuning delay parameters of the FPGA. This switches the input path of the carry chain unit corresponding to the tap with a time interval deviation exceeding a preset range from the second delay path of the carry chain delay tuning of the FPGA to the first delay path of the carry chain delay tuning of the FPGA, so that the carry chain delay tuning hybrid carry chain module of the FPGA forms a hybrid delay chain structure including the first delay path and the second delay path.

[0017] Furthermore, the output selection adjustment module includes a first-level register group, a second-level register group, and a third-level register group connected in sequence. The first-level register group of the carry chain delay tuning of the field-programmable gate array (FPGA) is used to capture the output signals of each carry chain unit. The second-level register group of the carry chain delay tuning of the FPGA is used to buffer the output of the first-level register group of the FPGA to isolate the driving load. The third-level register group of the FPGA is used to select the target tap signal as the final output from the output of the second-level register group of the FPGA according to the output selection parameters. The first-level register group of the FPGA and the corresponding carry chain unit are located in the same basic logic array block. The calibration signal source module includes a clock management unit configured in phase-shift mode and a multiplexer. The carry-chain delay-tuning clock management unit of the field-programmable gate array (FPGA) is used to generate a calibration signal with a fixed-time phase shift. The carry-chain delay-tuning multiplexer of the FPGA is used to dynamically switch between the carry-chain delay-tuning calibration signal of the FPGA and the external measurement signal before inputting it to the beginning of the carry-chain delay-tuning hybrid carry-chain module of the FPGA.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention constructs a hybrid delay chain structure that includes a first delay path and a second delay path. The second delay path with a larger delay is used as the basic skeleton, and the first delay path with a smaller delay is used as the main tuning means to dynamically insert or delete. This significantly expands the dynamic range of delay path tuning and fundamentally solves the problem of non-uniform tap delay in traditional single-type carry chain structures.

[0019] 2. This invention, by setting up an output selection adjustment module and employing a multi-level register buffer structure, finely selects the output signal of each tap, enabling the delay path to have local fine-tuning capabilities on the basis of global tuning. The first-level register group and the carry chain are located in the same basic logic unit to ensure low-jitter signal capture, and the introduction of the second-level register group effectively isolates the driving load of the capture register, avoiding adverse effects on the capture effect.

[0020] 3. This invention proposes an iterative calibration algorithm that first globally optimizes path selection parameters and then locally optimizes output selection parameters. In the global optimization phase, dynamic insertion or deletion of dedicated path carry chains ensures a uniform delay chain, while the local optimization phase achieves fine-tuning through a unidirectional search of output selection parameters. This algorithm effectively accelerates parameter optimization convergence, improves tuning efficiency, and enhances the final linearity index.

[0021] 4. The clock management module with built-in phase shift mode in this invention serves as a calibration signal source, which can generate a continuous signal with a fixed time phase shift. It can be dynamically switched with the external input signal through a multiplexer, providing an integrated precision signal reference for the iterative calibration of the carry chain without relying on an external dedicated signal source, thus reducing the system implementation cost and complexity. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the hybrid carry chain structure of the present invention; Figure 2 This is a flowchart of the hybrid carry chain tuning process of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings. Figure 1 This is a schematic diagram illustrating the principle of the hybrid carry chain structure of the present invention. Figure 2 This is a flowchart illustrating the hybrid carry chain tuning method of the present invention. The core concept of the present invention is to utilize the difference in delay magnitude between dedicated paths and general paths in the FPGA carry chain, and to achieve dynamic switching between the two delay effects in the same placement and routing operation through path selection parameters, thereby constructing a hybrid delay chain structure with relatively uniform tap spacing, and supplementing it with multi-level buffer output selection for local fine-tuning.

[0024] Taking the AMD 7 series FPGA as an example, the core physical carrier of the carry chain is the CARRY4 unit. Each CARRY4 unit contains four cascaded carry logic levels. Its input terminals include the cascaded signal port CI from the previous carry chain, the four-bit data input signal port DI[3:0], and the four-bit data selection signal port S[3:0]. When the data selection signal is logic '1', the signal enters from the output of the previous carry chain through the CI port; when the data selection signal is logic '0', the signal enters from the data input signal port DI[3:0]. The output terminals include the carry output signal port CO[3:0] and the four-bit sum output signal port O[3:0], which are transmitted to the next carry chain. Among them, the CI port of the next carry chain and the CO[3] port of the previous carry chain are directly connected through dedicated metal wiring in the vertical direction within the chip, forming a low-latency dedicated carry transmission channel (hereinafter referred to as the dedicated path), whose delay time is approximately on the order of tens of picoseconds. The O[3:0] or CO[3:0] ports are connected to the DI[3:0] ports via the chip’s internal universal interconnect matrix. The delay time is relatively large, on the order of hundreds of picoseconds (hereinafter referred to as the universal path). The specific value is related to the chip model. Moreover, the same chip model may vary in different chips or different positions of the same chip due to differences in temperature, voltage and process.

[0025] For ease of description, the delay time of the dedicated path is denoted as T2, and the delay time of the general path is denoted as T1, and T2... <T1。

[0026] Example 1 This embodiment provides a high-linearity FPGA carry chain delay tuning method, the specific steps of which are as follows: Step 1: Construct a hybrid carry chain structure like Figure 1 As shown, a delay chain is constructed by cascading multiple carry chain units. Each carry chain unit has a cascaded input terminal CI (i.e., the first input terminal) and a data input terminal DI (i.e., the second input terminal). When a signal is input through the cascaded input terminal CI, it is transmitted through dedicated metal wiring inside the chip and output through a dedicated path with a small delay; when a signal is input through the data input terminal DI, it is transmitted through a general interconnect matrix and output through a general path with a larger delay.

[0027] When constructing the interconnection structure, the carry output terminal CO[3] of the previous carry chain unit is simultaneously connected to the cascade input terminal CI and the data input terminal DI[0] (or DI[1]) of the next carry chain unit. In this way, at the position of the same carry chain unit, the selection of two delay paths can be achieved in the same layout and routing by means of the path selection parameter In_sel, according to the selection of the data selection signal S[0] (or S[1]). Specifically, when the path selection parameter In_sel is logic '0', the carry chain unit selects the general path (the signal enters from the DI port); when the path selection parameter In_sel is logic '1', the carry chain unit selects the dedicated path (the signal enters from the CI port). In this embodiment, the three high-order data selection signals S[1]-S[3] of the carry chain unit are all set to logic '1', indicating that all input signals come from the DI[0] or CI port, and the input signals of the DI[1]-DI[3] ports are disabled.

[0028] The output signals CO[3:0] of each carry chain unit are captured by register group A (i.e., the first-level register group) in the same SLICE structure. The signals in register group A are then buffered by register group B (i.e., the second-level register group) to isolate the driving load of register group A and avoid its impact on the capture effect. The output signals of register group B are selected by the output selection parameter Out_sel and buffered in register group C (i.e., the third-level register group). All register signals in register group C are arranged from low to high to obtain a binary signal arrangement with relatively uniform tap spacing. In terms of layout constraints, the carry chain unit and register group A must be located in the same SLICE to ensure that the output of the carry chain can take a dedicated path to register group A; register group B and register group C have no layout position constraints and can adopt flexible placement and routing strategies.

[0029] Step 2: Calibration Measurement and Global Path Tuning In this embodiment, the initial structure of the delay chain is that all carry chain units use a common path, that is, all path selection parameters In_sel=0. The initial value of the output selection parameter Out_sel is set to the CO[3] output of the Nth carry chain unit, that is, Out_sel=3+i×4 (i=0,1,...,N-1) corresponding to the i-th carry chain unit. For ease of description, i×4 in Out_sel will be omitted in the following.

[0030] The signal source used for calibration is a mixed-mode clock manager (MMCM) configured in phase-shifted mode. The MMCM is the clock generation module inside the FPGA. Phase-shifted mode generates a fixed-time phase shift with each input clock, approximately tens of picoseconds (related to the period of the phase-locked loop (VCO), e.g., Tvco / 56 in the 7 series). The MMCM's output signal and the external measurement signal are selected by a multiplexer and then fed into the input of the delay chain for calibration measurements.

[0031] Based on the operating frequency of the TDC module and the dedicated and general path delay times of the selected FPGA model, determine the number of taps N and the ideal tap time interval T0. The principle is to ensure that the tap time interval T0 is as close as possible to the sum of the dedicated path delay T2 and the general path delay T1, while also guaranteeing that T0 is divisible by the clock frequency cycle. Integer divisibility. Taking a clock frequency of 200MHz as an example, =5000ps, dedicated path delay T2 is approximately 40ps~50ps, general path delay T1 is approximately 400ps~500ps, and the sum of T1+T2 is approximately 440ps~550ps. Considering the above conditions, and selecting the number of taps N=11, the ideal tap interval is:

[0032] This value falls within the range of the sum of T1 and T2, satisfying the design principle. In this embodiment, T2=40ps is taken as a typical value for the dedicated path delay for threshold calculation. During actual tuning, parameter deviations are automatically corrected through iterative measurements.

[0033] The specific steps for global path tuning are as follows: First, a calibration measurement is performed to obtain the actual delay interval of each tap. The calibration measurement uses the code density test method: a calibration signal with a fixed phase shift step (approximately 17.86 ps) is generated using MMCM, and each delay interval is traversed sequentially. The number of measurement points falling within each tap interval is counted. The number of measurement points is proportional to the delay time of the tap interval, and the actual delay interval of each tap can be calculated accordingly. For carry chain units with a tap interval greater than (T0+T2), a dedicated path carry chain unit is inserted in front of the carry chain unit by changing the corresponding path selection parameter In_sel from '0' to '1'. Here, "inserting in front" means that after the placement and routing are completed, the control word is modified to switch the carry chain unit to a dedicated delay path, and the output of this tap is adjusted to the next carry chain unit using a general path. The subsequent dedicated path and general path carry chain structures are shifted backward as a whole. This step is repeated once.

[0034] Then, perform another calibration measurement. For carry chain units with tap intervals less than (T0-T2), insert a dedicated path carry chain unit after the current carry chain unit by modifying the path selection parameter In_sel. "Inserting after" here means switching the next carry chain unit using a general path to a dedicated path, shifting the entire subsequent carry chain structure to the next position. Repeat this step once.

[0035] Next, the absolute position deviation of each tap is checked sequentially from the least significant bit to the most significant bit to see if it falls within the range of [-T2, T2], i.e., the boundary of the error tolerance interval is the dedicated path delay time T2. If the position deviation of a tap is less than -T2, a dedicated path carry chain unit is inserted after that tap; if the position deviation is greater than T2, the dedicated path carry chain unit immediately following that tap is deleted (if it exists). After each adjustment, a practical test is performed to verify the change. If the measured interval improves, the change is retained; otherwise, it is revoked.

[0036] The complete process of the above global optimization is as follows: Figure 2 As shown, the calibration measurement, threshold judgment, path insertion / deletion, and actual measurement verification are formed in an iterative loop until the basic delay interval of all taps converges.

[0037] Step 3: Fine-tuning of local output After global path tuning is completed, local fine-tuning of output selection is performed. The local fine-tuning of each tap is based on the output of the general path carry chain unit, and the adjustment range includes the output of the corresponding general path carry chain unit and the output of the next adjacent dedicated path carry chain unit. For example, if the i-th tap corresponds to the i-th general path carry chain unit, and the general path carry chain unit is followed by m dedicated path carry chain units, then the candidate signal range for local fine-tuning includes the output of the i-th general path carry chain unit and the outputs of the m dedicated path carry chain units thereafter. The adjustment range of Out_sel is [0, 3+4×m] (where 4 is the number of carry logic levels contained in each carry chain unit, i.e., the four output ports CO[3:0]).

[0038] If the tap position deviation is less than -T2, the output selection parameter Out_sel is increased to select a candidate output signal in the direction of the subsequent tap; if the tap position deviation is greater than T2, the output selection parameter Out_sel is decreased to select a candidate output signal in the direction of the preceding tap. The search continues in a single direction until the position deviation falls within the preset error range [-T2, T2] or reaches the adjustment boundary of Out_sel, at which point the Out_sel parameter that minimizes the absolute value of the position deviation is selected.

[0039] The technical effectiveness is verified as follows: Table 1. Measurement results of carry chain 1

[0040] Path selection (In_sel) = 0b101011010110101010101110.

[0041] Table 2. Measurement results of carry chain 2

[0042] Path selection (In_sel) = 0b101010110101010101101011.

[0043] Table 3. Measurement results of carry chain 3

[0044] Path selection (In_sel) = 0b110110101101010111010111010111011.

[0045] Table 4. Measurement Results of Carry Chain 4

[0046] Path selection (In_sel) = 0b11011010101010110110010.

[0047] Tables 1 to 4 present the measurement results of the four carry chains before and after tuning using the code density method. The main frequency used in the experiment was 200MHz, the number of taps was 11, the VCO frequency of the MMCM was 1GHz, and the phase shift of each output was:

[0048] Each measurement group collected 11,200 points, covering approximately 40 passes of the entire carry chain. The experiment used the number of measurement points falling on each tap interval as the basis for the delay chain length; a higher number of measurement points indicated a longer delay for that tap interval. The table compares delays by tap width and tap position. The average unit delay of the untuned carry chain, calculated as the average of the measurement results of the first 10 taps in the four carry chains, is 407 ps (corresponding to an average of approximately 912 measurement counts). The ideal unit delay T0 of the tuned carry chain is 454.5 ps (corresponding to an ideal of approximately 1018 measurement counts).

[0049] The measurement results show that the differential and integral nonlinearity of each tap is significantly improved after adopting the carry chain tuning method proposed in this invention. Taking carry chain 1 as an example, the integral nonlinearity (INL) based on tap width decreased from 69.6% before tuning to 24.9% after tuning, and the integral nonlinearity based on tap position decreased from 182% before tuning to 20% after tuning. The INL (based on tap width) of carry chain 2 decreased from 80.7% to 33.7%, the INL of carry chain 3 decreased from 110.2% to 33.5%, and the INL of carry chain 4 decreased from 71.9% to 25.8%. The improvement in INL based on tap position is even more significant, with the four carry chains decreasing from 182%, 160%, 339%, and 121% to 20%, 36%, 20%, and 22%, respectively. The above data indicate that this invention effectively solves the problem of non-uniform carry chain delay and significantly improves the measurement linearity of TDC.

[0050] Example 2 The difference between this embodiment and Embodiment 1 lies in the specific implementation of the calibration signal source. In this embodiment, an external stable signal source is used instead of the internal phase shift signal of the MMCM. If the system has an external signal source capable of generating a fixed continuous phase shift (e.g., a high-precision delay line or an external phase-locked loop), this external signal can be directly input as the calibration signal to the delay chain. The external measurement signal and the external calibration signal are selected by a multiplexer and then enter the input of the carry chain. Except for the different calibration signal source, the remaining calibration measurement steps, global path tuning steps, and local output fine-tuning steps are the same as in Embodiment 1.

[0051] Example 3 This embodiment uses the AMD Ultrascale / Ultrascale+ series FPGA as an example to illustrate the implementation of the present invention on different FPGA models. In the Ultrascale / Ultrascale+ series, the CARRY8 unit replaces the CARRY4 unit. Each CARRY8 unit contains eight cascaded carry logic stages, and the port signal definitions and functions are similar to those of CARRY4. In this embodiment, the port correspondence of the path selection parameter In_sel needs to be adjusted according to the port characteristics of the specific CARRY8 model. Meanwhile, the delay times of the dedicated path and the general path vary depending on the process node (Ultrascale+ uses 16nm or more advanced processes), but the delay magnitude of the dedicated path is still significantly smaller than that of the general path (the former is approximately tens of picoseconds, and the latter is approximately hundreds of picoseconds). The algorithm framework for global path tuning and local output fine-tuning is consistent with that in Embodiment 1. Only the specific values ​​of the thresholds (T0+T2) and (T0-T2) need to be adjusted according to the actual delay parameters, and the adjustment range of the output selection parameter Out_sel needs to be redefined (each carry chain unit contains 8 carry logic stages, and the adjustment range is expanded accordingly). This embodiment demonstrates that the method of the present invention is not only applicable to AMD 7 series FPGA chips, but also to other brands and series of FPGA chips with carry chain structures.

[0052] Explanation of the attached drawings Figure 1 This is a schematic diagram illustrating the principle of the hybrid carry chain structure of the present invention. Figure 1 In this diagram, DI0-DI3 represent the data input terminals of the carry chain unit, CI represents the cascade input terminal, and S0-S3 represent the path selection signal terminals of the carry chain unit. Only the least significant bit S0 is used for path selection, while the three most significant bits S1-S3 are all set to logic '1'. CO0-CO3 are the output signal ports of the carry chain unit, captured by register group A. Register group A and the carry chain unit reside in the same SLICE. Register group B is a buffer register, and the signal in register group C is the final output signal. N is the number of taps in the delay chain, and M is the total number of carry chain units used.

[0053] Figure 2 This is a flowchart illustrating the hybrid carry chain tuning method of the present invention. Figure 2 As shown, the tuning process starts with the calibration signal input, and goes through two stages: global path tuning (including initialization, first round measurement, forward insertion, second round measurement, backward insertion, and dynamic verification of each tap) and local output fine-tuning (including unidirectional search and optimization of output selection parameters), and finally outputs a tuned uniform tap signal. Figure 2 In the text, In_sel represents the path selection parameter, and Out_sel represents the output selection parameter.

[0054] Definitions of terms In this specification, "dedicated path" refers to a path where signals are transmitted directly through dedicated metal wiring inside the FPGA chip (such as a dedicated vertical channel for carry chain cascaded signals), with a relatively small delay time, approximately on the order of tens of picoseconds. "General path" refers to a path where signals are transmitted through a general interconnect matrix inside the FPGA chip, with a relatively large delay time, approximately on the order of hundreds of picoseconds. The "path selection parameter" In_sel is a configuration parameter that controls whether each carry chain unit selects a dedicated or general path. The "output selection parameter" Out_sel is a configuration parameter that selects the final tap signal from the candidate output signals after multiple levels of buffering.

[0055] The parts of this invention not described in detail are prior art, therefore they are not described in detail here.

[0056] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0057] Although this document uses a considerable amount of technical terminology, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0058] This invention is not limited to the preferred embodiments described above. Anyone can derive other products in various forms under the guidance of this invention. However, regardless of any changes made to their shape or structure, any technical solution that is the same as or similar to this invention falls within the protection scope of this invention.

Claims

1. A carry chain delay tuning method for a field-programmable gate array, characterized in that, include: A delay chain is constructed by cascading multiple carry chain units, wherein each carry chain unit has a first input terminal and a second input terminal. The output signal of the previous carry chain unit is simultaneously guided to the first input terminal and the second input terminal of the next carry chain unit. When the signal is transmitted through the first input terminal, it passes through a first delay path with a smaller delay amount. When the signal is transmitted through the second input terminal, it passes through a second delay path with a larger delay amount. The current carry chain unit is controlled by the path selection parameter to select whether to transmit through the first delay path or the second delay path. Using the second delay path as the initial structure for all carry chain units, the delay parameters of each tap in the delay chain are calibrated and measured to obtain the delay parameters of each tap. Based on the delay parameter, by adjusting the path selection parameter, the input path of the carry chain unit corresponding to the tap whose actual delay interval between adjacent taps deviates from the preset ideal tap time interval by more than a preset range is switched from the second delay path to the first delay path, so as to form a hybrid delay chain structure including the first delay path and the second delay path.

2. The method according to claim 1, characterized in that, It also includes output selection adjustment steps: The output signals of each carry chain unit are captured by the first-level register group and then passed to the second-level register group for buffering. Then, the output selection parameter selects a signal from the output of the second-level register group and outputs it to the third-level register group. The signal in the third-level register group is the tuned tap output.

3. The method according to claim 2, characterized in that, The first-level register group and the corresponding carry chain unit are located in the same basic logic array block; the second-level register group is used to isolate the driving load of the first-level register group; the second-level register group and the third-level register group have no layout position constraints.

4. The method according to claim 1, characterized in that, The first delay path is the path through which the carry chain cascaded signal is directly transmitted via dedicated wiring resources inside the chip, and the second delay path is the path through which the signal is transmitted via a general interconnect matrix.

5. The method according to claim 1, characterized in that, The step of switching the input path of the carry chain unit from the second delay path to the first delay path by adjusting the path selection parameter according to the delay parameter includes a global optimization process: The initial state of the delay chain is configured such that all carry chain units use the second delay path; The first round of measurement and evaluation is conducted to identify carry chain units with adjacent tap intervals greater than the first threshold. By modifying the corresponding path selection parameters, a carry chain unit using the first delay path is inserted in front of the carry chain unit, and the carry chain structure behind the carry chain unit is logically shifted backward according to the extension of the path selection parameters. A second round of measurement and evaluation is performed to identify carry chain units where the interval between adjacent taps is less than the second threshold. By modifying the corresponding path selection parameters, a carry chain unit using the first delay path is inserted after the carry chain unit.

6. The method according to claim 5, characterized in that, The global optimization process also includes a dynamic verification step for each tap position: Check the absolute position deviation of each tap sequentially from low to high to see if it is within the preset error tolerance range; If the position deviation of the target tap is lower than the lower limit of the error tolerance range, then a carry chain unit using the first delay path is inserted after the carry chain unit corresponding to the target tap. If the position deviation of the target tap is higher than the upper limit of the error tolerance range, then delete the carry chain unit that is immediately adjacent to the carry chain unit corresponding to the target tap and uses the first delay path. After each adjustment, actual tests are conducted to verify the changes. If the nonlinearity of the measured delay interval is improved, the current modification is retained; otherwise, the current modification is withdrawn.

7. The method according to claim 2, characterized in that, It also includes local optimization processes: After completing the global optimization, based on the output of the carry chain unit using the second delay path, the adjustment range of the output selection parameter is set to include the output of the current level carry chain unit and the output of at least one of the next adjacent carry chain units using the first delay path. If the tap position deviation is lower than the preset fifth threshold, the output selection parameter is increased to search in the direction of the next stage output; if the tap position deviation is higher than the preset sixth threshold, the output selection parameter is decreased to search in the direction of the previous stage output. The search proceeds in a single direction until the tap position deviation falls within a preset error range or reaches the adjustment boundary of the output selection parameter, and then the output selection parameter that minimizes the absolute value of the position deviation is selected.

8. The method according to claim 1, characterized in that, The calibration measurement steps include: The clock management module inside the field-programmable gate array is configured to phase-shift mode to generate a calibration signal that produces a fixed-time phase shift with each input clock. The calibration signal and the external measurement signal are dynamically switched by a multiplexer, and the switched signal is input to the beginning of the delay chain.

9. A carry-chain delay tuning device for a field-programmable gate array, characterized in that, include: The hybrid carry chain module is formed by cascading multiple carry chain units. Each carry chain unit has a first input terminal and a second input terminal. The output signal of the previous carry chain unit is simultaneously guided to the first input terminal and the second input terminal of the next carry chain unit. When the signal is transmitted through the first input terminal, it passes through a first delay path with a smaller delay. When the signal is transmitted through the second input terminal, it passes through a second delay path with a larger delay. Each carry chain unit selects to transmit through the first delay path or the second delay path according to the path selection parameter. The calibration measurement module is used to perform calibration measurements on each tap in the hybrid carry chain module and obtain the delay parameters of each tap. The path tuning module is used to adjust the path selection parameters according to the delay parameters, and switch the input path of the carry chain unit corresponding to the tap whose actual delay interval between adjacent taps deviates from the preset ideal tap time interval by a preset range from the second delay path to the first delay path, so that the hybrid carry chain module forms a hybrid delay chain structure including the first delay path and the second delay path.

10. The apparatus according to claim 9, characterized in that, Also includes: The output selection and adjustment module includes a first-level register group, a second-level register group, and a third-level register group connected in sequence. The first-level register group is used to capture the output signals of each carry chain unit. The second-level register group is used to buffer the output of the first-level register group to isolate the driving load. The third-level register group is used to select the target tap signal from the output of the second-level register group as the final output according to the output selection parameters. The first-level register group and the corresponding carry chain unit are located in the same basic logic array block. The calibration signal source module includes a clock management unit configured in phase-shift mode and a multiplexer. The clock management unit is used to generate a calibration signal with a fixed time phase shift, and the multiplexer is used to dynamically switch between the calibration signal and an external measurement signal before inputting it to the beginning of the hybrid carry chain module.

Images