Subphylum resolution time measurement circuit and measurement instrument

Abstract

The application provides a sub-door resolution time measurement circuit and a measuring instrument, comprising an edge generator, a first delay chain, a second delay chain, two latch arrays and a quantization output unit. The edge generator generates a first jump signal and a second jump signal which are opposite to the initial output state and complementary to each other in response to a starting event of a signal to be measured. The first jump signal propagates in the first delay chain, and the second jump signal propagates in the second delay chain. When an ending event comes, the two latch arrays simultaneously latch the propagation states of the jump signals in the two delay chains. The quantization output unit calculates a quantization value corresponding to the signal to be measured according to the propagation signals recorded by the two latch arrays through the number of delay units. The application uses standard inverters as delay units to form a double delay chain structure, uses the inherent difference between rising edge signals and falling edge signals in CMOS units, indirectly divides the quantization size of a single delay unit, and realizes sub-door level resolution measurement.

Description

Technical Field

[0001] This application relates to the field of time measurement technology, and in particular to a time measurement circuit and measuring instrument with subgate resolution. Background Technology

[0002] Currently, time measurement circuits are widely used in fields such as autonomous driving LiDAR, time-of-flight ranging in consumer electronics, and timing testing within semiconductor chips. Their core function is to convert continuous time intervals into digital codes. Most mainstream time-to-digital converters (TD-SCDMA) employ delay chains composed of buffers or inverters, using triggers to latch the propagation state of signals within the delay chain to achieve time quantization. However, the minimum resolvable time interval of such circuits is limited by the propagation delay of a single delay unit, making it difficult to overcome the physical limitations of gate-level delay. Summary of the Invention

[0003] This application provides a subgate-resolution time measurement circuit and measuring instrument for achieving subgate-level time quantization accuracy.

[0004] In a first aspect, embodiments of this application provide a time measurement circuit with sub-gate resolution, comprising: An edge generator is used to respond to the start event of the signal under test, generating a first transition signal and a second transition signal that is logically complementary to the first transition signal; The first delay chain is composed of multiple standard inverters connected in series as the first delay unit, and is used to propagate the first transition signal. The second delay chain is composed of multiple standard inverters connected in series as second delay units, used to propagate the second transition signal, wherein the transition direction of the first transition signal is opposite to that of the second transition signal; Two latch arrays are respectively connected to the output terminals of each delay unit in the first delay chain and the output terminals of each delay unit in the second delay chain, and are used to latch the first output state of each delay unit in the first delay chain and the second output state of each delay unit in the second delay chain in response to the end event of the signal under test. The quantization output unit is used to determine the first propagation level accumulated in the first delay chain and the second propagation level accumulated in the second delay chain of the signal under test according to the first output state and the second output state, respectively, and to calculate the quantization value corresponding to the signal under test according to the first propagation level and the second propagation level.

[0005] In some embodiments, the initial logic state of the output terminals of each delay unit in the first delay chain is preset to a first alternating sequence, and the initial logic state of the output terminals of each delay unit in the second delay chain is preset to a second alternating sequence. The second alternating sequence is logically opposite to the first alternating sequence.

[0006] In some embodiments, when the quantization output unit determines the first propagation level accumulated in the first delay chain and the second propagation level accumulated in the second delay chain based on the first output state and the second output state, respectively, it specifically performs the following: The first output state is compared bit by bit with the first alternating sequence to determine the number of bits in which the state changes and use it as the first propagation level. The second output state is compared bit by bit with the second alternating sequence to determine the number of bits in which the state changes, which is then used as the second propagation level.

[0007] In some embodiments, after the first transition signal is input from the first delay unit of the first delay chain, the corresponding edge type is flipped once after passing through each first delay unit, so that the odd-numbered first delay units propagate the same type of edge, the even-numbered first delay units propagate the same type of edge, and the edge types propagated by the odd-numbered and even-numbered first delay units are opposite. After the second transition signal is input from the first second delay unit of the second delay chain, the corresponding edge type is flipped once after passing through each second delay unit, so that the edge type of the odd-numbered second delay unit is opposite to the edge type of the odd-numbered first delay unit, and the edge type of the even-numbered second delay unit is opposite to the edge type of the even-numbered first delay unit.

[0008] In some embodiments, when the quantization output unit calculates the quantization value corresponding to the signal under test based on the first propagation level and the second propagation level, it is specifically used for: Based on the first propagation level and the propagation delay of the first delay unit for the rising and falling edges, calculate the first delay range of the signal under test propagating in the first delay chain; Based on the second propagation level and the propagation delay of the rising and falling edges of the second delay unit, calculate the second delay range of the signal under test propagating in the second delay chain; The overlapping interval between the first delay range and the second delay range is selected, and the quantization value of the signal under test is determined based on the overlapping interval.

[0009] In some embodiments, determining the quantization value of the signal under test based on the overlapping interval includes: Take the median value of the overlapping interval as the estimated delay value of the signal under test; or, The lower or upper limit of the overlapping interval is taken as the delay estimate of the signal under test.

[0010] In some embodiments, the edge generator includes: a first data trigger, a first inverter, and a second inverter. The data input terminal of the data trigger is connected to the output terminal of the first inverter. The non-inverting output terminal of the data trigger is connected to the input terminal of the first inverter and the input terminal of the first delay unit in the first delay chain, respectively. The inverting output terminal of the data trigger is connected to the input terminal of the first delay unit in the second delay chain. The clock control terminal of the data trigger and the input terminal of the second inverter are both used to receive the signal under test. The output terminal of the second inverter is connected to the latch control terminals of two latch arrays, respectively. When the start event of the signal under test arrives, the clock control terminal of the first data flip-flop is triggered, the non-inverting output terminal of the first data flip-flop outputs a first transition signal that jumps from a first logic level to a second logic level, and the inverting output terminal of the first data flip-flop outputs a second transition signal that jumps from a second logic level to a first logic level; the first transition signal is inverted by the first inverter and fed back to the data input terminal of the first data flip-flop, causing the logic level of the data input terminal of the first data flip-flop to flip, preparing for the next trigger; When the end event of the signal under test arrives, the end event is inverted by the second inverter and simultaneously provided as a clock signal to the latch control terminals of the two latch arrays, triggering the latch operation.

[0011] In some embodiments, both latch arrays are composed of multiple latch units, each latch unit having a data input terminal, a clock control terminal, and an output terminal; In the latch array connected to the first delay chain, the data input terminal of each latch unit is connected to the output terminal of the first delay unit of the corresponding level; in the latch array connected to the second delay chain, the data input terminal of each latch unit is connected to the output terminal of the second delay unit of the corresponding level. The clock control terminals of all latching units receive the end event of the signal under test or the inverted signal of the end event, so as to simultaneously latch the current output state of each delay unit in the first delay chain and the second delay chain when the end event occurs.

[0012] Secondly, embodiments of this application provide a measuring instrument that performs time measurement on the signal under test based on a subgate resolution time measurement circuit as described in any one of the embodiments of this application.

[0013] This application provides a subgate resolution time measurement circuit, which includes: an edge generator, a first delay chain, a second delay chain, two latch arrays, and a quantization output unit; the edge generator is used to generate a first transition signal and a second transition signal logically complementary to the first transition signal in response to the start event of the signal under test; the first delay chain is composed of multiple first delay units connected in series and is used to propagate the first transition signal; the second delay chain is composed of multiple second delay units connected in series and is used to propagate the second transition signal, wherein the transition directions of the first transition signal and the second transition signal are opposite; two latch arrays... The circuit consists of two interconnected units, each connected to the output of a delay unit in the first delay chain and the second delay chain. The first unit latches the first output state of each delay unit in the first delay chain and the second output state of each delay unit in the second delay chain in response to the end event of the signal under test. The quantization output unit determines the first propagation level accumulated in the first delay chain and the second propagation level accumulated in the second delay chain based on the first and second output states, respectively. It then calculates the quantization value of the signal under test based on the first and second propagation levels. In this circuit, an edge generator generates a first and a second transition signal with complementary logic and opposite transition directions, which are injected into the first and second delay chains (composed of cascaded delay units) for propagation. Because CMOS delay units have inherent physical differences in the propagation delay of rising and falling edges, the propagation processes of their respective transition signals differ within the same time interval. After the end event triggers the latch array to simultaneously latch the output states of the two delay chains, the quantization output unit determines the cumulative propagation levels of the two delay chains based on the first and second output states, and then uses the difference between the two levels to quantize the time interval. This invention transforms the difference in propagation delay of rising and falling edges from an error source into a physical processing method for quantization subdivision. It indirectly achieves subgate-level time measurement with a resolution smaller than that of a single delay unit using a standard inverter, improving time measurement accuracy while maintaining a simple circuit structure and low resource overhead. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A schematic block diagram of a subgate resolution time measurement circuit provided for an embodiment of this application; Figure 2This is a circuit diagram of a subgate resolution time measurement circuit provided in an embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described below with reference to the accompanying drawings.

[0017] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0018] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] It should be understood that in this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0020] Time measurement circuits are widely used in fields such as autonomous driving LiDAR, time-of-flight ranging in consumer electronics, and timing testing within semiconductor chips. Their core function is to convert continuous time intervals into digital codes. Currently, most mainstream time-to-digital converters (TD-SCDMA) employ delay chains composed of buffers or inverters, using triggers to latch the propagation state of the signal within the delay chain to achieve time quantization. The basic principle is as follows: the starting edge of the time interval to be measured is injected into the delay chain; the signal propagates sequentially along the chain; the ending edge triggers triggers a trigger to latch the output state of each delay unit; and the quantized value of the time interval is calculated by statistically analyzing the number of stages the signal has traveled through in the delay chain.

[0021] However, the minimum resolvable time interval, i.e., the time measurement resolution, of such circuits directly depends on the propagation delay of a single delay unit. In standard CMOS technology, a single buffer is typically composed of two cascaded inverters, whose propagation delay is the sum of the rising edge delay and the falling edge delay. Due to the physical characteristics of semiconductor devices, this delay cannot be reduced indefinitely, resulting in the time measurement resolution of traditional delay chain structures being limited by the physical bottleneck of gate-level delay, making it difficult to achieve sub-gate-level accuracy measurements.

[0022] To address the aforementioned resolution bottleneck, the vernier delay chain method has been proposed in existing technologies. This method employs two delay chains, each with slightly different delay units. The small difference between the delay units of the two chains is used as the equivalent resolution, thereby achieving subgate-level measurement. However, the vernier method has significant limitations: firstly, it requires the design of a large number of delay units of varying sizes, resulting in high complexity in circuit design and layout; secondly, to achieve a sufficiently small equivalent resolution, the delay difference between the two chains must be extremely small, severely limiting the dynamic range of a single measurement; and thirdly, the introduction of dedicated delay units increases chip area and power consumption, hindering large-scale integration and cost control.

[0023] Furthermore, in CMOS circuits, there is an inherent difference in the propagation delay between the rising and falling edges, a physical phenomenon caused by the difference in carrier mobility between PMOS and NMOS transistors. In traditional delay chain designs, this difference is typically considered an error source that needs to be compensated for or eliminated, and its impact on measurement accuracy is reduced by adjusting the device size ratio or adding additional correction circuitry. There is currently no publicly available solution to actively utilize this inherent physical difference as a means to improve time measurement resolution.

[0024] To address the aforementioned technical problems, this application provides a subgate resolution time measurement circuit and measuring instrument.

[0025] Please see Figure 1 , Figure 1This is a schematic block diagram of a subgate resolution time measurement circuit provided in an embodiment of this application. Figure 1 As shown, the subgate resolution time measurement circuit 100 includes: an edge generator 11, a first delay chain 12, a second delay chain 13, two latch arrays 14, and a quantization output unit 15.

[0026] Edge generator 11 is used to respond to the start event of the signal under test and generate a first transition signal and a second transition signal that is logically complementary to the first transition signal.

[0027] For example, the signal under test is a pulse signal carrying time interval information, and its start event can be the rising edge or falling edge of the signal under test. The first transition signal and the second transition signal have the same transition time in the time domain, but the transition direction is opposite: when the first transition signal is a rising edge transitioning from low level to high level, the second transition signal is a falling edge transitioning from high level to low level; and vice versa.

[0028] Edge generator 11 ensures that the first transition signal and the second transition signal have strictly synchronized transition times and completely complementary logical relationships, providing a unified starting reference for the symmetrical propagation and differential accumulation of signals in the subsequent two delay chains.

[0029] The first delay chain 12 is composed of multiple first delay units connected in series and is used to propagate the first transition signal.

[0030] For example, the first delay chain 12 is composed of multiple first delay units connected in series, and is used to propagate the first transition signal.

[0031] The first delay unit is a circuit unit with signal delay function. It can be implemented using a CMOS standard inverter, or using a buffer, transmission gate, or other logic gate circuit with a deterministic propagation delay. Existing electronic components and corresponding circuit variations that can replace this application in implementing the same operating principle are all within the scope of protection of this application. Multiple first delay units are cascaded sequentially, with the output of the previous first delay unit connected to the input of the next first delay unit, forming a multi-stage series delay link.

[0032] The first transition signal is injected from the input of the first delay unit of the first delay chain 12 and propagates sequentially along the first delay chain 12. Since CMOS delay units have different propagation delays for rising and falling edges, the edge type of the first transition signal flips once after passing through each first delay unit; that is, a rising edge becomes a falling edge after propagation through an inverter, and a falling edge becomes a rising edge after propagation through an inverter. Therefore, if the first transition signal is a falling edge when injected, the odd-numbered first delay units propagate the falling edge, and the even-numbered first delay units propagate the rising edge; if the first transition signal is a rising edge when injected, the situation is reversed.

[0033] The output terminals of the first delay units at each stage of the first delay chain 12 are tapped and connected to the subsequent latch array 14 to capture the instantaneous output state of each delay unit when the end event occurs. The number of delay unit stages in the first delay chain 12 is determined according to the maximum range of the time interval to be measured, ensuring that the propagation stages of the first transition signal within the maximum time interval to be measured do not exceed the total number of stages of the delay chain.

[0034] The second delay chain 13 is composed of multiple second delay units connected in series and is used to propagate the second transition signal. The transition direction of the first transition signal is opposite to that of the second transition signal.

[0035] The second delay unit is implemented using the same type of circuit unit as the first delay unit to ensure that the two delay chains have comparable and separable delay characteristics. Multiple second delay units are cascaded sequentially to form a second delay chain 13 that is symmetrical to the first delay chain 12. Preferably, the second delay chain 13 has the same number of stages and the same delay unit type as the first delay chain 12 to simplify subsequent quantization calculations.

[0036] The second transition signal is injected from the input of the first second delay unit of the second delay chain 13 and propagates sequentially along the second delay chain 13. Since the transition direction of the second transition signal is opposite to that of the first transition signal, under the condition that both delay chains use the same type of delay unit, the edge type of each delay unit in the second delay chain 13 is opposite to the edge type of the corresponding delay unit in the first delay chain 12. For example, when a first delay unit in the first delay chain 12 propagates a falling edge, a second delay unit of the same level in the second delay chain 13 propagates a rising edge; and vice versa.

[0037] This symmetrical, opposite edge configuration results in different accumulations of propagation processes for the first delay chain 12 and the second delay chain 13 during the same measurement time interval. Since the propagation delay of a falling edge is typically shorter than that of a rising edge, the delay chain with more falling edges can accumulate more propagation levels within the same time frame. This difference in propagation levels, caused by the inherent physical characteristics of CMOS devices, forms the physical basis for subsequent subgate-level time quantization.

[0038] The output terminals of the second delay units at each stage of the second delay chain 13 are also led out with taps and connected to the corresponding latch array 14 so as to perform state latching simultaneously with the first delay chain 12.

[0039] Two latch arrays 14 are respectively connected to the output terminals of each delay unit in the first delay chain 12 and the output terminals of each delay unit in the second delay chain 13. They are used to respond to the end event of the signal under test, latch the first output state of each delay unit in the first delay chain 12, and simultaneously latch the second output state of each delay unit in the second delay chain 13.

[0040] For example, the two latch arrays 14 are respectively connected to the output terminals of each delay unit in the first delay chain 12 and the output terminals of each delay unit in the second delay chain 13, and are used to latch the first output state of each delay unit in the first delay chain 12 and the second output state of each delay unit in the second delay chain 13 in response to the end event of the signal under test.

[0041] Each latch array 14 consists of multiple latch units, the number of which matches the number of delay stages in the corresponding delay chain. Each latch unit has a data input, a clock control input, and an output. In the latch array 14 connected to the first delay chain 12, the data input of the k-th latch unit is connected one-to-one with the output of the k-th first delay unit, used to receive the current output logic level of the first delay unit at that stage. In the latch array 14 connected to the second delay chain 13, the data input of the k-th latch unit is connected one-to-one with the output of the k-th second delay unit. The latch unit can be implemented using a D flip-flop, or it can be implemented using a latch or other circuit units with state retention function.

[0042] The clock control terminals of all latch units receive the end event of the signal under test or its inverted signal to ensure strict synchronization of the triggering time. When the end event of the signal under test arrives, the end event or its inverted signal simultaneously acts on the clock control terminals of all latch units. All latch units sample and latch the logic level on their data input terminals at the same time, thereby simultaneously capturing the instantaneous output state of each delay unit in the first delay chain 12 and the second delay chain 13.

[0043] After latching is completed, the latch array 14 corresponding to the first delay chain 12 outputs a first output state. The first output state is a sequence of multiple logic levels, reflecting the propagation leading edge position of the first transition signal in the first delay chain 12 and the output polarity of each delay unit. The latch array 14 corresponding to the second delay chain 13 outputs a second output state, which is also a sequence of logic levels, reflecting the propagation leading edge position of the second transition signal in the second delay chain 13.

[0044] Since the termination event triggers the latching of both delay chains simultaneously, the first output state and the second output state correspond to the instantaneous propagation of the two delay chains at the same moment, providing a synchronous sampling data basis for subsequent joint quantization using the difference in the propagation process of the two delay chains.

[0045] The quantization output unit 15 is used to determine the first propagation level accumulated by the first delay chain 12 and the second propagation level accumulated by the signal under test in the second delay chain 13 according to the first output state and the second output state, respectively, and to calculate the quantization value corresponding to the signal under test according to the first propagation level and the second propagation level.

[0046] The quantization output unit 15 is used to determine the first propagation level accumulated by the first delay chain 12 and the second propagation level accumulated by the signal under test in the second delay chain 13 according to the first output state and the second output state, respectively, and to calculate the quantization value corresponding to the signal under test according to the first propagation level and the second propagation level.

[0047] The first propagation stage refers to the number of delay unit stages that the first transition signal actually propagates through in the first delay chain 12 from the injection of the initial event into the first delay chain 12 until the latch is triggered by the end event. The definition of the second propagation stage is similar.

[0048] The first propagation stage can be determined by comparing the logic levels output by each latch unit in the first output state with its initial state. In the initial state, the outputs of each delay unit in the first delay chain 12 are preset to a first alternation sequence (e.g., 1, 0, 1, 0…). When the first transition signal propagates along the first delay chain 12, the output states of each delay unit that the signal passes through are sequentially flipped. By comparing the latched first output state with the first alternation sequence bit by bit, the number of bits that change state can be determined as the first propagation stage. Similarly, by comparing the second output state with a preset second alternation sequence bit by bit, the second propagation stage can be determined. The second alternation sequence and the first alternation sequence are logically inverses of each other.

[0049] After determining the first and second propagation levels, the quantization output unit 15 performs quantization calculations based on the propagation delay parameters of each delay unit. Specifically, given the propagation delay of the first delay unit for the rising edge and the propagation delay of the first delay unit for the falling edge, combined with the first propagation level and the edge type of each delay unit, the delay range of the first transition signal propagating in the first delay chain 12 can be determined. Similarly, the delay range of the second transition signal propagating in the second delay chain 13 can be determined. By taking the overlapping interval of the two delay ranges, the quantized value of the time interval to be measured can be limited to a range smaller than the complete propagation delay of a single delay unit.

[0050] The quantization value can be the middle, upper, or lower limit of the overlapping interval, or it can be corrected by combining preset calibration parameters. The quantization output unit 15 is also used to subtract the fixed delay error introduced by the signal path from the calculated quantization value. The fixed delay error includes, but is not limited to, the propagation delay introduced by the edge generator 11, signal wiring, and the end event triggering path.

[0051] Through the above quantization process, the quantization output unit 15 uses the difference in the propagation order in the two delay chains to divide the complete propagation delay of a single delay unit into multiple smaller quantization intervals, thereby outputting the quantized value of the test time interval with subgate resolution.

[0052] This application provides a subgate resolution time measurement circuit, which includes: an edge generator 11, a first delay chain 12, a second delay chain 13, two latch arrays 14, and a quantization output unit 15. The edge generator 11 is used to generate a first transition signal and a second transition signal logically complementary to the first transition signal in response to the start event of the signal under test. The first delay chain 12 is composed of multiple first delay units connected in series and is used to propagate the first transition signal. The second delay chain 13 is composed of multiple second delay units connected in series and is used to propagate the second transition signal. The transition directions of the first transition signal and the second transition signal are opposite. The two latch arrays 14... 4. Connected to the output terminals of each delay unit in the first delay chain 12 and the second delay chain 13 respectively, for responding to the end event of the signal under test, latching the first output state of each delay unit in the first delay chain 12, and simultaneously latching the second output state of each delay unit in the second delay chain 13; quantization output unit 15 is used to determine the first propagation level accumulated in the first delay chain 12 and the second propagation level accumulated in the second delay chain 13 according to the first and second output states, and calculate the quantization value corresponding to the signal under test according to the first and second propagation levels. In the above circuit, the edge generator 11 generates a first transition signal and a second transition signal with complementary logic and opposite transition directions, which are injected into the first delay chain 12 and the second delay chain 13, which are composed of delay units connected in series, for propagation. Because CMOS delay units have inherent physical differences in the propagation delay of rising and falling edges, the two delay chains have different propagation processes for their respective transition signals within the same time interval. After the end event triggers the latch array 14 to simultaneously latch the output states of the two delay chains, the quantization output unit 15 determines the cumulative propagation levels of the two delay chains based on the first and second output states, and then uses the difference between the two levels to quantize the time interval. This invention transforms the difference in propagation delay of rising and falling edges from an error source into a physical processing method for quantization subdivision. It indirectly achieves subgate-level time measurement with a resolution smaller than that of a single delay unit using a standard inverter, improving the accuracy of time measurement while maintaining a simple circuit structure and low resource overhead.

[0053] To more clearly illustrate the technical solution of this application, the technical solution of this application will be described below through specific embodiments. It should be noted that the specific embodiments are used to expand the description of the technical solution of this application, and are not intended to limit this application.

[0054] In some embodiments, the initial logic state of the output terminals of each delay unit in the first delay chain 12 is preset to a first alternation sequence, and the initial logic state of the output terminals of each delay unit in the second delay chain 13 is preset to a second alternation sequence. The second alternation sequence and the first alternation sequence are logically opposite to each other.

[0055] The first alternation sequence refers to a binary sequence consisting of alternating logic "1"s and logic "0"s. The first alternation sequence can be "1, 0, 1, 0, 1, 0…", meaning the output of the odd-numbered delay unit is preset to logic "1" and the output of the even-numbered delay unit is preset to logic "0"; or it can be "0, 1, 0, 1, 0, 1…", meaning the output of the odd-numbered delay unit is preset to logic "0" and the output of the even-numbered delay unit is preset to logic "1". The second alternation sequence is logically opposite to the first alternation sequence; that is, when the first alternation sequence is "1, 0, 1, 0…", the second alternation sequence is "0, 1, 0, 1…" and vice versa.

[0056] When the delay chain consists of inverters and D flip-flops connected in series alternately, the non-inverting output of each D flip-flop is connected to the input of the next-stage inverter, and the inverting output of each D flip-flop is connected to the data input of the next-stage D flip-flop. During the reset or initialization phase, by setting the initial state of the first-stage flip-flop, and utilizing the natural logical inversion relationship between the non-inverting and inverting outputs, an alternating sequence of initial logic states can be automatically formed throughout the entire delay chain.

[0057] By presetting the initial states of the outputs of the two delay chains to an inverted alternating sequence, a clear comparison benchmark is provided for subsequently determining the propagation stage. As the transition signal propagates along the delay chain, the logic state of the output of each delay unit flips from its initial state to the opposite state, while subsequent stages not reached by the signal remain unchanged. Therefore, by simply comparing the latched output state bit-by-bit with the preset alternating sequence, the position of the signal propagation leading edge can be determined quickly and accurately, eliminating the need for complex edge detection circuits or analog comparison circuits, thus reducing the circuit complexity of the quantization output unit 15. Simultaneously, the use of an inverted alternating sequence ensures that the responses of the two chains to the transition signal are logically completely symmetrical, avoiding system deviations introduced by asymmetry in the initial states.

[0058] In some embodiments, when the quantization output unit 15 determines the first propagation level accumulated by the first delay chain 12 and the second propagation level accumulated by the signal under test in the second delay chain 13 based on the first output state and the second output state, it specifically performs the following: comparing the first output state with the first alternation sequence bit by bit to determine the number of bits that have undergone state changes as the first propagation level; comparing the second output state with the second alternation sequence bit by bit to determine the number of bits that have undergone state changes as the second propagation level.

[0059] Bit-by-bit comparison refers to comparing each logic value in the first output state sequence of the latch array 14 with the corresponding logic value in the first alternation sequence. If the output state of a certain bit differs from its initial state, it indicates that the transition signal has propagated to the output of that delay unit, and the output states of that stage and all previous delay units have been flipped. Since the transition signal propagates continuously along the delay chain, the bits that undergo state changes must appear consecutively from the beginning of the sequence until the leading edge of the signal propagation. Therefore, by counting the number of bits that undergo consecutive state changes starting from the beginning of the sequence, the first propagation stage can be directly obtained.

[0060] Assuming the first alternation sequence is "1, 0, 1, 0, 1, 0, 1, 0...", and the first output state obtained by latching is "0, 1, 0, 1, 0, 1, 0, 0...", comparing each bit reveals that the first 7 bits are different from the initial state, while the 8th bit and thereafter remain in the initial state. Therefore, the first propagation level can be determined to be 7. Similarly, the second propagation level is determined in the same way.

[0061] Bit-by-bit comparison and counting operations can be implemented using digital logic circuits, such as an XOR gate array with a priority encoder, or executed in a processor via software algorithms. Since only simple logic comparisons and counting are involved, no complex interpolation operations or analog measurements are required, resulting in a fast quantization process with low power consumption.

[0062] This propagation order determination method transforms the measurement of time quantities into the counting of bits of digital logic state changes, all performed in the digital domain, thus avoiding the adverse effects of the non-ideals of analog domain signal processing on measurement accuracy. The bit-by-bit comparison operation is simple and reliable, not easily affected by noise, and maintains stable judgment accuracy even under conditions of varying process technology, voltage, and temperature.

[0063] In some embodiments, after the first transition signal is input from the first first delay unit of the first delay chain 12, the corresponding edge type is flipped once after passing through each first delay unit, such that the odd-numbered first delay units propagate the same type of edge, the even-numbered first delay units propagate the same type of edge, and the edge types propagated by the odd-numbered and even-numbered first delay units are opposite; after the second transition signal is input from the first second delay unit of the second delay chain 13, the corresponding edge type is flipped once after passing through each second delay unit, such that the edge type propagated by the odd-numbered second delay units is opposite to the edge type propagated by the odd-numbered first delay units, and the edge type propagated by the even-numbered second delay units is opposite to the edge type propagated by the even-numbered first delay units.

[0064] When inverters are used as delay units, the logic polarity of the output signal is opposite to that of the input signal after each inverter stage. Therefore, the transition edge type of the signal will inevitably flip: when the input is a rising edge, the output is a falling edge; when the input is a falling edge, the output is a rising edge. Since the first delay chain 12 is composed of multiple inverters connected in series, the edge type alternates between rising and falling edges as the first transition signal propagates along the chain stage by stage.

[0065] Furthermore, since the first and second transition signals have opposite transition directions (one is a rising edge and the other is a falling edge), the edge types of the injected signals are already opposite at the first-stage inputs of the two delay chains. After propagation through their respective first-stage inverters, the edge type at the first-stage output of the first delay chain 12 continues to be opposite to the edge type at the first-stage output of the second delay chain 13. Because both chains are composed of cascaded inverters of the same type, this opposite edge type relationship at corresponding levels is maintained in each delay unit.

[0066] This edge-flipping rule ensures that the two delay chains propagate opposite signal edges at corresponding levels, thus maximizing the inherent difference in rising and falling edge propagation delays of CMOS inverters in the difference in propagation progress between the two delay chains. Within the same measured time interval, the delay chain with faster-propagating edges accumulates more propagation stages, while the chain with slower-propagating edges accumulates fewer. The difference in propagation stages directly reflects the difference in rising and falling edge propagation delays. This design transforms the inherent physical characteristic differences of the device from an error source into a physical processing method for quantization subdivision. It indirectly achieves sub-gate-level time measurement with a resolution smaller than a single delay unit using a standard inverter, without requiring any additional calibration circuits or compensation algorithms, thus enabling sub-gate-level subdivision quantization of time intervals.

[0067] In some embodiments, when the quantization output unit 15 calculates the quantization value corresponding to the signal under test based on the first propagation level and the second propagation level, it is specifically used to: calculate the first delay range of the signal under test propagating in the first delay chain 12 based on the first propagation level and the propagation delay of the rising edge and falling edge by the first delay unit; calculate the second delay range of the signal under test propagating in the second delay chain 13 based on the second propagation level and the propagation delay of the rising edge and falling edge by the second delay unit; take the overlapping interval between the first delay range and the second delay range, and determine the quantization value of the signal under test based on the overlapping interval.

[0068] The first delay range is calculated as follows: Given that the propagation delay of the first delay unit for the rising edge is Tlh, and the propagation delay for the falling edge is Thl. Assuming the propagation stage of the first delay chain is Na, based on the edge-flipping rules, the number of rising and falling edges experienced by the first transition signal during propagation can be determined. The total delay TA of the first transition signal propagating in the first delay chain 12 satisfies: If the initial value of the first delay chain is "0", when Na is even, the output edge type of the Na-th stage propagation is rising edge, and the TA delay experiences (Na / 2) falling edges and rising edges respectively. The minimum value of the TA range is (Na / 2)×(Thl+Tlh), and the maximum value of the TA range is ((Na / 2+1)×Thl)+(Na / 2)×Tlh). When Na is odd, the output edge type of the Na-th stage propagation is falling edge, and the TA delay experiences ((Na+1) / 2) falling edges and ((Na-1) / 2) rising edges. The minimum value of the TA range is (((Na+1) / 2)×Thl)+((Na-1) / 2)×Tlh), and the maximum value of the TA range is (((Na+1) / 2)×(Tlh+Thl)).

[0069] If the initial value of the first delay chain is "1", when Na is even, the output edge type of the Na-th stage propagation is a falling edge, and the TA delay experiences (Na / 2) rising edges and falling edges respectively. The minimum value of the TA range is (Na / 2)×(Tlh+Thl), and the maximum value of the TA range is ((Na / 2+1)×Tlh)+(Na / 2)×Thl). When Na is odd, the output edge type of the Na-th stage propagation is a rising edge, and the TA delay experiences ((Na+1) / 2) rising edges and ((Na-1) / 2) falling edges. The minimum value of the TA range is ((Na+1) / 2)×Tlh+((Na-1) / 2)×Thl), and the maximum value of the TA range is (((Na+1) / 2)×(Tlh+Thl)). Similarly, based on the second propagation stage NB and the edge type of each stage, the range of the total delay TB of the second transition signal propagating in the second delay chain 13 can be determined, that is, the second delay range.

[0070] Since the two delay chains propagate the signal corresponding to the same measured time interval, both delay ranges should simultaneously contain the true value of the measured time interval. Therefore, by taking the intersection of the first and second delay ranges, a narrower overlapping interval than either individual delay range can be obtained, and the true value of the measured time interval must lie within this overlapping interval. The width of this overlapping interval is less than the complete propagation delay of a single delay unit, thus achieving subgate-level resolution.

[0071] This quantization method, through the joint constraint of two delay chains, compresses the estimation range of the time interval to be measured from the order of the complete propagation delay of a single delay unit to the order of the difference between the propagation delays of the rising and falling edges, achieving fine quantization of the time interval. Compared to the traditional single-chain delay chain structure where the quantization value can only determine "how many complete delay units have passed," this scheme can further determine a more precise position of the time interval within a single delay unit, improving the resolution of time measurement. This method only requires simple addition, subtraction, and comparison operations using the known propagation delay parameters of the delay units, without the need for complex iterative algorithms or high-precision analog circuits, making it easy to implement in digital circuits.

[0072] In some embodiments, determining the quantization value of the signal under test based on the overlapping interval includes: taking the median value of the overlapping interval as the delay estimate of the signal under test; or taking the lower limit or upper limit value of the overlapping interval as the delay estimate of the signal under test.

[0073] The median value of the overlapping interval is the arithmetic mean of the upper and lower limits of the intersection of the first and second delay ranges. Taking the median value as the delay estimate ensures that the maximum possible estimation error does not exceed half the width of the overlapping interval, and has the smallest mean square error in a statistical sense.

[0074] The lower or upper limit of the overlapping interval can also be used as a delay estimate. Taking the lower limit as the estimate is suitable for application scenarios where the measured value is relatively small, such as some timing detection scenarios that need to guarantee the minimum delay. Taking the upper limit as the estimate is suitable for application scenarios where the measured value is relatively large, such as distance measurement scenarios that need to guarantee the maximum delay coverage.

[0075] Furthermore, the quantization output unit 15 can also combine the median, upper limit, or lower limit of the overlapping interval with preset calibration parameters. These calibration parameters can be obtained through calibration measurements under known time intervals and are used to compensate for systematic errors introduced by factors such as process deviations and temperature drift.

[0076] This quantization method offers a variety of flexible strategies for determining quantization values, allowing users to select appropriate estimates based on the accuracy requirements and error tolerance characteristics of different application scenarios. The strategy of taking the median value provides optimal statistical accuracy in general applications; while the strategy of taking the upper or lower limit provides deterministic error boundaries for specific applications, ensuring that the measurement results meet the safety requirements in a specific direction. Furthermore, this quantization method involves only simple arithmetic operations, has low hardware implementation costs, and is suitable for cost- and power-sensitive integrated circuit designs.

[0077] In some embodiments, such as Figure 2As shown, the edge generator 11 includes: a first data flip-flop DFF0, a first inverter INV0, and a second inverter INV1. The data input terminal D of the first data flip-flop DFF0 is connected to the output terminal of the first inverter INV0. The non-inverting output terminal Q of the first data flip-flop DFF0 is connected to the input terminal of the first inverter INV0 and the input terminal of the first first delay unit INVa0 in the first delay chain 12. The inverting output terminal Q of the first data flip-flop DFF0 is connected to the input terminal of the first second delay unit INVb0 in the second delay chain 13. The clock control terminal of the first data flip-flop DFF0 and the input terminal of the second inverter INV1 are both used to input the signal under test. The output terminal of the second inverter INV1 is connected to the latch control terminals of the two latch arrays.

[0078] When the start event of the signal under test arrives, the clock control terminal of the first data flip-flop DFF0 is triggered. The non-inverting output Q of the first data flip-flop DFF0 outputs a first transition signal that jumps from the first logic level to the second logic level, and the inverting output Q of the first data flip-flop DFF0 outputs a second transition signal that jumps from the second logic level to the first logic level. The first transition signal is inverted by the first inverter INV0 and fed back to the data input D of the first data flip-flop DFF0, causing the logic level of the data input D of the first data flip-flop DFF0 to flip, preparing for the next trigger.

[0079] When the end event of the signal under test arrives, the end event is inverted by the second inverter INV1 and used as a clock signal to simultaneously provide to the latch control terminals of the two latch arrays 14, triggering the latch operation.

[0080] In the initial state, the data input terminal D of the first data flip-flop DFF0 is biased to logic "1". When the start event of the signal under test (e.g., rising edge) arrives at the clock control terminal of the first data flip-flop DFF0, the first data flip-flop DFF0 samples the logic "1" of the data input terminal D. The non-inverting output terminal Q jumps from logic "0" to logic "1", generating a rising edge as the first transition signal; the inverting output terminal Q NOT jumps from logic "1" to logic "0", generating a falling edge as the second transition signal. The first transition signal is injected into the first delay unit INVa0 of the first delay chain 12 to begin propagation, and is also inverted by the first inverter INV0 to become logic "0" and fed back to the data input terminal D, completing the state flip of the data input terminal D and ensuring that the first data flip-flop DFF0 can generate a transition signal in the opposite direction when the next start event arrives.

[0081] When the end event of the signal under test (e.g., falling edge) arrives, the end event is inverted by the second inverter INV1 and becomes a rising edge, which serves as a unified latch trigger clock. At the same time, it is provided to the clock control terminal of all latch units in the two latch arrays 14, triggering a global latch operation.

[0082] This edge generator 11 achieves two functions simultaneously through a simple structure of one D flip-flop and two inverters. First, utilizing the non-natural logical complementarity of the non-inverting and inverting outputs Q of the D flip-flop, it generates two transition signals with opposite directions from a single signal under test. These two signals share the same trigger clock, ensuring strict synchronization of transition times and avoiding additional time deviations introduced by signal path asymmetry. Second, the first inverter INV0 inverts the Q-terminal output signal and feeds it back to the D-terminal input, forming a self-latching loop. This allows the logic level at the D-terminal input to automatically flip after each trigger, enabling continuous operation without an additional reset control signal. Furthermore, the end event is inverted by the second inverter INV1 and then uniformly triggered for latching, ensuring the compatibility of the latch trigger edge with the signal propagation polarity in the delay chain.

[0083] In some embodiments, such as Figure 2 As shown, the first delay chain 12 is used to receive and propagate the first transition signal. The first delay chain 12 is composed of multiple first delay units connected in series. The first delay chain 12 is composed of an even number of standard inverters INVa0, INVa1, ... INVan and a corresponding number of D flip-flops DFFa0, DFFa1, ... DFFan connected alternately. When the first transition signal propagates step by step along the first delay chain 12, the signal edge type flips once after passing through each first delay unit.

[0084] The second delay chain 13 is used to receive and propagate the second transition signal. The second delay chain 13 is composed of multiple second delay units connected in series. The second delay chain 13 consists of an even number of standard inverters INVb0, INVb1, ..., INVbn and a corresponding number of D flip-flops DFFb0, DFFb1, ..., DFFbn connected alternately. As the second transition signal propagates step-by-step along the second delay chain 13, the signal edge type flips once after each second delay unit.

[0085] Because the transition directions of the first transition signal and the second transition signal are opposite, the edge type of the odd-numbered first delay unit in the first delay chain 12 is opposite to the edge type of the odd-numbered second delay unit in the second delay chain 13, and the edge type of the even-numbered first delay unit in the first delay chain 12 is opposite to the edge type of the even-numbered second delay unit in the second delay chain 13.

[0086] Specifically, when the first transition signal is a rising edge, this rising edge enters the first first delay unit INVa0, and after being inverted by INVa0, it becomes a falling edge at its output; this falling edge enters the second first delay unit INVa1, and after being inverted by INVa1, it becomes a rising edge at its output; and so on. Therefore, in the first delay chain 12, the odd-numbered first delay units INVa0, INVa2, INVa4... propagate and output falling edges, while the even-numbered first delay units INVa1, INVa3, INVa5... propagate and output rising edges.

[0087] Meanwhile, the second transition signal is a falling edge. This falling edge enters the first second delay unit INVb0, and after being inverted by INVb0, it becomes a rising edge at its output. This rising edge enters the second second delay unit INVb1, and after being inverted by INVb1, it becomes a falling edge at its output. Therefore, in the second delay chain 13, the odd-numbered second delay units INVb0, INVb2, INVb4... propagate and output rising edges, while the even-numbered second delay units INVb1, INVb3, INVb5... propagate and output falling edges.

[0088] Therefore, when the first transition signal is a rising edge, the edge type (falling edge) of the output from the odd-numbered delay unit in the first delay chain 12 is opposite to the edge type (rising edge) of the output from the odd-numbered delay unit in the second delay chain 13; the edge types (rising edge / falling edge relationship reversed) of the output from the even-numbered delay units in the first delay chain 12 and the second delay chain 13 also remain opposite. In CMOS circuits, the propagation speed of a falling edge is faster than that of a rising edge. Therefore, within the same measured time interval, the delay chain that propagates more falling edges will accumulate more propagation stages, resulting in a difference in the propagation process between the two chains.

[0089] This propagation mechanism receives signals with opposite transition directions through two delay links, consistently propagating opposite signal edges at corresponding levels. This maximizes the inherent difference in propagation delay between rising and falling edges of CMOS inverters by reflecting it in the difference in propagation processes between the two links. This design transforms the inherent physical characteristic differences of the device from an error source into a physical processing method for quantization subdivision, achieving subgate-level time measurement with a resolution smaller than that of a single delay unit. Subgate-level subdivision quantization can be achieved without any additional calibration circuitry or special delay units. Furthermore, this mechanism relies solely on the signal inversion characteristics of standard inverters, resulting in a well-structured circuit that is fully compatible with standard CMOS processes. In one specific embodiment, the first delay chain 12 consists of 10 standard CMOS inverters INVa0, INVa1, ..., INVa9 connected in series, and the second delay chain 13 consists of 10 standard CMOS inverters INVb0, INVb1, ..., INVb9 connected in series. The propagation delay Thl of the falling edge of the inverter output is set to 10 ps, ​​and the propagation delay Tlh of the rising edge is set to 18 ps.

[0090] In the initial state, the non-inverting output Q of the first data flip-flop DFF0 outputs logic "0", and the inverting output Q not outputs logic "1". The outputs of each delay unit in the first delay chain 12 are preset to the first alternating sequence "1, 0, 1, 0, 1, 0, 1, 0, 1, 0", meaning the initial latching result of D flip-flops DFFa0~DFFa9 is 1010101010. The outputs of each delay unit in the second delay chain 13 are preset to the second alternating sequence "0, 1, 0, 1, 0, 1, 0, 1, 0, 1", meaning the initial latching result of D flip-flops DFFb0~DFFb9 is 0101010101. The second alternating sequence is logically inverse of the first alternating sequence.

[0091] The time interval of the signal under test is set to 50 ps. This signal is simultaneously connected to the clock control terminal of the first data flip-flop DFF0 and the input terminal of the second inverter INV1. After being inverted by the second inverter INV1, the signal under test serves as the clock trigger signal for each D flip-flop in delay chain A and delay chain B. The fixed delay introduced by this path is Tlh = 18 ps. Therefore, the actual measured signal width is 50 ps + 18 ps = 68 ps. This fixed delay can be eliminated in subsequent calculations.

[0092] When the start event (rising edge) of the signal under test arrives, the clock control terminal of the first data flip-flop DFF0 is triggered. DFF0 samples the initial logic "1" of its data input terminal D, and the non-inverting output terminal Q jumps from logic "0" to logic "1", generating a rising edge as the first transition signal, which is injected into the first inverter INVa0 of the first delay chain 12; the inverting output terminal Q NOT jumps from logic "1" to logic "0", generating a falling edge as the second transition signal, which is injected into the first inverter INVb0 of the second delay chain 13.

[0093] The first transition signal (rising edge) enters INVa0, is inverted by INVa0, and becomes a falling edge at the output of INVa0 (delay Thl = 10ps); after entering INVa1, it is inverted by INVa1 and becomes a rising edge at the output of INVa1 (delay Tlh = 18ps); and so on. In the first delay chain 12, the odd-numbered inverters INVa0, INVa2, INVa4, INVa6, and INVa8 propagate falling edges, while the even-numbered inverters INVa1, INVa3, INVa5, INVa7, and INVa9 propagate rising edges.

[0094] The second transition signal (falling edge) enters INVb0, is inverted by INVb0, and becomes a rising edge at the output of INVb0 (delay Tlh = 18ps); after entering INVb1, it is inverted by INVb1 and becomes a falling edge at the output of INVb1 (delay Thl = 10ps); and so on. In the second delay chain 13, the odd-numbered inverters INVb0, INVb2, INVb4, INVb6, and INVb8 propagate rising edges, while the even-numbered inverters INVb1, INVb3, INVb5, INVb7, and INVb9 propagate falling edges.

[0095] When the end event (falling edge) of the signal under test arrives, the end event is inverted by the second inverter INV1 to generate a rising edge, which simultaneously acts on the clock control terminals of D flip-flops DFFa0~DFFa9 and DFFb0~DFFb9, triggering a global latch operation.

[0096] After latching, the output of the D flip-flops DFFa0~DFFa9 corresponding to the first delay chain 12 is 0101001010. Comparing this first output state bit by bit with the first alternating sequence 1010101010, the first 5 bits undergo state changes (bit 1 changes from 1 to 0, bit 2 from 0 to 1, bit 3 from 1 to 0, bit 4 from 0 to 1, bit 5 from 1 to 0), and the initial state is maintained from bit 6 onwards. Therefore, the first propagation stage NA = 5, meaning the first transition signal propagates through 5 inverters. According to the edge propagation law, the first 5 stages are INVa0 (falling edge, 10ps), INVa1 (rising edge, 18ps), INVa2 (falling edge, 10ps), INVa3 (rising edge, 18ps), and INVa4 (falling edge, 10ps), with a cumulative delay of 10 + 18 + 10 + 18 + 10 = 66ps.

[0097] The output of the D flip-flops DFFb0~DFFb9 corresponding to the second delay chain 13 is 1010010101. Comparing this second output state bit by bit with the second alternating sequence 0101010101, the first four bits show state changes, while the initial state is maintained from the fifth bit onwards. Therefore, the second propagation stage NB = 4, meaning the second transition signal propagates through four inverters. According to the edge propagation law, the first four stages are INVb0 (rising edge, 18ps), INVb1 (falling edge, 10ps), INVb2 (rising edge, 18ps), and INVb3 (falling edge, 10ps), with a cumulative delay of 18 + 10 + 18 + 10 = 56ps.

[0098] The first propagation stage NA = 5. The leading edge of signal propagation is located at the 5th stage inverter INVa4 (falling edge), indicating that the propagating signal has passed through INVa4, with a minimum cumulative delay of 66ps; and the propagating signal has not yet entered the next stage (INVa5), with a maximum cumulative delay of 66ps + 18ps = 84ps. Therefore, the first delay range of the signal under test propagating in the first delay chain 12 is [66ps, 84ps].

[0099] The second propagation stage NB = 4, and the signal propagation leading edge is located at the falling edge of the fourth stage inverter INVb3. Similarly, the minimum cumulative delay is 56ps, and the maximum cumulative delay is 56ps + 18ps = 74ps. Therefore, the second delay range of the signal under test propagating in the second delay chain 13 is [56ps, 74ps].

[0100] The overlap between the first delay range [66ps, 84ps] and the second delay range [56ps, 74ps] is taken to obtain [66ps, 74ps]. The width of this overlap range is 8ps, which is less than the propagation delay of the rising or falling edge of the inverter alone, thus achieving sub-gate-level time resolution.

[0101] Taking the midpoint of the overlapping interval as the delay estimate, we get (66ps + 74ps) / 2 = 70ps. Subtracting the fixed delay error of 18ps introduced by the second inverter INV1 from this estimate, we finally obtain the quantized value of the time interval to be measured as 70ps - 18ps = 52ps.

[0102] In this embodiment, the true value of the time interval to be measured is 50 ps, ​​and the measurement result of the circuit of the present invention is 52 ps, with a measurement error of 2 ps. This error is less than the propagation delay of a single inverter (18 ps or 10 ps), verifying the measurement capability of subgate-level time resolution. The achieved equivalent resolution is approximately equal to the difference between the rising edge delay and the falling edge delay (Tlh - Thl = 8 ps), which is less than the resolution of 10 ps (falling edge) or 18 ps (rising edge) that can be achieved by the traditional single-chain delay chain structure.

[0103] This application also provides a measuring instrument that performs time measurement on the signal under test based on a subgate resolution time measurement circuit as described in any of the embodiments of this application.

[0104] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time measurement circuit with sub-gate resolution, characterized in that, include: An edge generator is used to respond to the start event of the signal under test, generating a first transition signal and a second transition signal that is logically complementary to the first transition signal; The first delay chain is composed of multiple standard inverters connected in series as the first delay unit, and is used to propagate the first transition signal. The second delay chain is composed of multiple standard inverters connected in series as second delay units, used to propagate the second transition signal, wherein the transition direction of the first transition signal is opposite to that of the second transition signal; Two latch arrays are respectively connected to the output terminals of each delay unit in the first delay chain and the output terminals of each delay unit in the second delay chain, and are used to latch the first output state of each delay unit in the first delay chain and the second output state of each delay unit in the second delay chain in response to the end event of the signal under test. The quantization output unit is used to determine the first propagation level accumulated in the first delay chain and the second propagation level accumulated in the second delay chain of the signal under test according to the first output state and the second output state, respectively, and to calculate the quantization value corresponding to the signal under test according to the first propagation level and the second propagation level.

2. The subgate resolution time measurement circuit as described in claim 1, characterized in that, The initial logic state of the output terminals of each delay unit in the first delay chain is preset to a first alternating sequence, and the initial logic state of the output terminals of each delay unit in the second delay chain is preset to a second alternating sequence. The second alternating sequence and the first alternating sequence are logically opposite to each other.

3. The subgate resolution time measurement circuit as described in claim 2, characterized in that, When the quantization output unit determines the first propagation level accumulated in the first delay chain and the second propagation level accumulated in the second delay chain based on the first output state and the second output state, respectively, it specifically performs the following: The first output state is compared bit by bit with the first alternating sequence to determine the number of bits in which the state changes and use it as the first propagation level. The second output state is compared bit by bit with the second alternating sequence to determine the number of bits in which the state changes, which is then used as the second propagation level.

4. The subgate resolution time measurement circuit as described in claim 2, characterized in that, After the first transition signal is input from the first delay unit of the first delay chain, the corresponding edge type is flipped once after passing through each first delay unit, so that the odd-numbered first delay units propagate the same type of edge, the even-numbered first delay units propagate the same type of edge, and the edge types propagated by the odd-numbered and even-numbered first delay units are opposite. After the second transition signal is input from the first second delay unit of the second delay chain, the corresponding edge type is flipped once after passing through each second delay unit, so that the edge type of the odd-numbered second delay unit is opposite to the edge type of the odd-numbered first delay unit, and the edge type of the even-numbered second delay unit is opposite to the edge type of the even-numbered first delay unit.

5. The subgate resolution time measurement circuit as described in claim 2, characterized in that, When the quantization output unit calculates the quantization value corresponding to the signal under test based on the first propagation level and the second propagation level, it is specifically used for: Based on the first propagation level and the propagation delay of the first delay unit for the rising and falling edges, calculate the first delay range of the signal under test propagating in the first delay chain; Based on the second propagation level and the propagation delay of the rising and falling edges of the second delay unit, calculate the second delay range of the signal under test propagating in the second delay chain; The overlapping interval between the first delay range and the second delay range is selected, and the quantization value of the signal under test is determined based on the overlapping interval.

6. The subgate resolution time measurement circuit as described in claim 5, characterized in that, Determining the quantization value of the signal under test based on the overlapping interval includes: Take the median value of the overlapping interval as the estimated delay value of the signal under test; or, The lower or upper limit of the overlapping interval is taken as the delay estimate of the signal under test.

7. The subgate resolution time measurement circuit as described in claim 1, characterized in that, The edge generator includes: a first data trigger, a first inverter, and a second inverter. The data input terminal of the data trigger is connected to the output terminal of the first inverter. The non-inverting output terminal of the data trigger is connected to the input terminal of the first inverter and the input terminal of the first delay unit in the first delay chain. The inverting output terminal of the data trigger is connected to the input terminal of the first delay unit in the second delay chain. The clock control terminal of the data trigger and the input terminal of the second inverter are both connected to the signal under test. The output terminal of the second inverter is connected to the clock control terminals of two latch arrays. When the start event of the signal under test arrives, the clock control terminal of the first data flip-flop is triggered, the non-inverting output terminal of the first data flip-flop outputs the first transition signal that jumps from the first logic level to the second logic level, and the inverting output terminal of the first data flip-flop outputs the second transition signal that jumps from the second logic level to the first logic level; the first transition signal is inverted by the first inverter and fed back to the data input terminal of the first data flip-flop, causing the logic level of the data input terminal of the first data flip-flop to flip; When the end event of the signal under test arrives, the end event is inverted by the second inverter and simultaneously provided as a clock signal to the latch control terminals of the two latch arrays, triggering the latch operation.

8. The subgate resolution time measurement circuit as described in claim 1, characterized in that, Both latch arrays consist of multiple latch units, each latch unit having a data input terminal, a clock control terminal, and an output terminal; In the latch array connected to the first delay chain, the data input terminal of each latch unit is connected to the output terminal of the first delay unit of the corresponding level; in the latch array connected to the second delay chain, the data input terminal of each latch unit is connected to the output terminal of the second delay unit of the corresponding level. The clock control terminals of all latching units receive the end event of the signal under test or the inverted signal of the end event, so as to simultaneously latch the current output state of each delay unit in the first delay chain and the second delay chain when the end event occurs.

9. A measuring instrument, characterized in that, The measuring instrument measures the time of the signal under test based on the subgate resolution time measurement circuit as described in any one of claims 1-8.

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