Time calibration apparatus, method, electronic device and computer program product

Abstract

The application relates to a time calibration device, method, equipment, medium and product. The device comprises a control module, a management unit and a function module, the management unit comprises a first global time counter and a first latch register, the function module comprises a second global time counter, a second latch register and a compensation unit; the function module sends a test signal to the management unit, and the count value of the second global time counter of the function module is latched to the second latch register; the management unit receives the test signal, and the count value of the first global time counter is latched to the first latch register; the control module obtains a compensation value according to the difference between the count value of the first global time counter and the count value of the second global time counter, and writes the compensation value into the compensation unit; and the function module outputs a calibrated output count value. The technical scheme of the application can improve the precision of the output count value of the function module.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a time calibration device, method, electronic device, and computer program product. Background Technology

[0002] Modern System-on-Chips (SoCs), especially multi-port Ethernet Interconnects, Time-Sensitive Networking (TSN) switching chips, 5G fronthaul chips, and automotive Ethernet chips, commonly require a high-precision, synchronized Global Time Counter (GTC) to obtain accurate timing. This is particularly relevant for Intellectual Property (IP) modules such as Ethernet port inter-symbol interference (ISI), Peripheral Component Interconnect Express (PCIE), and sensor interfaces. For example, a GTC can be used for cross-IP event timestamping, IEEE 1588 Precision Time Protocol (PTP) pass-through clocking, boundary clocking, TSN scheduling, Audio Video Bridging (AVB) stream orchestration, and cross-port message delay measurement.

[0003] Currently, a GTC (Global Counter) is typically set up in a central module, such as the Management Unit (MU). Other functional modules, such as IP modules, read the GTC's count value from the MU via the on-chip bus. Because other functional modules need to queue and wait for the bus to become idle before reading the GTC's count value from the MU, the GTC count value obtained by other functional modules has a large error compared to the GTC count value of the Management Unit. Summary of the Invention

[0004] The technical problem solved by this application is the poor timing synchronization accuracy of the module within the chip. It provides a time calibration device, method, electronic device and computer program product, which can improve the accuracy of the output count value of the functional module.

[0005] According to a first aspect of the embodiments of this application, a time calibration device is provided, including a control module, a management unit, and a functional module. The management unit includes a first global time counter and a first latch register, and the functional module includes a second global time counter, a second latch register, and a compensation unit. The functional module is configured to send a test signal to the management unit upon receiving a time calibration command from the control module, and latch the count value of the second global time counter of the functional module into the second latch register. The management unit is configured to latch the count value of the first global time counter into the first latch register upon receiving the test signal. The control module is further configured to acquire the count value of the second global time counter of the functional module and the count value of the first global time counter, and acquire a compensation value based on the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module, and write the compensation value into the compensation unit. The functional module is further configured to acquire and output the calibrated output count value of the second global time counter of the functional module based on the count value of the second global time counter of the functional module and the compensation value.

[0006] The aforementioned time calibration device sets global time counters in both the management unit and the functional modules, eliminating the need for the functional modules to read the GTC count value from the management unit via the on-chip bus. Furthermore, during time calibration, a compensation value can be obtained based on the difference between the count value of the first global time counter and the count value of the second global time counter in the functional module. This compensation value is then written to the compensation unit, and the output count value of the functional module is calibrated using this compensation value, thus improving the accuracy of the functional module's output count value.

[0007] In one embodiment, the time calibration device further includes a common-source enable signal line, which connects the management unit and the functional module. The management unit is used to send an enable signal to the functional module through the common-source enable signal line when it receives an enable command from the control module. The enable command is used to start the first global time counter, and the enable signal is used to start the second global time counter.

[0008] In one embodiment, the time calibration device further includes a test trigger line, which connects the management unit and the functional module. The functional module is used to send a test signal to the management unit through the test trigger line when it receives a time calibration command from the control module. The physical traces of the common source enable signal line and the test trigger line are of equal length, and the difference between the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit is less than or equal to a first preset delay threshold.

[0009] In one implementation, the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module is the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit, and the compensation value is half of the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit.

[0010] In one embodiment, the management unit further includes a three-level trigger synchronization unit, and the first latch register and the three-level trigger synchronization unit are electrically connected. The functional module further includes a three-level trigger delay unit, and the second latch register and the three-level trigger delay unit are electrically connected. The three-level trigger synchronization unit and the three-level trigger delay unit have the same structure. The functional module is used to send a test signal to the management unit when it receives a time calibration command from the control module, and latch the count value of the second global time counter of the functional module into the second latch register. This includes: the functional module is used to generate an initial test signal when it receives a time calibration command from the control module, pass it through the three-level trigger delay unit, output the test signal to the management unit at the edge of the output signal of the three-level trigger delay unit, and latch the count value of the second global time counter of the functional module into the second latch register. The management unit is used to latch the count value of the first global time counter into the first latch register when it receives a test signal, including: the management unit is used to latch the count value of the first global time counter into the first latch register at the edge of the output signal of the three-level trigger synchronization unit when it receives a test signal.

[0011] In one implementation, both the first global time counter and the second global time counter operate in the target clock domain, which is a circuit region where all registers are uniformly driven by the global counting clock signal, which is generated by the management unit.

[0012] According to a second aspect of the embodiments of this application, a time calibration method is provided, applied to a time calibration device. The time calibration device includes a control module, a management unit, and a functional module. The management unit includes a first global time counter and a first latch register. The functional module includes a second global time counter, a second latch register, and a compensation unit. The time calibration method includes: upon receiving a time calibration command from the control module, the functional module sends a test signal to the management unit and latches the count value of the second global time counter of the functional module into the second latch register; upon receiving the test signal, the management unit latches the count value of the first global time counter into the first latch register; the control module acquires the count value of the second global time counter of the functional module and the count value of the first global time counter, and acquires a compensation value based on the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module, and writes the compensation value into the compensation unit; the functional module acquires and outputs the calibrated output count value of the second global time counter of the functional module based on the count value of the second global time counter of the functional module and the compensation value.

[0013] In one embodiment, the time calibration method further includes: the time calibration device further includes a common source enable signal line, the common source enable signal line is connected to the management unit and the functional module, and the time calibration method further includes: when the management unit receives an enable command issued by the control module, it sends an enable signal to the functional module through the common source enable signal line; wherein, the enable command is used to start the first global time counter counting, and the enable signal is used to start the second global time counter counting.

[0014] In one embodiment, the time calibration device further includes a test trigger line connected to the management unit and the functional module. Sending an enable signal to the functional module includes sending an enable signal to the functional module via a common-source enable signal line. Sending a test signal to the management unit includes sending a test signal to the functional module via the test trigger line. The physical traces of the common-source enable signal line and the physical traces of the test trigger line are of equal length, such that the difference between the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit is less than or equal to a first preset delay threshold.

[0015] In one implementation, the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module is the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit, and the compensation value is half of the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit.

[0016] In one embodiment, the management unit further includes a three-level trigger synchronization unit, and the functional module further includes a three-level trigger delay unit. The three-level trigger synchronization unit and the three-level trigger delay unit have the same structure. When the functional module receives a time calibration command from the control module, it sends a test signal to the management unit and latches the count value of the second global time counter of the functional module into a second latch register. This includes: when the functional module receives a time calibration command from the control module, it generates an initial test signal, passes it through the three-level trigger delay unit, outputs the test signal to the management unit at the edge of the output signal of the three-level trigger delay unit, and latches the count value of the second global time counter of the functional module into the second latch register. When the management unit receives the test signal, it latches the count value of the first global time counter into the first latch register. This includes: when the management unit receives the test signal, it passes it through the three-level trigger synchronization unit, and latches the count value of the first global time counter into the first latch register at the edge of the output signal of the three-level trigger synchronization unit.

[0017] In one implementation, both the first global time counter and the second global time counter operate in the target clock domain, which is a circuit region where all registers are uniformly driven by the global counting clock signal, which is generated by the management unit.

[0018] According to a third aspect of the embodiments of this application, an electronic device is provided, including a memory and a processor. The memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the above-described time calibration method.

[0019] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, can implement the above-described time calibration method.

[0020] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described time calibration method. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating a time calibration device according to an exemplary embodiment.

[0022] Figure 2 This is a flowchart illustrating a time calibration method according to an exemplary embodiment.

[0023] Figure 3 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0024] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.

[0025] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] An exemplary embodiment of this application also provides a time calibration device, which is disposed within a chip. For example... Figure 1 As shown, in this embodiment, the time calibration device includes a control module 110, a MU120, and a functional module 130. In some embodiments, the functional module 130 can be an IP module. In some embodiments, the functional module 130 can be a PCIe controller. In some embodiments, the functional module 130 can be an Ethernet interconnect port. For example, the IP module number can be IP0, ..., IPn, where n is a positive integer. The functional module 130 is any other functional unit within the chip besides the control module 110 and MU120 that has timing requirements. In this application, the function of the functional module is not specifically limited, that is, the role played by the functional module is not specifically limited. It can be understood that... Figure 1 Only one functional module 130 is shown in the figure. In some embodiments, the time calibration device may include more functional modules 130, which will not be described in detail here.

[0027] In some embodiments, MU120 includes a first global time counter 1201 and a first latch register 1202, and functional module 130 includes a second global time counter 1301, a second latch register 1302, and a compensation unit 1303. The first latch register 1202 and the second latch register 1302 can be read-only timestamp latch registers. The first global time counter 1201 within MU120 is a global reference time base. Each GTC can be 64 bits.

[0028] In some embodiments, all GTCs operate in the target clock domain, and the clock frequency of each GTC is the same as the counter bit width. The clock module inside the MU120 generates a global counting clock signal gtc_clk, which is distributed to each GTC via a clock tree network. The clock tree network is an internal metal wiring structure formed according to standard Clock Tree Synthesis (CTS). The target clock domain is the circuit area where all registers are uniformly driven by the global counting clock signal gtc_clk. The global counting clock signal gtc_clk serves as the operating clock, driving the GTCs to complete the accumulation timing.

[0029] In some embodiments, the time calibration device further includes a common-source enable signal line, which connects MU120 and functional module 130. MU120 is used to send an enable signal to functional module 130 through the common-source enable signal line when it receives an enable command from control module 110. The enable command is used to start the first global time counter 1201 to count, and the enable signal is used to start the second global time counter 1301 to count.

[0030] In some embodiments, when there is only one functional module 130, MU120 outputs an enable signal, i.e., a common-source enable signal gtc_en, to the GTC of functional module 130 via a single common-source enable signal line. The single common-source enable signal line connects from the output of MU to the enable terminal of the GTC of functional module 130. In some embodiments, when there is more than one functional module 130, MU120 outputs an enable signal, i.e., a common-source enable signal gtc_en, to the GTC of each functional module 130 via a tree-structured common-source enable signal line. In this application, the logic width of the common-source enable signal gtc_en is 1 bit. The tree-structured common-source enable signal line connects from the output of MU to the enable terminal of each GTC. The chip back-end physical design (PD) uses timing constraint commands (set_max_delay) to control the length of the physical traces of the common-source enable signal lines in the tree-structured topology. This ensures that the signal transmission delay from MU to each functional module 130 is consistent, and that the difference between the transmission delays of the enable signal from MU to each functional module 130 is less than or equal to a second preset delay threshold. This allows the second global time counter 1301 of each functional module 130 to start counting approximately synchronously after the common-source enable signal gtc_en is valid. The baseline accuracy of the common-source enable signal gtc_en in the tree-structured topology is determined by the target value set in the constraint command and the process capability.

[0031] In some embodiments, the time calibration device further includes a test trigger line connecting MU120 and functional module 130. When there is only one functional module 130, a test trigger line is connected between MU120 and functional module 130. In some embodiments, when there is more than one functional module 130, a test trigger line is connected between MU120 and each functional module 130. Functional module 130 is used to send a test signal gtc_ctrl_test to MU120 via the test trigger line upon receiving a time calibration command from control module 110. The logic width of the test signal gtc_ctrl_test is 1 bit. The physical traces of the test trigger lines are all controlled by the timing constraint command (set_max_delay) to ensure that the physical traces of each test trigger line are of equal length, so that the transmission delay of the test signal gtc_ctrl_test from each functional module 130 to MU120 is approximately equal. That is, the difference between the transmission delays of the test signal gtc_ctrl_test from each functional module 130 to MU120 is less than or equal to the second preset delay threshold.

[0032] In some embodiments, the physical traces of the common-source enable signal line and the test trigger line are of equal length. It can be understood that equal lengths of the physical traces of the common-source enable signal line and the test trigger line mean that the same timing constraint command (set_max_delay) is used for equal-length control on both the common-source enable signal line and the test trigger line, making their physical trace lengths approximately equal. This ensures that the transmission delay of the enable signal from MU120 to functional module 130 and the transmission delay of the test signal gtc_ctrl_test from functional module 130 to MU120 are approximately equal, i.e., the difference between the two transmission delays is less than or equal to a first preset delay threshold.

[0033] In some embodiments, functional module 130 is configured to send a test signal to MU120 upon receiving a time calibration command from control module 110, and latch the count value of the second global time counter 1301 of functional module 130 to the second latch register 1302. For example, during calibration, functional module 130 outputs a test signal gtc_ctrl_test to MU120 via the test trigger line from functional module 130 to MU120. Management unit 120 is configured to latch the count value of the first global time counter 1201 to the first latch register 1202 upon receiving the test signal. Control module 110 is further configured to acquire the count values ​​of the second global time counter 1301 and the first global time counter of functional module 130, calculate the difference between the count values ​​of the second global time counter 1301 and the first global time counter 1201, and write half of the difference to compensation unit 1303. Functional module 130 is also used to output the calibrated output count value of functional module 130 based on the count value of the second global time counter 1301 of functional module 130 and half of the difference.

[0034] In some embodiments, a preset buffer can be set instead of a standard cell library buffer along the propagation path of the common-source enable signal gtc_en and the test signal gtc_ctrl_test to reduce signal propagation delay and timing jitter. For example, the preset buffer can be set at the output of MU120 (i.e., the starting point of the propagation path of the common-source enable signal gtc_en and the ending point of the propagation path of the test signal gtc_ctrl_test), the starting point of the branch of the propagation path of the common-source enable signal gtc_en, and the input of the second global time counter 1301 of each functional module 130 (the ending point of the branch of the propagation path of the common-source enable signal gtc_en and the starting point of the propagation path of the test signal gtc_ctrl_test). Furthermore, compared with the standard cell library buffer, the preset buffer has lower propagation delay, higher drive current, and lower output impedance. The specific type, size, and topology of the preset buffer can be determined by the implementation process, and are not specifically limited in this embodiment.

[0035] In some embodiments, MU120 further includes a three-level flip-flop synchronization unit. The first latch register 1202 is electrically connected to the three-level flip-flop synchronization unit. The synchronization path of MU120 and each functional module 130 adopts a structurally symmetrical design.

[0036] The test signal gtc_ctrl_test is input to MU120 from functional module 130. After passing through the three-stage flip-flop synchronization unit, at the edge of the output signal of the three-stage flip-flop synchronization unit, the count value of the first global time counter 1201 of MU120 is latched into the first latch register 1202. The three-stage flip-flop synchronization unit operates in the target clock domain and is used to eliminate metastability caused by the asynchronous input of the test signal gtc_ctrl_test (i.e., the cross-module asynchronous signal).

[0037] In some embodiments, functional module 130 (i.e., the transmitting end) further includes a three-stage flip-flop delay unit. The second latch register 1302 and the three-stage flip-flop delay unit are electrically connected. The initial test signal generated inside functional module 130 first passes through the three-stage flip-flop delay unit. At the edge of the output signal of the three-stage flip-flop delay unit, the test signal gtc_ctrl_test is output to MU, and the count value of the second global time counter 1301 of functional module 130 is latched into the second latch register 1302. The three-stage flip-flop delay unit operates in the target clock domain and is used for edge shaping and time domain synchronization of the initial test signal.

[0038] The three-level flip-flop synchronization unit and the three-level flip-flop delay unit have the same structure. Functional module 130 and MU120 adopt the same number of levels (both two levels), the same flip-flop type, and the same reset behavior at the Register Transfer Level (RTL) layer. Timing constraints at the physical implementation layer ensure symmetrical routing, guaranteeing a bidirectional transmission path between MU120 and functional module 130 (i.e., the transmission path for the enable signal and the test signal), meaning the transmission delay from MU120 to functional module 130 and from functional module 130 to MU120 is equal. For example, the three-level flip-flop synchronization unit in this application can also be a three-level flip-flop synchronization unit or a multi-level flip-flop synchronization unit; the three-level flip-flop delay unit can also be a three-level flip-flop delay unit or a multi-level flip-flop delay unit, which will not be elaborated further here.

[0039] During the calculation of the transmission delay of the test signal gtc_ctrl_test between functional module 130 and MU120 (i.e., the calculation of the receive timestamp minus the send timestamp), the N-cycle delay of functional module 130 and the N-cycle synchronization delay of MU120 (N is a natural number greater than 0) cancel each other out. The final measurement error only includes the delay deviation caused by the incomplete symmetry of the physical traces (which can be controlled by the constraint command set_max_delay) and the ±1 gtc_clk clock cycle quantization error generated by discrete sampling.

[0040] In this embodiment, two-stage synchronization units are retained at the MU120 receiver to eliminate metastability caused by asynchronous cross-clock domain. An additional identical two-stage delay unit is added to the functional module 130 side, so that the internal link delay of the functional module 130 is equal to the synchronous link delay of the MU120. The inherent delays at both ends are canceled out. The difference in transmission delay of the test signal gtc_ctrl_test between the functional module 130 and MU120 only includes the delay deviation caused by the incomplete symmetry of the physical traces and the ±1 gtc_clk clock cycle quantization error generated by discrete sampling, which improves the accuracy of the calibrated output count value of the functional module.

[0041] In this embodiment, the latching operations of the second latch register 1302 of functional module 130 and the first latch register 1202 on the MU120 side are both completed in the same clock domain. Therefore, there is no sampling uncertainty error caused by asynchronous cross-domain between the two timestamps. Furthermore, the two timestamps are automatically latched only at the clock edge, without the need for software-triggered fetching, and there is no additional delay caused by software reading.

[0042] In some embodiments, the output of the second global time counter 1301 of the functional module 130 further includes an addition unit to implement global time calibration compensation. The difference between the count value of the first global time counter and the count value of the second global time counter of the functional module is the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit, and the compensation value is half of the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit.

[0043] For example, GTC_out = GTC_cnt + offset_reg. Here, GTC_out is the calibrated output count value of the second global time counter 1301 within functional module 130. GTC_cnt is the initial count value of the second global time counter 1301 within functional module 130. offset_reg is the compensation value, i.e., the value of the compensation unit 1303. The initial value of the compensation unit 1303 upon power-on is 0. The addition unit is used to add the initial count value and the compensation value of the second global time counter 1301 within functional module 130 to obtain the calibrated output count value of the second global time counter 1301 within functional module 130.

[0044] In this embodiment, the value of the second global time counter 1301 within the functional module 130 is not directly modified. Instead, a transparent addition is performed at the output of the second global time counter 1301 in the functional module 130. The internal counting of the second global time counter 1301 is always monotonically continuous without any jumps, fundamentally avoiding time regression or jumps caused by preload. Furthermore, for upper-layer applications, GTC_out is a calibrated global time base value, and the application code does not need to be aware of the calibration process.

[0045] Another embodiment of this application provides a time calibration method. This time calibration method can... Figure 1 The time calibration device includes a control module 110, a management unit 120, and a functional module 130. The management unit 120 includes a first global time counter 1201 and a first latch register 1202. The functional module 130 includes a second global time counter 1301, a second latch register 1302, and a compensation unit 1303. (See also...) Figure 2 The calibration method may include the following steps: In step S201, upon receiving a time calibration command from the control module, the functional module sends a test signal to the management unit and latches the count value of the second global time counter of the functional module into the second latch register.

[0046] In some embodiments, after the internal MU and functional modules of the time calibration device are initialized, the control module of the time calibration device writes an enable command to the MU. After receiving the enable command, the MU sends an enable signal gtc_en and controls the built-in GTC start count.

[0047] In some embodiments, the MU receives an enable command from the control module and sends an enable signal to the functional module. The enable command is used to start the first global time counter, and the enable signal is used to start the second global time counter. Since the physical traces of the common-source enable signal line cannot be made to be completely equal in length, the actual start time of the GTC, including the first and second global time counters, still has a deviation (deviation ≤ nanoseconds).

[0048] In some embodiments, the control module sends a time calibration command to the functional module, which is used to initiate the time synchronization calibration process between the MU and the functional module.

[0049] In some embodiments, the functional module (i.e., the transmitting end) generates an initial test signal, which passes through a three-stage trigger delay unit. At the edge of the output signal of the three-stage trigger delay unit, the test signal gtc_ctrl_test is output to MU, and the count value of the second global time counter of the functional module is latched into the second latch register for storage.

[0050] If the count value of the second global time counter of the functional module is T_ip_send_i, then T_ip_send_i = T - d1_i. Here, T is the absolute time of the test signal gtc_ctrl_test under the global reference time base of the first global time counter of the MU, and d1_i is the transmission delay of the common-source enable signal line from the MU to the functional module (i.e., the GTC of the MU counts d1_i earlier than the GTC of the functional module), which is the transmission delay of the enable signal from the MU to the functional module.

[0051] In step S202, when the management unit receives the test signal, it latches the count value of the first global time counter into the first latch register.

[0052] In some embodiments, after the MU receives the test signal gtc_ctrl_test, it passes through the three-level trigger synchronization unit. At the edge of the output signal of the three-level trigger synchronization unit, the count value of the MU's first global time counter is latched into the first latch register for storage.

[0053] For example, the count value of the first global time counter of MU is T_MU_recv_i. T_MU_recv_i = T + d2_i. Where T is the absolute time of the test signal gtc_ctrl_test under the global reference time base of the first global time counter of MU, and d2_i is the transmission delay of the test trigger line from the functional module to MU, that is, the transmission delay of the test signal from the functional module to MU.

[0054] In step S203, the control module obtains the count value of the second global time counter and the count value of the first global time counter of the functional module, calculates the difference between the count value of the second global time counter and the count value of the first global time counter, and writes the difference into the compensation unit.

[0055] In some embodiments, the difference between the count value of the second global time counter of the functional module and the count value of the first global time counter of the MU is delta_i. delta_i = T_MU_recv_i T_ip_send_i = d1_i + d2_i.

[0056] Where T_MU_recv_i is the count value of the first global time counter of MU, T_ip_send_i is the count value of the second global time counter of functional module, d1_i is the transmission delay of the common source enable signal line from MU to functional module, and d2_i is the transmission delay of the test trigger line from functional module to MU.

[0057] In some embodiments, half the difference between the count value of the second global time counter of the functional module and the count value of the first global time counter of the MU, i.e., delta_i / 2, can be written into the compensation unit as a transmission delay compensation value between the functional module and the MU.

[0058] In step S204, the functional module obtains and outputs the calibrated output count value of the second global time counter based on the count value and difference of the second global time counter of the functional module.

[0059] For example, GTC_out = GTC_cnt + offset_reg. Here, GTC_out is the calibrated output count value of the second global time counter of the functional module. GTC_cnt is the initial count value of the second global time counter of the functional module. offset_reg is the compensation value for the transmission delay of the test signal gtc_ctrl_test between the functional module and the MU, i.e., the value of the compensation unit. offset_reg = delta_i / 2. The compensation unit is used to store the compensation value for the transmission delay of the test signal gtc_ctrl_test between the functional module and the MU. The initial value of the compensation unit upon power-up is 0.

[0060] It is understood that the time calibration of the second global time counter for each functional module can be performed separately. In this embodiment, the order of the calibration process for the second global time counter of each functional module is not specifically limited.

[0061] In the above testing method, global time counters are set in both the management unit and the functional modules, so that the functional modules do not need to sequentially read the GTC count value in the management unit via the on-chip bus. Furthermore, during time calibration, half the difference between the count value of the first global time counter and the count value of the second global time counter in the functional module—that is, half the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit—is written as a compensation value to the compensation unit. This allows the functional module to output a calibrated output count value based on the compensation value, improving the accuracy of the functional module's output count value and enhancing the synchronization timing accuracy of the modules within the chip (including the management unit and all functional modules). Moreover, the three-stage flip-flop delay unit of the management unit has the same structure as the three-stage flip-flop synchronization unit of the functional module, ensuring that the hardware link delays of the transmission links on the MU side and the functional module side are canceled out.

[0062] The method and apparatus embodiments of this application can complement each other.

[0063] Embodiments of this application also provide an electronic device, including a processor and a memory; the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the time calibration method of any of the above embodiments.

[0064] Embodiments of this application also propose a computer-readable storage medium that, when an executable computer program in the storage medium is executed by a processor, enables the implementation of the time calibration method of any of the above embodiments.

[0065] Embodiments of this application also propose a computer program product, including a computer program that, when executed by a processor, implements the time calibration method of any of the above embodiments.

[0066] Regarding the apparatus in the above embodiments, the specific manner in which the processor performs the operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0067] Embodiments of this application also provide an electronic device 600, such as... Figure 3 As shown, the electronic device 600 includes a memory 601 and a processor 602. The memory 601 is used to store computer programs executable by the processor 602; the processor 602 is used to execute the computer programs in the memory 601 to implement the time calibration method provided in any of the above embodiments.

[0068] The electronic device 600 also includes a communication interface 603. The processor 602, memory 601, and communication interface 603 are connected via a communication bus and communicate with each other.

[0069] Processor 602 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0070] Communication interface 603 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0071] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0072] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0073] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A time calibration device, characterized in that, The time calibration device includes a control module, a management unit, and a functional module. The management unit includes a first global time counter and a first latch register. The functional module includes a second global time counter, a second latch register, and a compensation unit. The functional module is used to send a test signal to the management unit when it receives a time calibration command from the control module, and to latch the count value of the second global time counter of the functional module into the second latch register; The management unit is used to latch the count value of the first global time counter into the first latch register when the test signal is received. The control module is also used to obtain the count value of the second global time counter of the functional module and the count value of the first global time counter, and obtain a compensation value based on the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module, and write the compensation value into the compensation unit. The functional module is also used to obtain and output the calibrated output count value of the second global time counter of the functional module based on the count value of the second global time counter of the functional module and the compensation value; The time calibration device also includes a common source enable signal line, which connects the management unit and the functional module. The management unit is used to send an enable signal to the functional module through the common source enable signal line when it receives an enable command from the control module. The enable command is used to start the first global time counter counting, and the enable signal is used to start the second global time counter counting. The time calibration device further includes a test trigger line, which connects the management unit and the functional module. The functional module is used to send a test signal to the management unit through the test trigger line when it receives a time calibration command from the control module. Wherein, the physical traces of the common source enable signal line and the physical traces of the test trigger line are of equal length, and the difference between the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit is less than or equal to a first preset delay threshold. The difference between the count value of the first global time counter and the count value of the second global time counter of the functional module is the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit. The compensation value is half of the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit.

2. The time calibration device according to claim 1, characterized in that, The management unit further includes a three-level trigger synchronization unit, the first latch register and the three-level trigger synchronization unit are electrically connected, and the functional module further includes a three-level trigger delay unit, the second latch register and the three-level trigger delay unit are electrically connected, and the three-level trigger synchronization unit and the three-level trigger delay unit have the same structure; The functional module is used to generate an initial test signal when it receives a time calibration command from the control module, and output the test signal to the management unit at the edge of the output signal of the three-level trigger delay unit after passing through the three-level trigger delay unit, and latch the count value of the second global time counter of the functional module into the second latch register. The management unit is used to, upon receiving the test signal, latch the count value of the first global time counter into the first latch register at the edge of the output signal of the three-level trigger synchronization unit.

3. The time calibration device according to claim 1, characterized in that, Both the first global time counter and the second global time counter operate in the target clock domain, which is a circuit region where all registers are uniformly driven by the global counting clock signal, which is generated by the management unit.

4. A time calibration method, applied to a time calibration device, characterized in that, The time calibration device includes a control module, a management unit, and a functional module. The management unit includes a first global time counter and a first latch register. The functional module includes a second global time counter, a second latch register, and a compensation unit. The time calibration method includes: Upon receiving a time calibration command from the control module, the functional module sends a test signal to the management unit and latches the count value of the second global time counter of the functional module into the second latch register. Upon receiving the test signal, the management unit latches the count value of the first global time counter into the first latch register. The control module obtains the count value of the second global time counter of the functional module and the count value of the first global time counter, and obtains a compensation value based on the difference between the count value of the first global time counter and the count value of the second global time counter of the functional module, and writes the compensation value into the compensation unit. The functional module obtains and outputs the calibrated output count value of the second global time counter based on the count value of the second global time counter of the functional module and the compensation value; The time calibration device further includes a common-source enable signal line, which connects the management unit and the functional module. The time calibration method further includes: When the management unit receives an enable command from the control module, it sends an enable signal to the functional module through the common source enable signal line. The enable command is used to start the first global time counter counting, and the enable signal is used to start the second global time counter counting. The time calibration device also includes a test trigger line, which connects the management unit and the functional module. Sending a test signal to the management unit includes: A test signal is sent to the management unit via the test trigger line; Wherein, the physical traces of the common source enable signal line and the physical traces of the test trigger line are of equal length, and the difference between the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit is less than or equal to a first preset delay threshold. The difference between the count value of the first global time counter and the count value of the second global time counter of the functional module is the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit. The compensation value is half of the sum of the transmission delay of the enable signal from the management unit to the functional module and the transmission delay of the test signal from the functional module to the management unit.

5. The time calibration method according to claim 4, characterized in that, The management unit also includes a three-level trigger synchronization unit, and the functional module also includes a three-level trigger delay unit. The three-level trigger synchronization unit and the three-level trigger delay unit have the same structure. Upon receiving a time calibration command from the control module, the functional module sends a test signal to the management unit and latches the count value of its second global time counter into the second latch register, including: Upon receiving a time calibration command from the control module, the functional module generates an initial test signal, which is then passed through the three-stage trigger delay unit. At the edge of the output signal of the three-stage trigger delay unit, the test signal is output to the management unit, and the count value of the second global time counter of the functional module is latched into the second latch register. Upon receiving the test signal, the management unit latches the count value of the first global time counter into the first latch register, including: Upon receiving the test signal, the management unit, through the three-level trigger synchronization unit, latches the count value of the first global time counter into the first latch register at the edge of the output signal of the three-level trigger synchronization unit.

6. The time calibration method according to claim 4, characterized in that, Both the first global time counter and the second global time counter operate in the target clock domain, which is a circuit region where all registers are uniformly driven by the global counting clock signal, which is generated by the management unit.

7. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the time calibration method as described in any one of claims 4 to 6.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the time calibration method as described in any one of claims 4 to 6.

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