An aircraft dynamic stealth system based on explicit model predictive control and online adaptive modeling

Abstract

This invention discloses a dynamic stealth system and method for aircraft based on explicit model predictive control and online adaptive modeling. The system includes a front-end perception module, a threat assessment module, a heterogeneous computing module (FPGA+CPU), a distributed intelligent skin actuator array, and a flight control collaborative interface module. The FPGA embeds a piecewise affine function table and a hierarchical hybrid lookup structure obtained by pre-solving a multi-parameter planning problem for an electromagnetic-thermal coupled reduced-order state-space model. In the online phase, the FPGA performs reduced-order projection, hierarchical hybrid lookup, affine operations, and hardware-forced physical boundary constraint gating in hard real-time. Its worst-case execution time is a fixed constant determined by the tree depth and state dimension, which does not change with partition complexity. The CPU updates the system matrix online in an asynchronous background task through recursive least squares with a forgetting factor, and triggers recursive eigenorthogonal decomposition to update the reduced-order basis functions and background repartition calculation under the control of the update arbitration state machine. The system incorporates candidate model verification, double-buffered atomic switching, and hard constraint mechanisms for the output physical feasible region to ensure decoupling of model updates and real-time control timing. This invention solves two major bottlenecks in stealth control: the lack of deterministic upper bounds in real-time calculations and the difficulty in adapting physical models online. It has the advantages of hard real-time and high adaptability, and is suitable for various platforms with stringent requirements for hard real-time online adaptive control, such as aircraft, ships, ground vehicles, and industrial robots.

Description

Technical Field

[0001] This invention belongs to the field of aircraft stealth control and embedded heterogeneous computing technology, specifically relating to an aircraft dynamic adaptive stealth system, method and aircraft based on explicit model predictive control and online adaptive reduced-order model. Background Technology

[0002] In the modern battlefield environment, detection systems have evolved into comprehensive networks that integrate radar, infrared, and optical technologies across multiple spectrums, providing multi-layered coverage and unified coordination. Faced with this threat, existing aircraft stealth technologies primarily follow two technical paths, both of which have inherent bottlenecks when dealing with dynamic and uncertain environments.

[0003] The first category is static design based on fixed physical characteristics. Once the aircraft is manufactured, its physical characteristics cannot be dynamically adjusted according to the mission environment. For example, Chinese patent CN119764865A discloses a circularly polarized antenna based on a multi-mode frequency-selective surface. Its absorption, diffuse reflection, and other functional layers are frequency-domain separated and solidified in the physical structure, and once fabricated, the operating frequency band remains fixed. Another example is patent CN113094814B, which discloses a method for optimizing ship stealth performance. Its core is to allocate stealth indicators for each component through simulation calculations and statically optimize the shape or materials during the design phase. This type of design is severely inadequate in adapting to threats that continuously change throughout the entire mission profile.

[0004] The second category is data-driven component-level adaptive adjustment. While this approach can achieve a certain degree of dynamic response, it has fundamental limitations. First, it heavily relies on a large amount of historical data from specific operating conditions for training, resulting in insufficient generalization ability when facing unknown threat patterns outside the training set. Second, the decision-making logic is encapsulated in the "black box" neural network connection weights, lacking physical interpretability and making it difficult to pass security certification. Third, it typically targets only a single physical field or a single component, failing to achieve global collaborative optimization of electromagnetic-thermal-optical multi-physics coupling. For example, patent CN114859710B discloses a neural network-based stealth signal characteristic control method for aero-engines, but it relies on data-driven fitting of control parameters, lacks an interpretable electromagnetic-thermal coupling partial differential equation model, and uses a single-component PID controller, making it unable to handle multi-objective dynamic optimization problems of the entire aircraft online.

[0005] In recent years, dynamic stealth methods based on Model Predictive Control (MPC) have been proposed. These methods solve optimization problems under multiphysics coupling constraints online in a rolling time domain manner, theoretically achieving global dynamic optimization of stealth characteristics. However, existing MPC methods face two major bottlenecks in real-time airborne applications:

[0006] Bottleneck 1: Lack of determinism in real-time computation. Conventional MPC requires online iterative solving of nonlinear, nonconvex optimization problems, and its convergence time varies significantly with the condition number, failing to provide the upper bound of the worst-case execution time (WCET) required by hard real-time systems. This is unacceptable for safety-critical systems such as flight control.

[0007] Bottleneck 2: Core physical models are difficult to obtain and prone to mismatch. High-fidelity models describing the electromagnetic-thermal-optical multiphysics coupling characteristics of the aircraft surface have extremely high dimensionality, requiring the use of model reduction techniques to construct surrogate models for online application. However, offline-trained reduced-order state-space models cannot cover the fast time-varying and strongly nonlinear dynamics within the entire flight envelope. Especially in hypersonic flight, effects such as shock waves and plasma sheaths can introduce severe model mismatches, leading to decreased control performance or even instability.

[0008] Therefore, there is an urgent need for a dynamic stealth control system and method for aircraft that combines real-time determinism with online model adaptation capabilities. Summary of the Invention

[0009] Purpose of the invention

[0010] This invention aims to address two core technical problems in existing dynamic stealth control technologies: the lack of deterministic upper bounds in real-time computation and the difficulty in online adaptation of physical models. It provides a dynamic adaptive stealth system and method for aircraft based on explicit model predictive control and an online adaptive reduced-order model. An explicit MPC piecewise affine control law is constructed through offline multi-parameter programming, and continuous model evolution is achieved through online recursive least squares and recursive eigenorthogonal decomposition. Furthermore, a heterogeneous collaborative architecture of FPGA and CPU physically separates real-time control from model learning. Simultaneously, update arbitration, double-buffered atomic switching, and physical boundary constraint mechanisms are introduced to simultaneously meet the stringent requirements of hard real-time performance, high adaptability, and high reliability.

[0011] Technical solution

[0012] To achieve the above objectives, the present invention provides a dynamic adaptive stealth system for aircraft, the system comprising:

[0013] The front-end perception module is used to acquire environmental and threat situation information, surface temperature field distribution of the aircraft, near-field electromagnetic scattering data, and attitude motion parameters of the aircraft in real time.

[0014] The threat assessment module is used to dynamically generate radar stealth priority weights and infrared stealth priority weights based on the information obtained by the front-end perception module.

[0015] The heterogeneous computing module includes a field-programmable gate array (FPGA) and a central processing unit (CPU). The FPGA and CPU are connected through shared memory or a high-speed bus to form a heterogeneous computing architecture.

[0016] The distributed intelligent skin actuator array includes multiple reconfigurable frequency selective surface (FSS) units and phase change material microcavity units, which are used to respectively control the electromagnetic scattering characteristics and infrared radiation characteristics of the aircraft surface.

[0017] The flight control coordination interface module is used to communicate with the flight control system and send flight trajectory correction commands.

[0018] In the heterogeneous computing module:

[0019] The FPGA's memory contains the partition boundaries and affine coefficients of a piecewise affine function obtained by offline solution of an electromagnetically-thermal coupled initial reduced-order state-space model using a multi-parameter programming method with finite-time-domain constrained optimal control, as well as a hierarchical hybrid search structure for fast partition lookup. The cost function of the piecewise affine function is weighted by the priority weights generated by the threat assessment module. The first level of the hierarchical hybrid search structure uses some dominant mode coefficients of the reduced-order state vector to construct a coarse-grained KD-Tree to locate the candidate partition set, and the second level performs precise linear hyperplane discrimination within the candidate set.

[0020] Within each fixed control cycle, the FPGA is configured to execute the following hardware logic sequentially in hard real-time:

[0021] S21: Project the real-time sensor data into a reduced-order state vector through a fixed projection matrix;

[0022] S22: Use the hierarchical hybrid search structure to find the partition to which the reduced-order state vector belongs and read the corresponding gain matrix and bias vector. The single query latency of the hierarchical hybrid search structure is a fixed constant that depends only on the tree depth and state dimension and does not change with the increase of the partition complexity.

[0023] S23: Calculate affine control variables;

[0024] S24: The affine control quantity is constrained by a hardware-forced physical boundary gating logic and then output to the distributed intelligent skinned actuator array. The hardware-forced physical boundary gating logic forces the actuator to perform saturation limit constraints, rate of change constraints, and physical feasible domain boundaries derived from physical laws, corresponding to each physical field component in the reduced-order state vector.

[0025] S25: Store the current reduced state and the constrained control quantity into a shared first-in-first-out queue.

[0026] The CPU is configured to execute the following logic in a background task asynchronous with the FPGA hard real-time control process:

[0027] Historical state-control sequences are read from the shared first-in-first-out queue. A recursive least squares algorithm with a forgetting factor is used to update the system matrix and input matrix of the initial reduced-order state-space model online. The ratio of the prediction residual to the norm of the reduced-order state vector is monitored. When this ratio exceeds a preset threshold for multiple consecutive steps, a structural mismatch is determined, and a base update request flag is set. Upon receiving the base update request flag, an update arbitration state machine, based on preset base update cooldown constraints, repartition cooldown constraints, and the current CPU load conditions, decides whether to trigger the CPU to execute recursive intrinsic orthogonal decomposition to update the reduced-order basis functions, or to trigger background repartition computation. Before model switching, candidate models are backtracked for prediction verification using recently stored or offline historical state-control sequences. Backtracking prediction is performed on the candidate model constructed from the new basis functions, and its root mean square error (RMSE) is calculated. Switching is only allowed when the percentage reduction in the RMSE of the candidate model compared to the currently active model exceeds a preset improvement threshold. If the change in the basis functions is detected to exceed the preset threshold and the repartitioning cooldown condition is met, background repartitioning calculation is triggered to generate an updated piecewise affine function table and write it to the spare buffer. The piecewise affine function table contains multiple sets of affine coefficients corresponding to different threat priority weight combinations, and each set of affine coefficients is stored in a contiguous address space. In each fixed control cycle, the FPGA directly indexes and loads the corresponding set of affine coefficients by adding a preset offset to the base address, based on the current priority weight pattern generated by the threat assessment module.

[0028] A dual buffer is provided between the FPGA and the CPU to store the projection matrix and the piecewise affine function table, so as to realize the model update without timing interference in the real-time control process. After the CPU writes complete data to the backup buffer, it sets the switching ready flag. The FPGA is also configured to check the switching ready flag at a fixed phase at the beginning of each control cycle. If it is valid, it completes the atomic switch with the backup buffer within one clock cycle by exchanging the base address pointer, so as to introduce the updated model into the real-time control loop without disturbance, and realize zero timing interference of model update to real-time control. This atomic switch is implemented by the control logic embedded in the FPGA and completes the overall switch of the control law parameter set within one bus cycle.

[0029] Step S4: Flight trajectory coordination

[0030] When the trajectory correction command received by the flight control coordination interface module meets the preset flight safety boundary, the command is sent to the flight control system to achieve joint dynamic optimization of stealth performance and flight trajectory.

[0031] In a further technical solution, the system also includes a degraded working mode: when the response frequency of the distributed intelligent skin actuator array is detected to be lower than a preset threshold, or the background model update fails continuously, or the CPU load exceeds the safety threshold for multiple consecutive background cycles, the system automatically switches to a pre-stored static feature control mode library, matches the optimal preset control scheme according to the current threat situation, and ensures that the system still operates reliably when hardware performance is limited or the model is abnormal.

[0032] Beneficial effects

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. Real-time Determinism. Explicit MPC transforms online optimization into offline partitioning and online table lookup. The WCET (Warning-Critical-Time) of control computation can be strictly predetermined, determined by the tree depth and state dimension of the hierarchical hybrid lookup structure, independent of the condition number of the optimization problem. The single-lookup latency of the hierarchical hybrid lookup structure within the FPGA is a fixed constant dependent only on the tree depth and state dimension, remaining unchanged with increasing partition complexity. Combined with the FPGA's hard pipelined architecture, the latency from state projection to control output is fixed and can be precisely calculated, meeting the hard real-time requirements of flight control.

[0035] The design philosophy of the hierarchical hybrid lookup structure lies in the following: the first-level KD-Tree uses partial dominant modes for pruning, not for approximate searching, but strategically to construct a controllable candidate set for precise decision-making in the second level. This makes it possible for the second level to exhaustively verify all candidates, and the maximum size of this candidate set can be rigorously calculated offline. It is this "approximation for certainty" architecture design that completely transforms the online lookup latency from a complex function related to the total number of partitions into a pre-computable, fixed constant determined only by the depth of the first-level tree and the size of the maximum candidate set in the second level. This fundamentally changes the design paradigm of airborne optimization control systems, shifting the complexity of the online optimization problem from "runtime" to "design time," providing pre-verifiable real-time behavioral guarantees for safety-critical systems.

[0036] 2. Online Model Adaptation. A two-layer adaptive mechanism is employed: recursive least squares updates the reduced-order system matrix in each background cycle to track the slow time-varying characteristics of the flight state; when structural errors that cannot be compensated by the system matrix update occur, the recursive POD triggers incremental updates of the basis functions, enabling the reduced-order state-space model to continuously track fast time-varying and strongly nonlinear dynamics. The stability and reliability of the model update process are ensured through updating the arbitration state machine, backtracking verification of candidate models, and an exponential decay weight mechanism for new snapshots. The recursive least squares and recursive POD are not simply sequentially linked, but rather, under the scheduling of updating the arbitration state machine, form a dual-time-scale adaptive closed loop that combines "continuous tracking of slow time-varying parameters" with "discrete reconstruction of structural mutations," enabling the system to maintain its adaptive capability to both slow and fast time-varying dynamics across a broad flight envelope. This synergy effectively solves the fundamental problem that offline-trained models cannot cover the entire flight envelope.

[0037] 3. Hardware and software co-decoupling. Real-time control is independently completed by the FPGA hardware pipeline, while model updates and repartitioning are executed asynchronously in the background by the CPU, achieving complete decoupling in time and space. By introducing an update arbitration cooling mechanism and CPU load monitoring, the preemption of real-time control resources by background learning tasks is effectively prevented, ensuring that the determinism of control is not disturbed by the model learning process. The specific design of the hierarchical hybrid search structure and the double-buffered atomic switching mechanism jointly solves the technical problem that "online learning systems cannot provide hard real-time control determinism"—the hierarchical hybrid search structure solidifies the search latency to a constant that depends only on the tree depth and state dimension, so that WCET can always be strictly calculated and guaranteed in advance, regardless of how the offline model is updated online or how the partitioning structure changes; the double-buffered atomic switching mechanism allows the CPU to perform costly model depth updates asynchronously and non-real-time, while achieving zero-time-sequence interference to the FPGA real-time control task through atomic pointer swapping. The two complement each other, achieving synergistic efficiency in the intersection of control theory, machine learning, and hardware implementation. At the same time, it supports continuous online evolution of the model, realizing the intelligent control paradigm of "flying, learning, and optimizing simultaneously".

[0038] 4. Threat Adaptation and Multi-Spectrum Coordination. By dynamically generating time-varying priority weights for radar and infrared sensors and coordinating them with normalization in the cost function, the optimization problem is mathematically forced to achieve joint optimality of electromagnetic, thermal, and optical properties, effectively alleviating the performance conflicts caused by multi-field coupling in traditional solutions.

[0039] 5. Engineering Robustness and Boundary Adaptability. This invention inherently integrates a multi-layered robustness enhancement design, including an updated arbitration state machine and forced cooling mechanism, CPU load monitoring and task priority scheduling, dual-buffer atomic switching, hard constraints on the output physical feasible region, and candidate model backtracking verification. These designs ensure that the system maintains stable, reliable, and predictable operation even when facing engineering boundary conditions such as timing competition between deep model updates and real-time control, FPGA storage resource constraints, and truncation errors in fast time-varying physical processes. Simulation verification shows that under extreme conditions with 8000 partitions, the storage capacity required for the affine coefficient matrix stored in compressed sparse row format is only about 8% of that of dense storage. The worst-case execution time of the hierarchical hybrid search architecture remains a fixed constant and is much smaller than the control cycle. In a high-frequency update scenario where 6 base update requests are triggered within 10 consecutive seconds, the cooling period constraint reduces the actual number of executions to 3, the peak CPU load does not exceed 55%, and the degradation threshold is not triggered. Candidate model backtracking verification ensures the decision safety of the algorithm at the control model update level, while hardware-forced physical boundary gating logic ensures the physical safety of the hardware at the actuator instruction level. Together with the flight safety boundary determination of the flight control coordination interface module, these two components constitute a three-level safety redundancy system from algorithm and hardware to flight mission, providing a design foundation for the high reliability requirements of the system to pass airworthiness certification. This invention is not only complete in its theoretical framework but has also been fully verified in terms of engineering practicality and reliability.

[0040] 6. Feasibility and High Reliability. The core algorithms employed, such as explicit MPC, RLS, and recursive POD, are all supported by mature numerical methods and industrial tools. The hardware resource requirements for FPGA-based table lookup and projection operations are moderate and can be implemented on existing domestic avionics computing platforms. The entire decision-making process is based on rigorous physical models and logical reasoning, making it fully explainable, verifiable, and certifiable, avoiding the safety risks associated with "black box" AI decision-making. The system has a built-in degradation mode; when the performance of core components fluctuates or fails, it can seamlessly switch to a preset static control law to ensure flight safety. Attached Figure Description

[0041] Figure 1 This is a diagram showing the overall architecture of the dynamic adaptive stealth system for aircraft of the present invention.

[0042] Figure 2 This is a block diagram of the hardware and software collaborative architecture of the heterogeneous computing module, showing the division and data interaction relationship between the FPGA real-time control domain and the CPU background learning domain.

[0043] Figure 3 This diagram illustrates the process of explicit MPC offline construction and online table lookup.

[0044] Figure 4The flowchart for updating the online adaptive reduced-order model shows the triggering logic for RLS parameter correction and recursive POD basis update, as well as the decision-making process for updating the arbitration state machine. Detailed Implementation

[0045] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. This embodiment uses hypersonic vehicles as the application background, but the hard real-time online adaptive control technology provided by the present invention is also applicable to other aircraft (such as stealth drones, stealth fighters, etc.), as well as various platforms with stringent requirements for hard real-time online adaptive control, such as ships, ground vehicles, industrial robots, precision CNC machine tools, and satellites. Those skilled in the art should understand that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0046] Example 1: System Overall Architecture

[0047] See Figure 1 and Figure 2 The aircraft dynamic adaptive stealth system in this embodiment includes five functional modules: front-end perception module, threat assessment module, heterogeneous computing module, distributed intelligent skin actuator array, and flight control collaborative interface module.

[0048] 1. Front-end perception module

[0049] The front-end sensing module includes the following sensor group:

[0050] Wideband radar alarm receiver: covers the 2GHz to 40GHz frequency band, with a threat parameter update rate of no less than 100Hz, and outputs threat azimuth, elevation angle, carrier frequency, pulse repetition frequency and power estimation;

[0051] Mid-wave / long-wave dual-color infrared imaging sensor: resolution not less than 640×512 pixels, frame rate not less than 100Hz, used to detect background infrared radiation intensity;

[0052] Laser alarm: Four-quadrant detector configuration, providing information on the location and wavelength of threat lasers;

[0053] Distributed temperature sensor array on the surface of the aircraft: It adopts fiber optic grating sensors with a spatial resolution of no more than 5cm, covering the main skin area of ​​the aircraft.

[0054] Near-field electromagnetic probe array: embedded in the inner layer of smart skin for real-time sensing of near-field electromagnetic distribution;

[0055] Fiber optic gyroscope inertial measurement unit and BeiDou / inertial navigation system: provides three-axis attitude angle, angular rate and acceleration information of the aircraft, with an update rate of not less than 500Hz.

[0056] All sensor data are timestamped via a precision time synchronization bus and then sent to the heterogeneous computing module.

[0057] 2. Threat Assessment Module

[0058] The threat assessment module runs in the CPU background learning domain and is used to dynamically generate radar stealth priority weights based on information such as threat location, carrier frequency, power estimation, and infrared radiation intensity obtained by the front-end perception module. Priority weighting of infrared stealth The priority weights are then input into the cost function of the explicit MPC to achieve multi-spectral collaborative optimization. For details on the specific generation method of the priority weights, please refer to step 2 of Example 3.

[0059] 3. Heterogeneous computing module

[0060] The heterogeneous computing module adopts a CPU and FPGA heterogeneous architecture. In this embodiment, the CPU is a Phytium FT-2000 / 4 quad-core ARM processor, and the FPGA is a Fudan Microelectronics JFM7VX690T (compatible with Xilinx Virtex-7, approximately 200K logic units). Both share an 8GB DDR4-3200 memory (with ECC check) via an AXI high-speed bus, enabling zero-copy transfer of gradient tensors and control instructions.

[0061] The heterogeneous computing module is internally divided into two physically isolated but logically collaborative processing domains:

[0062] The FPGA real-time control domain undertakes hard real-time tasks, including sensor data reduction projection, explicit MPC lookup table lookup and affine control quantity calculation, physical feasible region constraint enforcement, and control command bus distribution. The physical feasible region constraint enforcement is implemented by a hardware-enforced physical boundary gating logic located between the FPGA's affine control quantity calculation unit and the actuator bus output unit. This logic is used to apply boundary constraints to the calculated affine control quantities before output. This domain operates with a strictly lockstepped control cycle of 10ms.

[0063] CPU background learning domain: This domain handles soft real-time tasks, including threat assessment and dynamic weight calculation, online updating of the RLS system matrix, update arbitration and load monitoring, candidate model backtracking verification, recursive POD basis function updates, and triggered background explicit MPC repartitioning calculations. This domain runs asynchronously with a 1-second background update cycle.

[0064] In the physical boundary selection logic, the physical feasible region boundary corresponding to each physical field component in the reduced-order state vector, derived from physical laws, is derived as follows: For the temperature field modal coefficients, the boundary is determined using the POD mode matrix. The temperature constraint in physical space is transformed into a linear inequality constraint for the modal coefficients: ,in It is a reduced-order state vector The sub-vectors corresponding to the thermal field. Determined by the law of absolute zero ( ), The upper limit of the material's temperature resistance is defined as the maximum allowable temperature. For electromagnetic field modal coefficients, the feasible region boundary is derived from the material's breakdown field strength or maximum power capacity. This transformed constraint constitutes the feasible region boundary of the modal coefficients, enforced by the FPGA's hardware-enforced physical boundary gating logic. This hardware-enforced physical boundary gating logic acts as the final safety verification step before the control command output, ensuring that any calculated control quantity is physically within the safe feasible region, providing final protection for the actuator at the hardware level. Therefore, this physical feasible region constraint is not a simple limitation on the control quantity, but rather, through the POD modal matrix, it precisely maps the hard safety boundaries of physical quantities such as temperature and electric field strength in the physical space into linear inequality constraints on the modal coefficients in the reduced-order state space. This ensures that while rapid optimization is performed in the reduced-order subspace, the physical realizability of the solution is rigorously guaranteed in the final stage of hardware execution, traceable to fundamental physical laws, forming a complete closed loop of "online model learning—online control computation—online physical constraints."

[0065] 4. Distributed intelligent skinned actuator array

[0066] The actuator array adopts a two-level distributed architecture of "regional controller-end node". Assuming the aircraft skin area is about 50 square meters, it is equipped with about 5,000 reconfigurable FSS units based on microelectromechanical systems (each unit is 1cm×1cm in size, and the surface electromagnetic impedance is adjusted by changing the resonant length of the butterfly gap through electrostatic comb drive) and about 2,000 phase change material microcavity units (the microcavities are filled with paraffin-based composite phase change material, and the surface infrared emissivity is independently controlled by the pulse width modulation signal of the micro electric heating wire).

[0067] One area controller is configured for every 100 FSS cells, addressed and driven via SPI or I²C bus. The area controller communicates with the FPGA via a dual-redundant CAN-FD bus. The phase change material microcavity array adopts a similar area control architecture, with PWM drive power of approximately 0.1W to 1W per cell.

[0068] 5. Flight control collaboration interface module

[0069] The flight control collaboration interface module employs a dual-redundant AFDX Ethernet interface to connect to the flight control computer. It transmits the aircraft's current attitude and trajectory commands uplink and trajectory correction suggestions generated by the system downlink. The communication cycle is 50ms. It is understood that when the technical solution of this invention is applied to other platforms such as ships, ground vehicles, and industrial robots, the function of this collaboration interface module can be correspondingly expanded to connect to the motion control system of that platform, acquire the platform's current motion state and control commands uplink, and send adjustment suggestions generated by the system related to the platform's specific performance indicators downlink, thereby achieving joint optimization of the platform's dynamic characteristics and stealth or other performance indicators without departing from the heterogeneous computing collaborative control architecture disclosed in this invention.

[0070] 6. Summary of key parameters

[0071] In this embodiment, the key preset parameters involved in system operation are shown in the table below:

[0072]

[0073] Example 2: Construction of the Initial Reduced-Order State-Space Model

[0074] This embodiment details the method for constructing the initial reduced-order state-space model in the offline phase. This method is completed offline before the system is powered on and provides the initial basis and prior matrix for online adaptive updates.

[0075] Electromagnetic order reduction model construction. The method for constructing the electromagnetic order reduction model is as follows: For the aircraft's baseline shape, a parameterized RCS database is established through full-wave simulation (such as the method of moments / multilayer fast multipole). The sampling space includes: FSS control parameter vector, threat azimuth and pitch angles, and threat carrier frequency. RCS perturbation is calculated at each sampling point. Based on the sampled dataset, dominant modes are extracted using intrinsic orthogonal decomposition (POD), and a nonlinear mapping model (POD-DNN ROM) from control parameters to POD coefficients is constructed using a deep neural network. This model can output predicted RCS values ​​within microseconds for a given control parameter and provides automatic gradient differentiation.

[0076] Construction of the thermal order reduction model. The method for constructing the thermal order reduction model is as follows: For the composite structure of the aircraft surface, a three-dimensional transient heat conduction partial differential equation is established:

[0077]

[0078] In control parameter space High-fidelity finite element simulation parameters were sampled within typical thermal load ranges to generate a temperature field snapshot matrix. The reduced-order state-space equations (reduced-order dimension) were obtained using the POD-Galogen projection method. The coefficient of performance is approximately 20 to 50, and an empirical interpolation method is used to handle the nonlinear radiation term. The resulting reduced-order thermal model can predict the surface temperature field distribution under a given control input within microseconds.

[0079] Multiphysics coupling. The method for constructing the multiphysics coupling model is as follows: the electromagnetic reduced-order model and the thermal reduced-order model are coupled within a linearized state-space framework to form a unified initial reduced-order state-space model. The temperature field distribution output by the thermal model is used as one of the input parameters of the electromagnetic model to characterize the effect of temperature changes on the dielectric constant and RCS. The state vector of the initial reduced-order state-space model... Includes reduced-order temperature field modal coefficients and reduced-order electromagnetic field modal coefficients, control vector It includes at least the FSS unit deformation, the material complex permittivity modulation, the thermal conductivity modulation, and the active cooling heat flux density. The discrete-time form of the initial reduced-order state-space model is as follows:

[0080]

[0081] Example 3: Explicit MPC Offline Construction Method

[0082] This embodiment uses a reduced-order dimension. Prediction time domain Control Time Domain Taking an example, this describes the construction method for explicit MPC in the offline phase. This construction process is completed before the system is powered on, and the construction result is permanently stored in the FPGA's memory.

[0083] Step 1: Based on the initial reduced-order state-space model constructed in Example 2, obtain the discrete-time linear time-invariant state-space expression. .

[0084] Step 2: Define the quadratic cost function:

[0085]

[0086] in To predict the time domain, This is the weight matrix. This is for reference output. The weight matrix is ​​based on radar stealth priority weights. Priority weighting of infrared stealth Dynamic adjustment. The method for generating the priority weights is as follows:

[0087] Calculate the normalized signal factor for each threat source, assign tactical coefficients according to the threat type, and obtain the threat exposure factor for the corresponding direction based on the current aircraft attitude;

[0088] Based on the aforementioned signal factor, tactical coefficient, and exposure factor, the radar comprehensive threat index is calculated respectively. Infrared Comprehensive Threat Index ;

[0089] Each comprehensive threat index is independently mapped to its original weight using the Sigmoid function. and ;

[0090] The original weights of radar and infrared sensors are summed and normalized. The mathematical essence of this summation and normalization is a continuous and smooth Lebesgue measure redistribution in the weight matrix of the cost function, calculated on a one-dimensional weight manifold using the inverse transformation of the Sigmoid function, after which the threat level is determined. This redistribution is not a simple discrete mode switch and satisfies the following conditions:

[0091]

[0092] The weighted modes are discretized into a finite number (e.g., 3 to 5 groups), each group corresponding to an independent explicit controller. The controllers share the partition geometry, differing only in their affine coefficients. Mode switching is achieved through base address pointer offset. The control input is constrained by physical limits, and the actuator speed is constrained by the rate of change.

[0093] Step 3: Using a multi-parameter quadratic programming (mp-QP) solver, the constrained finite-time optimal control problem is solved offline as a set of piecewise affine (PWA) functions:

[0094]

[0095] in For the reduced-order state vector, For control vectors, Partition the state space. Here are the gain matrix and bias vector for each partition. The total number of partitions determined for offline calculation.

[0096] To control the partition size, a moving block strategy is adopted to divide the state space into several overlapping sub-regions for separate solving. Specifically, the moving block strategy involves defining an r-dimensional hyperrectangular window in the r-dimensional state space, and sliding the window along each dimension with a fixed step size half the window width. For the 8-dimensional system in this embodiment, each dimension slides independently, and the overlap rate of adjacent windows is 50%. The local optimal control problem within each window is solved independently, generating several locally effective partitions. Then, a merging algorithm based on convex hull calculation is used to traverse all local partitions, merging any two intersecting partitions with the same affine control law to eliminate redundant boundaries until a minimum, non-overlapping global convex partition set is generated. The reduced-order system, number of partitions Keep it under 2000. (Each partition) For a convex polyhedron, there are several hyperplane inequalities. Define and attach an affine control law. .

[0097] Step 4: Encode the hyperplane information and affine coefficients of all partitions into a hierarchical hybrid search structure. This hierarchical hybrid search structure is a hybrid search method that combines approximate search based on a spatial index tree with precise geometric discrimination based on hyperplane inequalities. The "hybrid" aspect means: the first level uses a state-space index tree structure to quickly narrow the search range, providing a non-precise, coarse location; the second level uses a strict set of linear inequalities for precise attribution judgment, ensuring the absolute correctness of the search results. The specific construction method is as follows: First level, for all partitions generated offline... Feature points (such as Chebyshev centers of each partition) are used to construct a coarse-grained KD-Tree using the partial dominant mode coefficients (such as the first four dominant mode coefficients) of the reduced-order state vector. The partial dominant mode coefficients are the first few mode coefficients whose cumulative contribution to the system energy exceeds a preset threshold. During online searching, inputting the corresponding mode coefficient of the current state vector quickly locates a small set of candidate partitions containing that state point. The second level substitutes the reduced-order state vector sequentially into the hyperplane inequalities of each partition in the candidate partition set. Verify to determine its unique partition. Affine coefficient matrix Compressed Sparse Row (CSR) format is used for storage, storing only non-zero elements and their indices. This CSR format ensures that even in high-dimensional, massively partitioned scenarios, the FPGA's on-chip storage resources can still meet hard real-time requirements. It also provides a data foundation for subsequent efficient indexing and loading of affine coefficients corresponding to different threat modes using base addresses plus preset offsets. The first-level tree depth is approximately 11. The main body of the lookup table is stored in the FPGA's external high-speed SRAM, along with the upper-level nodes of the on-chip BRAM cache tree and the currently active partition coefficients.

[0098] Example 4: Online Adaptive Model Update Method

[0099] This embodiment details the implementation process of the CPU background learning domain. The CPU updates in each background cycle... The following operations are performed internally. Steps S31-S38 correspond to specific implementation methods of the CPU background task logic in the technical solution.

[0100] S31: Read the state-control sequence from the shared FIFO for the most recent second. There are approximately 100 samples in total (when the control period is 10ms).

[0101] S32: RLS recursive update. Forgetting factor. Initial covariance matrix The RLS recursion is performed sequentially on the 100 read samples in chronological order to obtain the updated system matrix estimate. Then and It is stored in CPU memory for the next cycle to continue the recursion.

[0102] S33: Mismatch Detection. The criterion for mismatch detection is: calculating the one-step prediction residual. Monitor the ratio of the residual to the norm of the reduced-order state vector. Simultaneously monitor the spectral characteristics of the residual; if the residual exhibits high-frequency broadband characteristics, it is determined to be a basis mismatch; if the residual exhibits low-frequency drift characteristics, the RLS forgetting factor is adjusted preferentially. If the ratio exceeds a threshold for 10 consecutive steps... (This threshold is the adaptive baseline obtained by multiplying the arithmetic mean of the norms of all reduced-order state vectors in the most recent background update cycle by 0.05), then it is determined that the model has a structural mismatch, and the "base update request" flag is set.

[0103] S34: Update Arbitration. The decision logic of the update arbitration state machine is as follows: it internally maintains a finite state machine containing at least the following states: "Idle State," "Monitor State," "Base Update Cooling State," "Repartition Cooling State," "Base Update Execution State," and "Repartition Execution State." After receiving the base update request flag in the "Monitor State," the state machine checks the following conditions in sequence:

[0104] Does it meet the base update cooldown constraint (at least 3 seconds since the last base update)?

[0105] Is a non-repartitioning calculation currently in progress?

[0106] Is the current CPU load below the safe threshold (default is 60%)?

[0107] If all conditions are met, the state machine transitions from the "monitoring state" to the "base update execution state," initiating a recursive POD base update. If any condition is not met, the state machine enters the corresponding cooling state, recording only the request and delaying execution until the condition is met. The CPU continuously monitors its own load; if the load exceeds a preset threshold, it automatically pauses low-priority tasks (including base updates and repartitioning calculations) to prioritize the timely execution of RLS updates.

[0108] S35: When the base update is triggered, the method of the recursive POD base update is: collect all new snapshot matrices since the last base update. An exponentially decaying weight is introduced for the new snapshot, while a larger retention weight is assigned to the old basis. The weight decay factor is set to 0.95. The projected residuals are then calculated.

[0109]

[0110] Singular value decomposition (SVD) is performed on the residual matrix to obtain Take the front. left singular vectors With the old base merge:

[0111]

[0112] For the merged base Perform SVD decomposition again, and take the first... The left singular vectors are used as the updated basis functions. This compresses the basis function dimension back to the original reduced-order dimension. The updated projection matrix is: The introduction of exponentially decaying weights to new snapshots aims to assign higher weights to recent data to track rapid time-varying dynamics. Simultaneously, this decay strategy, combined with the direct retention of old bases in the merging step, constitutes a "memory-learning" balancing mechanism. The retention of old bases ensures that the reduced-order subspace information established under historical flight states is not lost, preventing performance degradation when the model returns to previous flight states. This is a key design feature enabling this scheme to cover the entire flight envelope.

[0113] S36: Candidate Model Validation. The criterion for candidate model validation is as follows: The CPU uses recent historical data (usually the state sequence of the last 5 background cycles) to validate the candidate model (new base). +New projection matrix Perform backtracking prediction and calculate its root mean square error (RMSE). Only when the percentage reduction in RMSE of the candidate model compared to the currently active model exceeds a preset threshold (20%) is the candidate model allowed to be written to the standby buffer B and the switching ready flag set.

[0114] Meanwhile, the basis functions of the validated candidate models With the current active basis function Calculate the subspace angle between the two. The method for calculating the subspace angle is as follows: by calculating... The singular values ​​are calculated, and the inverse cosine is used to obtain the main characters. The largest main character is taken as the subspace angle. If the angle is greater than the preset threshold (5°), it indicates that the dynamic characteristics of the system have changed significantly, and the "repartition request" flag is set.

[0115] S37: Repartition Arbitration and Execution. The decision logic for repartition arbitration is as follows: When updating the arbitration state machine to check the repartition request, an additional repartition cooldown constraint must be met (at least 30 seconds since the last repartition). If the condition is met, the state machine jumps to the "repartition execution state," and the CPU starts repartition calculation in the background to update the... Re-execute the full mp-QP solution, and generate The lookup tree overwrites the backup buffer B. During the repartitioning process (which may take several seconds), the FPGA continues to work using the old partition table of the currently active buffer A to ensure uninterrupted real-time control. While the CPU is performing the repartitioning calculation, its background tasks do not stop; the CPU will continue to execute the recursive least squares algorithm in parallel on the system matrix. Perform micro-updates; after the repartitioning is complete, these micro-updated matrices will be combined with the new base. Together, they are used to generate the final affine function table, ensuring that once the new partition table is switched, it already contains the latest system dynamics information during the computation execution, achieving uninterrupted adaptive evolution.

[0116] S38: Atomic Switching. The dual-buffer atomic switching method is as follows: The control logic embedded in the FPGA includes a three-input instruction selector, whose inputs are connected to the active buffer, the spare buffer, and the zero-order hold, respectively. At the beginning of each 10ms control cycle, the control state machine checks the "switching ready" flag at the fixed read cycle start phase (e.g., the 3rd clock cycle). If the flag is valid, the base address is swapped on the rising edge of the next read cycle. The address swapping operation is completed within a single clock cycle, and the input of the instruction selector immediately switches from the old buffer to the new buffer. During this period, the zero-order hold continuously outputs the valid control quantity of the previous cycle to ensure no glitches in the output. After the address swap is completed, the control state machine performs a CRC32 check on the new spare buffer. If the check passes, the "switching ready" flag is cleared; otherwise, the address is rolled back and an error is reported. The entire switching process is transparent to the current control cycle and does not introduce intermediate states. The control quantity output sequence of each control cycle before and after the switch has no jumps or glitches. The old buffer A then becomes the new spare buffer for the next round of updates. It is understood that, in addition to switching base address pointers, the atomic switching mechanism can also be implemented by using a multi-port memory controller to achieve hardware-free memory mapping switching. Any scheme that can guarantee that the FPGA completes the overall switching of the control law parameter set within a single bus cycle should be considered to fall within the protection scope of the "atomic switching" of this invention.

[0117] Example 5: Real-time simulation verification

[0118] Under typical operating conditions (reduced dimension) Number of partitions KD-Tree Depth The real-time performance of the system in this embodiment is verified by simulation.

[0119] FPGA hardware implementation: Sensor data projection calculation uses an 8-stage fixed-pipeline multiply-accumulate processor with a delay of 8 FPGA clock cycles (approximately 40ns at a 200MHz clock frequency). Hierarchical hybrid search and affine transformation operations are implemented using a hard-wired state machine. First-level tree search uses a fixed traversal. There are 11 nodes (1 cycle per node, 11 cycles in total). The upper limit of the precise discrimination loop for the second-level candidate set is fixed at the maximum size of the candidate set. The affine operation is a fixed number of multiplications and accumulations. (Several operations, 4-stage pipeline parallelism). Actual measurements from state... Input to control quantity The output hardware delay is 563ns, plus approximately 650ns for sensor projection and physical constraint gating. This delay is a fixed constant and does not change with state position or solver iteration; the worst-case execution time is this fixed value.

[0120] Regarding CPU background updates, RLS processes 100 sets of 8-dimensional samples in no more than 5ms; SVD processing of recursive PODs takes approximately 80ms (based on the standard LAPACK library, single-core). Candidate model backtracking verification takes approximately 12ms. All of the above calculations can be completed within a 1-second background cycle, without hindering real-time control.

[0121] To verify the control timing stability of the system under airborne environmental conditions, temperature stress and vibration stress simulation analysis was performed on the FPGA control delay. Within a temperature range of -55℃ to +125℃, based on the temperature drift model of the timing parameters provided in the FPGA datasheet, the simulation showed a control delay fluctuation of less than ±3ns. Under 20g random vibration power spectral density conditions, simulation based on a vibration fatigue model of solder joints and interconnect structures also showed a control delay fluctuation of less than ±3ns. These simulation results demonstrate that the hard real-time control timing of this system remains stable under extreme temperature and vibration stress conditions, verifying its applicability in airborne environments.

[0122] Example 6: Verification of System Robustness and Adaptability to Extreme Operating Conditions

[0123] To ensure the system remains stable and reliable under extreme conditions such as flight envelope edges, limited computing resources, and sudden changes in physical characteristics, this embodiment further verifies the synergistic effect of the following enhancement mechanisms based on the above embodiments.

[0124] I. Extreme stress test of partitioned storage and fast lookup

[0125] The number of explicit MPC partitions was gradually increased from 1200 in the standard operating condition to 8000 to simulate extremely complex control law scenarios. When the number of partitions reached 8000, the storage capacity required for the affine coefficient matrix stored in a compressed sparse row format was only about 8% of that required for dense storage. The worst-case execution time of the hierarchical hybrid search architecture increased from 563ns to 685ns, but remained a constant and was much less than the 10ms control cycle.

[0126] II. Update the abnormal operating condition test of arbitration and load monitoring

[0127] The simulation involved triggering 6 base update requests within 10 consecutive seconds (a probability extremely low under normal operating conditions). Under cooldown constraints, only 3 base updates were actually executed. CPU load monitoring showed that the CPU load peaked at 55% during the third base update, without triggering the degradation threshold. In another test, the CPU load was artificially increased to over 60% for three consecutive background cycles. The system automatically paused base updates and repartitioning calculations, maintaining only RLS operation. After the load dropped to 35% in the fourth background cycle, the normal update process automatically resumed.

[0128] III. Validity Testing of Candidate Model Backtracking Validation

[0129] A 10% anomalous perturbation sample was artificially injected into the snapshot data. Without enabling candidate model validation, the RMSE of the updated model was only reduced by 8% compared to before the update, and performance fluctuated in subsequent cycles. After enabling candidate model validation, this update was rejected because the RMSE improvement did not reach the 20% threshold, and the system continued to use the currently active model, avoiding degraded updates. Subsequently, a base update triggered under normal snapshot data reduced the RMSE by 35%, successfully passed validation, and completed the switch.

[0130] IV. Synchronization Verification of Double-Buffered Atomic Switching

[0131] During the repartitioning process (approximately 8 seconds), an emergency base update request is simulated. After the cooling-off period following the repartitioning, the CPU initiates the base update, writing the new base to the standby buffer B without affecting the FPGA's currently used primary buffer A. The primary / standby switchover is completed in the third clock cycle of the 10ms control cycle. Timing waveforms captured by the logic analyzer show that the control output sequence for 100 control cycles before and after the switchover is free of jumps and glitches, ensuring complete control continuity.

[0132] V. Verification of the protective effect of hard constraints on the physically feasible region

[0133] A transient anomalous disturbance (simulating short-term model mismatch caused by extreme shock waves) is artificially injected into the reduced-order state-space model, causing the affine output to generate a control command that exceeds the physical limits of the actuator. Without physical constraints, this command would cause the actuator to saturate and generate shocks; however, under the gating logic of the physical feasible region of this system, the anomalous command is restricted within the preset safety boundary, and the actuator output is smooth and shock-free.

[0134] VI. Comparison and Verification with Conventional Online MPC Solutions

[0135] Under the same simulation conditions (reduced dimension) Predicting the time domain This system is compared with a conventional MPC system that uses the interior-point method for online solution. The results show:

[0136] WCET determinism: The single-cycle control delay of this system is 650ns (a fixed constant with a variance of 0); the single-cycle solution time of conventional MPC fluctuates between 0.8ms and 8.3ms (with a variance of 2.1ms) and is unpredictable when the condition number deteriorates.

[0137] Model mismatch recovery time: After injecting the same degree of structural model mismatch, this system completes model adaptive recovery within 3 background cycles (3 seconds) through RLS+recursive POD; conventional MPC has a continuous decline in control performance due to the lack of an online model update mechanism.

[0138] Extreme operating condition safety: In the actuator saturation boundary test, the physical constraint gating logic of this system successfully limited abnormal instructions in 100% of the test cases; the conventional MPC output out-of-bounds control values ​​in 17% of the test cases.

[0139] VII. Creative Comparative Analysis with the Closest Existing Technology Combination

[0140] To illustrate the synergistic effect of the key mechanisms in this scheme, it is compared and analyzed with two existing technical schemes. Let D1 be a scheme using explicit MPC for flight control, which uses offline POD to construct a reduced-order state-space model. However, once the model is trained offline, it remains fixed and cannot be updated online using the POD basis functions. Let D2 be an online POD update scheme for flow field prediction, which runs on a general-purpose CPU and can update the POD basis functions based on new data. However, the computational delay during the update is unpredictable and cannot be directly used for hard real-time control.

[0141] If D1 and D2 are simply combined, the resulting explicit MPC controller with an online-updable reduced-order state-space model will face the following contradictions: online model updates will generate new and more complex state-space partitioning structures, making it impossible to determine the worst-case execution time of online table lookup in advance; at the same time, the computational delay of the model update task itself is unpredictable, which will directly impact the real-time control task.

[0142] To address the aforementioned contradictions, this plan resolves them through the following two mechanisms:

[0143] The hierarchical hybrid search structure solidifies WCET into a constant that depends only on tree depth and state dimension, decoupling it from partition complexity and quantity, and ensuring that the real-time determinism of control is always guaranteed no matter how the model is updated;

[0144] The updated arbitration state machine and double-buffered atomic switching mechanism allow the CPU to perform deep model updates asynchronously and non-real-time, while atomic pointer swapping enables zero-time-disruption switching between old and new model data. The combination of these two mechanisms gives the online learning system hard real-time control determinism.

[0145] Therefore, this invention is not a simple combination of D1 and D2, but rather achieves synergistic effect by revealing and resolving the fundamental contradiction of "determinism-adaptability" that arises when the two are combined and has not been recognized by the prior art, thus enabling the online learning system to possess hard real-time control determinism for the first time.

Claims

1. A dynamic adaptive stealth system for aircraft, a heterogeneous computing collaborative system constructed to address the problems of lack of worst-case execution time upper bound and difficulty in online adaptation of physical models in airborne environments for dynamic stealth control, characterized in that... include: The front-end perception module is used to acquire threat situation information, aircraft surface temperature field distribution, and near-field electromagnetic scattering data. The threat assessment module is used to dynamically generate radar stealth priority weights and infrared stealth priority weights based on the information obtained by the front-end perception module. The heterogeneous computing module includes a field-programmable gate array (FPGA) and a general-purpose processor (CPU), wherein the FPGA and the CPU are connected via shared memory or a high-speed bus; A distributed smart skin actuator array, comprising multiple reconfigurable frequency-selective surface units and phase change material microcavity units; Flight control collaboration interface module, used for communication with the flight control system; The FPGA's memory contains the partition boundaries and affine coefficients of a piecewise affine function obtained by offline solution of an electromagnetically-thermal coupled initial reduced-order state-space model using a multi-parameter programming method with finite-time-domain constrained optimal control, as well as a hierarchical hybrid search structure for fast partition lookup. The cost function of the piecewise affine function is weighted by the priority weights generated by the threat assessment module. The first level of the hierarchical hybrid search structure uses some dominant mode coefficients of the reduced-order state vector to construct a coarse-grained KD-Tree to locate the candidate partition set, and the second level performs precise linear hyperplane discrimination within the candidate set. Within each fixed control cycle, the FPGA is configured to execute the following hardware logic sequentially in hard real-time: Real-time sensor data is projected into a reduced-order state vector through a fixed projection matrix; The hierarchical hybrid search structure is used to find the partition to which the reduced-order state vector belongs and read the corresponding gain matrix and bias vector. The single query latency of the hierarchical hybrid search structure is a fixed constant that depends only on the tree depth and state dimension and does not change with the increase of the partition complexity. Calculate affine control variables; The affine control quantity is constrained by a hardware-forced physical boundary gating logic and then output to the distributed intelligent skinned actuator array. The hardware-forced physical boundary gating logic enforces the actuator's saturation limit constraint, rate of change constraint, and physical feasible domain boundary derived from physical laws, corresponding to each physical field component in the reduced-order state vector. And store the current reduced state and the constrained control quantity into a shared first-in-first-out queue; The CPU is configured to execute the following logic in a background task asynchronous with the FPGA hard real-time control process: Historical state-control sequences are read from the shared first-in-first-out queue. A recursive least squares algorithm with a forgetting factor is used to update the system matrix and input matrix of the initial reduced-order state-space model online. The ratio of the prediction residual to the norm of the reduced-order state vector is monitored. When this ratio exceeds a preset threshold for multiple consecutive steps, a structural mismatch is determined, and a base update request flag is set. Upon receiving the base update request flag, an update arbitration state machine, based on preset base update cooldown constraints, repartition cooldown constraints, and the current CPU load conditions, decides whether to trigger the CPU to execute recursive intrinsic orthogonal decomposition to update the reduced-order basis functions, or to trigger background repartition computation. Before model switching, candidate models are backtracked for prediction verification using recently stored or offline historical state-control sequences. Backtracking prediction is performed on the candidate model constructed from the new basis functions, and its root mean square error (RMSE) is calculated. Switching is only allowed when the percentage reduction in the RMSE of the candidate model compared to the currently active model exceeds a preset improvement threshold. If the change in the basis functions is detected to exceed the preset threshold and the repartitioning cooldown condition is met, background repartitioning calculation is triggered to generate an updated piecewise affine function table and write it to the spare buffer. The piecewise affine function table contains multiple sets of affine coefficients corresponding to different threat priority weight combinations, and each set of affine coefficients is stored in a contiguous address space. In each fixed control cycle, the FPGA directly indexes and loads the corresponding set of affine coefficients by adding a preset offset to the base address, based on the current priority weight pattern generated by the threat assessment module. A dual buffer is provided between the FPGA and the CPU to store the projection matrix and the piecewise affine function table, so as to realize the model update without timing interference in the real-time control process. After the CPU writes complete data to the backup buffer, it sets the switching ready flag. The FPGA is also configured to check the switching ready flag at a fixed phase at the beginning of each control cycle. If it is valid, it completes the atomic switch with the backup buffer within one clock cycle by exchanging the base address pointer, so as to introduce the updated model into the real-time control loop without disturbance, and realize zero timing interference of model update to real-time control. This atomic switch is implemented by the control logic embedded in the FPGA and completes the overall switch of the control law parameter set within one bus cycle.

2. The system according to claim 1, characterized in that, The hierarchical hybrid search structure is a hybrid search structure that combines approximate search based on spatial index trees with precise geometric discrimination based on hyperplane inequalities. Its construction and operation features include the deterministic nature of online table lookup latency, including: The first stage uses some dominant mode coefficients of the reduced-order state vector to construct a coarse-grained KD-Tree to locate the candidate partition set. The construction of the first-stage KD-Tree is completed offline based on the Chebyshev centers of each partition as feature points, and the maximum size of this candidate partition set is... It is recorded during the offline phase and fixed together with the search structure; The second level performs precise linear hyperplane discrimination within the candidate set. During online lookup, the upper bound of the number of times the second-level discrimination logic traverses the candidate partition set is the [missing information]. ; The dominant mode coefficients are the first few order mode coefficients whose cumulative contribution to system energy exceeds a preset threshold; the gain matrix of the affine coefficients is stored in a compressed sparse row format; the worst-case execution time of the lookup and affine operation is determined by the offline calculated tree depth, etc. The state dimension is predetermined, is a fixed constant, and is decoupled from the total number of partitions N of the piecewise affine function.

3. The system according to claim 1, characterized in that, The recursive POD update of the reduced-order basis function includes: collecting a new snapshot matrix, introducing exponentially decaying weights to the new snapshots to give higher weight to recent data to track fast time-varying dynamics, while retaining the old basis to ensure that the reduced-order subspace information established under historical flight states is not lost; calculating the projection residual of the weighted new snapshot onto the current basis, performing singular value decomposition on the residual matrix, taking the first few left singular vectors and merging them with the current basis, performing SVD decomposition on the merged basis again and taking the first r left singular vectors as the updated basis function, thereby compressing back to the original reduced-order dimension; the preset threshold for the change of the basis function is the subspace angle between the new and old basis functions.

4. The system according to claim 1, characterized in that, The update arbitration state machine is also configured to: when repartitioning calculation is in progress, newly arriving base update requests are queued and waited for repartitioning to be completed before starting; and continuously monitor the CPU's own load, and if the load exceeds a preset threshold of the CPU's current load condition, automatically pause low-priority tasks, including base update and repartitioning calculation.

5. The system according to claim 1, characterized in that, The physical feasible domain boundary of the hardware-forced physical boundary gating logic is constructed by mapping the hard safety boundaries of physical quantities such as temperature and electric field intensity in the physical space to linear inequality constraints on modal coefficients in the reduced state space through the POD mode matrix of the reduced state space model. This ensures that while performing rapid optimization in the reduced subspace, the physical realization of the solution is guaranteed by a forced guarantee traceable to the fundamental physical laws in the final stage of hardware execution.

6. The system according to claim 1, characterized in that, The threat assessment module generates radar stealth priority weights in the following manner. Priority weighting of infrared stealth : Calculate the normalized signal factor for each threat source, assign tactical coefficients according to the threat type, and obtain the threat exposure factor for the corresponding direction based on the current aircraft attitude; Based on the aforementioned signal factor, tactical coefficient, and exposure factor, the radar comprehensive threat index and the infrared comprehensive threat index are calculated respectively. Each comprehensive threat index is independently mapped to its original weight using the Sigmoid function; The original weights of radar and infrared sensors are subjected to normalization processing to satisfy... In essence, it is a continuous and smooth Lebesgue measure redistribution implemented in the cost function.

7. The system according to claim 1, characterized in that, The candidate model backtracking prediction verification, the hardware-forced physical boundary gating logic, and the flight safety boundary determination set in the flight control collaborative interface module together constitute a three-level safety redundancy architecture: At the first level, the candidate model backtracking prediction verification ensures decision safety at the model update level; At the second level, the hardware-forced physical boundary gating logic ensures hardware physical security at the executor instruction level. At the third level, the flight control coordination interface module ensures flight safety at the flight mission level by determining the flight safety boundary of the trajectory correction command.

8. The system according to claim 1, characterized in that, It also includes a degraded working mode: when the response frequency of the distributed intelligent skin actuator array is detected to be lower than a preset threshold, or the background model update fails continuously, or the CPU load exceeds the safety threshold for multiple consecutive background cycles, the system automatically switches to a pre-stored static feature control mode library. The static feature control mode library contains multiple sets of pre-generated offline open-loop control instruction sequences corresponding to different typical threat scenarios. After switching, the system directly retrieves and outputs the open-loop control instruction sequence based on the threat situation output by the current threat assessment module, so as to maintain basic stealth capability in an open-loop manner.

9. A dynamic adaptive stealth method for aircraft, deployed on a heterogeneous computing platform including FPGA and CPU, characterized in that, include: The FPGA performs hard real-time execution within each fixed control cycle: using a piecewise affine function table and a hierarchical hybrid lookup structure pre-stored in memory, obtained by solving an electromagnetic-thermal coupling initial reduced-order state space model through offline multi-parameter programming, the real-time sensing data is projected into a reduced-order state vector. The affine control quantity is obtained online by looking up the table through the hierarchical hybrid lookup structure, and then output to the distributed intelligent skinned actuator array after being subjected to hardware-forced physical boundary constraints. The first level of the hierarchical hybrid search structure uses some dominant mode coefficients of the reduced-order state vector to construct a coarse-grained KD-Tree to locate the candidate partition set. The second level performs precise linear hyperplane discrimination within this candidate set. The piecewise affine function table contains multiple sets of affine coefficients corresponding to different threat priority weight combinations, and each set of affine coefficients is stored in a contiguous address space. The FPGA directly indexes and loads the corresponding set of affine coefficients according to the current priority weight mode by adding a preset offset to the base address. The CPU executes the following in a background task asynchronous with the FPGA control cycle: It retrieves the historical state and control sequence stored in the FPGA from shared memory; it updates the system matrix and input matrix of the initial reduced-order state-space model online using a recursive least squares algorithm with a forgetting factor; it monitors the prediction residuals and, when the model mismatch exceeds a threshold, an update arbitration state machine decides whether to trigger recursive intrinsic orthogonal decomposition to update the reduced-order basis functions, or trigger background repartitioning calculation, based on preset basis update cooling-off period constraints, repartitioning cooling-off period constraints, and the current CPU load conditions; before model switching, it performs backtracking prediction verification on the candidate model, using recently stored or offline historical state-control sequences to perform backtracking prediction on the candidate model composed of new basis functions, calculating its root mean square error (RMSE); switching is only allowed when the percentage reduction in the RMSE of the candidate model compared to the currently active model exceeds a preset improvement threshold; if the change in the basis functions exceeds a preset threshold and meets the repartitioning cooling-off period conditions, it triggers background repartitioning calculation to generate an updated piecewise affine function table. The CPU writes the updated projection matrix and piecewise affine function table into a spare buffer in a double buffer and sets the switching ready flag. The FPGA checks the ready flag at a fixed phase at the beginning of each control cycle. If it is valid, it completes the atomic switching with the spare buffer within one clock cycle by exchanging the base address pointer, so as to introduce the updated model into the real-time control loop without disturbance.

10. An aircraft comprising a fuselage and skin, characterized in that, The skin integrates a distributed intelligent skin actuator array as described in any one of claims 1 to 8, and the aircraft carries the heterogeneous computing module and the threat assessment module.

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