Synchronization system, synchronization method and parameter adaptive configuration method for pencil beam scanning controller

Abstract

The application discloses a synchronization system, a synchronization method and a parameter adaptive configuration method for a pencil beam scanning controller, and belongs to the technical field of proton treatment equipment control; the synchronization system comprises a master real-time controller, a slave real-time controller, at least one set of electrometers and at least one set of I / O modules; the master real-time controller serves as a management node of global synchronization time and a coordination node of a scanning control task, and is integrated with a control unit and a board-mounted time-sensitive network exchange unit; the slave real-time controller, the electrometers and the I / O modules serve as remote synchronization nodes and are connected with the master real-time controller respectively, and perform sampling, output, integration, feedback calculation and interlocking judgment based on a unified global time reference; the slave real-time controller, the electrometers and the I / O modules are respectively integrated with control units and board-mounted precise time Ethernet physical layer units; unified time reference of multiple nodes, deterministic time distribution, link delay compensation and execution layer closed-loop calibration are realized.

Description

Technical Field

[0001] This application belongs to the field of proton therapy equipment control technology, specifically relating to a synchronization system, synchronization method, and parameter adaptive configuration method for a pencil beam scanning controller. Background Technology

[0002] In proton therapy, pencil beam scanning technology achieves precise point-to-point irradiation of the tumor target area by adjusting the scanning magnet current in real time to deflect the beam position and simultaneously modulating the beam intensity (dose rate). The pencil beam scanning controller mainly includes a real-time controller (master and slave), an electrometer, and an I / O module.

[0003] The real-time control workflow of the pencil beam scanning controller is as follows: It receives a scan map from the Treatment Control System (TCS), which contains the location of each irradiation point, the dose, and the corresponding magnet power supply current value for each scan location. The real-time controller executes the scan according to this predetermined sequence and sends synchronous control commands to the I / O module and electrometer. The I / O module updates the scanning magnet settings according to a preset scan control cycle. Simultaneously, monitoring equipment such as the ionization chamber provides real-time feedback on the beam's position, size, and dose information at the same rate. The real-time controller compares this feedback data with the planned values. If an error exceeds a preset threshold, it must trigger an interlock mechanism within an extremely short time (milliseconds or even microseconds) to immediately stop the beam and prevent the delivery of erroneous doses.

[0004] The entire scanning and irradiation process places extremely stringent requirements on the real-time performance of the scanning controller and the synchronization accuracy between multiple devices. If precise time synchronization is lacking between the real-time controllers (master and slave), the electrometer, and the I / O modules after the scanning and irradiation begins, the following problems will occur: Firstly, there is a discrepancy between the actual irradiation dose and the dose setting in the scan file: Irradiation at the same scan point must be strictly performed according to the contents specified in the scan file. It is essential to ensure that the two key steps—controlling the scanning magnet to deflect the beam position and reading the beam position and dose in real time based on feedback from the ionization chamber—are strictly synchronized. If these two steps are not synchronized, the position command may have been updated to the next scan point, while the dose integration window remains at the previous scan point. This could cause the dose that should belong to the previous point to be incorrectly added to the current point, leading to inaccurate feedback dose calculation.

[0005] Secondly, the interlocking mechanism may be falsely triggered or the dose deposition may exceed the threshold: Inaccurate feedback dose calculation can lead to two consequences: on the one hand, a calculated value higher than the actual value may falsely trigger the interlocking mechanism, causing unnecessary irradiation interruption; on the other hand, a calculated value lower than the actual value may cause the dose deposition to exceed the safety threshold without timely cessation, posing a clinical safety risk. Furthermore, the master controller and slave controller must also maintain operational synchronization; otherwise, calculation deviations caused by inconsistent sampling times in the slave controller may also lead to misjudgments or missed judgments of safety interlocks. Summary of the Invention

[0006] To address the technical problems of dose deviation and interlocking misjudgment caused by the lack of precise time synchronization in existing scanning controllers, this application proposes a synchronization system, synchronization method, and parameter adaptive configuration method for pencil beam scanning controllers, which realizes unified time reference for multiple nodes, deterministic time distribution, link delay compensation, execution layer closed-loop calibration, and configurable design.

[0007] The technical solution is as follows: On the one hand, a synchronization system for a pencil beam scanning controller is provided, including: a master real-time controller, a slave real-time controller, at least one set of electrometers, and at least one set of I / O modules; The main real-time controller serves as the management node for global synchronization time and the coordination node for scan control tasks. It integrates a control unit and an onboard Time Sensitive Network (TSN) exchange unit. The real-time controller, electrometer, and I / O module serve as remote synchronization nodes, which are connected to the main real-time controller and perform sampling, output, integration, feedback calculation, and interlocking judgment based on a unified global time reference. The onboard Time-Sensitive Network (TSN) switching unit includes at least one Ethernet switching chip that supports IEEE 1588 V2 protocol hardware timestamps, a board-level synchronization clock generation and distribution circuit for providing a common reference clock for each Ethernet switching chip, and an external reference clock interface for receiving external reference clocks. The real-time controller, electrometer, and I / O module each integrate corresponding control units and onboard Precision Time (PTP) Ethernet physical layer (PHY) units. The onboard Precision Time (PTP) Ethernet Physical Layer (PHY) unit is used to hardware timestamp the precision time synchronization messages and provide the synchronized frequency reference, pulse of second (PPS), periodic trigger pulse and global timestamp register to the corresponding control unit.

[0008] In a preferred embodiment, the board-level synchronous clock generation and distribution circuit includes a highly stable local reference crystal oscillator, a clock generator, a phase-locked loop, and a low-jitter clock buffer fan-out. When the external reference source is valid, the phase-locked loop locks the external reference source and generates a board-level synchronous reference clock; when the external reference source is invalid, it switches to a highly stable local reference crystal to maintain operation. The clock buffer fanout uses equal-length or calibrated clock traces to distribute a common reference clock to each Ethernet switching chip, and writes the fixed phase deviation as a board-level fixed delay compensation parameter into the configuration table of the main real-time controller.

[0009] In a preferred embodiment, the highly stable local reference crystal oscillator is a temperature-compensated crystal oscillator (TCXO), which is used to generate a local synchronization reference when there is no external reference source input.

[0010] In a preferred embodiment, both the Ethernet switching chip and the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit are based on the IEEE 1588 V2 standard for hardware timestamp marking of synchronization messages. Each Ethernet switching chip in the onboard Time-Sensitive Network (TSN) switching unit is connected to the control unit of the main real-time controller via a high-speed interconnect interface, and establishes a physical link with each remote synchronization node via a gigabit Ethernet port.

[0011] In a preferred embodiment, the master real-time controller and the slave real-time controller are built on a field-programmable gate array (FPGA) and embedded Linux; the control units corresponding to the electrometer and I / O modules run bare-core programs or lightweight real-time operating systems.

[0012] Secondly, a synchronization method for a pencil beam scanning controller is provided, applied to the aforementioned synchronization system for a pencil beam scanning controller, including a network layer synchronization step, a link layer compensation step, and an execution layer closed-loop compensation step: The network layer synchronization steps include: the onboard time-sensitive network switching unit of the main real-time controller receives and locks an external high-precision reference source or a local reference crystal oscillator, generates a global synchronization time reference, interacts with each remote synchronization node through a precise time protocol, and uses time-aware scheduling to reserve a transmission time window for the synchronization message. The link layer compensation steps include: the onboard time-sensitive network switching unit of the main real-time controller measures the transmission path delay between itself and each remote synchronization point in real time, and corrects the synchronization error by combining the pre-calibrated link asymmetric compensation parameters, the switching chip dwell time correction amount, and the board-level fixed delay compensation parameters; the onboard precise time protocol Ethernet physical layer unit of each remote synchronization node marks the received synchronization message with a hardware timestamp at the physical layer; the control unit of each remote synchronization node calculates the phase offset and frequency deviation of the local clock relative to the master clock according to the hardware timestamp, the master clock transmission timestamp, and the link delay measurement results, and corrects the local time base through an internal digital phase-locked loop; each remote synchronization node generates a periodic trigger signal based on the corrected local time base frequency division to uniformly trigger the scan set value update, sampling, integral window switching, and interlock judgment. The execution layer closed-loop compensation step includes: while sending a physical trigger pulse to an external device, the control unit of each remote synchronization node also sends the physical trigger pulse back to the event capture pin of the onboard Precision Time Protocol Ethernet physical layer unit to capture the actual execution time; the main real-time controller calculates a compensation correction value based on the difference between the actual execution time and the expected execution time, and sends the compensation correction value to the remote node to dynamically update the sending time of the physical trigger pulse.

[0013] In a preferred embodiment, the phase offset is calculated as follows: ; In the formula, This is the local timestamp recorded by the remote synchronization node when it receives the synchronization message. The master clock timestamp recorded when the master clock sends a synchronization message. The average propagation delay of the link, This is the pre-calibrated link asymmetric compensation amount. This is the sum of the correction fields for the precise time protocol message, the correction amount for the switching chip dwell time, and other fixed path corrections.

[0014] In a preferred embodiment, the frequency deviation is calculated as follows: The frequency drift coefficient is obtained by dividing the difference between the phase offset calculated in the current synchronization cycle and the phase offset in the previous synchronization cycle by the time interval between the two synchronization cycles. The digital phase-locked loop of the FPGA in the remote synchronization node dynamically adjusts the increment step of the local time base counter according to the phase offset and the frequency drift coefficient, so as to keep the local time base aligned with the master clock in frequency and phase.

[0015] A preferred technical solution also includes open-loop manual delay compensation: The main real-time controller calculates the difference between the actual execution time and the expected execution time to obtain the current cycle error value. This error is then smoothed using an inertial filtering algorithm to obtain the compensation correction value obtained from automatic closed-loop compensation. ; in, This is the compensation correction value for automatic closed-loop compensation. These are the filter coefficients. This is the current period error value. This is the compensation correction value calculated in the previous period; Each remote synchronization node's control unit is equipped with an independent manual delay offset register for each physical trigger output channel, and the master real-time controller sends manual compensation parameters to the target slave node. The manual compensation parameters and the compensation correction values ​​obtained from automatic closed-loop compensation After superposition, the emission time of the final physical trigger pulse is obtained. : ； In the formula, For manual compensation parameters, The setting value for the expected execution time. To compensate for the correction value, This is the moment when the final physical trigger pulse is emitted.

[0016] Thirdly, a parameter adaptive configuration method for a synchronization system of a pencil beam scanning controller is provided, applied to the aforementioned synchronization system for a pencil beam scanning controller, including: Parametric modeling: The key physical quantities involved in the pencil beam scanning controller are abstracted into configurable mathematical models; wherein, the key physical quantities include at least the magnet response transfer function, the maximum network transmission delay, and the maximum phase uncertainty introduced by the cross-clock domain processing of the field-programmable gate array (FPGA).

[0017] Constraint Quantification and Tabulation: Based on the mathematical model, the final synchronization accuracy is taken as the top-level constraint, and the error budget allocation method is used to decompose it to each intermediate link step by step. A dynamic advance configuration table with the scan point index or energy layer number as the address base is established. Hardware mapping and configuration generation: Based on the dynamic advanced configuration table, configuration parameters for each hardware unit are automatically generated and written to the corresponding underlying registers through the configuration bus, thereby decoupling the synchronization strategy from the underlying hardware driver parameters; Online self-calibration and iteration: During actual operation or offline testing, the execution timestamp error of each remote synchronization node is continuously collected, and the parameters in the dynamic advance configuration table are updated in real time.

[0018] The technical solution includes at least the following technical effects: Firstly, at the network layer synchronization and link layer compensation level, the main real-time controller's built-in onboard switching unit receives and locks onto an external high-precision reference source or a local reference crystal oscillator to generate a global synchronization time base. Synchronization messages are exchanged with each remote synchronization node via a precise time protocol, and time-aware scheduling is introduced to reserve a deterministic transmission window for synchronization messages. Simultaneously, by combining pre-calibrated link asymmetric compensation parameters, switching chip dwell time corrections, and board-level fixed delay compensation parameters, the clock synchronization accuracy between multiple nodes is improved from the microsecond level of traditional solutions to the nanosecond level, resolving the issues caused by local clock frequency drift in each device. The mismatch between the dose integration window and the switching time of the scanning magnet current caused by network transmission delay uncertainty avoids dose assignment errors and inaccurate feedback dose calculations. Secondly, at the execution layer closed-loop compensation level, the physical trigger pulse issued by the FPGA in the control unit of the remote synchronization node is fed back to the event capture pin of the onboard precise-time Ethernet physical layer unit to accurately measure the actual execution time. The main real-time controller then dynamically calculates and issues compensation correction values ​​based on the difference between the actual and expected execution times using an inertial filtering algorithm, in conjunction with independent manual delay offset registers for each channel. Open-loop coarse tuning enables the system to automatically track and compensate for FPGA internal logic delay drift caused by changes in ambient temperature, device aging, and power supply voltage fluctuations, continuously converging the deviation in physical execution timing within the system's preset synchronization accuracy tolerance. Furthermore, multiple Ethernet switching chips correspond to the physical isolation architecture of different treatment rooms or equipment groups, ensuring that the fault domains of each synchronization link are independent. Network anomalies in a single treatment room will not propagate to other treatment rooms, enhancing the long-term operational reliability and availability of the system in multi-treatment-room clinical environments. Thirdly, the parameter adaptive configuration method using parametric modeling and tabular configuration abstracts key physical quantities such as the magnet response transfer function, network transmission delay, and FPGA cross-clock domain phase uncertainty into configurable mathematical models. A dynamic advance configuration table is established through error budget allocation, and underlying hardware register parameters are automatically generated, achieving complete decoupling between synchronization logic and underlying hardware. When treatment modes are upgraded or hardware platforms are iterated, there is no need to redesign the FPGA timing logic or modify the underlying firmware code; only updating the model parameters and regenerating the configuration table is required for adaptation. This shortens the product development cycle and improves the system's maintainability and cross-platform portability. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1A schematic block diagram of a board-level synchronization clock generation and distribution circuit in a synchronization system for a pencil beam scanning controller, provided as a preferred embodiment of this application; Figure 2 A schematic diagram of a synchronization system for a pencil beam scanning controller provided in a preferred embodiment of this application; Figure 3 A synchronization method flow for a pencil beam scanning controller is provided as a preferred embodiment of this application; Figure 4 A flowchart of the demodulation processing of each node in the synchronization method for a pencil beam scanning controller provided in a preferred embodiment of this application; Figure 5 This is a flowchart of a parameter adaptive configuration method for a synchronization system of a pencil beam scanning controller provided in a preferred embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Explanation of related terms: TSN (Time-Sensitive Networking) PTP (Precision Time Protocol): Precision Time Protocol; IEEE 1588 V2 / PTP (Precision Time Protocol): A precision time (PTP) protocol based on the IEEE 1588 V2 standard.

[0024] FPGA (Field-Programmable Gate Array): Field-programmable gate array.

[0025] ARM: A Reduced Instruction Set Computing (RISC) processor architecture.

[0026] PHY (Physical Layer): Physical layer (interface / transceiver). Ethernet PHY refers to the Ethernet physical layer transceiver.

[0027] ADC (Analog-to-Digital Converter): A converter that converts data from one digital source to another.

[0028] TCS (Treatment Control System): Treatment control system.

[0029] TCXO (Temperature Compensated Crystal Oscillator): Temperature-compensated crystal oscillator.

[0030] As attached Figure 2 As shown, a preferred embodiment of this application provides a synchronization system for a pencil beam scanning controller, including a master real-time controller, slave real-time controllers, at least one set of electrometers, and at least one set of I / O modules. The master real-time controller serves as the management node for global synchronization time and the coordination node for scanning control tasks; the slave real-time controllers, electrometers, and I / O modules are connected to the master real-time controller as remote synchronization nodes, and perform sampling, output, integration, feedback calculation, and interlocking judgment based on a unified global time reference.

[0031] The main real-time controller integrates a control unit and an onboard Time-Sensitive Network (TSN) switching unit.

[0032] The control unit, based on a field-programmable gate array (FPGA) and an embedded Linux operating system, is responsible for task scheduling, data processing, and communication management. In a preferred embodiment, the control unit of the main real-time controller uses a Zynq MPSoC computing platform.

[0033] The onboard TSN switching unit includes at least one Ethernet switching chip that supports IEEE 1588 V2 Precision Time Protocol (PTP) hardware timestamps, a board-level synchronous clock generation and distribution circuit for generating and distributing the same source reference clock required by each Ethernet switching chip, and an external reference clock interface for receiving external reference clocks.

[0034] The board-level synchronous clock generation and distribution circuit includes a highly stable local reference crystal oscillator, a clock generator, a phase-locked loop, and a low-jitter clock buffer fanout.

[0035] like Figure 1As shown, the external reference clock interface is used to receive accelerator synchronization timing signals or a unified clock from the treatment control system. When the external reference source is valid, the clock generator and phase-locked loop lock the external reference source and generate a board-level synchronization reference clock; when the external reference source is invalid, it switches to a highly stable local reference crystal to maintain operation. The generated board-level synchronization reference clock is sent to the reference clock input of each Ethernet switching chip via a low-jitter clock buffer fan-out.

[0036] To ensure that multiple Ethernet switching chips are in the same board-level synchronous time domain, the clock buffer fan-outer uses equal-length or calibrated clock traces to distribute the same source reference clock to each Ethernet switching chip, and writes the fixed phase deviation between each output as a board-level fixed delay compensation parameter into the configuration table of the main real-time controller.

[0037] In a preferred embodiment, the high-stability local reference crystal oscillator employs a temperature-compensated crystal oscillator (TCXO) as a low-phase-noise reference source to generate a local synchronization reference when no external reference source input is available.

[0038] In one embodiment, the onboard Time-Sensitive Networking (TSN) switching unit includes seven Ethernet switching chips. One chip is used to synchronize the real-time controller with three I / O modules, and the remaining six Ethernet switching chips correspond to six treatment rooms, with each chip responsible for synchronizing four electrometers within that treatment room. This architecture using seven Ethernet switching chips ensures that the synchronization links corresponding to each treatment room are isolated from each other at the physical layer and on the switching and forwarding path. Each Ethernet switching chip serves as a time distribution node for its corresponding partition within the same Precise Time Protocol (PTP) time domain, thus balancing physical isolation between treatment rooms, non-propagation of faults, deterministic synchronization paths, and long-term operational reliability.

[0039] Each Ethernet switching chip is connected to the control unit of the main real-time controller through a high-speed interconnect interface (such as SGMII or RGMII) to achieve high-speed interaction of clock synchronization parameters and control data. At the same time, each Ethernet switching chip establishes a physical link with each remote synchronization node (from the real-time controller, electrometer, I / O module) through the gigabit Ethernet port on the rear panel of the main real-time controller, forming a star synchronization network topology.

[0040] The real-time controller, electrometer, and I / O module each integrate corresponding control units and onboard Precision Time (PTP) Ethernet physical layer (PHY) units. The onboard Precision Time (PTP) Ethernet Physical Layer (PHY) unit is used to hardware timestamp the precision time synchronization messages and provide the synchronized frequency reference, pulse of second (PPS), periodic trigger pulse and global timestamp register to the corresponding control unit.

[0041] Both the Ethernet switching chip and the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit are based on the IEEE 1588 V2 standard for hardware timestamp marking of synchronization messages. Each Ethernet switching chip in the onboard Time-Sensitive Networking (TSN) switching unit is connected to the control unit of the main real-time controller via a high-speed interconnect interface, and establishes a physical link with each distributed node via a gigabit Ethernet port.

[0042] The master and slave real-time controllers are built on field-programmable gate arrays (FPGAs) and embedded Linux; the control units corresponding to the electrometer and I / O modules run bare-core programs or lightweight real-time operating systems. The time-critical logic related to scan setpoint updates, ADC sampling, DAC output, integral window switching, and fast interlocking is implemented in the FPGAs of the slave real-time controllers, electrometers, and I / O module control units.

[0043] The onboard Precision Time (PTP) Ethernet Physical Layer (PHY) unit is used to hardware timestamp Precision Time Protocol (PTP) synchronization messages and provide the synchronized frequency reference, PPS second pulse, periodic trigger pulse and global timestamp register to the Field Programmable Gate Array (FPGA).

[0044] like Figure 3 As shown, in another embodiment, based on the above hardware architecture, a synchronization mechanism of "network layer synchronization - link layer compensation - execution layer closed loop" is constructed, providing a synchronization method for the pencil beam scanning controller, including the following steps: The network layer synchronization steps include: the onboard time-sensitive network switching unit of the main real-time controller receives and locks an external high-precision reference source or a local reference crystal oscillator, generates a global synchronization time reference, interacts with each remote synchronization node through a precise time protocol, and uses time-aware scheduling to reserve a transmission time window for the synchronization message. The link layer compensation steps include: the onboard time-sensitive network switching unit of the main real-time controller measures the transmission path delay between itself and each remote synchronization node in real time, and corrects the synchronization error by combining pre-calibrated link asymmetric compensation parameters, Ethernet switching chip dwell time correction amount, and board-level fixed delay compensation parameters; the onboard precise time protocol Ethernet physical layer unit of each remote synchronization node marks the received synchronization message with a hardware timestamp at the physical layer; the control unit of each remote synchronization node calculates the phase offset and frequency deviation of the local clock relative to the master clock according to the hardware timestamp, the master clock transmission timestamp, and the link delay measurement results, and corrects the local time base through an internal digital phase-locked loop; each remote synchronization node generates a periodic trigger signal based on the corrected local time base frequency division to uniformly trigger the scan setpoint update, sampling, integral window switching, and interlock judgment. The execution layer closed-loop compensation step includes: while sending a physical trigger pulse to an external device, the control unit of each remote synchronization node also sends the physical trigger pulse back to the event capture pin of the onboard Precision Time Protocol Ethernet physical layer unit to capture the actual execution time; the main real-time controller calculates a compensation correction value based on the difference between the actual execution time and the expected execution time, and sends the compensation correction value to the remote synchronization node to dynamically update the sending time of the physical trigger pulse.

[0045] like Figure 4 As shown, the specific process steps are as follows: After the system starts up, the onboard TSN switching unit inside the main real-time controller operates as follows during the synchronization process: It receives and locks an external high-precision reference source or a local reference crystal oscillator, generates a global synchronization time base, and exchanges synchronization messages with each remote synchronization node through the PTP protocol.

[0046] The onboard time-sensitive network switching unit of the main real-time controller measures the transmission path delay between each remote synchronization node in real time, and corrects it by combining pre-calibrated link asymmetry compensation parameters, switching chip dwell time correction amount and board-level fixed delay compensation parameters, so as to reduce the synchronization error introduced by physical link delay, link asymmetry and fixed phase difference between chips.

[0047] The IEEE 802.1Qbv time-aware scheduling is adopted to reserve a deterministic transmission time window for PTP synchronization messages and scan synchronization control messages, thereby reducing the queuing and blocking impact of non-real-time processes (such as receiving scan files and uploading logs) on synchronization messages.

[0048] After receiving the PTP synchronization message, the onboard Precise Time (PTP) Ethernet physical layer (PHY) unit of each remote synchronization node completes the hardware timestamp marking at the physical layer. Based on this hardware timestamp and the link delay estimate obtained by the PTP Delay_Req / Delay_Resp mechanism, the FPGA of the remote node calculates the phase offset and frequency deviation of the local clock relative to the master clock, and corrects the local time base through the FPGA's internal digital phase-locked loop.

[0049] The specific demodulation process for each node is as follows: Each remote synchronization node (such as the real-time controller, I / O module, electrometer) reads the master clock transmission timestamp, remote node reception timestamp, and link delay measurement results of the PTP message from the FPGA. Combined with the fixed link delay and link asymmetry compensation parameters pre-calibrated in the configuration table, the local clock phase offset relative to the master clock is calculated.

[0050] This is the local timestamp recorded by the remote synchronization node when it receives the synchronization message. The master clock timestamp recorded when the master clock sends a synchronization message. The average propagation delay of the link, This is the pre-calibrated link asymmetric compensation amount. This includes correction fields for PTP messages, correction amounts for switch chip dwell time, and other fixed-path corrections. When the synchronization message is a single-hop or boundary clock-corrected synchronization message, the phase offset is... Represented as: ; In the formula, This is the local timestamp recorded by the remote synchronization node when it receives the synchronization message. The master clock timestamp recorded when the master clock sends a synchronization message. The average propagation delay of the link, This is the pre-calibrated link asymmetric compensation amount. This is the sum of the correction fields for the precise time protocol message, the correction amount for the switching chip dwell time, and other fixed path corrections.

[0051] The FPGA of each remote synchronization node will calculate the phase offset during the current synchronization cycle. Phase offset from the previous synchronization cycle The difference, divided by the time interval between two synchronization cycles, yields the frequency drift coefficient. .

[0052] FPGA digital phase-locked loop according to and frequency drift coefficient The increment step size of the local time base counter is dynamically adjusted to keep the local time base aligned with the master clock in frequency and phase. When the phase offset exceeds the preset threshold or the PTP lock state is lost, the node enters a synchronization abnormal state and triggers a beamout prohibition or interlocking process.

[0053] Each node generates a scan timeslice period trigger signal based on the corrected local global time base frequency division, which is used to uniformly trigger the update of the scan magnet setpoint, ionization chamber sampling, dose integration window switching, and rapid interlock judgment.

[0054] Each remote synchronization node's FPGA generates a synchronization frequency reference, a PPS second pulse, or a periodic trigger pulse based on the corrected local global time base. The synchronization frequency reference is used for the operation or frequency division of local time-critical logic; the PPS second pulse is used for time counter alignment and synchronization status monitoring; and the periodic trigger pulse is used to trigger the node's sampling, output, integration, and interlocking actions.

[0055] Due to cross-clock domain transitions, logic path delays, interface driver delays, and peripheral response delays within the FPGA, the network layer time synchronization accuracy may exhibit deterministic or slowly drifting time deviations when mapped to the actual physical output. This application utilizes the event capture function of the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit to perform closed-loop back-injection calibration on the actual execution pulses (such as DAC output lock signals, ADC conversion start signals, and integrator reset signals) emitted by each node FPGA.

[0056] While sending physical trigger pulses to the scanning magnet power supply, ionization chamber integrating circuit, or other external devices, each node's FPGA also feeds back the pulse signal to the event capture input pin of the local onboard Precision Time (PTP) Ethernet physical layer (PHY) unit. Upon detecting the rising edge of the pulse, the current global timestamp is captured in a register and subsequently uploaded to the main real-time controller via Ethernet or local bus.

[0057] The main real-time controller receives and summarizes feedback from each node, and determines the actual execution time. With the expected execution time The difference is calculated to obtain the execution time error. The compensation correction value is obtained by smoothing the process using an inertial filtering algorithm: ; in, This is the compensation correction value for automatic closed-loop compensation. For smoothing coefficients, This is the current period error value. The compensation correction value calculated in the previous cycle is dynamically updated by sending messages to each node.

[0058] Based on the above closed-loop injection and dynamic compensation mechanism, even if the internal logic delay of the FPGA drifts due to changes in ambient temperature, device aging, or power supply voltage fluctuations, the synchronization system can still converge the deviation of the physical execution time to within the system's preset synchronization accuracy tolerance within several synchronization cycles.

[0059] As a supplement to the aforementioned automatic closed-loop compensation, this application also provides open-loop manual delay compensation to address the deterministic dynamic response delay introduced by factors such as differences in physical cable length, inherent response time differences of actuators, or differences in wiring between channels among slave devices. Specifically, in the FPGA of each remote synchronization node, an independent manual delay offset register is configured for each physical trigger output channel. This register uses nanoseconds as the minimum step unit, supports online reading and writing via the configuration bus, and stores user-defined additional lead or lag delay values.

[0060] During the offline debugging or calibration phase of the system, operators can send manual compensation parameters to the target slave nodes through the main real-time controller. The manual compensation parameter is compared with the compensation correction value obtained from the aforementioned automatic closed-loop calculation. After superposition, the emission time of the final physical trigger pulse is obtained. : ; In the formula, For manual compensation parameters, The setting value for the expected execution time. To compensate for the correction value, This is the moment when the final physical trigger pulse is emitted.

[0061] In summary, this application innovatively constructs a three-layer collaborative architecture of "network layer synchronization—link layer compensation—execution layer closed loop" for the specific application scenario of pencil beam scanning control in proton therapy: the onboard time-sensitive network switching unit of the main real-time controller interacts with each remote synchronization node through a precise time protocol to exchange synchronization messages, measures the transmission path delay between each remote synchronization node in real time, and corrects the synchronization error by combining pre-calibrated link asymmetric compensation parameters, switching chip dwell time correction, and board-level fixed delay compensation parameters; each remote synchronization node communicates through the onboard precise time (PTP) Ethernet physical layer (… The PHY unit marks synchronization messages with hardware timestamps at the physical layer. Combining the master clock transmission timestamp and link delay measurement results, it calculates the phase offset and frequency deviation. The local time base is then dynamically corrected by the FPGA's internal digital phase-locked loop, improving multi-node clock synchronization accuracy from microseconds to nanoseconds in traditional solutions. Furthermore, by redirecting the physical trigger pulses emitted by the FPGA back to the event capture pin of the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit, the actual execution time is accurately measured. The main real-time controller then sends out the data based on the difference between the actual and expected times, after inertial filtering. The compensation correction value, combined with independent manual delay offset registers for each channel, achieves closed-loop adaptive compensation for FPGA internal logic path delay, interface driver delay, and peripheral response delay drift, ensuring that the deviation of physical execution time continuously converges within the system's preset tolerance. In addition, the physical isolation architecture of multiple Ethernet switching chips corresponding to different treatment rooms or equipment groups makes each synchronous link fault domain independent of each other, and network anomalies in a single treatment room will not spread to other treatment rooms, significantly enhancing the long-term operational reliability in clinical multi-treatment room environments. At the same time, the parameter adaptive configuration method of parameterized modeling and tabular configuration provided in the third aspect abstracts key physical quantities such as magnet response transfer function, network transmission delay, and FPGA cross-clock domain phase uncertainty into configurable mathematical models. By establishing a dynamic advance configuration table through error budget allocation and automatically generating underlying hardware register parameters, the synchronous logic and underlying hardware are completely decoupled. When the treatment mode is upgraded or the hardware platform is iterated, there is no need to redesign the FPGA timing logic. Only the model parameters need to be updated and the configuration table needs to be regenerated to complete the adaptation, which greatly shortens the development cycle and improves the system's maintainability and cross-platform portability.

[0062] like Figure 5 As shown, in another embodiment, a parameter adaptive configuration method for a synchronization system of a pencil beam scanning controller is provided, applied to the above-described synchronization system for a pencil beam scanning controller, comprising the following steps: Parametric modeling: Key physical quantities involved in the synchronization system are abstracted into configurable mathematical models. These mathematical models include at least: the magnet response transfer function (including the relationship between rise time and current amplitude and energy layer), the maximum network transmission delay of the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit, and the maximum phase uncertainty introduced by cross-clock domain processing within the FPGA. All model parameters are exposed to upper-layer software in the form of registers or configuration tables, supporting online reading, writing, and dynamic modification. The key physical quantities include at least the magnet response transfer function, the maximum network transmission delay, and the maximum phase uncertainty introduced by cross-clock domain processing within the FPGA.

[0063] Constraint Quantification and Tabulation: Based on the mathematical model, the final synchronization accuracy required for clinical / physical procedures is taken as the top-level constraint, and an error budget allocation method is used to decompose it step by step to each intermediate link (such as network jitter, local clock skew, and magnet rising edge dispersion). A dynamic advance configuration table is established with scan point index or energy layer number as the addressing base address, and the error budget of each link is converted into specific advance compensation parameters, which are pre-stored in the memory of the real-time controller.

[0064] Hardware mapping and configuration generation: Based on the dynamic advance configuration table, the system automatically generates PTP domain scheduling parameters for the TSN switching chip and synchronization trigger pulse phase offsets for the onboard Precision Time (PTP) Ethernet Physical Layer (PHY) units of each node. During FPGA startup, these parameters are written to the internal registers of the onboard Time Sensitive Network (TSN) switching units and onboard Precision Time (PTP) Ethernet Physical Layer (PHY) units via a configuration bus (such as AXI-Lite), achieving complete decoupling between the synchronization strategy and the underlying hardware driver parameters.

[0065] Online self-calibration and iteration: During actual operation or offline testing, the FPGA periodically uploads the timestamp error (i.e., the difference between the set execution time and the actual capture time) of each irradiation action recorded by the onboard Precision Time (PTP) Ethernet physical layer (PHY) unit to the main real-time controller. The main real-time controller uses an inertial filtering algorithm to smooth the error sequence and updates the parameters in the dynamic advance configuration table in real time, enabling the synchronization system to have long-term adaptive capabilities to hardware aging, temperature drift, and changes in beam conditions.

[0066] The aforementioned parameter adaptive configuration method for the synchronization system achieves decoupling between the synchronization logic and the underlying hardware through parametric modeling and tabular configuration. When the treatment mode is upgraded (such as adding a FLASH mode or arc-shaped treatment mode) or the hardware platform is iterated (such as replacing different series of FPGAs or Ethernet transceiver chips), there is no need to redesign the FPGA timing logic or modify the underlying firmware code. Only the corresponding parameters in the mathematical model need to be updated and the dynamic advance configuration table needs to be regenerated to complete the rapid porting and adaptation of the synchronization system. This effectively shortens the development cycle and significantly improves the maintainability and portability of the system.

[0067] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

Claims

1. A synchronization system for a pencil beam scanning controller, characterized in that, include: A master real-time controller, slave real-time controllers, at least one set of electrometers, and at least one set of I / O modules; The main real-time controller serves as the management node for global synchronization time and the coordination node for scan control tasks. It integrates a control unit and an onboard time-sensitive network switching unit. The real-time controller, electrometer, and I / O module serve as remote synchronization nodes, which are connected to the main real-time controller and perform sampling, output, integration, feedback calculation, and interlocking judgment based on a unified global time reference. The onboard time-sensitive network switching unit includes at least one Ethernet switching chip that supports IEEE 1588 V2 protocol hardware timestamps, a board-level synchronization clock generation and distribution circuit for generating and distributing the same source reference clock required by each Ethernet switching chip, and an external reference clock interface for receiving external reference clocks. The real-time controller, electrometer, and I / O module each integrate corresponding control units and onboard precision time Ethernet physical layer units. The onboard precision time Ethernet physical layer unit is used to hardware timestamp the precision time synchronization message and provide the synchronized frequency reference, second pulse, periodic trigger pulse and global timestamp register to the corresponding control unit.

2. The synchronization system for a pencil beam scanning controller according to claim 1, characterized in that, The board-level synchronous clock generation and distribution circuit includes a highly stable local reference crystal oscillator, a clock generator, a phase-locked loop, and a low-jitter clock buffer fan-out. When the external reference source is valid, the clock generator and phase-locked loop lock the external reference source and generate a board-level synchronous reference clock; When the external reference source is invalid, switch to a highly stable local reference crystal to keep running; The clock buffer fanout uses equal-length or calibrated clock traces to distribute a common reference clock to each Ethernet switching chip, and writes the fixed phase deviation as a board-level fixed delay compensation parameter into the configuration table of the main real-time controller.

3. The synchronization system for a pencil beam scanning controller according to claim 2, characterized in that, The highly stable local reference crystal oscillator employs a temperature-compensated crystal oscillator, which is used to generate a local synchronization reference when there is no external reference source input.

4. The synchronization system for a pencil beam scanning controller according to claim 1, characterized in that, Both the Ethernet switching chip and the onboard precise time Ethernet physical layer unit are based on the IEEE 1588 V2 standard for hardware timestamp marking of synchronization messages. Each Ethernet switching chip in the onboard time-sensitive network switching unit is connected to the control unit of the main real-time controller through a high-speed interconnect interface, and establishes a physical link with each remote synchronization node through a gigabit Ethernet port.

5. The synchronization system for a pencil beam scanning controller according to claim 1, characterized in that, The master real-time controller and slave real-time controller are built on a field-programmable gate array (FPGA) and embedded Linux; the control units corresponding to the electrometer and I / O modules run bare-core programs or lightweight real-time operating systems.

6. A synchronization method for a pencil beam scanning controller, applied in the synchronization system for a pencil beam scanning controller as described in any one of claims 1 to 5, characterized in that, This includes network layer synchronization steps, link layer compensation steps, and execution layer closed-loop compensation steps: The network layer synchronization steps include: the onboard time-sensitive network switching unit of the main real-time controller receives and locks an external high-precision reference source or a local reference crystal oscillator, generates a global synchronization time reference, interacts with each remote synchronization node through a precise time protocol, and uses time-aware scheduling to reserve a transmission time window for the synchronization message. The link layer compensation steps include: the onboard time-sensitive network switching unit of the main real-time controller measures the transmission path delay between itself and each remote synchronization node in real time, and corrects the synchronization error by combining pre-calibrated link asymmetric compensation parameters, Ethernet switching chip dwell time correction amount, and board-level fixed delay compensation parameters; the onboard precise time protocol Ethernet physical layer unit of each remote synchronization node marks the received synchronization message with a hardware timestamp at the physical layer; the control unit of each remote synchronization node calculates the phase offset and frequency deviation of the local clock relative to the master clock according to the hardware timestamp, the master clock transmission timestamp, and the link delay measurement results, and corrects the local time base through an internal digital phase-locked loop; each remote synchronization node generates a periodic trigger signal based on the corrected local time base frequency division to uniformly trigger the scan set value update, sampling, integral window switching, and interlock judgment. The execution layer closed-loop compensation step includes: while sending a physical trigger pulse to an external device, the control unit of each remote synchronization node also sends the physical trigger pulse back to the event capture pin of the onboard Precision Time Protocol Ethernet physical layer unit to capture the actual execution time; the main real-time controller calculates a compensation correction value based on the difference between the actual execution time and the expected execution time, and sends the compensation correction value to the remote synchronization node to dynamically update the sending time of the physical trigger pulse.

7. The synchronization method for a pencil beam scanning controller according to claim 6, characterized in that, The phase offset is calculated as follows: ； in, This is the local timestamp recorded by the remote synchronization node when it receives the synchronization message. The master clock timestamp recorded when the master clock sends a synchronization message. The average propagation delay of the link, This is the pre-calibrated link asymmetric compensation amount. This is the sum of the correction fields for the precise time protocol message, the correction amount for the switching chip dwell time, and other fixed path corrections.

8. The synchronization method for a pencil beam scanning controller according to claim 6, characterized in that, include: The frequency deviation is calculated as follows: The frequency drift coefficient is obtained by dividing the difference between the phase offset calculated in the current synchronization cycle and the phase offset in the previous synchronization cycle by the time interval between the two synchronization cycles. The digital phase-locked loop of the FPGA in the remote synchronization node dynamically adjusts the increment step of the local time base counter according to the phase offset and the frequency drift coefficient, so as to keep the local time base aligned with the master clock in frequency and phase.

9. The synchronization method for a pencil beam scanning controller according to claim 6, characterized in that, It also includes open-loop manual delay compensation: The main real-time controller calculates the difference between the actual execution time and the expected execution time to obtain the current cycle error value. This error is then smoothed using an inertial filtering algorithm to obtain the compensation correction value obtained from automatic closed-loop compensation. ； in, This is the compensation correction value for automatic closed-loop compensation. These are the filter coefficients. This is the current period error value. This is the compensation correction value calculated in the previous period; Each remote synchronization node's control unit is equipped with an independent manual delay offset register for each physical trigger output channel, and the master real-time controller sends manual compensation parameters to the target slave node. The manual compensation parameters and the compensation correction values ​​obtained from automatic closed-loop compensation After superposition, the emission time of the final physical trigger pulse is obtained. : ； In the formula, For manual compensation parameters, The setting value for the expected execution time. To compensate for the correction value, This is the moment when the final physical trigger pulse is emitted.

10. A parameter adaptive configuration method for a synchronization system of a pencil beam scanning controller, applied to the synchronization system for a pencil beam scanning controller as described in any one of claims 1 to 6, characterized in that, include: Parametric modeling: The key physical quantities involved in the pencil beam scanning controller are abstracted into configurable mathematical models; wherein, the key physical quantities include at least the magnet response transfer function, the maximum network transmission delay, and the maximum phase uncertainty introduced by FPGA cross-clock domain processing; Constraint Quantification and Tabulation: Based on the mathematical model, the final synchronization accuracy is taken as the top-level constraint, and the error budget allocation method is used to decompose it to each intermediate link step by step. A dynamic advance configuration table with the scan point index or energy layer number as the address base is established. Hardware mapping and configuration generation: Based on the dynamic advanced configuration table, configuration parameters for each hardware unit are automatically generated and written to the corresponding underlying registers through the configuration bus, thereby decoupling the synchronization strategy from the underlying hardware driver parameters; Online self-calibration and iteration: During actual operation or offline testing, the execution timestamp error of each remote synchronization node is continuously collected, and the parameters in the dynamic advance configuration table are updated in real time.

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