A CAN bus status detection and wake-up detection circuit

Abstract

This invention relates to the field of CAN bus, specifically to a CAN bus status detection and wake-up detection circuit, including an enable signal output module, a receiving front-end module, a high-speed signal receiver, a wake-up detection comparator, and a multiplexer. The receiving front-end module includes a voltage divider unit, a switching unit, and a bias unit. The input terminal of the voltage divider unit is electrically connected to the CANL and CANH buses, and the voltage divider unit is electrically connected to the switching unit, outputting a divided voltage signal to the high-speed signal receiver and the wake-up detection comparator. The bias unit is electrically connected to the switching unit and outputs a bias voltage control to the high-speed signal receiver. The enable signal output module outputs an enable signal to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer. Common-mode voltage self-stabilization is achieved through an analog switching network directly controlled by the bus voltage divider, eliminating the need for an independent common-mode feedback amplifier and reducing area and power consumption.

Description

Technical Field

[0001] This invention relates to the field of CAN bus, and specifically to a CAN bus status detection and wake-up detection circuit. Background Technology

[0002] CAN bus is a fieldbus communication protocol widely used in automotive electronics, industrial automation, and other fields. It aims to address the high reliability and real-time communication requirements between complex electronic control units within automobiles. Its core design concept utilizes differential signal transmission and a distributed architecture to achieve efficient data interaction among multiple nodes without a central host control, offering significant advantages such as strong anti-interference capabilities, long transmission distances, and low cost. It uses twisted-pair cables as the physical medium, transmitting data through the potential difference between two signal lines (CAN_H and CAN_L). The differential signal effectively suppresses electromagnetic interference.

[0003] The CAN bus status detection and wake-up detection circuit is a core module for ensuring the reliable operation of the CAN bus system. Its design must balance real-time performance, low power consumption, and anti-interference capabilities. Traditional CAN bus status detection and wake-up detection circuits typically rely on independent common-mode feedback amplifiers to stabilize the common-mode voltage received from the front end, resulting in a larger chip area and higher power consumption. Furthermore, the need for additional buffer circuits leads to higher power consumption and latency. Summary of the Invention

[0004] The purpose of this invention is to provide a CAN bus status detection and wake-up detection circuit, which aims to improve the problems of traditional CAN bus status detection and wake-up detection circuits that usually rely on independent common-mode feedback amplifiers to stabilize the common-mode voltage of the receiving front end, resulting in large chip area and power consumption, and requiring additional buffer circuits, which leads to high power consumption and delay.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A CAN bus status detection and wake-up detection circuit includes an enable signal output module, a receiving front-end module, a high-speed signal receiver, a wake-up detection comparator, and a multiplexer. The receiving front-end module includes a voltage divider unit, a switching unit, and a bias unit. The input terminal of the voltage divider unit is electrically connected to the CANL and CANH buses. The voltage divider unit is also electrically connected to the switching unit and outputs voltage divider signals C4_IN1 and C4_IN2 to the high-speed signal receiver and the wake-up detection comparator. The bias unit is electrically connected to the switching unit, provides bias current to the switching unit, and outputs a bias voltage control to the high-speed signal receiver. The enable signal output module outputs an enable signal to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer to control the opening and closing of the receiving front-end module and the high-speed signal receiver. The output terminal of the high-speed signal receiver outputs signal MUX_D1 and the output signal MUX_D0 of the wake-up detection comparator to the input terminal of the multiplexer, and the output terminal of the multiplexer outputs signal RXD.

[0006] Furthermore, the high-speed signal receiver includes a folded common-source cascode amplifier unit, a control unit, an output receiving unit, a bias receiving unit, and a first output unit; The output terminal of the bias unit is electrically connected to the input terminal of the bias receiving unit, and the output terminal of the bias receiving unit is electrically connected to the folded common source cascode amplifier unit and the output receiving unit, providing bias current for the folded common source cascode amplifier unit and the output receiving unit; The voltage divider signals C4_IN1 and C4_IN2 and the bias voltage VB2 are input to the input terminal of the folded common source cascode amplifier unit. The output terminal of the folded common source cascode amplifier unit and the bias voltage VB1 are electrically connected to the output receiving unit. The output terminal of the output receiving unit is electrically connected to the first output unit. The first output unit outputs the signal MUX_D1 to the input terminal of the multiplexer. The enable signal output module outputs an enable signal to the control unit, and the control unit is electrically connected to the ground terminal of the folded common source common grid amplifier unit and the output receiving unit.

[0007] Furthermore, the wake-up detection comparator includes an input protection unit, a two-stage operational amplifier comparator unit, and a second output unit; External power supply VCC and bias voltage VB1 are input to the two-stage operational amplifier comparator unit; The voltage divider signals C4_IN1 and C4_IN2 are input to the input protection unit. The output terminal of the input protection unit is electrically connected to the input terminal of the second operational amplifier comparator unit. The output terminal of the second operational amplifier protection unit is electrically connected to the second output unit. The second output unit outputs the signal MUX_D0 to the input terminal of the multiplexer.

[0008] Furthermore, the voltage divider unit includes resistors R1, R2, R3, R4, R5, and R6; The bias unit includes MOSFET P0, MOSFET P3 and resistor R0; The switching unit includes MOSFETs P1, P2, N1, N2, N0, N3, and N4. One end of resistor R1 is electrically connected to the CANL bus, and the other end of resistor R1 is electrically connected to one end of resistor R3, the gate of MOSFET P2, and the gate of MOSFET N2; the other end of resistor R3 is electrically connected to one end of resistor R5, and outputs a voltage divider signal C4_IN1 to the high-speed signal receiver and wake-up detection comparator. One end of resistor R2 is electrically connected to the CANH bus, and the other end of resistor R2 is electrically connected to one end of resistor R4, the gate of MOSFET P1, and the gate of MOSFET N1; the other end of resistor R4 is electrically connected to one end of resistor R6, and outputs a voltage divider signal C4_IN2 to the high-speed signal receiver and wake-up detection comparator. An external power supply VCC is input to the drain of MOSFET P0. The source of MOSFET P0 is electrically connected to one end of resistor R0 and the source of MOSFET P3. The other end of resistor R0 is electrically connected to the gate of MOSFET P3, the gate of MOSFET P0, and the drain of MOSFET N4, and outputs a bias voltage control to the high-speed signal receiver. The drain of MOSFET P3 is electrically connected to the source of MOSFET P1 and the source of MOSFET P2. The enable signal output module outputs enable signal MUX_S1 to the gates of MOS transistor N3 and MOS transistor N4, and the enable signal output module outputs enable signal MUX_S2 to the gate of MOS transistor N0. The drain of MOS transistor N0 is electrically connected to the other end of resistor R5, the other end of resistor R6, the drain of MOS transistor P1, the drain of MOS transistor P2, the drain of MOS transistor N1, and the drain of MOS transistor N2. The drain of MOS transistor N3 is electrically connected to the source of MOS transistor N1 and the source of MOS transistor N2. The sources of MOS transistors N0, N3, and N4 are all grounded.

[0009] Furthermore, the MOSFETs P1, P2, N1, and N2 satisfy the following condition: ; Among them, W p1,2 / L p1,2 W represents the width-to-length ratio of MOSFETs P1 and P2. n1,2 / L n1,2 Vthp is the width-to-length ratio of MOSFETs N1 and N2, Vthn is the threshold voltage of the PMOS transistor, and μ is the threshold voltage of the NMOS transistor. n The electron mobility of an NMOS transistor is μ. p The electron mobility of the PMOS transistor is denoted as .

[0010] Furthermore, the folded common-source common-gate amplifier unit includes MOSFETs P5, P6, P7, P8, P12, P13, N5, N6, N7, N8, N9, N10, N11, transistor Q0, transistor Q1, and resistor R8; The control unit includes MOSFET N13, MOSFET N14 and MOSFET P11; The output receiving unit includes inverter U200 and inverter U201; The bias receiving unit includes MOS transistor P4, MOS transistor P5 and resistor R7; An external power supply VCC is input to the drain of MOSFET P4 and the source of MOSFET P11; the bias voltage control is input to the gate of MOSFET P4, one end of resistor R7, and the gate of MOSFET P5; the source of MOSFET P4 is electrically connected to the other end of resistor R7 and the source of MOSFET P5; the drain of MOSFET P5 is electrically connected to the source of MOSFET P6, the source of MOSFET P7, the source of MOSFET P8, the source of MOSFET P9, and the source of MOSFET P10. The gate and drain of MOS transistor P6 are electrically connected to the source and gate of MOS transistor N5, the gate of MOS transistor P7, and the gate of MOS transistor P8; the drain of MOS transistor N5 is electrically connected to the gate of MOS transistor P12, the gate of MOS transistor P13, and the drain of MOS transistor N6. The voltage divider signals C4_IN1 and C4_IN2 are respectively input to the base of transistor Q1 and the base of transistor Q0; the external bias voltage VB1 is input to the gate of MOSFET N15, and the external bias voltage VB2 is input to the gates of MOSFET N6, MOSFET N7, and MOSFET N8; the signal RXD is input to the gate of MOSFET N9. The drain of MOSFET P7 is electrically connected to the collector of transistor Q0 and the source of MOSFET P12; the drain of MOSFET P8 is electrically connected to the collector of transistor Q1 and the source of MOSFET P13; the drain of MOSFET P12 is electrically connected to the gate and drain of MOSFET N10 and the gate of MOSFET N11; and the drain of MOSFET P13 is electrically connected to the drain of MOSFET N11 and the gate of MOSFET N12. The emitter of transistor Q0 is electrically connected to one end of resistor R8, the emitter of transistor Q1 is electrically connected to the other end of resistor R8, the drain of MOSFET N8 and the drain of MOSFET N7, and the source of MOSFET N7 is electrically connected to the drain of MOSFET N9. The enable signal output module outputs an enable signal MUX_S1 to the gates of MOSFET N13, MOSFET N14, and MOSFET P11. The drain of MOSFET N13 is electrically connected to the sources of MOSFETs N6, N9, N8, N10, N11, and N12. The drain of MOSFET N14 is electrically connected to the gates and drains of MOSFET P9 and P10, and the source of MOSFET N14 is electrically connected to the drain of MOSFET N15. The drain of MOSFET P11 is electrically connected to the drains of MOSFET P10 and N12, and the positive terminal of inverter U200. The negative terminal of inverter U200 is electrically connected to the positive terminal of inverter U201. The negative terminal of inverter U201 outputs a signal MUX_D1 to the input of the multiplexer. The sources of both MOS transistor N15 and MOS transistor N13 are grounded.

[0011] Furthermore, the input protection unit includes MOSFETs N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, and N32. The secondary operational amplifier comparator unit includes MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, N16, N17, N18, N19, N20, Q2, Q3, and resistor R9. The second output unit includes inverter U300 and inverter U301; An external power supply VCC is input to the source of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21; an external bias voltage VB1 is input to the gate of MOSFET N16; the voltage divider signal C4_IN1 is input to the drain of MOSFETs N23 and N22, and the voltage divider signal C4_IN2 is input to the drain of MOSFETs N29 and N28. The gate and drain of MOSFET P14 are electrically connected to the gates of MOSFETs P15, P16, and P17, and the drain of MOSFET N16. The drain of MOSFET P15 is electrically connected to the gate and source of MOSFET N26 and the base of transistor Q3. The drain of MOSFET P16 is electrically connected to the gate and source of MOSFET N32 and the base of transistor Q2. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET N19 and the gate of MOSFET N20. The gate of MOSFET P18 is electrically connected to the gate and drain of MOSFET P19 and the collector of transistor Q2. The drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N17 and the gate of MOSFET N18. The gate and drain of MOSFET P20 are both electrically connected to the gate of MOSFET P21 and the collector of transistor Q3. The emitter of transistor Q2 is electrically connected to one end of resistor R9 and the drain of MOSFET N20, and the emitter of transistor Q3 is electrically connected to the other end of resistor R9. The drain of MOSFET P21 is electrically connected to the drain of MOSFET N18 and the positive terminal of inverter U300. The negative terminal of U300 is electrically connected to the positive terminal of inverter U301. The negative terminal of inverter U301 outputs the signal MUX_D0 to the input terminal of the multiplexer. The drain of MOSFET N26 is electrically connected to the gate and source of MOSFET N25; the drain of MOSFET N25 is electrically connected to the gate and source of MOSFET N24; the drain of MOSFET N24 is electrically connected to the gate and source of MOSFET N23; the gate and source of MOSFET N22 are both electrically connected to the drain of MOSFET N21; the drain of MOSFET N32 is electrically connected to the gate and source of MOSFET N31; the drain of MOSFET N31 is electrically connected to the gate and source of MOSFET N30; the drain of MOSFET N30 is electrically connected to the gate and source of MOSFET N29; and the gate and source of MOSFET N28 are both electrically connected to the drain of MOSFET N27. The source of MOSFET N16, the gate and source of MOSFET N21, the gate and source of MOSFET N27, the source of MOSFET N19, the source of MOSFET N17, the source of MOSFET N20, and the source of MOSFET N18 are all grounded.

[0012] Furthermore, the multiplexer includes MOSFETs P23, P24, P25, P26, P27, P28, P29, P30, N33, N34, N35, N36, N37, N38, N39, and N40; An external power supply VCC is input to the sources of MOSFETs P23, P24, P25, P26, P29, and P30; the signal MUX_D1 is input to the gates of MOSFETs P24 and N34; the signal MUX_S1 is input to the gates of MOSFETs P25 and N38; the signal MUX_S2 is input to the gates of MOSFETs P28 and N37; and the signal MUX_D0 is input to the gates of MOSFETs P23 and N33. The drains of MOSFET P23 and N33 are electrically connected to the gates of MOSFET P27 and N35; the drains of MOSFET P24 and N34 are electrically connected to the gates of MOSFET P26 and N36; the drain of MOSFET P25 is electrically connected to the drain of MOSFET P26, the source of MOSFET P28, and the source of MOSFET P27; the drain of MOSFET P27 is electrically connected to the drains of MOSFET P28, N35, N36, the gate of MOSFET P29, and the gate of MOSFET N39; the source of MOSFET N35 is electrically connected to the drain of MOSFET N37; and the source of MOSFET N36 is electrically connected to the drain of MOSFET N38. The drain of MOSFET P29 is electrically connected to the drain of MOSFET N39, the gate of MOSFET P30, and the gate of MOSFET N40. The drain of MOSFET P30 is electrically connected to the drain of MOSFET N40, and outputs the signal RXD. The sources of MOSFETs N33, N34, N37, N38, N39, and N40 are all grounded.

[0013] Furthermore, the enable signal output module includes inverter U100, inverter U101, inverter U103, inverter U104 and OR gate U102; An enable input signal ENA is input to the positive terminal of inverter U100. The negative terminal of inverter U100 is electrically connected to the positive terminal of inverter U101. The negative terminal of inverter U101 is electrically connected to the first input terminal of OR gate U102. An enable input signal ENB is input to the positive terminal of inverter U104. The negative terminal of inverter U104 is electrically connected to the second input terminal of OR gate U102. The output terminal of OR gate U102 is electrically connected to the positive terminal of inverter U103 and outputs an enable signal MUX_S1 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer. The negative terminal of inverter U103 outputs an enable signal MUX_S2 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer.

[0014] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: 1. Common-mode voltage self-stabilization is achieved through an analog switch network directly controlled by the bus voltage divider, eliminating the need for an independent common-mode feedback amplifier and reducing area and power consumption.

[0015] 2. The wake-up detection comparator is directly driven by bus voltage divider, which avoids the power consumption and delay caused by additional buffer circuits, while ensuring that the wake-up detection comparator can detect changes in bus status as soon as possible, thus improving the detection response speed.

[0016] 3. The enable signal output module outputs an enable signal to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer to control the opening and closing of the receiving front-end module and the high-speed signal receiver, effectively reducing standby current. At the same time, the dual comparator architecture of the high-speed signal receiver and the low-power wake-up detection comparator works together to ensure the reliability of detection. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the CAN bus status detection and wake-up detection circuit described in this invention; Figure 2 This is a circuit diagram of the receiving front-end module of the CAN bus status detection and wake-up detection circuit described in this invention; Figure 3 This is a circuit diagram of the high-speed signal receiver for the CAN bus status detection and wake-up detection circuit described in this invention; Figure 4 This is a circuit diagram of the wake-up detection comparator of the CAN bus status detection and wake-up detection circuit described in this invention; Figure 5 This is a circuit diagram of the multiplexer for the CAN bus status detection and wake-up detection circuit described in this invention. Figure 6This is a simulation diagram of the CAN bus status detection and wake-up detection circuit described in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0020] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0021] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0022] Please refer to Figure 1-6As shown, this embodiment provides a CAN bus status detection and wake-up detection circuit, including an enable signal output module, a receiving front-end module, a high-speed signal receiver, a wake-up detection comparator, and a multiplexer. The receiving front-end module includes a voltage divider unit, a switching unit, and a bias unit. The input terminal of the voltage divider unit is electrically connected to the CANL and CANH buses, and the voltage divider unit is electrically connected to the switching unit, outputting voltage divider signals C4_IN1 and C4_IN2 to the high-speed signal receiver and the wake-up detection comparator. The bias unit is electrically connected to the switching unit, providing bias current to the switching unit and outputting a bias voltage control to the high-speed signal receiver. The enable signal output module outputs an enable signal to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer, controlling the opening and closing of the receiving front-end module and the high-speed signal receiver. The output terminal of the high-speed signal receiver outputs signal MUX_D1, and the output terminal of the wake-up detection comparator outputs signal MUX_D0 to the input terminal of the multiplexer. The output terminal of the multiplexer outputs signal RXD.

[0023] In normal mode, signal MUX_S1 is high and signal MUX_S2 is low. Differential signals C4_IN1 and C4_IN2 are output from the CANH or CANL bus via the receiver front-end module. The high-speed signal receiver compares and amplifies this pair of low-voltage analog differential signals C4_IN1 and C4_IN2, converting the analog signals on the bus into digital signals. The output of the differential receiver is transmitted to the RXD pin via a multiplexer.

[0024] In standby mode, MUX_S1 is low and MUX_S2 is high. Both the receiver front-end module and the receiver are turned off. The wake-up detection comparator continuously monitors the bus, and once a valid wake-up event is detected, the multiplexer connects the output of the wake-up detection comparator to the RXD pin, which is then driven low, thus outputting a wake-up signal.

[0025] Common-mode voltage self-stabilization is achieved through an analog switch network directly controlled by the bus voltage divider, eliminating the need for a separate common-mode feedback amplifier and reducing area and power consumption. Furthermore, the wake-up detection comparator is directly driven by the bus voltage divider, avoiding the power consumption and delay caused by additional buffer circuits. At the same time, it ensures that the wake-up detection comparator can detect changes in bus status immediately, improving the detection response speed. The enable signal output module outputs an enable signal to the control terminal of the switch unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer to control the opening and closing of the receiving front-end module and the high-speed signal receiver, effectively reducing standby current. Meanwhile, the dual comparator architecture of the high-speed signal receiver and the low-power wake-up detection comparator works together to ensure the reliability of detection.

[0026] Please refer to Figure 1 As shown, the enable signal output module includes inverter U100, inverter U101, inverter U103, inverter U104 and OR gate U102; The enable input signal ENA is input to the positive terminal of inverter U100, the negative terminal of inverter U100 is electrically connected to the positive terminal of inverter U101, and the negative terminal of inverter U101 is electrically connected to the first input terminal of OR gate U102. The enable input signal ENB is input to the positive terminal of inverter U104. The negative terminal of inverter U104 is electrically connected to the second input terminal of OR gate U102. The output terminal of OR gate U102 is electrically connected to the positive terminal of inverter U103, and outputs enable signal MUX_S1 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer. The negative terminal of inverter U103 outputs enable signal MUX_S2 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer.

[0027] Please refer to Figure 1 and Figure 2 As shown, specifically, the voltage divider unit includes resistors R1, R2, R3, R4, R5, and R6; the bias unit includes MOSFETs P0 and P3 and resistor R0; and the switching unit includes MOSFETs P1, P2, N1, N2, N0, N3, and N4.

[0028] One end of resistor R1 is electrically connected to the CANL bus, and the other end of resistor R1 is electrically connected to one end of resistor R3, the gate of MOSFET P2, and the gate of MOSFET N2. The other end of resistor R3 is electrically connected to one end of resistor R5, and outputs a voltage divider signal C4_IN1 to the high-speed signal receiver and wake-up detection comparator.

[0029] One end of resistor R2 is electrically connected to the CANH bus, and the other end of resistor R2 is electrically connected to one end of resistor R4, the gate of MOSFET P1, and the gate of MOSFET N1. The other end of resistor R4 is electrically connected to one end of resistor R6, and outputs a voltage divider signal C4_IN2 to the high-speed signal receiver and wake-up detection comparator.

[0030] An external power supply VCC is input to the drain of MOSFET P0. The source of MOSFET P0 is electrically connected to one end of resistor R0 and the source of MOSFET P3. The other end of resistor R0 is electrically connected to the gate of MOSFET P3, the gate of MOSFET P0, and the drain of MOSFET N4, and outputs a bias voltage control to the high-speed signal receiver. The drain of MOSFET P3 is electrically connected to the source of MOSFET P1 and the source of MOSFET P2.

[0031] The enable signal output module outputs enable signal MUX_S1 to the gates of MOSFET N3 and MOSFET N4, and enable signal output module outputs enable signal MUX_S2 to the gate of MOSFET N0. The drain of MOSFET N0 is electrically connected to the other end of resistor R5, the other end of resistor R6, the drains of MOSFET P1, MOSFET P2, MOSFET N1, and MOSFET N2. The drain of MOSFET N3 is electrically connected to the source of MOSFET N1 and the source of MOSFET N2. The sources of MOSFET N0, MOSFET N3, and MOSFET N4 are all grounded.

[0032] MOSFET P0 and resistor R0 form a diode-connected configuration, providing a stable bias current for MOSFET P3 and outputting a bias voltage control to the high-speed signal receiver. MOSFETs P1 and N1, along with MOSFETs P2 and N2, form a switching network of two inverters. Together with a voltage divider unit, they form a feedback loop, clamping the voltage at point X to 0.5 times VCC to provide the common-mode voltage for the bus. Therefore, MOSFETs P1, P2, N1, and N2 satisfy the following condition: ; Among them, W p1,2 / L p1,2 W represents the width-to-length ratio of MOSFETs P1 and P2. n1,2 / L n1,2 Vthp is the width-to-length ratio of MOSFETs N1 and N2, Vthn is the threshold voltage of the PMOS transistor, and μ is the threshold voltage of the NMOS transistor. n The electron mobility of an NMOS transistor is μ. p The electron mobility of the PMOS transistor is denoted as .

[0033] MOSFETs N0, N3, and N4 are switching NMOS transistors. In normal mode, signal MUX_S1 is high and signal MUX_S2 is low, MOSFET N0 is off, and MOSFETs N3 and N4 are on, allowing the receiver front-end module to operate normally. In standby mode, signal MUX_S1 is low and signal MUX_S2 is high, MOSFET N0 is on, and MOSFETs N3 and N4 are off, disabling the receiver front-end module and effectively reducing standby power consumption.

[0034] Please refer to Figure 1 and Figure 3As shown, the high-speed signal receiver includes a folded cascode amplifier unit, a control unit, an output receiving unit, a bias receiving unit, and a first output unit. The output terminal of the bias unit is electrically connected to the input terminal of the bias receiving unit, and the output terminal of the bias receiving unit is electrically connected to the folded cascode amplifier unit and the output receiving unit, providing bias current to the folded cascode amplifier unit and the output receiving unit. Voltage divider signals C4_IN1 and C4_IN2 and bias voltage VB2 are input to the input terminal of the folded cascode amplifier unit. The output terminal of the folded cascode amplifier unit and the bias voltage VB1 are electrically connected to the output receiving unit, and the output terminal of the output receiving unit is electrically connected to the first output unit. The first output unit outputs signal MUX_D1 to the input terminal of the multiplexer. The enable signal output module outputs an enable signal to the control unit, and the control unit is electrically connected to the ground terminal of the folded cascode amplifier unit and the output receiving unit. The high-speed signal receiver is used for high-speed transmission of bus signals.

[0035] Specifically, the folded common-source common-gate amplifier unit includes MOSFETs P5, P6, P7, P8, P12, P13, N5, N6, N7, N8, N9, N10, and N11, transistor Q0, transistor Q1, and resistor R8; the control unit includes MOSFETs N13, N14, and P11; the output receiving unit includes inverters U200 and U201; and the bias receiving unit includes MOSFETs P4 and P5, and resistor R7.

[0036] An external power supply VCC is input to the drain of MOSFET P4 and the source of MOSFET P11. A bias voltage control is input to the gate of MOSFET P4, one end of resistor R7, and the gate of MOSFET P5. The source of MOSFET P4 is electrically connected to the other end of resistor R7 and the source of MOSFET P5. The drain of MOSFET P5 is electrically connected to the sources of MOSFETs P6, P7, P8, P9, and P10.

[0037] The gate and drain of MOSFET P6 are electrically connected to the source and gate of MOSFET N5, the gate of MOSFET P7, and the gate of MOSFET P8. The drain of MOSFET N5 is electrically connected to the gate of MOSFET P12, the gate of MOSFET P13, and the drain of MOSFET N6. Voltage divider signals C4_IN1 and C4_IN2 are input to the base of transistor Q1 and the base of transistor Q0, respectively. External bias voltage VB1 is input to the gate of MOSFET N15, and external bias voltage VB2 is input to the gates of MOSFETs N6, N7, and N8; signal RXD is input to the gate of MOSFET N9.

[0038] The drain of MOSFET P7 is electrically connected to the collector of transistor Q0 and the source of MOSFET P12. The drain of MOSFET P8 is electrically connected to the collector of transistor Q1 and the source of MOSFET P13. The drain of MOSFET P12 is electrically connected to the gate and drain of MOSFET N10 and the gate of MOSFET N11. The drain of MOSFET P13 is electrically connected to the drain of MOSFET N11 and the gate of MOSFET N12. The emitter of transistor Q0 is electrically connected to one end of resistor R8. The emitter of transistor Q1 is electrically connected to the other end of resistor R8, the drain of MOSFET N8, and the drain of MOSFET N7. The source of MOSFET N7 is electrically connected to the drain of MOSFET N9. The enable signal output module outputs an enable signal MUX_S1 to the gates of MOSFETs N13, N14, and P11. The drain of MOSFET N13 is electrically connected to the sources of MOSFETs N6, N9, N8, N10, N11, and N12. The drain of MOSFET N14 is electrically connected to the gates of MOSFETs P9 and P10. The source of MOSFET N14 is electrically connected to the drain of MOSFET N15. The drain of MOSFET P11 is electrically connected to the drain of MOSFET P10, the drain of MOSFET N12, and the positive terminal of inverter U200. The negative terminal of inverter U200 is electrically connected to the positive terminal of inverter U201. The negative terminal of inverter U201 outputs the signal MUX_D1 to the input terminal of the multiplexer. The sources of MOSFET N15 and MOSFET N13 are both grounded.

[0039] MOSFET P4 and resistor R7 form a diode connection for receiving the bias voltage control and providing bias current for MOSFET P5. MOSFET N5 uses an NMOS diode connection, utilizing the voltage drop across the body diode to adjust the gate voltage of MOSFETs P12 and P13. MOSFETs P11, N13, and N14 are all switching MOSFETs, reducing power consumption in standby mode. Bias voltage VB1 controls the gate voltage of MOSFET N15 and adjusts the mirror current flowing through MOSFETs P9 and P10. Inverters U200 and U201 shape the output voltage. In standby mode, the bias voltage control signal and the enable signal MUX_S1 control the signal receiver module to shut down, reducing circuit power consumption. Resistor R8 controls the receiver threshold voltage, and bias voltage VB2 adjusts the current flowing through resistor R8 by controlling the gate voltages of MOSFETs N7 and N8, controlling the magnitude of the hysteresis voltage. Let the total current flowing through MOSFETs N7 and N8 be ISS. When the input voltage difference between voltage divider signals C4_IN1 and C4_IN2 is V_indiff = 0.5 * ISS * R8, signal RXD is at the inversion point.

[0040] In normal mode, when the CANH and CANL buses are recessive, the input signals of transistors Q0 and Q1 are equal, the gate voltage of MOSFET N12 remains low, the output signal MUX_D1 of the high-speed signal receiver remains high, and the R signal XD is high. When the CANH and CANL buses are dominant, the input signals of transistors Q0 and Q1 are different, the output signal MUX_D1 of the high-speed signal receiver remains low, and the signal RXD is low.

[0041] When the signal RXD is high, MOSFET N9 is turned on, the total ISS current is large, and the voltage difference across resistor R8 is larger at the switching point, resulting in a higher switching point. When the signal RXD is low, MOSFET N9 is turned off, the total ISS current is small, the voltage difference across resistor R8 is smaller at the switching point, resulting in a lower switching point. This achieves input hysteresis for the high-speed signal receiver by controlling the switching state of MOSFET N9.

[0042] Please refer to Figure 1 and Figure 4 As shown, the wake-up detection comparator further includes an input protection unit, a two-stage operational amplifier comparator unit, and a second output unit. External power supply VCC and bias voltage VB1 are input to the two-stage operational amplifier comparator unit. Voltage divider signals C4_IN1 and C4_IN2 are input to the input protection unit. The output of the input protection unit is electrically connected to the input of the two-stage operational amplifier comparator unit. The output of the two-stage operational amplifier comparator unit is electrically connected to the second output unit. The second output unit outputs signal MUX_D0 to the input of the multiplexer.

[0043] Specifically, the input protection unit includes MOSFETs N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, and N32; the second-stage operational amplifier comparator unit includes MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, N16, N17, N18, N19, N20, transistor Q2, transistor Q3, and resistor R9; the second output unit includes inverters U300 and U301.

[0044] External power supply VCC is input to the sources of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21. External bias voltage VB1 is input to the gate of MOSFET N16; voltage divider signal C4_IN1 is input to the drains of MOSFETs N23 and N22, and voltage divider signal C4_IN2 is input to the drains of MOSFETs N29 and N28.

[0045] The gate and drain of MOSFET P14 are electrically connected to the gates of MOSFETs P15, P16, and P17, and the drain of MOSFET N16. The drain of MOSFET P15 is electrically connected to the gate and source of MOSFET N26 and the base of transistor Q3. The drain of MOSFET P16 is electrically connected to the gate and source of MOSFET N32 and the base of transistor Q2. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET N19 and the gate of MOSFET N20. The gate of MOSFET P18 is electrically connected to the gate and drain of MOSFET P19 and the collector of transistor Q2. The drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N17 and the gate of MOSFET N18. The gate and drain of MOSFET P20 are electrically connected to the gate of MOSFET P21 and the collector of transistor Q3. The emitter of transistor Q2 is electrically connected to one end of resistor R9 and the drain of MOSFET N20, while the emitter of transistor Q3 is electrically connected to the other end of resistor R9. The drain of MOSFET P21 is electrically connected to the drain of MOSFET N18 and the positive terminal of inverter U300. The negative terminal of U300 is electrically connected to the positive terminal of inverter U301. The negative terminal of inverter U301 outputs the signal MUX_D0 to the input of the multiplexer.

[0046] The drain of MOSFET N26 is electrically connected to the gate and source of MOSFET N25; the drain of MOSFET N25 is electrically connected to the gate and source of MOSFET N24; the drain of MOSFET N24 is electrically connected to the gate and source of MOSFET N23; the gate and source of MOSFET N22 are both electrically connected to the drain of MOSFET N21; the drain of MOSFET N32 is electrically connected to the gate and source of MOSFET N31; the drain of MOSFET N31 is electrically connected to the gate and source of MOSFET N30; the drain of MOSFET N30 is electrically connected to the gate and source of MOSFET N29; and the gate and source of MOSFET N28 are both electrically connected to the drain of MOSFET N27.

[0047] The source of MOSFET N16, the gate and source of MOSFET N21, the gate and source of MOSFET N27, the source of MOSFET N19, the source of MOSFET N17, the source of MOSFET N20, and the source of MOSFET N18 are all grounded.

[0048] The second-stage operational amplifier comparator unit serves as a wake-up detection unit. MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21 form a current mirror structure. The bias voltage VB1 controls the gate voltage of MOSFET N16 to adjust the bias current of the current mirror. Resistor R9 provides a bias current path for transistors Q2 and Q3. MOSFETs N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, and N32 are connected in diode configuration to provide input protection and clamping for the input voltage divider signals C4_IN1 and C4_IN2.

[0049] The input signal is output as MUX_D0 by the second-stage operational amplifier, and then output to the RXD pin via a multiplexer. In standby mode, if the bus CANL and bus CANH change from recessive to dominant, the output of the second-stage operational amplifier's comparator unit will flip, and the RXD pin will go low, thus serving as a wake-up signal monitor. Inverters U300 and U301 are used for output voltage shaping.

[0050] Please refer to Figure 1 and Figure 5As shown, specifically, the multiplexer includes MOSFETs P23, P24, P25, P26, P27, P28, P29, P30, N33, N34, N35, N36, N37, N38, N39, and N40.

[0051] External power supply VCC is input to the sources of MOSFETs P23, P24, P25, P26, P29, and P30. Signal MUX_D1 is input to the gates of MOSFETs P24 and N34; signal MUX_S1 is input to the gates of MOSFETs P25 and N38; signal MUX_S2 is input to the gates of MOSFETs P28 and N37; and signal MUX_D0 is input to the gates of MOSFETs P23 and N33.

[0052] The drains of MOSFETs P23 and N33 are electrically connected to the gates of MOSFETs P27 and N35, respectively. The drains of MOSFETs P24 and N34 are electrically connected to the gates of MOSFETs P26 and N36, respectively. The drain of MOSFET P25 is electrically connected to the drain of MOSFET P26, the source of MOSFET P28, and the source of MOSFET P27. The drain of MOSFET P27 is electrically connected to the drains of MOSFETs P28, N35, and N36, as well as the gates of MOSFETs P29 and N39. The source of MOSFET N35 is electrically connected to the drain of MOSFET N37, and the source of MOSFET N36 is electrically connected to the drain of MOSFET N38.

[0053] The drain of MOSFET P29 is electrically connected to the drain of MOSFET N39, the gate of MOSFET P30, and the gate of MOSFET N40. The drain of MOSFET P30 is electrically connected to the drain of MOSFET N40, and outputs the signal RXD. The sources of MOSFETs N33, N34, N37, N38, N39, and N40 are all grounded.

[0054] MOSFETs P23, N33, P24, N34, P29, N39, P30, and N40 form four inverters. MOSFETs P25, P26, P27, P28, N35, N36, N37, and N38 form a four-input NOR gate.

[0055] PIN_RXD is used to detect the bus status. In normal mode, signal MUX_S1 is high, signal MUX_S2 is low, MOSFETs P25 and N37 are off, and MOSFETs P28 and N38 are on. In dominant mode, signal MUX_D0 is high and signal MUX_D1 is low. After being output by an inverter, MOSFETs N36 and P27 are on, and MOSFETs N35 and P26 are off, resulting in a low RXD pin. Similarly, in recessive mode, RXD goes high. Likewise, in standby mode, signal MUX_S1 is low and signal MUX_S2 is high. When the bus is detected to be awakened from a recessive state, the RXD output is low; when the bus is in a recessive state and not awakened, the RXD output is high.

[0056] Please refer to the appendix. Figure 6 , attached Figure 6 This is a simulation diagram, provided by [the relevant authority]. Figure 6 As can be seen, in standby mode, the MUX_S1 signal is low, the MUX_S2 signal is high, and the input voltages of the bus CANH and CANL are approximately 2.5V under high impedance conditions. Under normal conditions, the CANH input voltage is 3.6V, and the CANL input voltage is 1.4V. When the bus CANH and CANL voltages jump from 2.5V to CANH=3.6V and CANL=1.4V, the RXD level changes from high to low. That is, when the standby mode detects that the bus has been woken up from a recessive state, the RXD pin goes low; when the bus is in a recessive state and not woken up, RXD is high.

[0057] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A CAN bus status detection and wake-up detection circuit, characterized in that, This includes an enable signal output module, a receiver front-end module, a high-speed signal receiver, a wake-up detection comparator, and a multiplexer; The receiving front-end module includes a voltage divider unit, a switching unit, and a bias unit. The input terminal of the voltage divider unit is electrically connected to the CANL and CANH buses. The voltage divider unit is also electrically connected to the switching unit and outputs voltage divider signals C4_IN1 and C4_IN2 to the high-speed signal receiver and the wake-up detection comparator. The bias unit is electrically connected to the switching unit, provides bias current to the switching unit, and outputs a bias voltage control to the high-speed signal receiver. The enable signal output module outputs an enable signal to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer to control the opening and closing of the receiving front-end module and the high-speed signal receiver. The output terminal of the high-speed signal receiver outputs signal MUX_D1 and the output signal MUX_D0 of the wake-up detection comparator to the input terminal of the multiplexer, and the output terminal of the multiplexer outputs signal RXD.

2. The CAN bus status detection and wake-up detection circuit according to claim 1, characterized in that, The high-speed signal receiver includes a folded common-source common-gate amplifier unit, a control unit, an output receiving unit, a bias receiving unit, and a first output unit; The output terminal of the bias unit is electrically connected to the input terminal of the bias receiving unit, and the output terminal of the bias receiving unit is electrically connected to the folded common source cascode amplifier unit and the output receiving unit, providing bias current for the folded common source cascode amplifier unit and the output receiving unit; The voltage divider signals C4_IN1 and C4_IN2 and the bias voltage VB2 are input to the input terminal of the folded common source cascode amplifier unit. The output terminal of the folded common source cascode amplifier unit and the bias voltage VB1 are electrically connected to the output receiving unit. The output terminal of the output receiving unit is electrically connected to the first output unit. The first output unit outputs the signal MUX_D1 to the input terminal of the multiplexer. The enable signal output module outputs an enable signal to the control unit, and the control unit is electrically connected to the ground terminal of the folded common source common grid amplifier unit and the output receiving unit.

3. The CAN bus status detection and wake-up detection circuit according to claim 1, characterized in that, The wake-up detection comparator includes an input protection unit, a two-stage operational amplifier comparator unit, and a second output unit; External power supply VCC and bias voltage VB1 are input to the two-stage operational amplifier comparator unit; The voltage divider signals C4_IN1 and C4_IN2 are input to the input protection unit. The output terminal of the input protection unit is electrically connected to the input terminal of the second operational amplifier comparator unit. The output terminal of the second operational amplifier protection unit is electrically connected to the second output unit. The second output unit outputs the signal MUX_D0 to the input terminal of the multiplexer.

4. The CAN bus status detection and wake-up detection circuit according to claim 2, characterized in that, The voltage divider unit includes resistors R1, R2, R3, R4, R5, and R6; The bias unit includes MOSFET P0, MOSFET P3 and resistor R0; The switching unit includes MOSFETs P1, P2, N1, N2, N0, N3, and N4. One end of resistor R1 is electrically connected to the CANL bus, and the other end of resistor R1 is electrically connected to one end of resistor R3, the gate of MOSFET P2, and the gate of MOSFET N2; the other end of resistor R3 is electrically connected to one end of resistor R5, and outputs a voltage divider signal C4_IN1 to the high-speed signal receiver and wake-up detection comparator. One end of resistor R2 is electrically connected to the CANH bus, and the other end of resistor R2 is electrically connected to one end of resistor R4, the gate of MOSFET P1, and the gate of MOSFET N1; the other end of resistor R4 is electrically connected to one end of resistor R6, and outputs a voltage divider signal C4_IN2 to the high-speed signal receiver and wake-up detection comparator. An external power supply VCC is input to the drain of MOSFET P0. The source of MOSFET P0 is electrically connected to one end of resistor R0 and the source of MOSFET P3. The other end of resistor R0 is electrically connected to the gate of MOSFET P3, the gate of MOSFET P0, and the drain of MOSFET N4, and outputs a bias voltage control to the high-speed signal receiver. The drain of MOSFET P3 is electrically connected to the source of MOSFET P1 and the source of MOSFET P2. The enable signal output module outputs enable signal MUX_S1 to the gates of MOS transistor N3 and MOS transistor N4, and the enable signal output module outputs enable signal MUX_S2 to the gate of MOS transistor N0. The drain of MOS transistor N0 is electrically connected to the other end of resistor R5, the other end of resistor R6, the drain of MOS transistor P1, the drain of MOS transistor P2, the drain of MOS transistor N1, and the drain of MOS transistor N2. The drain of MOS transistor N3 is electrically connected to the source of MOS transistor N1 and the source of MOS transistor N2. The sources of MOS transistors N0, N3, and N4 are all grounded.

5. The CAN bus status detection and wake-up detection circuit according to claim 4, characterized in that, The MOSFETs P1, P2, N1, and N2 satisfy the following condition: ； Among them, W p1,2 / L p1,2 W represents the width-to-length ratio of MOSFETs P1 and P2. n1,2 / L n1,2 Vthp is the width-to-length ratio of MOSFETs N1 and N2, Vthn is the threshold voltage of the PMOS transistor, and μ is the threshold voltage of the NMOS transistor. n The electron mobility of an NMOS transistor is μ. p The electron mobility of the PMOS transistor is denoted as .

6. The CAN bus status detection and wake-up detection circuit according to claim 2, characterized in that, The folded common-source common-gate amplifier unit includes MOSFETs P5, P6, P7, P8, P12, P13, N5, N6, N7, N8, N9, N10, N11, transistor Q0, transistor Q1, and resistor R8; The control unit includes MOSFET N13, MOSFET N14 and MOSFET P11; The output receiving unit includes inverter U200 and inverter U201; The bias receiving unit includes MOS transistor P4, MOS transistor P5 and resistor R7; An external power supply VCC is input to the drain of MOSFET P4 and the source of MOSFET P11; the bias voltage control is input to the gate of MOSFET P4, one end of resistor R7, and the gate of MOSFET P5; the source of MOSFET P4 is electrically connected to the other end of resistor R7 and the source of MOSFET P5; the drain of MOSFET P5 is electrically connected to the source of MOSFET P6, the source of MOSFET P7, the source of MOSFET P8, the source of MOSFET P9, and the source of MOSFET P10. The gate and drain of MOS transistor P6 are electrically connected to the source and gate of MOS transistor N5, the gate of MOS transistor P7, and the gate of MOS transistor P8; the drain of MOS transistor N5 is electrically connected to the gate of MOS transistor P12, the gate of MOS transistor P13, and the drain of MOS transistor N6. The voltage divider signals C4_IN1 and C4_IN2 are respectively input to the base of transistor Q1 and the base of transistor Q0; the external bias voltage VB1 is input to the gate of MOSFET N15, and the external bias voltage VB2 is input to the gates of MOSFET N6, MOSFET N7, and MOSFET N8; the signal RXD is input to the gate of MOSFET N9. The drain of MOSFET P7 is electrically connected to the collector of transistor Q0 and the source of MOSFET P12; the drain of MOSFET P8 is electrically connected to the collector of transistor Q1 and the source of MOSFET P13; the drain of MOSFET P12 is electrically connected to the gate and drain of MOSFET N10 and the gate of MOSFET N11; and the drain of MOSFET P13 is electrically connected to the drain of MOSFET N11 and the gate of MOSFET N12. The emitter of transistor Q0 is electrically connected to one end of resistor R8, the emitter of transistor Q1 is electrically connected to the other end of resistor R8, the drain of MOSFET N8 and the drain of MOSFET N7, and the source of MOSFET N7 is electrically connected to the drain of MOSFET N9. The enable signal output module outputs an enable signal MUX_S1 to the gates of MOSFET N13, MOSFET N14, and MOSFET P11. The drain of MOSFET N13 is electrically connected to the sources of MOSFETs N6, N9, N8, N10, N11, and N12. The drain of MOSFET N14 is electrically connected to the gates and drains of MOSFET P9 and P10, and the source of MOSFET N14 is electrically connected to the drain of MOSFET N15. The drain of MOSFET P11 is electrically connected to the drains of MOSFET P10 and N12, and the positive terminal of inverter U200. The negative terminal of inverter U200 is electrically connected to the positive terminal of inverter U201. The negative terminal of inverter U201 outputs a signal MUX_D1 to the input of the multiplexer. The sources of both MOS transistor N15 and MOS transistor N13 are grounded.

7. The CAN bus status detection and wake-up detection circuit according to claim 3, characterized in that, The input protection unit includes MOSFETs N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, and N32. The secondary operational amplifier comparator unit includes MOSFETs P14, P15, P16, P17, P18, P19, P20, P21, N16, N17, N18, N19, N20, Q2, Q3, and resistor R9. The second output unit includes inverter U300 and inverter U301; An external power supply VCC is input to the source of MOSFETs P14, P15, P16, P17, P18, P19, P20, and P21; an external bias voltage VB1 is input to the gate of MOSFET N16; the voltage divider signal C4_IN1 is input to the drain of MOSFETs N23 and N22, and the voltage divider signal C4_IN2 is input to the drain of MOSFETs N29 and N28. The gate and drain of MOSFET P14 are electrically connected to the gates of MOSFETs P15, P16, and P17, and the drain of MOSFET N16. The drain of MOSFET P15 is electrically connected to the gate and source of MOSFET N26 and the base of transistor Q3. The drain of MOSFET P16 is electrically connected to the gate and source of MOSFET N32 and the base of transistor Q2. The drain of MOSFET P17 is electrically connected to the gate and drain of MOSFET N19 and the gate of MOSFET N20. The gate of MOSFET P18 is electrically connected to the gate and drain of MOSFET P19 and the collector of transistor Q2. The drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N17 and the gate of MOSFET N18. The gate and drain of MOSFET P20 are both electrically connected to the gate of MOSFET P21 and the collector of transistor Q3. The emitter of transistor Q2 is electrically connected to one end of resistor R9 and the drain of MOSFET N20, and the emitter of transistor Q3 is electrically connected to the other end of resistor R9. The drain of MOSFET P21 is electrically connected to the drain of MOSFET N18 and the positive terminal of inverter U300. The negative terminal of U300 is electrically connected to the positive terminal of inverter U301. The negative terminal of inverter U301 outputs the signal MUX_D0 to the input terminal of the multiplexer. The drain of MOSFET N26 is electrically connected to the gate and source of MOSFET N25; the drain of MOSFET N25 is electrically connected to the gate and source of MOSFET N24; the drain of MOSFET N24 is electrically connected to the gate and source of MOSFET N23; the gate and source of MOSFET N22 are both electrically connected to the drain of MOSFET N21; the drain of MOSFET N32 is electrically connected to the gate and source of MOSFET N31; the drain of MOSFET N31 is electrically connected to the gate and source of MOSFET N30; the drain of MOSFET N30 is electrically connected to the gate and source of MOSFET N29; and the gate and source of MOSFET N28 are both electrically connected to the drain of MOSFET N27. The source of MOSFET N16, the gate and source of MOSFET N21, the gate and source of MOSFET N27, the source of MOSFET N19, the source of MOSFET N17, the source of MOSFET N20, and the source of MOSFET N18 are all grounded.

8. The CAN bus status detection and wake-up detection circuit according to claim 1, characterized in that, The multiplexer includes MOSFETs P23, P24, P25, P26, P27, P28, P29, P30, N33, N34, N35, N36, N37, N38, N39, and N40. An external power supply VCC is input to the sources of MOSFETs P23, P24, P25, P26, P29, and P30; the signal MUX_D1 is input to the gates of MOSFETs P24 and N34; the signal MUX_S1 is input to the gates of MOSFETs P25 and N38; the signal MUX_S2 is input to the gates of MOSFETs P28 and N37; and the signal MUX_D0 is input to the gates of MOSFETs P23 and N33. The drains of MOSFET P23 and N33 are electrically connected to the gates of MOSFET P27 and N35; the drains of MOSFET P24 and N34 are electrically connected to the gates of MOSFET P26 and N36; the drain of MOSFET P25 is electrically connected to the drain of MOSFET P26, the source of MOSFET P28, and the source of MOSFET P27; the drain of MOSFET P27 is electrically connected to the drains of MOSFET P28, N35, N36, the gate of MOSFET P29, and the gate of MOSFET N39; the source of MOSFET N35 is electrically connected to the drain of MOSFET N37; and the source of MOSFET N36 is electrically connected to the drain of MOSFET N38. The drain of MOSFET P29 is electrically connected to the drain of MOSFET N39, the gate of MOSFET P30, and the gate of MOSFET N40. The drain of MOSFET P30 is electrically connected to the drain of MOSFET N40, and outputs the signal RXD. The sources of MOSFETs N33, N34, N37, N38, N39, and N40 are all grounded.

9. The CAN bus status detection and wake-up detection circuit according to claim 1, characterized in that, The enable signal output module includes inverter U100, inverter U101, inverter U103, inverter U104 and OR gate U102; An enable input signal ENA is input to the positive terminal of inverter U100. The negative terminal of inverter U100 is electrically connected to the positive terminal of inverter U101. The negative terminal of inverter U101 is electrically connected to the first input terminal of OR gate U102. An enable input signal ENB is input to the positive terminal of inverter U104. The negative terminal of inverter U104 is electrically connected to the second input terminal of OR gate U102. The output terminal of OR gate U102 is electrically connected to the positive terminal of inverter U103 and outputs an enable signal MUX_S1 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer. The negative terminal of inverter U103 outputs an enable signal MUX_S2 to the control terminal of the switching unit, the control terminal of the high-speed signal receiver, and the input terminal of the multiplexer.

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