A control method for power failure recovery by an embedded controller
Patent Information
- Application Number
- CN202610848722.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-12
- Publication Date
- 2026-08-18
AI Technical Summary
然而，此类基于I2C总线和MCU的实现方案存在诸多局限性：一方面，I2C总线的通信速率和数据传输稳定性有限，在工业复杂电磁环境下易受干扰，导致掉电策略传输错误、状态检测延迟，影响Power Loss（失电恢复）控制的可靠性；另一方面，MCU芯片的功能集成度较低，需额外搭配多种外围电路实现电源监测、中断处理等功能，不仅增加了硬件设计复杂度和成本，还降低了系统的集成度和抗干扰能力，难以适配飞腾CPU在关键领域的高可靠性应用需求
本发明让飞腾CPU与EC（嵌入式控制器）协同工作，可靠实现Power Loss（失电恢复）控制功能，保障系统掉电后恢复供电时的稳定运行，避免数据丢失和系统误启动。
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Abstract
Description
Technical Field
[0001] This invention relates to a control method for power failure recovery using an embedded controller, and more particularly to a CPU-based control method for power failure recovery using an embedded controller. Background Technology
[0002] In industrial real-time applications, unattended equipment, and other scenarios, AC Power Loss control is an indispensable core technology that directly affects the operational stability and maintenance efficiency of equipment, ensures continuous system operation, and avoids data loss and equipment damage.
[0003] Because the Phytium CPU uses the ARM architecture, its boot sequence needs to be controlled by other chips such as embedded controllers (ECs). The Phytium CPU itself cannot actively emit a signal similar to the SLP_Sx signal of Intel x86 architecture CPUs, which means that the Power Loss control function commonly used in the traditional computer industry cannot be implemented on computers with Phytium CPUs.
[0004] Currently, some existing solutions for Power Loss (Power Recovery) control of Phytium CPUs use an MCU chip as an I2C slave device to communicate with the Phytium CPU and BIOS via the I2C bus, enabling functions such as power-down policy transmission, state storage, and interrupt detection. However, this I2C bus-based MCU-based implementation has several limitations: First, the communication speed and data transmission stability of the I2C bus are limited, making it susceptible to interference in complex industrial electromagnetic environments, leading to power-down policy transmission errors and state detection delays, thus affecting the reliability of Power Loss (Power Recovery) control. Second, the MCU chip has low functional integration, requiring additional peripheral circuits to implement power monitoring, interrupt handling, and other functions, which not only increases hardware design complexity and cost but also reduces system integration and anti-interference capabilities, making it difficult to meet the high reliability requirements of Phytium CPUs in critical applications.
[0005] Based on the above situation, and addressing the technical pain points of existing Phytium CPU Power Loss control schemes, such as insufficient reliability, high hardware complexity, and low integration, this paper proposes to develop a method for implementing Phytium CPU Power Loss control function based on EC chips, leveraging the advantages of EC chips. This method aims to improve system reliability, integration, and anti-interference capabilities, and adapt to the application needs of Phytium CPUs in various key fields, thus becoming an urgent technical problem to be solved. Summary of the Invention
[0006] To address the aforementioned technical problems, the purpose of this invention is to provide a control method for power loss recovery using an embedded controller.
[0007] To achieve the above objectives, the present invention adopts the following technical solution: A control method for power failure recovery using an embedded controller includes the following steps: Step 1: Use the embedded controller (EC) as a power management peripheral for the computer to establish data interaction and command communication between the computer and the embedded controller; Step 2: Define the interaction protocol instructions in the embedded controller to communicate with the computer's BIOS; Step 3: Connect AC power, and the embedded controller enters the startup program; Step 4: After the embedded controller enters the boot program, it reads the power failure recovery strategy stored in the flash memory area of the embedded controller and clarifies the user-preset power failure recovery boot rules; Step 5: Combining the effective value of power loss recovery in Step 4 and the judgment strategy of the last power-off state, the embedded controller selects whether to enter the power-on sequence to realize automatic control after the system recovers from power failure.
[0008] Preferably, in the control method for power loss recovery via an embedded controller, in step 1, the data interaction and instruction communication between the computer and the embedded controller are established by the CPU and BIOS in the computer connected to the embedded controller through the standard low pin count bus (LPC) bus protocol.
[0009] Preferably, in the control method for power loss recovery via an embedded controller, the interaction protocol instructions include a power loss recovery validity value and a previous power-off state value.
[0010] Preferably, in the control method for power loss recovery via an embedded controller, the effective power loss recovery value includes: During the power-on phase, the BIOS writes a power-loss recovery valid value of 01 to the embedded controller's flash memory via port 62 / 66; During the shutdown phase, the BIOS writes a power-loss recovery valid value of 00 to the embedded controller's flash memory via port 62 / 66; During the previous state phase, the BIOS wrote a power-off recovery valid value of 02 to the embedded controller flash memory via port 62 / 66.
[0011] Preferably, the control method for power loss recovery via an embedded controller includes the following previous state phase: The BIOS default setting indicates that the last shutdown status was an abnormal shutdown, which is then marked as abnormal. The BIOS was modified to change the last shutdown status to normal shutdown.
[0012] Preferably, in the control method for power loss recovery via an embedded controller, the judgment strategy in step 5 is as follows: 1) If it is in the normal power-on phase, it is determined to be powered on; 2) If it is in the normal shutdown phase, it is determined to be shut down; 3) If it is in the previous state stage, make a judgment based on the previous shutdown state.
[0013] Preferably, the control method for power loss recovery via an embedded controller further determines the power-off state as follows: If the device is in a normal shutdown state, it is considered to be shut down. If the device is in an abnormal shutdown state, it will be considered as powered on.
[0014] Preferably, in the control method for power failure recovery via an embedded controller, the embedded controller is connected to an external input device, and a homogeneous low pin count bus calls the external interface of the embedded controller to modify the power failure recovery strategy and query the system shutdown status in real time.
[0015] By means of the above-described solution, the present invention has at least the following advantages: This invention enables Phytium CPUs and ECs (embedded controllers) to work together to reliably implement Power Loss control, ensuring stable operation when power is restored after a power outage and preventing data loss and system restarts.
[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the principle of the present invention; Figure 2 This is a flowchart of the BIOS writing an AC power-loss recovery strategy to an embedded controller according to the present invention; Figure 3 The flowchart of the embedded controller of the present invention implementing the AC power failure recovery function is shown. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0021] Example like Figure 1 As shown, a control method for power failure recovery using an embedded controller includes the following steps: Step 1: Use the embedded controller (EC) as a power management peripheral for the computer to establish data interaction and command communication between the computer and the embedded controller; Step 2: Define the interaction protocol instructions in the embedded controller to communicate with the computer's BIOS; Step 3: Connect AC power, and the embedded controller enters the startup program; Step 4: After the embedded controller enters the boot program, it reads the power failure recovery strategy stored in the flash memory area of the embedded controller and clarifies the user-preset power failure recovery boot rules; Step 5: Combining the effective value of power loss recovery in Step 4 and the judgment strategy of the last power-off state, the embedded controller selects whether to enter the power-on sequence to realize automatic control after the system recovers from power failure.
[0022] This invention utilizes the characteristic of embedded controller (EC) Flash memory that does not lose data when power is off. It achieves data interaction and command communication between BIOS and EC through the standard LPC protocol. After the user sets the Power Loss policy in BIOS, such as Power On, Power Off, and Last State, the BIOS will write the corresponding flag to a fixed location in EC Flash memory through port 62 / 66. EC reads the flag and performs the corresponding function. like Figure 2 and Figure 3 As shown in the embodiment, in step 1, the data interaction and instruction communication between the computer and the embedded controller are established by the CPU and BIOS in the computer connecting to the embedded controller through the standard low pin count bus (LPC) bus protocol.
[0023] In this embodiment, the interaction protocol instructions include a power failure recovery validity value and a previous power-off state value, wherein the power failure recovery validity value includes: During the power-on phase, the BIOS writes a power-loss recovery valid value of 01 to the embedded controller's flash memory via port 62 / 66; During the shutdown phase, the BIOS writes a power-loss recovery valid value of 00 to the embedded controller's flash memory via port 62 / 66; During the previous state phase, the BIOS wrote a power-off recovery valid value of 02 to the embedded controller flash memory via port 62 / 66.
[0024] Meanwhile, the previous state phase included: The BIOS default setting indicates that the last shutdown status was an abnormal shutdown, which is then marked as abnormal. The BIOS was modified to change the last shutdown status to normal shutdown.
[0025] The judgment strategy in step 5 is as follows: 1) If it is in the normal power-on phase, it is determined to be powered on; 2) If it is in the normal shutdown phase, it is determined to be shut down; 3) If it is in the previous state stage, make a judgment based on the previous shutdown state.
[0026] Based on the previous shutdown status, the following judgment is made: If the device is in a normal shutdown state, it is considered to be shut down. If the device is in an abnormal shutdown state, it will be considered as powered on.
[0027] In this embodiment, the embedded controller is connected to an external input device, and the homogeneous low pin count bus calls the external interface of the embedded controller to modify the power failure recovery strategy and query the system shutdown status in real time.
[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0029] In the description of this application, it should be noted that the terms "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0030] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or vertical, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0031] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A control method for power loss recovery using an embedded controller, characterized in that, Includes the following steps: Step 1: Use the embedded controller as a power management peripheral for the computer to establish data interaction and command communication between the computer and the embedded controller; Step 2: Define the interaction protocol instructions in the embedded controller to communicate with the computer's BIOS; Step 3: Connect AC power, and the embedded controller enters the startup program; Step 4: After the embedded controller enters the boot program, it reads the power failure recovery strategy stored in the flash memory area of the embedded controller and clarifies the user-preset power failure recovery boot rules; Step 5: Combining the effective value of power loss recovery in Step 4 and the judgment strategy of the last power-off state, the embedded controller selects whether to enter the power-on sequence to realize automatic control after the system recovers from power failure.
2. The control method for power loss recovery via an embedded controller according to claim 1, characterized in that: In step 1, the data interaction and instruction communication between the computer and the embedded controller are established by the CPU and BIOS in the computer connecting to the embedded controller through the standard Low Pin Count Bus (LPC) bus protocol.
3. The control method for power loss recovery via an embedded controller according to claim 1, characterized in that: The interaction protocol instructions include the power failure recovery validity value and the last power-off status value.
4. The control method for power loss recovery via an embedded controller according to claim 3, characterized in that: The effective value for power recovery includes: During the power-on phase, the BIOS writes a power-loss recovery valid value of 01 to the embedded controller's flash memory via port 62 / 66; During the shutdown phase, the BIOS writes a power-loss recovery valid value of 00 to the embedded controller's flash memory via port 62 / 66; During the previous state phase, the BIOS wrote a power-off recovery valid value of 02 to the embedded controller flash memory via port 62 / 66.
5. The control method for power loss recovery via an embedded controller according to claim 4, characterized in that: The previous state phase included: The BIOS default setting indicates that the last shutdown status was an abnormal shutdown, which is then marked as abnormal. The BIOS was modified to change the last shutdown status to normal shutdown.
6. The control method for power loss recovery via an embedded controller according to claim 1, characterized in that: The judgment strategy in step 5 is as follows: 1) If it is in the normal power-on phase, it is determined to be powered on; 2) If it is in the normal shutdown phase, it is determined to be shut down; 3) If it is in the previous state stage, make a judgment based on the previous shutdown state.
7. The control method for power loss recovery via an embedded controller according to claim 6, characterized in that: Based on the previous shutdown status, the following judgment is made: If the device is in a normal shutdown state, it is considered to be shut down. If the device is in an abnormal shutdown state, it will be considered as powered on.
8. The control method for power loss recovery via an embedded controller according to claim 1, characterized in that: The embedded controller connects to external input devices, and the homogeneous low pin count bus calls the external interface of the embedded controller to modify the power failure recovery strategy and query the system shutdown status in real time.