Control method for logical distribution of submersible motor

Abstract

The application relates to the technical field of programmable logic controllers, and discloses a control method for logic distribution of submersible motors, which comprises the following steps: dividing a plurality of control program blocks corresponding to each submersible motor in a storage area; calculating address rearrangement pointers of each control program block based on collected current signals and phase deviation signals; constructing a dynamic scanning sequence containing address jump sequences at the starting moment of a cyclic scanning period; and calling each control program block in sequence according to the address jump sequences to recombine a physical mapping register. The application breaks the fixed time sequence layout, reduces the task scheduling time delay under the condition of multi-path fluctuation load, eliminates the processing loss and control jitter caused by frequent hard interrupts, and optimizes the effective utilization rate of tasks in a unit scanning period.

Description

Technical Field

[0001] This invention relates to a control method for logic allocation of submersible motors, belonging to the field of programmable logic controller technology. Background Technology

[0002] The current cyclic scanning control architecture based on fixed time series typically follows a fixed sequence of input refresh, step calculation, and output refresh evolution. Under steady-state conditions, it has timing determinism. In a multi-channel parallel scheduling system, the central processing unit reads the instruction code blocks corresponding to each channel in sequence according to the preset physical slot order, and completes the state transition and register rewriting. This polling method ensures the closed loop of the control path and is a commonly used control design method.

[0003] Existing technologies mostly focus on optimizing impeller profiles or adding flow channels to alleviate congestion through hardware structural modifications. These physical improvements increase manufacturing difficulty. Furthermore, software control methods also have shortcomings when facing transient load changes caused by complex water quality. For example, Chinese invention patent CN110778527B discloses a control method for a high-lift submersible pump. This method monitors the absolute value of a single-channel current and compares it to a fixed threshold to initiate a specific duration of deceleration or reverse dredging control. This method relies on the engineering premise of independent single-channel operation and a relatively stable flow field. However, in actual operating conditions with multiple parallel channels and nonlinear fluid interference, the physical impedance of each channel exhibits asynchronous and concurrent fluctuations, leading to preset misalignment. Its rigid single-variable branching mechanism and fixed time delay... The waiting logic, when multiple channels experience simultaneous parameter mutations, causes task queuing and latency accumulation in the polling addressing link. It can even lead to data stack backlog conflicts due to disordered preemption. With the deployment of multiple controlled objects in complex fluid environments, the nonlinear flow of the fluid causes asynchronous fluctuations in the physical impedance of each channel. Under transient load conditions, multiple channels simultaneously experience mutations in characteristic parameters. Since the physical address arrangement of each instruction code block in the storage space is completely fixed, the central processing unit cannot dynamically adjust the task call level within the scan cycle according to the operating conditions. This causes the control instructions corresponding to the load-changing channels to queue and wait in the instruction stack, which in turn causes the control response latency to accumulate, resulting in intermittent physical output image refresh and weakening the real-time control accuracy of the system.

[0004] Therefore, conventional methods that rely on increasing hardware computing resources or disrupting the fixed-scan architecture cannot effectively resolve the technical contradiction between fixed scan cycles and real-time response to transient load changes. Thus, the technical problem this invention aims to solve is how to reorganize the internal logical address space of the memory, combined with real-time rewriting of program jump pointers, to enable the controller to dynamically calculate control weights based on the real-time operating characteristic parameters of multiple channels and accordingly change the addressing path, thereby constructing an adaptive preemptive scheduling sequence that adapts to load changes. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A control method for logic allocation of a submersible motor, comprising the following steps:

[0006] Step S1: Collect the real-time operating current signal and real-time phase deviation signal of each controlled motor, and establish the current operating condition state vector in the memory mapping area of ​​the programmable logic controller.

[0007] Step S2: Smooth the operating condition state vector using a first-order hysteresis filtering algorithm to eliminate high-frequency electrical noise and instantaneous load spike disturbances, and generate the corresponding filter vector sequence.

[0008] Step S3: In each scan cycle of the programmable logic controller, extract the current filter operating current value and filter phase deviation value from the filter vector sequence, and calculate the dynamic control weight value corresponding to each controlled motor.

[0009] Step S4: Compare the dynamic control weight with the determined safety weight limit. When the dynamic control weight of any independent controlled motor is greater than the safety weight limit, cut off the default instruction addressing optimization path, forcibly redirect the physical addressing pointer to the front physical memory area where the emergency unload instruction block is located, and output a safety cut-off signal.

[0010] Step S5: When the dynamic control weight is within the upper limit of the safety weight, the programmable logic instruction blocks in the control task logic stack are reordered according to the size of the dynamic control weight, and a new task scheduling sequence is generated.

[0011] Step S6: According to the reconstructed task scheduling sequence, sequentially read the corresponding logical memory addresses to reassemble the physical image register, and refresh the physical output mapping table to send logical control signals to the external drive unit.

[0012] Preferably, step S2 includes the following sub-steps: step S21, obtaining the current sampling value and phase deviation sampling value for the current cycle; step S22, based on the filtered current value and filtered phase deviation value stored in historical cycles, weighting and smoothing the current sampling value according to the filter time constant range of 1ms to 5ms to generate the filtered current value for the current cycle; step S23, weighting and smoothing the phase deviation sampling value according to the filter time constant range to generate the filtered phase deviation value for the current cycle, and assembling it into a filter vector sequence; wherein, the filter time constant range is dynamically constrained by the time change rate of the current sampling value.

[0013] Preferably, step S4 includes the following sub-steps: Step S41, comparing the calculated dynamic control weights of each controlled motor with the set safety weight threshold; Step S42, when the dynamic control weight of an independent controlled motor is greater than the safety weight threshold, determining that the safety assertion is true and triggering a high-priority hardware interrupt request; Step S43, the interrupt controller responds to the hardware interrupt request, truncates the default addressing logic in the current scan cycle, jumps the program counter to the corresponding emergency unload service subroutine address, and sends a safety cut-off signal to the corresponding external drive unit.

[0014] Preferably, step S5 includes the following sub-steps: Step S51, in the logical reconstruction stage of each scan cycle, the bubble sort algorithm is called to sort the dynamic control weights of all controlled motors in descending order to establish the priority order of each controlled motor; Step S52, according to the priority order, the logical starting address of the programmable logic instruction block of each controlled motor in the memory image area is written into the reconstruction index table; Step S53, using the logical starting address and the relative offset of the programmable logic instruction block, the addressing pointer sequence in the task scheduling stack is updated and combined to form the reconstructed task scheduling sequence.

[0015] Preferably, step S6 includes the following sub-steps: step S61, according to the updated address pointer sequence, write the operation control instructions of each controlled motor into the channel output register of the programmable logic controller in sequence; step S62, call the physical bus data refresh mapping mechanism to centrally refresh the instruction data in the channel output register to the hardware output latch register, and centrally update the status of the external physical output port.

[0016] Preferably, when calculating the dynamic control weights of each controlled motor in step S3, the operating condition drift degradation degree is introduced as a correction compensation coefficient for the control weight calculation benchmark. The control method also includes the following sub-steps: Step S31, continuously record the operating deviation variance of the operating current signal of each controlled motor in the historical operating cycle, and construct a load characteristic evolution sequence in the time dimension; Step S32, calculate the operating condition drift degradation degree of each controlled motor based on the load characteristic evolution sequence; Step S33, when the operating condition drift degradation degree exceeds the determined degradation threshold upper limit, reduce the control weight calculation benchmark of the controlled motor.

[0017] Preferably, before constructing the operating condition state vector in step S1, the control method further includes the following sub-steps for providing data input: Step S11, acquiring the current analog signal and phase analog signal of the controlled motor group input by external sensors through the analog input channel of the programmable logic controller; Step S12, converting the current analog signal and phase analog signal into corresponding digital data streams through an analog-to-digital converter, writing them into the determined first high-speed sampling latch register and second high-speed sampling latch register respectively, and combining them to form the original operating condition state vector in the memory mapping area to establish the operating condition state vector.

[0018] Preferably, when calculating the dynamic control weights of each controlled motor in step S3, the total load temperature rise rate is loaded as a constraint term for the dynamic weight allocation. The control method also includes the following sub-steps: step S34, monitoring the total load temperature rise rate of the entire controlled motor group; step S35, when the total load temperature rise rate is greater than 0.5℃ / s, increasing the weighting coefficient of the phase deviation when calculating the dynamic control weights.

[0019] Preferably, after sending the logic control signal to the external drive unit in step S6, the control method further includes the following sub-steps: step S63, encapsulating the logic control signal in the refreshed physical output mapping table into a serial bus data frame; step S64, distributing the serial bus data frame to the external drive unit of each controlled motor through the industrial Ethernet bus protocol, and having the external drive unit parse the serial bus data frame and drive the corresponding controlled motor.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. In the control of the logic allocation of the submersible motor, an independent logical address space is allocated in the memory area and each control instruction block is stored discretely. With the real-time extraction of the current and phase deviation signals from multiple sampling channels, the processor dynamically calculates the control weights at the beginning of the cyclic scanning cycle. The controller updates the jump pointer in the main loop program in real time according to the high and low order of the control weights, changing the mapping arrangement of each control instruction block in the memory space. This ensures that the control instructions corresponding to the load change channel are given priority in the front refresh bit. This mechanism changes the fixed timing layout, transforms the rigid sequential scanning into working condition adaptive scheduling, effectively eliminates timing blockage caused by multi-channel concurrent changes, and improves the processing efficiency of key control tasks in a single scanning cycle.

[0022] 2. The processor periodically acquires the operating current and phase difference of multiple control channels using the input module and stores them in the register area. The processor introduces a first-order hysteresis filter to smooth the operating current and phase difference. Based on the filtered vector sequence, the processor calculates dynamic control weights containing multi-dimensional operating condition characteristics, eliminating parameter mutations caused by instantaneous electrical noise or instantaneous load spikes in the complex external fluid environment. This collaborative processing between the data level and the logic level avoids frequent reconfiguration of the instruction stack during the cyclic scan cycle, maintains the stability of the system control logic evolution process, reduces the risk of system self-oscillation caused by high-frequency mutations, and ensures the reliable operation of the overall architecture.

[0023] 3. Introduce a safety assertion check in the instruction stack refactoring logic. When the control weight value obtained by dynamic calculation exceeds the preset safety threshold, the processor directly truncates the normal address rearrangement path and forcibly calls the preset protection logic interrupt subroutine. The jump pointer bypasses the normal loop task allocation sequence and redirects the physical address pointer to the front physical memory area where the emergency unload instruction block is located. The corresponding safety cut-off signal is output to the external drive unit. This multi-layer nested interrupt protection path integrates fault determination into the underlying timing of memory addressing, eliminates the protection response delay caused by software scanning lag, and prevents timing deadlock of the control logic under high load risk environment. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the overall steps of the control method for logic allocation of a submersible motor according to the present invention.

[0025] Figure 2 This is a dynamic scheduling optimization diagram in the control method for logic allocation of submersible motors according to the present invention.

[0026] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0028] A control method for logic assignment of submersible motors includes the following steps:

[0029] Step S1: Collect the real-time operating current signal and real-time phase deviation signal of each controlled motor, and establish the current operating condition state vector in the memory mapping area of ​​the programmable logic controller.

[0030] Step S2: Smooth the operating condition state vector using a first-order hysteresis filtering algorithm to eliminate high-frequency electrical noise and instantaneous load spike disturbances, and generate the corresponding filter vector sequence.

[0031] Step S3: In each scan cycle of the programmable logic controller, extract the current filter operating current value and filter phase deviation value from the filter vector sequence, and calculate the dynamic control weight value corresponding to each controlled motor.

[0032] Step S4: Compare the dynamic control weight with the determined safety weight limit. When the dynamic control weight of any independent controlled motor is greater than the safety weight limit, cut off the default instruction addressing optimization path, forcibly redirect the physical addressing pointer to the front physical memory area where the emergency unload instruction block is located, and output a safety cut-off signal.

[0033] Step S5: When the dynamic control weight is within the upper limit of the safety weight, the programmable logic instruction blocks in the control task logic stack are reordered according to the size of the dynamic control weight, and a new task scheduling sequence is generated.

[0034] Step S6: According to the reconstructed task scheduling sequence, sequentially read the corresponding logical memory addresses to reassemble the physical image register, and refresh the physical output mapping table to send logical control signals to the external drive unit.

[0035] Preferably, step S2 includes the following sub-steps: step S21, obtaining the current sampling value and phase deviation sampling value for the current cycle; step S22, based on the filtered current value and filtered phase deviation value stored in historical cycles, weighting and smoothing the current sampling value according to the filter time constant range of 1ms to 5ms to generate the filtered current value for the current cycle; step S23, weighting and smoothing the phase deviation sampling value according to the filter time constant range to generate the filtered phase deviation value for the current cycle, and assembling it into a filter vector sequence; wherein, the filter time constant range is dynamically constrained by the time change rate of the current sampling value.

[0036] Preferably, step S4 includes the following sub-steps: Step S41, comparing the calculated dynamic control weights of each controlled motor with the set safety weight threshold; Step S42, when the dynamic control weight of an independent controlled motor is greater than the safety weight threshold, determining that the safety assertion is true and triggering a high-priority hardware interrupt request; Step S43, the interrupt controller responds to the hardware interrupt request, truncates the default addressing logic in the current scan cycle, jumps the program counter to the corresponding emergency unload service subroutine address, and sends a safety cut-off signal to the corresponding external drive unit.

[0037] Preferably, step S5 includes the following sub-steps: Step S51, in the logical reconstruction stage of each scan cycle, the bubble sort algorithm is called to sort the dynamic control weights of all controlled motors in descending order to establish the priority order of each controlled motor; Step S52, according to the priority order, the logical starting address of the programmable logic instruction block of each controlled motor in the memory image area is written into the reconstruction index table; Step S53, using the logical starting address and the relative offset of the programmable logic instruction block, the addressing pointer sequence in the task scheduling stack is updated and combined to form the reconstructed task scheduling sequence.

[0038] Preferably, step S6 includes the following sub-steps: step S61, according to the updated address pointer sequence, write the operation control instructions of each controlled motor into the channel output register of the programmable logic controller in sequence; step S62, call the physical bus data refresh mapping mechanism to centrally refresh the instruction data in the channel output register to the hardware output latch register, and centrally update the status of the external physical output port.

[0039] Preferably, when calculating the dynamic control weights of each controlled motor in step S3, the operating condition drift degradation degree is introduced as a correction compensation coefficient for the control weight calculation benchmark. The control method also includes the following sub-steps: Step S31, continuously record the operating deviation variance of the operating current signal of each controlled motor in the historical operating cycle, and construct a load characteristic evolution sequence in the time dimension; Step S32, calculate the operating condition drift degradation degree of each controlled motor based on the load characteristic evolution sequence; Step S33, when the operating condition drift degradation degree exceeds the determined degradation threshold upper limit, reduce the control weight calculation benchmark of the controlled motor.

[0040] Preferably, before constructing the operating condition state vector in step S1, the control method further includes the following sub-steps for providing data input: Step S11, acquiring the current analog signal and phase analog signal of the controlled motor group input by external sensors through the analog input channel of the programmable logic controller; Step S12, converting the current analog signal and phase analog signal into corresponding digital data streams through an analog-to-digital converter, writing them into the determined first high-speed sampling latch register and second high-speed sampling latch register respectively, and combining them to form the original operating condition state vector in the memory mapping area to establish the operating condition state vector.

[0041] Preferably, when calculating the dynamic control weights of each controlled motor in step S3, the total load temperature rise rate is loaded as a constraint term for the dynamic weight allocation. The control method also includes the following sub-steps: step S34, monitoring the total load temperature rise rate of the entire controlled motor group; step S35, when the total load temperature rise rate is greater than 0.5℃ / s, increasing the weighting coefficient of the phase deviation when calculating the dynamic control weights.

[0042] Preferably, after sending the logic control signal to the external drive unit in step S6, the control method further includes the following sub-steps: step S63, encapsulating the logic control signal in the refreshed physical output mapping table into a serial bus data frame; step S64, distributing the serial bus data frame to the external drive unit of each controlled motor through the industrial Ethernet bus protocol, and having the external drive unit parse the serial bus data frame and drive the corresponding controlled motor.

[0043] Example 1: In an industrial operation scenario involving the group control of submersible motors, the system collects the current and phase deviation signals of multiple submersible motors located in a complex fluid environment in real time and records them in the memory mapping area of ​​the programmable logic controller (PLC). When the concentration of sediment in the fluid medium fluctuates in real time, the load current of each submersible motor changes asynchronously, causing fluctuations in the physical load of each channel. The logic control unit of the PLC allocates an independent instruction block space for each submersible motor in its internal memory area and stores the control program blocks of each motor as discrete objects. The control logic periodically collects the real-time current signals of the submersible motors through the input module. and phase deviation signal ,in This is the motor number.

[0044] The processor reads the aforementioned current signal Phase deviation signal It then executes feature evaluation logic and calculates the logical weights within the current scan cycle. The process is as follows: ,in, The preset reference current value, This is the current fluctuation gain coefficient. For phase deviation gain coefficient, logic weight To characterize the degree of load anomaly of the submersible motor within the current scan cycle, in the underlying data processing of the actual controller, to ensure data determinism when parameters of different physical dimensions are superimposed, the absolute difference of current and phase deviation input to the formula are pre-processed in the internal registers using normalization mapping based on their respective rated ranges. That is, the current difference is calibrated based on the rated operating current, and the phase deviation is calibrated based on the maximum safe deviation angle. This eliminates the dimensional differences between amperes and angles at the underlying data structure, achieving unified normalization of physical dimensions at the digital logic level. The processor then uses the logical weights of each motor... The addresses of control program blocks within the memory space are remapped to generate a dynamic execution sequence. ,in, The program block index corresponding to the submersible motor is arranged in descending order of weights. This logical refactoring process is implemented by updating the program jump pointer of the programmable logic controller, which changes the logical weights. The program block address corresponding to the larger submersible motor is adjusted to the front address area of ​​the logic scan, while the program block address corresponding to the smaller submersible motor is placed in the back address area.

[0045] According to the dynamic execution sequence The programmable logic controller (PLC) sequentially reads the corresponding memory addresses, executes the corresponding control algorithms, and refreshes the physical output mapping table. When the current signal of a certain submersible motor... Significant fluctuations cause the corresponding logical weights When the preset safety weight threshold is exceeded, the processor triggers a high-priority interrupt, jumps the program counter to the emergency unload service subroutine, and outputs a safety cut-off signal to the corresponding submersible motor drive unit. Specifically, the preset safety weight threshold is set to a fixed scalar value of 10.0. This safety weight threshold is an engineering limit value calculated by substituting the maximum permissible safe overload current and the limit phase deviation boundary of the combined system into the weighting formula. When the calculated dynamic logic weight... When the threshold is exceeded and reaches 10.72 under extremely severe sediment conditions, it means that the motor has entered an irreversible stall or phase loss high-risk state. Microsecond-level cut-off protection is achieved through forced redirection of the underlying memory addressing. This dynamic mapping mechanism avoids the problem of lag response of high-load motors under fixed cyclic scanning architecture through real-time intervention of the software addressing layer, and improves the determinism of logic control and the stability of system operation in complex fluid environments.

[0046] Example 2: This example quantitatively verifies the actual performance of the submersible motor logic allocation control method on an industrial-grade submersible motor test platform. This platform includes four submersible motors with a rated power of 15.0kW, a matching variable frequency drive unit, and a test tank simulating a complex fluid environment. The programmable logic controller (PLC) communicates with the variable frequency drive unit via an Ethernet interface to execute logic allocation control. During the experiment, sediment concentrations ranging from 10.0% to 25.0% were injected into the test tank to simulate current disturbances in the submersible motor under varying load conditions. An experimental group and a control group were set up. The control group used a fixed cyclic scanning logic with a scan period of 20.0ms. The experimental group used a dynamic allocation control method, with a current sampling period of 5.0ms for each submersible motor and a phase deviation signal sampling period of 5.0ms. The current fluctuation gain coefficient of the experimental group was... Phase deviation gain coefficient .

[0047] Under conditions where the sediment concentration increased from 10.0% to 25.0%, the load on each channel fluctuated. In the control group, due to the fixed program scan cycle, the average delay from current sampling to issuing the correction command was 42.6ms when handling load anomalies, resulting in system control jitter. In the experimental group, the logical weights calculated by the processor... The logic weights of a certain motor are updated in real time according to changes in current and phase deviation, under the condition of a sediment mass concentration of 25.0%. A peak occurred, according to calculations The system indexes the motor's program blocks in real time. Mapping to the front scan queue reduced the average response latency of the channel to 8.4ms, a decrease of approximately 80.3% compared to the control group.

[0048] To verify the rationality of the parameter boundaries, an out-of-range control group was set up in the experiment. When the gain coefficient... When set to 0.1, the system's response to current fluctuations is lagging, and it cannot reorder the program stack in time during sudden load changes; when the gain coefficient is... When set to 5.0, the system frequently triggers task reordering in response to minute electrical noise, causing the logic scan pointer to jump repeatedly at high frequency, resulting in a decrease in logic execution efficiency. Experimental data shows that... Values ​​between 1.0 and 1.5 can maintain a balance between the control logic's response speed to sudden load changes and the system's resource utilization. Experimental results confirm that calculating the logic weights... The program block jump sequence is dynamically adjusted based on the weight, which can reduce the response delay of multiple loads in parallel under complex fluid conditions. The dynamic allocation control method shows better control performance than the fixed cyclic scanning logic under the environment of fluctuating sediment concentration, and the optimization space of this parameter meets the system engineering constraints.

[0049] Example 3: In the logic monitoring scenario of a deep-water pumping station, the programmable logic controller (PLC) needs to process the real-time status data of four submersible motors. Due to underwater sediment deposition, the motor operating load exhibits dynamic nonlinear characteristics, and the system faces the problem that a fixed scan cycle cannot cover sudden load responses. The PLC allocates four instruction block spaces in the program storage area, with physical addresses as follows: A logic scan control table was constructed in the register area, and the logic allocation unit reads the current value of the submersible motor. Phase deviation value And based on first-order hysteresis filtering, smooth operating condition feature values ​​are generated. and The filter input is connected to the variable frequency drive unit's data output register to acquire a digital data stream with an operating frequency of not less than 50Hz and a current measurement sampling rate of not less than 10kHz. The processing logic is as follows: calculate the difference between two consecutive cycles of operating current sampling values ​​to obtain the time change rate of the operating current sampling value. When the time change rate is greater than the set current change rate threshold, the filter time constant is linearly reduced from 5ms to 1ms to improve the response speed. In actual industrial field configurations, the set current change rate threshold is explicitly set to 15% of the rated operating current per millisecond. The basis for determining this value is that the submersible motor encounters complex current... When a sudden load change or momentary blockage of silt occurs in the body, the rate of increase of its characteristic current usually exceeds this boundary, while the rate of change caused by conventional random electrical noise is much lower than this threshold. Therefore, this specific threshold can accurately distinguish between transient electrical disturbances and substantial mechanical overloads, ensuring the accuracy of the filter time constant switching. When the time change rate is not greater than the set current change rate threshold, the filter time constant is kept at 5ms to smooth electrical noise. To eliminate the interference of grid voltage disturbances on the extraction of operating condition characteristics, grid voltage interference elimination calculation is added after filtering. Specifically, the correction formula for smoothing the operating condition current value is as follows: ,in, This represents the smoothing current value to eliminate voltage interference. This represents the smoothed operating current value obtained through filtering. Indicates the rated voltage of the motor, Ureal The value of Ureal ranges from 80% to 120% of the rated voltage. This proportional relationship eliminates spurious current fluctuations caused by bus voltage fluctuations, and the smoothed operating current value, which eliminates voltage interference, replaces the original smoothed operating current characteristic value in subsequent calculations. Logical weights... The solution procedure is as follows: ,in, For current fluctuation sensitivity coefficient, a dimensionless parameter; This is the rated operating current of the motor. This is the phase deviation sensitivity coefficient. Dimensionless parameters, logical weights This represents the task urgency of the channel in the next scan cycle. Specifically, this invention records the operating current and rated current deviation of each controlled motor at fixed scan cycles throughout the historical operating cycle, and calculates the variance of the operating deviation over several consecutive cycles. The variances obtained from each calculation are arranged in chronological order to assemble a load characteristic evolution sequence in the time dimension. Based on this, the ratio of the mean variance of this load characteristic evolution sequence within the current sliding window to the initial steady-state variance is calculated to obtain the operating condition drift degradation degree. When this ratio is greater than a preset multiple that serves as the upper limit of the degradation threshold, the operating condition drift degradation degree is obtained to quantify the degree of mechanical wear and the accumulation of mud and sand obstructions in the motor. When this ratio is greater than a clearly defined fixed degradation threshold multiple of 2.50, it indicates that the motor has experienced continuous mud and sand obstruction or mechanical wear. At this time, the system directly and proportionally reduces the current fluctuation sensitivity coefficient of the controlled motor. This control weight calculation benchmark is used to prevent faulty channels from abnormally occupying the scanning resources of normal channels. The logical allocation unit executes the address mapping reconstruction logic: Arrange in descending order to generate a mapping vector. The processor will Write to the offset register of the program jump table, update the program scan pointer, when When the order changes, the logical control flow automatically jumps to the new instruction block physical address, realizing task scheduling based on load priority.

[0050] When any channel current value Exceeding the preset physical boundary value When the processor triggers the exception handler, the system sets the corresponding error flag, stops allocating a scan time slice to that address block, redirects the logical mapping pointer to the physical memory area of ​​the emergency unload instruction block, sends a cut-off signal to the motor drive unit, and waits for the current signal to recover. During the normal fluctuation range, the processor resets the error flag and re-incorporates the logic address of the motor's control program block. Dynamic sequence, gain coefficient and The calibration procedure is as follows: Under constant flow conditions, gradually increase... Through experimental observation, when When the value is greater than 1.8, the control logic causes stack accumulation due to frequent address reordering, resulting in system response jitter; when When the value is less than 0.8, the response lag caused by sudden load changes exceeds 50.0 ms. The calibration is set to 1.25 to ensure a balance between system response sensitivity and logic scan stability. A collaborative management mechanism is established for the four-channel submersible motor group. The temperature sensor monitors the real-time temperature of the motor group at a sampling frequency of 20Hz. When the target temperature rise rate is greater than 0.5℃ / s, the phase deviation sensitivity coefficient is adjusted. Multiply by a fixed expansion factor of 1.5 to increase the task priority of the corresponding temperature rise channel. When reconstructing and generating a new task scheduling sequence, the programmable logic controller sequentially reads the logic memory address, updates the reconstructed operation control instructions to the channel output register via parallel bus writing, changes the output channel switch state and peripheral voltage duty cycle, and distributes serial bus data frames to the external drive unit via the industrial Ethernet bus protocol. The external drive unit microprocessor parses the frequency control word in the data frame, adjusts the inverter bridge pulse width modulation duty cycle in real time to change the output current frequency, and drives the corresponding submersible motor to reduce its operating speed to suppress overheating. This calibration value ensures that the proportion of logic jump overhead to the total scan time is not higher than 15.0%, and the response deviation of the system control logic under variable load environment is controlled within 10.0ms.

[0051] Example 4: During the long-term operation of the submersible motor group control system, the original instruction block address of the controller memory unit... As hardware ages, static memory offsets occur, causing misalignment between logical addressing timing and the signal response of physical actuators, resulting in execution lag. To eliminate this effect, the processor performs an initial physical baseline calibration procedure before the system enters its working state: under no-load, idle rotation conditions, test logic weight allocation is sequentially triggered for each channel, and the physical time difference between the moment the logic scan instruction is issued and the moment of the electromagnetic response current jump fed back by the corresponding drive unit is measured. Based on this, the inherent signal transmission link compensation time constant of the system can be calculated in reverse. The system will Stored in the reference compensation register, and in subsequent logical weights During the calculation, this value is used as the physical calibration parameter for the logic trigger point. The real-time solution formula has been adjusted to: ,in, To compensate for the weighting coefficient, a value of 0.50 is set to ensure that the logic scan allocation instructions can be accurately aligned with the actual electromagnetic response time of the drive mechanism.

[0052] When multi-channel data logic is injected concurrently, the processor introduces an anti-jitter procedure based on the address scan stack: the processor periodically monitors the jump frequency of the program scan pointer in the logical address space. When the pointer repeatedly jumps between two non-adjacent memory addresses at a frequency higher than 5 times per scan cycle, the processor determines that the system logic state has entered a high-frequency oscillation region. At this time, the processor starts a logic smoothing algorithm: a logic attenuation factor η based on historical weights is forcibly inserted into the rearrangement logic of the address mapping vector M', and the mapping rules are updated to... The threshold for logical address switching is smoothed, where η is 0.20. To smoothly update the new address image vector, This is the historical address mapping vector from the previous cycle. The address mapping vector is calculated in real time for the current cycle, thereby blocking the frequent out-of-order jumps in the scan pointer address space caused by instantaneous load noise. The above engineering compensation measures improve the timing control accuracy of the logic allocation control system from 10.0ms to 2.0ms, ensuring that the program execution sequence and the physical load state of the motor are consistent with high-precision timing.

[0053] Example 5: Before the submersible motor group control system is put into industrial operation, a physical baseline calibration procedure is performed to eliminate hardware timing deviations. A submersible motor is selected as the reference unit. Under the rated speed condition with zero load, the current waveform is acquired by the high-frequency data acquisition module at a sampling frequency of 100.0kHz. The processor performs FFT transformation on the current waveform, calculates the power spectral density of the main frequency component, and extracts the amplitude of the first characteristic harmonic that characterizes the electromagnetic response. After the drive unit outputs a command, the lag time of the motor current response fluctuation is measured. Under load conditions of 20.0%, 50.0%, and 80.0%, the amplitude of the first characteristic harmonic was repeatedly measured. With response lag time The compensation operator is obtained by fitting using the least squares method. ,in, This represents the load current fluctuation value. The slope of the load current fluctuation. The operator, which is the zero-point drift correction value, is stored in the controller's non-volatile memory. During this fitting process, the first characteristic harmonic amplitude... As a key boundary constraint reflecting the electromagnetic degradation and mechanical wear inside the motor, the load current fluctuation slope is determined when solving using the least squares method. With zero drift correction value The reference selection; specifically, the system pre-establishes different harmonic amplitude values. The coefficient correction mapping table at each level, when hardware aging leads to... When the slope increases, the processor increases the slope accordingly by looking up a table. The corrected weights are used to indirectly map and integrate the electromagnetic harmonic characteristics of the surface layer into the overall current fluctuation compensation operator.

[0054] During system logic scanning, the processor executes a logic state self-test procedure to eliminate timing blockages. The processor periodically monitors the jump frequency of the program scan pointer within the memory address space. When the jump frequency between two non-adjacent memory addresses exceeds 5 times per scan cycle, the processor determines that the system logic is in an oscillation range. At this point, the processor initiates a logic smoothing procedure: in the address mapping vector... Introducing a decay factor in the update logic By reconstructing mapping rules This smooths out the abrupt changes in address jumps, where With a value of 0.20, this calibration procedure and smoothing logic improve the system's logic timing control accuracy from 10.0ms to 2.0ms, ensuring that the logic scan allocation instructions can accurately align with the actual electromagnetic response time of the motor. In specific data closed-loop interactions, the compensation operator... The real-time calculated response lag time is periodically output and directly overwrites or updates the transmission link compensation time constant stored in the register. Because this time constant is used as a physical calibration parameter in real time to participate in the dynamic control weights; The correction calculation, therefore, when external load fluctuations cause a drift in the response lag time, it changes by altering... Ultimately, it directly intervened in the rearrangement depth of the main loop program's jump pointer and the reconstruction priority of the address sequence, thereby establishing a complete closed-loop adaptive adjustment link from the overall operating condition response time difference to the rewriting of the underlying memory logic address pointer.

[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A control method for logical distribution of submersible motors, characterized in that, Includes the following steps: Step S1: Collect the real-time operating current signal and real-time phase deviation signal of each controlled motor, and establish the current operating condition state vector in the memory mapping area of ​​the programmable logic controller. Step S2: Smooth the operating condition state vector using a first-order hysteresis filtering algorithm to eliminate high-frequency electrical noise and instantaneous load spike disturbances, and generate the corresponding filter vector sequence. Step S3: In each scan cycle of the programmable logic controller, extract the current filter operating current value and filter phase deviation value from the filter vector sequence, and calculate the dynamic control weight value corresponding to each controlled motor. Step S4: Compare the dynamic control weight with the determined safety weight limit. When the dynamic control weight of any independent controlled motor is greater than the safety weight limit, cut off the default instruction addressing optimization path, forcibly redirect the physical addressing pointer to the front physical memory area where the emergency unload instruction block is located, and output a safety cut-off signal. Step S5: When the dynamic control weight is within the upper limit of the safety weight, the programmable logic instruction blocks in the control task logic stack are reordered according to the size of the dynamic control weight, and a new task scheduling sequence is generated. Step S6: According to the reconstructed task scheduling sequence, sequentially read the corresponding logical memory addresses to reassemble the physical image register, and refresh the physical output mapping table to send logical control signals to the external drive unit.

2. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, Step S2 includes the following sub-steps: Step S21, obtain the current sampling value and phase deviation sampling value of the current cycle; Step S22, based on the filtered current value and filtered phase deviation value stored in the historical cycle, weight smooth the current sampling value according to the filter time constant range of 1ms to 5ms to generate the filtered current value of the current cycle; Step S23, weight smooth the phase deviation sampling value according to the filter time constant range to generate the filtered phase deviation value of the current cycle, and assemble them into a filter vector sequence; wherein, the filter time constant range is dynamically constrained by the time change rate of the current sampling value.

3. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, Step S4 includes the following sub-steps: Step S41, compare the dynamic control weights of each controlled motor obtained by the solution with the set safety weight threshold; Step S42, when the dynamic control weight of an independent controlled motor is greater than the safety weight threshold, determine that the safety assertion is true and trigger a high-priority hardware interrupt request. In step S43, the interrupt controller responds to the hardware interrupt request, truncates the default addressing logic in the current scan cycle, jumps the program counter to the address of the corresponding emergency unload service subroutine, and sends a safety cut-off signal to the corresponding external driver unit.

4. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, Step S5 includes the following sub-steps: Step S51, in the logical reconstruction stage of each scan cycle, the bubble sort algorithm is called to sort the dynamic control weights of all controlled motors in descending order to establish the priority order of each controlled motor; Step S52, according to the priority order, the logical starting address of the programmable logic instruction block of each controlled motor in the memory image area is written into the reconstruction index table; Step S53, using the logical starting address and the relative offset of the programmable logic instruction block, the addressing pointer sequence in the task scheduling stack is updated and combined to form the reconstructed task scheduling sequence.

5. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, Step S6 includes the following sub-steps: Step S61, according to the updated address pointer sequence, write the operation control instructions of each controlled motor into the channel output register of the programmable logic controller in sequence; Step S62, call the physical bus data refresh mapping mechanism to centrally refresh the instruction data in the channel output register to the hardware output latch register, and centrally update the status of the external physical output port.

6. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, When calculating the dynamic control weights of each controlled motor in step S3, the operating condition drift degradation degree is imported as a correction compensation coefficient for the control weight calculation benchmark. The control method also includes the following sub-steps: Step S31, continuously record the operating deviation variance of the operating current signal of each controlled motor in the historical operating cycle, and construct a load characteristic evolution sequence in the time dimension; Step S32, calculate the operating condition drift degradation degree of each controlled motor based on the load characteristic evolution sequence; Step S33, when the operating condition drift degradation degree exceeds the determined degradation threshold upper limit, reduce the control weight calculation benchmark of the controlled motor.

7. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, Before constructing the operating condition state vector in step S1, the control method further includes the following sub-steps for providing data input: Step S11, acquiring the current analog signal and phase analog signal of the controlled motor group input by external sensors through the analog input channel of the programmable logic controller; Step S12, converting the current analog signal and phase analog signal into corresponding digital data streams through an analog-to-digital converter, writing them into the determined first high-speed sampling latch register and second high-speed sampling latch register respectively, and combining them to form the original operating condition state vector in the memory mapping area to establish the operating condition state vector.

8. The control method for logic allocation of a submersible motor according to claim 1, characterized in that, When calculating the dynamic control weights of each controlled motor in step S3, the total load temperature rise rate is loaded as a constraint term for the dynamic weight allocation. The control method also includes the following sub-steps: Step S34, monitor the total load temperature rise rate of the entire controlled motor group; Step S35, when the total load temperature rise rate is greater than 0.5℃ / s, increase the weighting coefficient of the phase deviation when calculating the dynamic control weights.

9. A control method for logic allocation of a submersible motor according to claim 1, characterized in that, After sending the logic control signal to the external drive unit in step S6, the control method further includes the following sub-steps: Step S63, encapsulate the logic control signal in the refreshed physical output mapping table into a serial bus data frame; Step S64: The serial bus data frame is distributed to the external drive unit of each controlled motor through the industrial Ethernet bus protocol. The external drive unit parses the serial bus data frame and drives the corresponding controlled motor.

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