Parallel control method and system of formation and component equipment

Abstract

The application provides a parallel control method and system of formation and distribution equipment, wherein the method comprises the following steps: a host computer sends a first control instruction to a first DSP chip of a first formation and distribution equipment and a second DSP chip of a second formation and distribution equipment; when the level state of a fifth level signal input by a first enable end and the level state of an eighth level signal input by a second enable end satisfy that both are "1", a third output pin of a first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip, and a fourth output pin of a second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip; the first DSP chip outputs a first power transmission waveform, and the second DSP chip outputs a second power transmission waveform, so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

Description

Technical Field

[0001] This application relates to the field of battery formation and capacity testing equipment technology, and in particular to a parallel control method and system for a formation and capacity testing equipment. Background Technology

[0002] Currently, the mainstream parallel power supply technologies on the market include designating master and slave modules via button controls on the power modules, and using CAN communication or other parallel lines (drooping method / master-slave method) to detect the output current of each module and adjust its output voltage reference, utilizing slight voltage differences to balance the current. Alternatively, one power module can be designated as the master module (controlling voltage), and the other power modules as slave modules (following current).

[0003] Due to the lack of a unified microsecond-level synchronous startup signal, the DSP startup time of each power module exhibits random errors. This can cause the first power module to start to instantly bear the entire load current, triggering overcurrent protection (OCP) or even causing a system failure, while subsequent power modules have not yet started operating, resulting in poor system stability. In the breakdown capacity cabinet, the number of channels is enormous. If it is necessary to replace modules or change the number of parallel connections (e.g., from 3 parallel to 4 parallel), the traditional master-slave mode often requires resetting the DIP switches to determine which is the master and which is the slave, which is a complex operation. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a parallel control method and system for a batch capacity-breaking device. When the level of the fifth-level signal input to the first enable terminal and the level of the eighth-level signal input to the second enable terminal are both simultaneously "1", the third output pin of the first isolation chip outputs a ninth-level signal with a level of "1" to the first DSP chip, and the fourth output pin of the second isolation chip outputs a tenth-level signal with a level of "1" to the second DSP chip. The first DSP chip outputs a first power transmission waveform, and the second DSP chip outputs a second power transmission waveform, ensuring that the interval between the output of the first power transmission waveform and the output of the second power transmission waveform by the first DSP chip is less than a preset threshold. By employing this application, on the one hand, it ensures that all parallel DSP chips receive the start-up command at the same time (nanosecond / microsecond level error) and simultaneously output power transmission waveforms, fundamentally eliminating instantaneous circulating current and uneven current distribution caused by the start-up time difference of different power modules, thus protecting the power devices. On the other hand, the first DSP chip and the second DSP chip are connected by a CAN bus, a first switch control circuit, a second switch control circuit, a third switch control circuit and a fourth switch control circuit; the host computer can send a first control command to the first DSP chip and the second DSP chip to determine whether the first formation and capacity testing device and the second formation and capacity testing device can work in parallel without manual modification of the hardware jumpers.

[0005] In a first aspect, this application provides a parallel control method for a chemical separation and capacity testing device, comprising:

[0006] The host computer sends first control commands via twisted-pair cables to the first DSP chip of the first formation and capacity testing device, the second DSP chip of the second formation and capacity testing device, the first switch control circuit, the second switch control circuit, the third switch control circuit, and the fourth switch control circuit. A CAN bus connects the first and second DSP chips. The first formation and capacity testing device also includes: a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit. The second formation and capacity testing device also includes: a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit. The CAN bus includes: a first differential signal line, a second differential signal line, a power line, and a ground line. The first and fifth switch control circuits are located on the first differential signal line, the second and sixth switch control circuits are located on the second differential signal line, the third and seventh switch control circuits are located on the power line, and the fourth and eighth switch control circuits are located on the ground line.

[0007] In response to the received first control command, the first DSP chip sends a first-level signal to the first switch control circuit via the first differential signal line to control the first switch control circuit to turn on, sends a first-level signal to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on, sends a first-level signal to the third switch control circuit via the power line to control the third switch control circuit to turn on, and sends a first-level signal to the fourth switch control circuit via the ground line to control the fourth switch control circuit to turn on, with the level state of the first-level signal being "1"; In response to the received first control command, the second DSP chip sends a second-level signal to the fifth switch control circuit via the first differential signal line, to the sixth switch control circuit via the second differential signal line, to the seventh switch control circuit via the power line, and to the eighth switch control circuit via the ground line to control the fifth, sixth, seventh, and eighth switch control circuits to turn off respectively; the level state of the second-level signal is "0" to realize parallel operation of the first and second formation capacity testing devices;

[0008] The host computer sends the second control command to the first DSP chip and the second DSP chip respectively;

[0009] In response to the received second control command, the first DSP chip inputs a third-level signal to the first isolation chip through the first input pin, outputs a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then outputs a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit. In response to the received second control command, the second DSP chip inputs a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second formation and capacity-setting device, outputs a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then outputs an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit. The first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are all connected on a common line.

[0010] When the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip, and the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip.

[0011] In response to receiving a ninth-level signal with a level of "1", the first DSP chip outputs a first power transmission waveform. In response to receiving a tenth-level signal with a level of "1", the second DSP chip outputs a second power transmission waveform, so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

[0012] In conjunction with the first aspect, in one alternative implementation,

[0013] The first switch control circuit includes: a first input terminal connected to a first DSP chip; a first MOSFET, a first optocoupler, a second MOSFET, and a third MOSFET; a first power supply and a second power supply for supplying power to the first switch control circuit, respectively.

[0014] The gate (G) of the first MOSFET is connected to the first input terminal, the source (S) of the first MOSFET is grounded, the drain (D) of the first MOSFET is connected to the first terminal of the first optocoupler, the second terminal of the first optocoupler is also connected to the gates of the second and third MOSFETs respectively, the gates of the second and third MOSFETs are directly connected, the sources of the second and third MOSFETs are directly connected, the third terminal of the first optocoupler is connected to the first power supply through the first resistor, and the fourth terminal of the first optocoupler is connected to the second power supply through the second resistor.

[0015] In conjunction with the first aspect, in one alternative implementation,

[0016] The first DSP chip sends a first level signal to the first switch control circuit via a first differential signal line to control the first switch control circuit to turn on, specifically including:

[0017] The first DSP chip sends a first-level signal to the first input terminal of the first switch control circuit of the first formation and capacity device via the first differential signal line of the CAN bus. When the first-level signal is input to the gate of the first MOSFET, the drain and source of the first MOSFET are connected, causing the first optocoupler to work and output an eleventh-level signal to the gates of the second and third MOSFETs respectively, triggering the connection between the drain and source of the second MOSFET and between the drain and source of the third MOSFET, thus realizing the short-circuit conduction of the first switch control circuit. The level state of the eleventh-level signal is "1".

[0018] In conjunction with the first aspect, in one alternative implementation,

[0019] The first synchronization circuit includes: a second input terminal connected to the first DSP chip, a fourth MOSFET, a fifth MOSFET, a third power supply, a fourth power supply for supplying power to the first synchronization circuit, and a first output terminal; wherein...

[0020] The gate (G) of the fourth MOSFET is connected to the second input terminal, the source (S) of the fourth MOSFET is grounded, the drain (D) of the fourth MOSFET is connected to the gate (G) of the fifth MOSFET, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the first output terminal, the first output terminal is also connected to the first enable terminal of the first isolation chip, the drain (D) of the fourth MOSFET is also connected to the third power supply through the third resistor, and the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fourth resistor.

[0021] In conjunction with the first aspect, in one alternative implementation,

[0022] When the level state of the fourth level signal is "1",

[0023] After the fourth-level signal is output to the first synchronization circuit through the first output pin of the first isolation chip, the fifth-level signal is output to the first enable pin of the first isolation chip through the first output terminal of the first synchronization circuit, specifically including:

[0024] The fourth level signal is output through the first output pin of the first isolation chip to the second input terminal of the first synchronization circuit. When the fourth level signal is input to the gate of the fourth MOSFET, the drain and source of the fourth MOSFET are short-circuited and grounded, so that the gate of the fifth MOSFET is input to the twelfth level signal, triggering the disconnection between the drain and source of the fifth MOSFET, and triggering the first output terminal of the first synchronization circuit to output the fifth level signal to the first enable terminal of the first isolation chip.

[0025] The level of the twelfth level signal is "0", and the level of the fifth level signal is "1".

[0026] In conjunction with the first aspect, in one alternative implementation,

[0027] The second synchronization circuit includes: a third input terminal connected to the second DSP chip, a sixth MOSFET, a seventh MOSFET, a fifth power supply, a sixth power supply for powering the second synchronization circuit, and a second output terminal; wherein...

[0028] The gate (G) of the fifth MOSFET is connected to the third input terminal, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the gate (G) of the sixth MOSFET, the source (S) of the sixth MOSFET is grounded, the drain (D) of the sixth MOSFET is connected to the second output terminal, the second output terminal is also connected to the second enable terminal of the second isolation chip, the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fifth resistor, and the drain (D) of the sixth MOSFET is also connected to the fifth power supply through the sixth resistor.

[0029] In conjunction with the first aspect, in one alternative implementation,

[0030] When the level state of the seventh level signal is "1",

[0031] After the seventh-level signal is output to the second synchronization circuit through the second output pin of the second isolation chip, the eighth-level signal is output to the second enable pin of the second isolation chip through the second output terminal of the second synchronization circuit, specifically including:

[0032] The second output pin of the second isolation chip outputs a seventh-level signal to the third input of the second synchronization circuit. When the gate of the sixth MOSFET receives a seventh-level signal, the drain and source of the sixth MOSFET are short-circuited and grounded, causing the gate of the seventh MOSFET to receive a thirteenth-level signal. This triggers the disconnection between the drain and source of the seventh MOSFET, which in turn triggers the second output of the second synchronization circuit to output an eighth-level signal to the second enable pin of the second isolation chip.

[0033] The thirteenth level signal has a level of "0", and the eighth level signal has a level of "1".

[0034] In conjunction with the first aspect, in one alternative implementation,

[0035] The preset threshold is 1 microsecond.

[0036] In conjunction with the first aspect, in one alternative implementation,

[0037] The second switch control circuit includes: a fourth input terminal connected to the first DSP chip; an eighth MOSFET, a second optocoupler, a ninth MOSFET, and a tenth MOSFET; and a seventh power supply and an eighth power supply for supplying power to the second switch control circuit respectively.

[0038] The gate (G) of the eighth MOSFET is connected to the fourth input terminal, the source (S) of the eighth MOSFET is grounded, the drain (D) of the eighth MOSFET is connected to the first terminal of the second optocoupler, the second terminal of the second optocoupler is also connected to the gate (G) of the ninth MOSFET and the gate (G) of the tenth MOSFET, the source (S) of the ninth MOSFET is connected to the source (S) of the tenth MOSFET, the third terminal of the second optocoupler is connected to the seventh power supply through the seventh resistor, and the fourth terminal of the second optocoupler is connected to the eighth power supply through the eighth resistor.

[0039] In conjunction with the first aspect, in one alternative implementation,

[0040] A first-level signal is sent to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on. Specifically, this includes:

[0041] The first level signal is sent to the fourth input terminal of the second switch control circuit of the first formation and capacity device via the second differential signal line of the CAN bus. When the first level signal is input to the gate of the eighth MOSFET, the drain and source of the eighth MOSFET are connected, which makes the second optocoupler work and outputs the fourteenth level signal to the gate of the ninth MOSFET and the gate of the tenth MOSFET respectively, triggering the connection between the drain and source of the ninth MOSFET and the connection between the drain and source of the tenth MOSFET, realizing the short circuit of the second switch control circuit. The level state of the fourteenth level signal is "1".

[0042] In conjunction with the first aspect, in one alternative implementation,

[0043] The third switch control circuit includes: a fifth input terminal connected to the first DSP chip; an eleventh MOSFET; a third optocoupler; a twelfth MOSFET; a thirteenth MOSFET; and a ninth and tenth power supply units for supplying power to the third switch control circuit, respectively.

[0044] The gate (G) of the eleventh MOSFET is connected to the fifth input terminal, the source (S) of the eleventh MOSFET is grounded, the drain (D) of the eleventh MOSFET is connected to the first terminal of the third optocoupler, the second terminal of the third optocoupler is also connected to the gates of the twelfth and thirteenth MOSFETs respectively, the gates of the twelfth and thirteenth MOSFETs are directly connected, the sources of the twelfth and thirteenth MOSFETs are directly connected, the third terminal of the third optocoupler is connected to the ninth power supply through the ninth resistor, and the tenth resistor at the fourth terminal of the third optocoupler is connected to the tenth power supply.

[0045] In conjunction with the first aspect, in one alternative implementation,

[0046] Sending a first-level signal to the third switch control circuit via the power line to control the third switch control circuit to turn on, specifically including:

[0047] The first level signal is sent to the fifth input terminal of the third switch control circuit of the first formation and capacity device via the power line of the CAN bus. When the first level signal is input to the gate of the eleventh MOSFET, the drain and source of the eleventh MOSFET are connected, which makes the third optocoupler work and outputs the fifteenth level signal to the gate of the twelfth MOSFET and the gate of the thirteenth MOSFET respectively, triggering the connection between the drain and source of the twelfth MOSFET and the connection between the drain and source of the thirteenth MOSFET, realizing the short circuit of the third switch control circuit. The level state of the fifteenth level signal is "1".

[0048] In conjunction with the first aspect, in one alternative implementation,

[0049] The fourth switch control circuit includes: a sixth input terminal connected to the first DSP chip; a fourteenth MOSFET; a fourth optocoupler; a fifteenth MOSFET; a sixteenth MOSFET; and an eleventh and twelfth power supply for supplying power to the fourth switch control circuit, respectively.

[0050] The gate (G) of the fourteenth MOSFET is connected to the sixth input terminal, the source (S) of the fourteenth MOSFET is grounded, the drain (D) of the fourteenth MOSFET is connected to the first terminal of the fourth optocoupler, the second terminal of the fourth optocoupler is also connected to the gates of the fifteenth and sixteenth MOSFETs respectively, the gates of the fifteenth and sixteenth MOSFETs are directly connected, the sources of the fifteenth and sixteenth MOSFETs are directly connected, the third terminal of the fourth optocoupler is connected to the eleventh power supply through the eleventh resistor, and the twelfth resistor at the fourth terminal of the fourth optocoupler is connected to the twelfth power supply.

[0051] In conjunction with the first aspect, in one alternative implementation,

[0052] Sending a first-level signal to the fourth switch control circuit via the ground wire to control the fourth switch control circuit to turn on, specifically including:

[0053] A first-level signal is sent to the sixth input terminal of the fourth switch control circuit of the first formation and capacity device via the ground line of the CAN bus. When the first-level signal is input to the gate of the fourteenth MOSFET, the drain and source of the fourteenth MOSFET are connected, causing the fourth optocoupler to work and output a sixteenth-level signal to the gates of the fifteenth and sixteenth MOSFETs respectively. This triggers the connection between the drain and source of the fifteenth MOSFET and the connection between the drain and source of the sixteenth MOSFET, thus achieving short-circuit conduction of the fourth switch control circuit. The level of the sixteenth-level signal is "1".

[0054] Secondly, this application provides a parallel control method for a chemical separation and capacity testing device, comprising:

[0055] The system includes a host computer, a first formation and capacity testing device, a second formation and capacity testing device, a twisted pair cable, and a CAN bus. The first formation and capacity testing device further includes: a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit. The second formation and capacity testing device further includes: a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit. The CAN bus includes: a first differential signal line, a second differential signal line, a power line, and a ground line. The system also includes: a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit. A CAN bus connects the first DSP chip and the second DSP chip.

[0056] The host computer is used to send first control commands to the first DSP chip of the first formation and capacity device and the second DSP chip of the second formation and capacity device respectively via twisted pair cables.

[0057] The first DSP chip is configured to: in response to a received first control command, send a first level signal to a first switch control circuit via a first differential signal line to control the first switch control circuit to turn on; send a first level signal to a second switch control circuit via a second differential signal line to control the second switch control circuit to turn on; send a first level signal to a third switch control circuit via a power line to control the third switch control circuit to turn on; and send a first level signal to a fourth switch control circuit via a ground line to control the fourth switch control circuit to turn on, wherein the level state of the first level signal is "1";

[0058] The second DSP chip is used to: respond to a received first control command by sending a second-level signal to the fifth switch control circuit via a first differential signal line, sending a second-level signal to the sixth switch control circuit via a second differential signal line, sending a second-level signal to the seventh switch control circuit via a power line, and sending a second-level signal to the eighth switch control circuit via a ground line, so as to control the fifth, sixth, seventh, and eighth switch control circuits to be disconnected respectively; the level state of the second-level signal is "0" to realize parallel operation of the first and second formation capacity devices;

[0059] The host computer is also used to: send second control commands to the first DSP chip and the second DSP chip respectively;

[0060] The first DSP chip is also used to: in response to a received second control command, input a third level signal to the first isolation chip through the first input pin of the first isolation chip;

[0061] The first isolation chip is used to: output a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then output a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit.

[0062] The second DSP chip is also used to: in response to a received second control command, input a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second conversion and capacity device;

[0063] The first isolation chip is used to: output a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then output an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit; wherein the first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are connected in a common line;

[0064] The first isolation chip is also used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip.

[0065] The second isolation chip is also used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip.

[0066] The first DSP chip is also used to: output a first power transmission waveform in response to receiving a ninth level signal with a level state of "1";

[0067] The second DSP chip is also used to: in response to receiving a tenth-level signal with a level state of "1", output a second power transmission waveform, so as to ensure that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

[0068] Compared to existing technologies, in this application, the first switch control circuit, the second switch control circuit, the third switch control circuit, the fourth switch control circuit, the fifth switch control circuit, the sixth switch control circuit, the seventh switch control circuit, the eighth switch control circuit, the first synchronization circuit, and the second synchronization circuit are all original designs. When the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip, and the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip. The first DSP chip outputs a first power transmission waveform, and the second DSP chip outputs a second power transmission waveform, so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold. By employing this application, on the one hand, it ensures that all parallel DSP chips receive the start command at the same moment (nanosecond / microsecond level error) and simultaneously output power transmission waveforms, fundamentally eliminating instantaneous circulating current and uneven current distribution caused by the start-up time difference of different power modules, thus protecting power devices. On the other hand, the first DSP chip and the second DSP chip are connected by a CAN bus, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit; a first control command can be sent from the host computer to the first DSP chip and the second DSP chip to determine whether the first and second formation and capacity testing devices should operate in parallel, without the need for manual modification of the hardware jumpers. Attached Figure Description

[0069] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a schematic flowchart of a parallel control method for a chemical separation and capacity testing device provided in this application;

[0071] Figure 2 This is a schematic diagram of a parallel control system for a chemical separation and capacity testing device provided in this application;

[0072] Figure 3 This is a schematic diagram of a switch control circuit in a first type of formation and capacity device provided in this application;

[0073] Figure 4 This is a schematic diagram of the connection of the first synchronization circuit in a first formation and capacity-building device provided in this application;

[0074] Figure 5 This is a schematic diagram of the connection of the second synchronization circuit in a second formation and capacity device provided in this application. Detailed Implementation

[0075] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] It should be noted that the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth," "ninth," "tenth," "eleventh," "twelfth," "thirteenth," "fourteenth," "fifteenth," and "sixteenth" in this application are only used to distinguish different MOS transistors, optocouplers, DSP chips, input terminals, switch control circuits, isolation chips, enable terminals, input terminals, output terminals, batching and capping devices, level signals, control commands, differential signal lines, power supplies, resistors, etc., and have no other special meanings, and should not limit the scope of protection of this application.

[0077] Figure 1 This is a flowchart illustrating a dual-model prediction method.

[0078] This can be combined with the appendix in this application. Figure 1 The parallel control method for a chemical separation and capacity testing device provided in this application may include, but is not limited to, the following steps:

[0079] S101, the host computer sends the first control command to the first DSP chip of the first formation and capacity device and the second DSP chip of the second formation and capacity device respectively via twisted pair cable.

[0080] In this application, there are a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit; a CAN bus connects the first DSP (Digital Signal Processor) chip and the second DSP chip; the first formation and capacity testing device may also include, but is not limited to, a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit; the second formation and capacity testing device may also include, but is not limited to, a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit; the CAN bus includes, a first differential signal line, a second differential signal line, a power line, and a ground line; the first and fifth switch control circuits are both located on the first differential signal line, the second and sixth switch control circuits are both located on the second differential signal line, the third and seventh switch control circuits are both located on the power line, and the fourth and eighth switch control circuits are both located on the ground line;

[0081] It should be noted that the first control command can be used to: indicate that the first, second, third, and fourth switch control circuits in the first formation and capacity setting device are all turned on, and to indicate that the fifth, sixth, seventh, and eighth switch control circuits in the second formation and capacity setting device are all turned off.

[0082] Optionally, the twisted pair in this application may include, but is not limited to, RS485 cables.

[0083] S102. In response to the received first control command, the first DSP chip sends a first level signal to the first switch control circuit via the first differential signal line to control the first switch control circuit to turn on, sends a first level signal to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on, sends a first level signal to the third switch control circuit via the power line to control the third switch control circuit to turn on, and sends a first level signal to the fourth switch control circuit via the ground line to control the fourth switch control circuit to turn on; In response to the received first control command, the second DSP chip sends a second level signal to the fifth switch control circuit via the first differential signal line, sends a second level signal to the sixth switch control circuit via the second differential signal line, sends a second level signal to the seventh switch control circuit via the power line, and sends a second level signal to the eighth switch control circuit via the ground line to control the fifth, sixth, seventh, and eighth switch control circuits to turn off respectively.

[0084] In this application, the level state of the first level signal is "1" and the level state of the second level signal is "0", so as to realize the parallel operation of the first formation and capacity device and the second formation and capacity device.

[0085] Figure 3 An exemplary schematic diagram of the connection of the switch control circuit in a first-stage capacity-forming device is shown, such as... Figure 3 As shown,

[0086] Optionally, the first switch control circuit may include, but is not limited to: a first input terminal connected to the first DSP chip, a first MOS (Metal-Oxide-Semiconductor) transistor, a first optocoupler, a second MOS transistor, a third MOS transistor, a first power supply, and a second power supply for supplying power to the first switch control circuit respectively.

[0087] The gate (G) of the first MOSFET is connected to the first input terminal, the source (S) of the first MOSFET is grounded, the drain (D) of the first MOSFET is connected to the first terminal of the first optocoupler, the second terminal of the first optocoupler is also connected to the gates of the second and third MOSFETs respectively, the gates of the second and third MOSFETs are directly connected, the sources of the second and third MOSFETs are directly connected, the third terminal of the first optocoupler is connected to the first power supply through the first resistor, and the fourth terminal of the first optocoupler is connected to the second power supply through the second resistor.

[0088] Optionally, the first DSP chip sends a first level signal to the first switch control circuit via a first differential signal line to control the first switch control circuit to turn on, specifically including but not limited to:

[0089] The first DSP chip sends a first-level signal to the first input terminal of the first switch control circuit of the first formation and capacity device via the first differential signal line of the CAN bus. When the first-level signal is input to the gate of the first MOSFET, the drain and source of the first MOSFET are connected, causing the first optocoupler to work and output an eleventh-level signal to the gates of the second and third MOSFETs respectively, triggering the connection between the drain and source of the second MOSFET and between the drain and source of the third MOSFET, thus realizing the short-circuit conduction of the first switch control circuit. The level state of the eleventh-level signal is "1".

[0090] Optionally, the second switch control circuit may include, but is not limited to: a fourth input terminal connected to the first DSP chip; an eighth MOSFET, a second optocoupler, a ninth MOSFET, and a tenth MOSFET; and a seventh power supply and an eighth power supply for supplying power to the second switch control circuit respectively.

[0091] The gate (G) of the eighth MOSFET is connected to the fourth input terminal, the source (S) of the eighth MOSFET is grounded, the drain (D) of the eighth MOSFET is connected to the first terminal of the second optocoupler, the second terminal of the second optocoupler is also connected to the gate (G) of the ninth MOSFET and the gate (G) of the tenth MOSFET, the source (S) of the ninth MOSFET is connected to the source (S) of the tenth MOSFET, the third terminal of the second optocoupler is connected to the seventh power supply through the seventh resistor, and the fourth terminal of the second optocoupler is connected to the eighth power supply through the eighth resistor.

[0092] Optionally, a first-level signal is sent to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on, specifically including but not limited to:

[0093] The first level signal is sent to the fourth input terminal of the second switch control circuit of the first formation and capacity device via the second differential signal line of the CAN bus. When the first level signal is input to the gate of the eighth MOSFET, the drain and source of the eighth MOSFET are connected, which makes the second optocoupler work and outputs the fourteenth level signal to the gate of the ninth MOSFET and the gate of the tenth MOSFET respectively, triggering the connection between the drain and source of the ninth MOSFET and the connection between the drain and source of the tenth MOSFET, realizing the short circuit of the second switch control circuit. The level state of the fourteenth level signal is "1".

[0094] Optionally, the third switch control circuit includes: a fifth input terminal connected to the first DSP chip; an eleventh MOSFET; a third optocoupler; a twelfth MOSFET; a thirteenth MOSFET; and a ninth and tenth power supply for supplying power to the third switch control circuit, respectively.

[0095] The gate (G) of the eleventh MOSFET is connected to the fifth input terminal, the source (S) of the eleventh MOSFET is grounded, the drain (D) of the eleventh MOSFET is connected to the first terminal of the third optocoupler, the second terminal of the third optocoupler is also connected to the gates of the twelfth and thirteenth MOSFETs respectively, the gates of the twelfth and thirteenth MOSFETs are directly connected, the sources of the twelfth and thirteenth MOSFETs are directly connected, the third terminal of the third optocoupler is connected to the ninth power supply through the ninth resistor, and the tenth resistor at the fourth terminal of the third optocoupler is connected to the tenth power supply.

[0096] Optionally, a first-level signal is sent to the third switch control circuit via the power line to control the third switch control circuit to turn on, which may include, but is not limited to:

[0097] The first level signal is sent to the fifth input terminal of the third switch control circuit of the first formation and capacity device via the power line of the CAN bus. When the first level signal is input to the gate of the eleventh MOSFET, the drain and source of the eleventh MOSFET are connected, which makes the third optocoupler work and outputs the fifteenth level signal to the gate of the twelfth MOSFET and the gate of the thirteenth MOSFET respectively, triggering the connection between the drain and source of the twelfth MOSFET and the connection between the drain and source of the thirteenth MOSFET, realizing the short circuit of the third switch control circuit. The level state of the fifteenth level signal is "1".

[0098] Optionally, the fourth switch control circuit may include, but is not limited to: a sixth input terminal connected to the first DSP chip; a fourteenth MOSFET; a fourth optocoupler; a fifteenth MOSFET; a sixteenth MOSFET; an eleventh power supply and a twelfth power supply for supplying power to the fourth switch control circuit, respectively.

[0099] The gate (G) of the fourteenth MOSFET is connected to the sixth input terminal, the source (S) of the fourteenth MOSFET is grounded, the drain (D) of the fourteenth MOSFET is connected to the first terminal of the fourth optocoupler, the second terminal of the fourth optocoupler is also connected to the gates of the fifteenth and sixteenth MOSFETs respectively, the gates of the fifteenth and sixteenth MOSFETs are directly connected, the sources of the fifteenth and sixteenth MOSFETs are directly connected, the third terminal of the fourth optocoupler is connected to the eleventh power supply through the eleventh resistor, and the twelfth resistor at the fourth terminal of the fourth optocoupler is connected to the twelfth power supply.

[0100] Optionally, a first-level signal is sent to the fourth switch control circuit via a ground wire to control the fourth switch control circuit to turn on, which may include, but is not limited to:

[0101] A first-level signal is sent to the sixth input terminal of the fourth switch control circuit of the first formation and capacity device via the ground line of the CAN bus. When the first-level signal is input to the gate of the fourteenth MOSFET, the drain and source of the fourteenth MOSFET are connected, causing the fourth optocoupler to work and output a sixteenth-level signal to the gates of the fifteenth and sixteenth MOSFETs respectively. This triggers the connection between the drain and source of the fifteenth MOSFET and the connection between the drain and source of the sixteenth MOSFET, thus achieving short-circuit conduction of the fourth switch control circuit. The level of the sixteenth-level signal is "1".

[0102] It should be noted that the first, seventh, ninth, and eleventh power supplies can be the same power supply, wherein the voltage of this power supply can be 3.3V DC. The second, eighth, tenth, and twelfth power supplies are four different power supplies, wherein the voltage of the above four different power supplies can be 5V DC.

[0103] S103 and the host computer respectively send the second control command to the first DSP chip and the second DSP chip.

[0104] In this application, the second control instruction is used to instruct both the first DSP chip and the second DSP chip to start the power transmission mode. That is, the second control instruction is used to instruct the first DSP chip to send a first power transmission waveform, or to instruct the second DSP chip to send a second power transmission waveform.

[0105] S104. In response to the received second control command, the first DSP chip inputs a third-level signal to the first isolation chip through the first input pin of the first isolation chip, outputs a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then outputs a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit. In response to the received second control command, the second DSP chip inputs a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second formation and capacity device, outputs a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then outputs an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit.

[0106] In this application, the first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are connected in a common line. Figure 4 An exemplary diagram illustrates the connection of the first synchronization circuit in the first formation and capacity-building device, as shown below. Figure 4 As shown,

[0107] The first synchronization circuit may include, but is not limited to: a second input terminal connected to the first DSP chip, a fourth MOSFET, a fifth MOSFET, a third power supply, a fourth power supply, and a first output terminal for supplying power to the first synchronization circuit; wherein...

[0108] The gate (G) of the fourth MOSFET is connected to the second input terminal, the source (S) of the fourth MOSFET is grounded, the drain (D) of the fourth MOSFET is connected to the gate (G) of the fifth MOSFET, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the first output terminal, the first output terminal is also connected to the first enable terminal of the first isolation chip, the drain (D) of the fourth MOSFET is also connected to the third power supply through the third resistor, and the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fourth resistor.

[0109] Optionally, when the level state of the fourth level signal is "1",

[0110] After the fourth-level signal is output to the first synchronization circuit through the first output pin of the first isolation chip, the fifth-level signal is output to the first enable pin of the first isolation chip through the first output terminal of the first synchronization circuit. Specifically, this may include, but is not limited to:

[0111] The fourth level signal is output through the first output pin of the first isolation chip to the second input terminal of the first synchronization circuit. When the fourth level signal is input to the gate of the fourth MOSFET, the drain and source of the fourth MOSFET are short-circuited and grounded, so that the gate of the fifth MOSFET is input to the twelfth level signal, triggering the disconnection between the drain and source of the fifth MOSFET, and triggering the first output terminal of the first synchronization circuit to output the fifth level signal to the first enable terminal of the first isolation chip.

[0112] The level of the twelfth level signal is "0", and the level of the fifth level signal is "1".

[0113] Figure 5 An exemplary diagram illustrates the connection of the second synchronization circuit in the second formation and capacity-building device, as shown below. Figure 5 As shown,

[0114] The second synchronization circuit includes: a third input terminal connected to the second DSP chip, a sixth MOSFET, a seventh MOSFET, a fifth power supply, a sixth power supply for powering the second synchronization circuit, and a second output terminal; wherein...

[0115] The gate (G) of the fifth MOSFET is connected to the third input terminal, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the gate (G) of the sixth MOSFET, the source (S) of the sixth MOSFET is grounded, the drain (D) of the sixth MOSFET is connected to the second output terminal, the second output terminal is also connected to the second enable terminal of the second isolation chip, the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fifth resistor, and the drain (D) of the sixth MOSFET is also connected to the fifth power supply through the sixth resistor.

[0116] Optionally, when the level state of the seventh level signal is "1",

[0117] After the seventh-level signal is output to the second synchronization circuit through the second output pin of the second isolation chip, the eighth-level signal is output to the second enable pin of the second isolation chip through the second output terminal of the second synchronization circuit. Specifically, this may include, but is not limited to:

[0118] The second output pin of the second isolation chip outputs a seventh-level signal to the third input of the second synchronization circuit. When the gate of the sixth MOSFET receives a seventh-level signal, the drain and source of the sixth MOSFET are short-circuited and grounded, causing the gate of the seventh MOSFET to receive a thirteenth-level signal. This triggers the disconnection between the drain and source of the seventh MOSFET, which in turn triggers the second output of the second synchronization circuit to output an eighth-level signal to the second enable pin of the second isolation chip.

[0119] The thirteenth level signal has a level of "0", and the eighth level signal has a level of "1".

[0120] It should be noted that the first output terminal, the second output terminal, the first enable terminal, and the second enable terminal are connected collinearly at the same point.

[0121] S105. When the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip, and the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip.

[0122] S106. In response to receiving a ninth-level signal with a level state of "1", the first DSP chip outputs a first power transmission waveform. In response to receiving a tenth-level signal with a level state of "1", the second DSP chip outputs a second power transmission waveform, so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

[0123] In this application, the preset threshold is preferably 1 microsecond or 10 microseconds.

[0124] It should be noted that both the first power transmission waveform and the second power transmission waveform can be in the form of PWM signals (Pulse Width Modulation).

[0125] It should be noted that the first power transmission waveform can be used to instruct the first formation and capacity-conducting device to perform power transmission, such as instructing the first formation and capacity-conducting device to charge or discharge; the second power transmission waveform can be used to instruct the second formation and capacity-conducting device to perform power transmission, such as instructing the second formation and capacity-conducting device to charge or discharge, thereby enabling the first formation and capacity-conducting device and the second formation and capacity-conducting device to work in parallel.

[0126] This application provides a parallel control system for a chemical composition and capacity testing device, such as... Figure 2 As shown, the system may include, but is not limited to:

[0127] The system includes a host computer, a first type formation and capacity testing device, a second type formation and capacity testing device, a third type formation and capacity testing device, a twisted pair cable, and a CAN bus. The first type formation and capacity testing device further includes: a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit. The second type formation and capacity testing device further includes: a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit. The CAN bus includes: a first differential signal line, a second differential signal line, a power supply line, and a ground line. A CAN bus and the first, second, third, and fourth switch control circuits are connected between the first and second DSP chips. A CAN bus, the fifth switch control circuit, the sixth switch control circuit, the seventh switch control circuit, and the eighth switch control circuit are also connected between the second and third DSP chips.

[0128] The third formation and capacity testing device may include: a third DSP chip, a ninth switch control circuit, a tenth switch control circuit, an eleventh switch control circuit, a twelfth switch control circuit, and a third isolation chip.

[0129] The host computer can be used to send first control commands to the first DSP chip of the first formation and capacity testing device and the second DSP chip of the second formation and capacity testing device respectively via twisted pair;

[0130] The first DSP chip can be used to: respond to a received first control command by sending a first level signal to a first switch control circuit via a first differential signal line to control the first switch control circuit to turn on; sending a first level signal to a second switch control circuit via a second differential signal line to control the second switch control circuit to turn on; sending a first level signal to a third switch control circuit via a power line to control the third switch control circuit to turn on; and sending a first level signal to a fourth switch control circuit via a ground line to control the fourth switch control circuit to turn on, wherein the level state of the first level signal is "1".

[0131] The second DSP chip can be used to: in response to a received first control command, send a second-level signal to the fifth switch control circuit via a first differential signal line, send a second-level signal to the sixth switch control circuit via a second differential signal line, send a second-level signal to the seventh switch control circuit via a power line, and send a second-level signal to the eighth switch control circuit via a ground line, so as to control the fifth, sixth, seventh, and eighth switch control circuits to be disconnected respectively; the level state of the second-level signal is "0", that is, the second DSP chip is disconnected from the third DSP chip, so as to realize the parallel operation of the first and second formation capacity devices.

[0132] In other words, when the first, second, third, and fourth switch control circuits are all turned on, and the fifth, sixth, seventh, and eighth switch control circuits are all turned off, the first and second batching and capacity-forming devices are connected in parallel (i.e., they work in parallel).

[0133] The host computer can also be used to send second control commands to the first DSP chip and the second DSP chip respectively;

[0134] The first DSP chip can also be used to: in response to a received second control command, input a third-level signal to the first isolation chip through the first input pin of the first isolation chip;

[0135] The first isolation chip can be used to: output a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then output a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit.

[0136] The second DSP chip can also be used to: in response to a received second control command, input a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second conversion and capacity device;

[0137] The first isolation chip can be used to: output a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then output an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit; wherein the first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are connected in a common line;

[0138] The first isolation chip can also be used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip.

[0139] The second isolation chip can also be used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip.

[0140] The first DSP chip can also be used to: output a first power transmission waveform in response to receiving a ninth level signal with a level state of "1";

[0141] The second DSP chip can also be used to: output a second power transmission waveform in response to receiving a tenth-level signal with a level state of "1", so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

[0142] Figures 1-5 This is only used to illustrate the embodiments of this application and should not be construed as limiting the scope of protection of this application.

[0143] Those skilled in the art will recognize that the method steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0144] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the devices and equipment described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0145] In the several embodiments provided in this application, it should be understood that the methods can be implemented in other ways. For example, the composition and steps of each example have been described. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0146] The embodiments described above are merely illustrative. The mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface or module, or it may be an electrical, mechanical or other form of connection.

[0147] Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A parallel control method for a chemical separation and capacity testing device, characterized in that, include: The host computer sends the first control command to the first DSP chip of the first formation and capacity testing device and the second DSP chip of the second formation and capacity testing device respectively via twisted pair cable; The first formation and capacity testing device further includes: a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit; a CAN bus connects the first DSP chip and the second DSP chip; the second formation and capacity testing device further includes: a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit; the CAN bus includes: a first differential signal line, a second differential signal line, a power line, and a ground line; the first and fifth switch control circuits are both located on the first differential signal line, the second and sixth switch control circuits are both located on the second differential signal line, the third and seventh switch control circuits are both located on the power line, and the fourth and eighth switch control circuits are both located on the ground line; In response to the received first control command, the first DSP chip sends a first-level signal to the first switch control circuit via the first differential signal line to control the first switch control circuit to turn on, sends a first-level signal to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on, sends a first-level signal to the third switch control circuit via the power line to control the third switch control circuit to turn on, and sends a first-level signal to the fourth switch control circuit via the ground line to control the fourth switch control circuit to turn on; in response to the received first control command, the second DSP chip sends a second-level signal to the fifth switch control circuit via the first differential signal line, sends a second-level signal to the sixth switch control circuit via the second differential signal line, sends a second-level signal to the seventh switch control circuit via the power line, and sends a second-level signal to the eighth switch control circuit via the ground line to control the fifth, sixth, seventh, and eighth switch control circuits to turn off respectively; the level state of the first level signal is "1", and the level state of the second level signal is "0", so as to realize the parallel operation of the first and second formation capacity devices; The host computer sends the second control command to the first DSP chip and the second DSP chip respectively; In response to the received second control command, the first DSP chip inputs a third-level signal to the first isolation chip through the first input pin, outputs a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then outputs a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit. In response to the received second control command, the second DSP chip inputs a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second formation and capacity-setting device, outputs a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then outputs an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit. The first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are all connected on a common line. When the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip, and the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip. In response to receiving a ninth-level signal with a level of "1", the first DSP chip outputs a first power transmission waveform. In response to receiving a tenth-level signal with a level of "1", the second DSP chip outputs a second power transmission waveform, so that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

2. The parallel control method for the formation and capacity testing equipment as described in claim 1, characterized in that, The first switch control circuit includes: a first input terminal connected to a first DSP chip; a first MOSFET, a first optocoupler, a second MOSFET, and a third MOSFET; a first power supply and a second power supply for supplying power to the first switch control circuit, respectively. The gate (G) of the first MOSFET is connected to the first input terminal, the source (S) of the first MOSFET is grounded, the drain (D) of the first MOSFET is connected to the first terminal of the first optocoupler, the second terminal of the first optocoupler is also connected to the gates of the second and third MOSFETs respectively, the gates of the second and third MOSFETs are directly connected, the sources of the second and third MOSFETs are directly connected, the third terminal of the first optocoupler is connected to the first power supply through the first resistor, and the fourth terminal of the first optocoupler is connected to the second power supply through the second resistor.

3. The parallel control method for the formation and capacity testing equipment as described in claim 2, characterized in that, The first DSP chip sends a first level signal to the first switch control circuit via a first differential signal line to control the first switch control circuit to turn on, specifically including: The first DSP chip sends a first-level signal to the first input terminal of the first switch control circuit of the first formation and capacity device via the first differential signal line of the CAN bus. When the first-level signal is input to the gate of the first MOSFET, the drain and source of the first MOSFET are connected, causing the first optocoupler to work and output an eleventh-level signal to the gates of the second and third MOSFETs respectively, triggering the connection between the drain and source of the second MOSFET and the connection between the drain and source of the third MOSFET, thus realizing the short-circuit conduction of the first switch control circuit. The level state of the eleventh-level signal is "1".

4. The parallel control method for the formation and capacity testing equipment as described in claim 1, characterized in that, The first synchronization circuit includes: a second input terminal connected to the first DSP chip, a fourth MOSFET, a fifth MOSFET, a third power supply, a fourth power supply for supplying power to the first synchronization circuit, and a first output terminal; wherein... The gate (G) of the fourth MOSFET is connected to the second input terminal, the source (S) of the fourth MOSFET is grounded, the drain (D) of the fourth MOSFET is connected to the gate (G) of the fifth MOSFET, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the first output terminal, the first output terminal is also connected to the first enable terminal of the first isolation chip, the drain (D) of the fourth MOSFET is also connected to the third power supply through the third resistor, and the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fourth resistor.

5. The parallel control method for the formation and capacity testing equipment as described in claim 4, characterized in that, When the level state of the fourth level signal is "1", After the fourth-level signal is output to the first synchronization circuit through the first output pin of the first isolation chip, the fifth-level signal is output to the first enable pin of the first isolation chip through the first output terminal of the first synchronization circuit, specifically including: The fourth level signal is output through the first output pin of the first isolation chip to the second input terminal of the first synchronization circuit. When the fourth level signal is input to the gate of the fourth MOSFET, the drain and source of the fourth MOSFET are short-circuited and grounded, so that the gate of the fifth MOSFET is input to the twelfth level signal, triggering the disconnection between the drain and source of the fifth MOSFET, and triggering the first output terminal of the first synchronization circuit to output the fifth level signal to the first enable terminal of the first isolation chip. The level of the twelfth level signal is "0", and the level of the fifth level signal is "1".

6. The parallel control method for the formation and capacity testing equipment as described in claim 5, characterized in that, The second synchronization circuit includes: a third input terminal connected to the second DSP chip, a sixth MOSFET, a seventh MOSFET, a fifth power supply, a sixth power supply for powering the second synchronization circuit, and a second output terminal; wherein... The gate (G) of the fifth MOSFET is connected to the third input terminal, the source (S) of the fifth MOSFET is grounded, the drain (D) of the fifth MOSFET is connected to the gate (G) of the sixth MOSFET, the source (S) of the sixth MOSFET is grounded, the drain (D) of the sixth MOSFET is connected to the second output terminal, the second output terminal is also connected to the second enable terminal of the second isolation chip, the drain (D) of the fifth MOSFET is also connected to the fourth power supply through the fifth resistor, and the drain (D) of the sixth MOSFET is also connected to the fifth power supply through the sixth resistor.

7. The parallel control method for the formation and capacity testing equipment as described in claim 6, characterized in that, When the level state of the seventh level signal is "1", After the seventh-level signal is output to the second synchronization circuit through the second output pin of the second isolation chip, the eighth-level signal is output to the second enable pin of the second isolation chip through the second output terminal of the second synchronization circuit, specifically including: The second output pin of the second isolation chip outputs a seventh-level signal to the third input of the second synchronization circuit. When the gate of the sixth MOSFET receives a seventh-level signal, the drain and source of the sixth MOSFET are short-circuited and grounded, causing the gate of the seventh MOSFET to receive a thirteenth-level signal. This triggers the disconnection between the drain and source of the seventh MOSFET, which in turn triggers the second output of the second synchronization circuit to output an eighth-level signal to the second enable pin of the second isolation chip. The thirteenth level signal has a level of "0", and the eighth level signal has a level of "1".

8. The parallel control method for the formation and capacity testing equipment as described in claim 1, characterized in that, The preset threshold is 1 microsecond.

9. The parallel control method for the formation and capacity testing equipment as described in claim 1, characterized in that, The second switch control circuit includes: a fourth input terminal connected to the first DSP chip; an eighth MOSFET, a second optocoupler, a ninth MOSFET, and a tenth MOSFET; and a seventh power supply and an eighth power supply for supplying power to the second switch control circuit respectively. The gate (G) of the eighth MOSFET is connected to the fourth input terminal, the source (S) of the eighth MOSFET is grounded, the drain (D) of the eighth MOSFET is connected to the first terminal of the second optocoupler, the second terminal of the second optocoupler is also connected to the gate (G) of the ninth MOSFET and the gate (G) of the tenth MOSFET, the source (S) of the ninth MOSFET is connected to the source (S) of the tenth MOSFET, the third terminal of the second optocoupler is connected to the seventh power supply through the seventh resistor, and the fourth terminal of the second optocoupler is connected to the eighth power supply through the eighth resistor.

10. The parallel control method for the formation and capacity testing equipment as described in claim 9, characterized in that, A first-level signal is sent to the second switch control circuit via the second differential signal line to control the second switch control circuit to turn on. Specifically, this includes: The first level signal is sent to the fourth input terminal of the second switch control circuit of the first formation and capacity device via the second differential signal line of the CAN bus. When the first level signal is input to the gate of the eighth MOSFET, the drain and source of the eighth MOSFET are connected, which makes the second optocoupler work and outputs the fourteenth level signal to the gate of the ninth MOSFET and the gate of the tenth MOSFET respectively, triggering the connection between the drain and source of the ninth MOSFET and the connection between the drain and source of the tenth MOSFET, realizing the short circuit of the second switch control circuit. The level state of the fourteenth level signal is "1".

11. The parallel control method for a formation and capacity testing device as described in claim 1, characterized in that, The third switch control circuit includes: a fifth input terminal connected to the first DSP chip; an eleventh MOSFET; a third optocoupler; a twelfth MOSFET; a thirteenth MOSFET; and a ninth and tenth power supply units for supplying power to the third switch control circuit, respectively. The gate (G) of the eleventh MOSFET is connected to the fifth input terminal, the source (S) of the eleventh MOSFET is grounded, the drain (D) of the eleventh MOSFET is connected to the first terminal of the third optocoupler, the second terminal of the third optocoupler is also connected to the gates of the twelfth and thirteenth MOSFETs respectively, the gates of the twelfth and thirteenth MOSFETs are directly connected, the sources of the twelfth and thirteenth MOSFETs are directly connected, the third terminal of the third optocoupler is connected to the ninth power supply through the ninth resistor, and the tenth resistor at the fourth terminal of the third optocoupler is connected to the tenth power supply.

12. The parallel control method for the formation and capacity testing equipment as described in claim 11, characterized in that, Sending a first-level signal to the third switch control circuit via the power line to control the third switch control circuit to turn on, specifically including: The first level signal is sent to the fifth input terminal of the third switch control circuit of the first formation and capacity device via the power line of the CAN bus. When the first level signal is input to the gate of the eleventh MOSFET, the drain and source of the eleventh MOSFET are connected, which makes the third optocoupler work and outputs the fifteenth level signal to the gate of the twelfth MOSFET and the gate of the thirteenth MOSFET respectively. This triggers the connection between the drain and source of the twelfth MOSFET and the connection between the drain and source of the thirteenth MOSFET, thus realizing the short circuit and conduction of the third switch control circuit. The level state of the fifteenth level signal is "1".

13. The parallel control method for the formation and capacity testing equipment as described in claim 1, characterized in that, The fourth switch control circuit includes: a sixth input terminal connected to the first DSP chip; a fourteenth MOSFET; a fourth optocoupler; a fifteenth MOSFET; a sixteenth MOSFET; and an eleventh and twelfth power supply for supplying power to the fourth switch control circuit, respectively. The gate (G) of the fourteenth MOSFET is connected to the sixth input terminal, the source (S) of the fourteenth MOSFET is grounded, the drain (D) of the fourteenth MOSFET is connected to the first terminal of the fourth optocoupler, the second terminal of the fourth optocoupler is also connected to the gates of the fifteenth and sixteenth MOSFETs respectively, the gates of the fifteenth and sixteenth MOSFETs are directly connected, the sources of the fifteenth and sixteenth MOSFETs are directly connected, the third terminal of the fourth optocoupler is connected to the eleventh power supply through the eleventh resistor, and the twelfth resistor at the fourth terminal of the fourth optocoupler is connected to the twelfth power supply.

14. The parallel control method for a formation and capacity testing device as described in claim 13, characterized in that, Sending a first-level signal to the fourth switch control circuit via the ground wire to control the fourth switch control circuit to turn on, specifically including: A first-level signal is sent to the sixth input terminal of the fourth switch control circuit of the first formation and capacity device via the ground line of the CAN bus. When the first-level signal is input to the gate of the fourteenth MOSFET, the drain and source of the fourteenth MOSFET are connected, causing the fourth optocoupler to work and output a sixteenth-level signal to the gates of the fifteenth and sixteenth MOSFETs respectively, triggering the connection between the drain and source of the fifteenth MOSFET and the connection between the drain and source of the sixteenth MOSFET, thus achieving short-circuit conduction of the fourth switch control circuit. The level state of the sixteenth-level signal is "1".

15. A parallel control system for a chemical composition and capacity testing device, characterized in that, include: The system includes a host computer, a first formation and capacity testing device, a second formation and capacity testing device, twisted-pair cables, and a CAN bus. The first formation and capacity testing device further includes: a first isolation chip, a first synchronization circuit, a first switch control circuit, a second switch control circuit, a third switch control circuit, and a fourth switch control circuit. The second formation and capacity testing device further includes: a second isolation chip, a second synchronization circuit, a fifth switch control circuit, a sixth switch control circuit, a seventh switch control circuit, and an eighth switch control circuit. The CAN bus includes: a first differential signal line, a second differential signal line, a power line, and a ground line. A CAN bus connects the first DSP chip and the second DSP chip. The host computer is used to send first control commands to the first DSP chip of the first formation and capacity device and the second DSP chip of the second formation and capacity device respectively via twisted pair cables. The first DSP chip is configured to: in response to a received first control command, send a first level signal to a first switch control circuit via a first differential signal line to control the first switch control circuit to turn on; send a first level signal to a second switch control circuit via a second differential signal line to control the second switch control circuit to turn on; send a first level signal to a third switch control circuit via a power line to control the third switch control circuit to turn on; and send a first level signal to a fourth switch control circuit via a ground line to control the fourth switch control circuit to turn on, wherein the level state of the first level signal is "1"; The second DSP chip is used to: in response to a received first control command, send a second-level signal to the fifth switch control circuit via a first differential signal line, send a second-level signal to the sixth switch control circuit via a second differential signal line, send a second-level signal to the seventh switch control circuit via a power line, and send a second-level signal to the eighth switch control circuit via a ground line, so as to control the fifth, sixth, seventh, and eighth switch control circuits to be disconnected respectively; the level state of the second-level signal is "0" to realize parallel operation of the first and second formation capacity devices; The host computer is also used to: send second control commands to the first DSP chip and the second DSP chip respectively; The first DSP chip is also used to: in response to a received second control command, input a third level signal to the first isolation chip through the first input pin of the first isolation chip; The first isolation chip is used to: output a fourth-level signal to the first synchronization circuit through the first output pin of the first isolation chip, and then output a fifth-level signal to the first enable terminal of the first isolation chip through the first output terminal of the first synchronization circuit. The second DSP chip is also used to: in response to a received second control command, input a sixth-level signal to the second isolation chip through the second input pin of the second isolation chip of the second conversion and capacity device; The first isolation chip is used to: output a seventh-level signal to the second synchronization circuit through the second output pin of the second isolation chip, and then output an eighth-level signal to the second enable terminal of the second isolation chip through the second output terminal of the second synchronization circuit; wherein the first output terminal, the first enable terminal, the second output terminal, and the second enable terminal are connected in a common line; The first isolation chip is also used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the third output pin of the first isolation chip outputs a ninth level signal with a level state of "1" to the first DSP chip. The second isolation chip is also used to: when the level state of the fifth level signal input to the first enable terminal and the level state of the eighth level signal input to the second enable terminal are both "1", the fourth output pin of the second isolation chip outputs a tenth level signal with a level state of "1" to the second DSP chip. The first DSP chip is also used to: output a first power transmission waveform in response to receiving a ninth level signal with a level state of "1"; The second DSP chip is also used to: in response to receiving a tenth-level signal with a level state of "1", output a second power transmission waveform, so as to ensure that the interval between the time when the first DSP chip outputs the first power transmission waveform and the time when the second DSP chip outputs the second power transmission waveform is less than a preset threshold.

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