A current limiting circuit for a low dropout voltage regulator

Abstract

The application discloses a current limiting circuit for a low dropout regulator, comprising a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, an error amplifier, a comparator, a D flip-flop and a level shifter, when the current limiting voltage exceeds the threshold voltage of the fifth field effect transistor, the fifth field effect transistor is turned on, with the increase of the current passing through the thirteenth field effect transistor, the current limiting voltage decreases, and the first voltage signal increases, so as to limit the current of the low dropout regulator. The application can realize the current limiting of the high-voltage LDO circuit, improve the current driving capacity of the LDO output, and reduce the requirement of the high-voltage LDO circuit on the DC-DC power supply.

Description

Technical Field

[0001] This invention relates to the field of functional circuits, and in particular to a current limiting circuit for a low dropout voltage regulator. Background Technology

[0002] A low-dropout regulator (LDO), also known as a low-dropout linear regulator or low-voltage-drop regulator, is a type of linear DC regulator used to provide a stable DC voltage power supply. Compared to a typical linear DC regulator, a low-dropout regulator can operate with a smaller output-input voltage difference.

[0003] LDO (Low Dropout Linear Regulator) is used in large-scale circuits to improve power supply efficiency. An external DC-DC converter is typically used to boost the low-voltage supply to a high-voltage supply, and then an LDO circuit is used to reduce the high-voltage supply to the desired output voltage. For example, an LDO with an input voltage of 20V and an output voltage of 15V might be used. The power-on current limiting module is a crucial component. It protects the chip's high-voltage power supply from damage caused by the large currents generated by the transient power-on of multiple LDOs. Furthermore, once the LDO output voltage reaches a predetermined value, the current limiting circuit shuts down without affecting the LDO's original current-driving capability.

[0004] In view of the above-mentioned shortcomings, the present invention proposes a current limiting circuit for low dropout voltage regulators.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art. Summary of the Invention

[0006] To address the problems in the prior art, the present invention aims to provide a current limiting circuit for low dropout regulators, which overcomes the difficulties of the prior art, and can improve the current driving capability of the LDO output while realizing current limiting of the high voltage LDO circuit, and reduce the requirements of the high voltage LDO circuit on the DC-DC power supply.

[0007] An embodiment of the present invention provides a current limiting circuit for a low dropout voltage regulator, comprising:

[0008] A first field-effect transistor is used to switch the current path between the positive voltage signal and the first node in response to the first voltage signal of the sixth node;

[0009] A second field-effect transistor is used to switch the current path between the first node and the second node in response to the voltage signal of the second voltage signal.

[0010] A third field-effect transistor is used to switch the current path between the second node and the first ground terminal in response to the voltage signal of the second node;

[0011] A fourth field-effect transistor is used to switch the current path between the third node and the first ground terminal in response to the voltage signal of the second node;

[0012] A fifth field-effect transistor is used to switch the current path between the positive voltage signal and the first voltage signal in response to the voltage signal of the third node, and the third node generates a current-limiting voltage;

[0013] A sixth field-effect transistor is used to switch the current path between the positive voltage signal and the fourth node in response to the voltage signal of the third voltage signal;

[0014] A seventh field-effect transistor is used to switch the current path between the fourth and fifth nodes in response to the voltage signal of the fifth node;

[0015] An eighth field-effect transistor is used to switch the current path between the seventh node and the first ground terminal in response to the voltage signal of the seventh node;

[0016] A ninth field-effect transistor is used to switch the current path between the eighth and ninth nodes in response to the voltage signal of the third voltage signal.

[0017] A tenth field-effect transistor is used to switch the current path between the ninth node and the sixth node in response to the voltage signal of the fourth voltage signal.

[0018] An eleventh field-effect transistor is used to switch the current path between the eighth node and the sixth node in response to the voltage signal of the third voltage signal.

[0019] A twelfth field-effect transistor is used to switch the current path between the sixth and seventh nodes in response to the voltage signal of the fifth node;

[0020] A thirteenth field-effect transistor is used to respond to the first voltage signal of the sixth node, and to switch the current path between the positive voltage signal and the tenth node, wherein the tenth node generates the output voltage of the low dropout regulator;

[0021] An error amplifier is provided, wherein the positive input terminal of the error amplifier is connected to the second proportional voltage at the output terminal of the low dropout regulator, the negative input terminal is connected to a reference voltage, and the output terminal is connected to the fifth node.

[0022] A comparator, wherein the positive input terminal of the comparator is connected to a first proportional voltage of the output voltage, and the negative input terminal is connected to a reference voltage;

[0023] A D flip-flop, wherein the input of the D flip-flop is connected to the output of the comparator to store and synchronize signals; and

[0024] A level shifter, the input of which is connected to the output of the D flip-flop, is used to switch to different voltage domains to generate a second voltage signal, a third voltage signal, and a fourth voltage signal.

[0025] Preferably, it further includes: a first resistor, a second resistor, and a third resistor, which are connected in series between the tenth node and the second ground terminal, wherein the first resistor and the second resistor generate the first proportional voltage, and the second resistor and the third resistor generate the second proportional voltage at the output terminal.

[0026] Preferably, it further includes a fourth resistor, which is connected in series between the positive voltage signal and the third node.

[0027] Preferably, it further includes a fifth resistor, which is connected in series between the eighth field-effect transistor and the first ground terminal.

[0028] Preferably, it further includes: a first capacitor connected in series between the fifth node and the eleventh node, wherein the eleventh node receives the output voltage.

[0029] Preferably, it further includes: a second capacitor connected in series between the eleventh node and the twelfth node, the twelfth node receiving the second proportional voltage.

[0030] Preferably, it further includes: a third capacitor, one end of which is connected to the tenth node and the other end of which is connected to the second ground terminal.

[0031] Preferably, when the current limiting voltage exceeds the threshold voltage of the fifth field-effect transistor, the fifth field-effect transistor is turned on. As the current through the thirteenth field-effect transistor increases, the current limiting voltage decreases, and the first voltage signal increases to limit the current of the low-dropout regulator.

[0032] Preferably, when the output voltage meets a preset percentage of a predetermined voltage, the first proportional voltage is compared with the reference voltage. The comparison result changes from low to high, generating a rising edge. After the output voltage of the D flip-flop becomes high, it passes through the level shifter to generate the second voltage signal, which drives the second field-effect transistor and the sixth field-effect transistor to turn off, while simultaneously turning on the tenth field-effect transistor to close the current limiting circuit.

[0033] Preferably, the first field-effect transistor is a PMOS field-effect transistor, the second field-effect transistor is an NMOS field-effect transistor, the third field-effect transistor is an NMOS field-effect transistor, the fourth field-effect transistor is an NMOS field-effect transistor, the fifth field-effect transistor is a PMOS field-effect transistor, the sixth field-effect transistor is a PMOS field-effect transistor, the seventh field-effect transistor is a PMOS field-effect transistor, the eighth field-effect transistor is an NMOS field-effect transistor, the ninth field-effect transistor is a PMOS field-effect transistor, the tenth field-effect transistor is a PMOS field-effect transistor, the eleventh field-effect transistor is a PMOS field-effect transistor, the twelfth field-effect transistor is a PMOS field-effect transistor, and the thirteenth field-effect transistor is a PMOS field-effect transistor.

[0034] This invention can improve the current driving capability of the LDO output while achieving current limiting in a high-voltage LDO circuit, and reduce the requirements of the high-voltage LDO circuit for the DC-DC power supply. Based on common knowledge in the field, the above-mentioned preferred conditions can be arbitrarily combined to obtain various preferred embodiments of this invention.

[0035] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description

[0036] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0037] Figure 1 This is a circuit diagram of the current limiting circuit for a low-dropout regulator according to the present invention.

[0038] Figure 2 This is a circuit diagram of the current limiting circuit for a low dropout voltage regulator according to the present invention.

[0039] Figure 3 The circuit simulation results of the current limiting circuit for the low dropout voltage regulator of the present invention are shown in the figure. Detailed Implementation

[0040] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0041] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0042] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0043] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0044] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0045] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0046] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0047] While the terms first, second, etc., are used in some instances herein to refer to various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of a feature, step, operation, component, element, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of components, functions, steps, or operations are inherently mutually exclusive in some way.

[0048] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in the specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0049] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0050] Figure 1 This is a circuit diagram of the current limiting circuit for a low-dropout regulator according to the present invention. Figure 2 This is a circuit diagram of the current-limiting circuit for a low-dropout voltage regulator according to the present invention. Figure 1 and 2 As shown, the current-limiting circuit for a low-dropout regulator of the present invention includes: 13 field-effect transistors, an error amplifier (Amp), a comparator, a D flip-flop (D1), and a level shifter. The connection relationships of the components are as follows:

[0051] The first field-effect transistor M1 is used to respond to the first voltage signal V at the sixth node N6. pThe current path between the positive voltage signal VDD and the first node N1 is switched.

[0052] The second field-effect transistor M2 is used to switch the current path between the first node N1 and the second node N2 in response to the voltage signal of the second voltage signal Vctrl.

[0053] The third field-effect transistor M3 is used to switch the current path between the second node N2 and the first ground terminal GND1 in response to the voltage signal of the second node N2.

[0054] The fourth field-effect transistor M4 is used to switch the current path between the third node N3 and the first ground terminal GND1 in response to the voltage signal of the second node N2.

[0055] The fifth field-effect transistor M5 is used to respond to the voltage signal at the third node N3, and to the positive voltage signal VDD and the first voltage signal V. p The current path between them is switched, and the third node N3 generates a current-limiting voltage V. C .

[0056] The sixth field-effect transistor M17 is used to switch the current path between the positive voltage signal VDD and the fourth node N4 in response to the voltage signal of the third voltage signal OUTP.

[0057] The seventh MOSFET M18 is used to switch the current path between the fourth node N4 and the fifth node N5 in response to the voltage signal of the fifth node N5. The fifth node N5 is connected to the output voltage node of the low dropout regulator.

[0058] The eighth field-effect transistor M21 is used to switch the current path between the seventh node N7 and the first ground terminal GND1 in response to the voltage signal of the seventh node N7.

[0059] The ninth field-effect transistor M22 is used to respond to the third voltage signal V. BP The voltage signal is used to switch the current path between the eighth node N8 and the ninth node N9.

[0060] The tenth field-effect transistor M23 is used to switch the current path between the ninth node N9 and the sixth node N6 in response to the voltage signal of the fourth voltage signal OUTN.

[0061] The eleventh field-effect transistor M19 is used to respond to the third voltage signal V. BP The voltage signal is used to switch the current path between the eighth node N8 and the sixth node N6.

[0062] The twelfth field-effect transistor M20 is used to switch the current path between the sixth node N6 and the seventh node N7 in response to the voltage signal of the fifth node N5.

[0063] The thirteenth field-effect transistor Mp is used to switch the current path between the positive voltage signal VDD and the tenth node N10 in response to the first voltage signal Vp at the sixth node N6. The tenth node N10 generates the output voltage V of the low-dropout regulator. OUT .

[0064] Error amplifier Amp is connected to the second proportional voltage V at the output of a low dropout regulator. BK The negative input terminal is connected to a reference voltage V. REF The output is connected to the fifth node N5.

[0065] The comparator is connected to the output voltage V at its positive input terminal. OUT The first proportional voltage V BK1 The negative input terminal is connected to a reference voltage V. REF .

[0066] D flip-flop D1, whose input is connected to the output of a comparator, is used to store and synchronize signals.

[0067] A level shifter connects its input to the output of a D flip-flop D1 to switch to different voltage domains, generating a second voltage signal Vctrl, a third voltage signal OUTP, and a fourth voltage signal OUTN.

[0068] This invention proposes a switchable current-limiting circuit for high-voltage LDOs to address the problems of weak current drive capability, complex current-limiting circuits, and low performance in high-voltage LDOs with built-in current-limiting circuits. The invention includes 13 MOSFETs M1-M5, M17-M23, and Mp; 5 resistors R1-R5; 3 capacitors C1-C3; an error amplifier amp; a comparator; a D flip-flop D1; and a level shifter. A current sampling transistor M1 is connected in parallel with the power transistor Mp. The sampled current generates a current-limiting voltage V through resistor R4. C This voltage is compared with the threshold voltage of transistor M5, and the gate voltage V of transistor M5 relative to power transistor Mp. P To control, M17-M18 and M21 control V. P Voltage clamping achieves current limiting. The comparator compares the proportional voltage V at the LDO output. BK1 and reference voltage V REFThe comparator output is output via D1, and then transformed into the expected high level by the level shifter, thus shutting down the current limiting circuit. Furthermore, M22 and M23 prevent V from being interrupted when the current limiting circuit is off. P Voltage drops and power transistor current rises. This achieves current limiting in the high-voltage LDO circuit while improving the current drive capability of the LDO output and reducing the requirements of the high-voltage LDO circuit on the DC-DC power supply.

[0069] In a preferred embodiment, the system further includes: a first resistor R1, a second resistor R2, and a third resistor R3, connected in series between the tenth node N10 and the second ground terminal GND2, wherein a first proportional voltage V is generated between the first resistor R1 and the second resistor R2. BK1 The second resistor R2 and the third resistor R3 generate a second proportional voltage V at the output terminal. BK However, this is not the only limit.

[0070] In a preferred embodiment, it further includes a fourth resistor R4, which is connected in series between the positive voltage signal VDD and the third node N3, but is not limited thereto.

[0071] In a preferred embodiment, it further includes a fifth resistor R5, which is connected in series between the eighth field-effect transistor M21 and the first ground terminal GND1, but is not limited thereto.

[0072] In a preferred embodiment, it further includes: a first capacitor C1, connected in series between the fifth node N5 and the eleventh node N11, the eleventh node N11 receiving the output voltage V. OUT However, this is not the only limit.

[0073] In a preferred embodiment, it further includes: a second capacitor C2, connected in series between the eleventh node N11 and the twelfth node N12, the twelfth node N12 receiving a second proportional voltage V. BK However, this is not the only limit.

[0074] In a preferred embodiment, it further includes: a third capacitor C L The third capacitor C L One end is connected to the tenth node N10, and the other end is connected to the second grounding terminal GND2, but this is not a limitation.

[0075] In a preferred embodiment, when the current limiting voltage V C If the threshold voltage of the fifth field-effect transistor M5 is exceeded, the fifth field-effect transistor M5 will turn on. As the current flowing through the thirteenth field-effect transistor Mp increases, the current-limiting voltage V... C Decrease, first voltage signal V p Increase to limit current in low-dropout regulators, but do not limit it.

[0076] In a preferred embodiment, when the output voltage V OUT The first proportional voltage V satisfies a preset percentage of the predetermined voltage. BK1 With reference voltage V REF The comparison is performed, and the comparison result changes from low to high, generating a rising edge. This causes the output voltage V1 of the D flip-flop D1 to become high. After passing through the level shifter, a second voltage signal Vctrl is generated to drive the second field-effect transistor M2 and the sixth field-effect transistor M17 to turn off, while simultaneously turning on the tenth field-effect transistor M23 to close the current-limiting circuit, but not to limit the current.

[0077] In a preferred embodiment, the first field-effect transistor M1 is a PMOS field-effect transistor, the second field-effect transistor M2 is an NMOS field-effect transistor, the third field-effect transistor M3 is an NMOS field-effect transistor, the fourth field-effect transistor M4 is an NMOS field-effect transistor, the fifth field-effect transistor M5 is a PMOS field-effect transistor, the sixth field-effect transistor M17 is a PMOS field-effect transistor, the seventh field-effect transistor M18 is a PMOS field-effect transistor, the eighth field-effect transistor M21 is an NMOS field-effect transistor, the ninth field-effect transistor M22 is a PMOS field-effect transistor, the tenth field-effect transistor M23 is a PMOS field-effect transistor, the eleventh field-effect transistor M19 is a PMOS field-effect transistor, the twelfth field-effect transistor M20 is a PMOS field-effect transistor, and the thirteenth field-effect transistor Mp is a PMOS field-effect transistor, but this is not a limitation.

[0078] The specific embodiments of the present invention are as follows:

[0079] This invention provides a switchable current-limiting circuit for a high-voltage LDO. The system implementing this circuit includes an output current detection module, a current limiting module, and a current-limiting circuit control signal generation module. First, the current of the thirteenth field-effect transistor Mp (power transistor Mp) is detected. The first field-effect transistor M1 replicates the current of the power transistor proportionally. The fourth field-effect transistor M4 further replicates the current of the first field-effect transistor M1. The current of the fourth field-effect transistor M4, combined with the current-limiting resistor R4, generates a current-limiting voltage V. C V C The voltage is compared with the threshold voltage of the fifth field-effect transistor M5. Once the current-limiting voltage V... C If the voltage is too high, the fifth MOSFET M5 will be activated, limiting the current voltage V. C The value of the fifth field-effect transistor M5 determines the response of the first voltage signal V. P (gate voltage V) P The pull-up capability of the voltage increases with the larger the current of the Mp transistor, the lower the current-limiting voltage V. C The smaller the voltage, the lower the V P The higher the voltage, the more effective the current limiting in the LDO circuit becomes. Once the output voltage reaches 97% of the predetermined voltage, V...BK1 Voltage and reference voltage V REF The comparison result changes from low to high, generating a rising edge that makes the V1 voltage high. After passing through the level shifter, the Vctrl voltage is generated, which turns off the second field-effect transistor M2 and the sixth field-effect transistor M17 and turns on the tenth field-effect transistor M23, thus turning off the current limiting circuit. After that, the V1 voltage will remain high unless the D flip-flop is reset by a reset signal, which will lower the V1 voltage.

[0080] In the current detection module, the aspect ratio of the thirteenth MOSFET Mp and the first MOSFET M1 is N. M1 replicates the current of the power transistor Mp at a ratio of 1 / N. The current of M1 flows to M3, and M4 replicates the current of M3 at a certain ratio, forming a detection current that is fed into the fourth resistor R4. The detection current and the fourth resistor R4 generate a current-limiting voltage V. C .

[0081] In the current limiting module, resistor R4 controls V based on the magnitude of the detected current. C Size, V C The voltage is compared with the threshold voltage of transistor M5 to determine whether the fifth field-effect transistor M5 is turned on or off, and the effect of the fifth field-effect transistor M5 on V. P The pull-up value of the voltage.

[0082] The output voltage V is generated in the current limiting circuit control signal generation module. OUT Partial proportional values ​​and V REF The comparison generates a control signal for the current-limiting circuit, thereby controlling the opening and closing of the current-limiting circuit.

[0083] Among them, the first field-effect transistor M1 is a PMOS field-effect transistor, the second field-effect transistor M2 is an NMOS field-effect transistor, the third field-effect transistor M3 is an NMOS field-effect transistor, the fourth field-effect transistor M4 is an NMOS field-effect transistor, the fifth field-effect transistor M5 is a PMOS field-effect transistor, the sixth field-effect transistor M17 is a PMOS field-effect transistor, the seventh field-effect transistor M18 is a PMOS field-effect transistor, the eighth field-effect transistor M21 is an NMOS field-effect transistor, the ninth field-effect transistor M22 is a PMOS field-effect transistor, the tenth field-effect transistor M23 is a PMOS field-effect transistor, the eleventh field-effect transistor M19 is a PMOS field-effect transistor, the twelfth field-effect transistor M20 is a PMOS field-effect transistor, and the thirteenth field-effect transistor Mp is a PMOS field-effect transistor.

[0084] In the current detection module, the gate of the first field-effect transistor M1 is connected to the gate of the thirteenth field-effect transistor Mp and the drain of the tenth field-effect transistor M23; the drain of the first field-effect transistor M1 is connected to the drain of the second field-effect transistor M2; the source of the second field-effect transistor M2 is connected to the gate and drain of the third field-effect transistor M3; the gate of the third field-effect transistor M3 is connected to the gate of the fourth field-effect transistor M4; and the drain of the fourth field-effect transistor M4 is connected to the fourth resistor R4.

[0085] In the current limiting module, the gate of the fifth field-effect transistor M5 is connected to the drain of the fourth field-effect transistor M4 and the fourth resistor R4, and the drain of the fifth field-effect transistor M5 is connected to the gate of the thirteenth field-effect transistor Mp and the drain of the tenth field-effect transistor M23.

[0086] In the current limiting control signal generation module, the third resistor R3 is connected to the positive terminal of the error amplifier Amp, and the second resistor R2 is connected to the positive terminal of the comparator. REF The voltage is connected to the negative terminals of the error amplifier Amp and the comparator. The output of the comparator is connected to the clk terminal of the D flip-flop D1. The Q terminal of the D flip-flop D1 is connected to the level shifter. The level shifter is connected to the gates of the second field-effect transistor M2, the sixth field-effect transistor M17, and the tenth field-effect transistor M23.

[0087] Figure 1 This is a schematic diagram of an LDO with a current limiting circuit, which includes an error amplifier, power transistor, feedback resistor, current detection circuit, current limiting circuit, and current limiting circuit control signal generation module. Figure 2 This is the schematic diagram of an LDO with a current-limiting circuit. (Reference) Figure 1 and 2 To ensure that the power transistor has a large current driving capability, the design value of the power transistor size is very large. Therefore, when the high voltage power supply is powered on, the current of the power transistor is large.

[0088] The first field-effect transistor M1 copies the current of the thirteenth field-effect transistor Mp, and the fourth field-effect transistor M4 further copies the current of the first field-effect transistor M1. Combined with the fourth resistor R4, this generates a current-limiting voltage V. C Current limiting voltage V C This controls the on / off state of the fifth field-effect transistor M5. When the fifth field-effect transistor M5 is on, it controls the gate voltage V of the power transistor. P Pull it up to limit the output current of the thirteenth field-effect transistor Mp (power transistor Mp).

[0089] When the LDO output voltage exceeds 97% of the predetermined value, V BK1 Voltage greater than V REFThe voltage comparator outputs a high voltage, generating a rising edge. The V1 voltage changes from low to high and remains constant. After passing through the level shifter, Vctrl and OUTN voltages change from high to low, and OUTP voltage changes from low to high. The second MOSFET M2 is turned off, the current detection returns to zero, and V... C As the voltage rises, the fifth field-effect transistor M5 turns off, and the current limiting effect of the thirteenth field-effect transistor Mp (power transistor Mp) disappears.

[0090] When the fifth MOSFET M5 is turned off, its current becomes zero. The current contributed by the fifth MOSFET M5 to the twelfth MOSFET M20 disappears, and the current in the twelfth MOSFET M20 decreases. This means the gate-source voltage difference of the twelfth MOSFET M20 decreases, and the Vo of the power transistor decreases. P The voltage will drop to some extent, and the power transistor current will increase significantly. As the OUTN voltage decreases, the tenth MOSFET M23 turns on, and the current from the ninth MOSFET M22 flows to the twelfth MOSFET M20. This compensates for the decrease in current of the twelfth MOSFET M20 caused by the turn-off of the fifth MOSFET M5, thus shutting down the current-limiting circuit and ensuring that the power transistor current remains within a reasonable range at the moment the current-limiting circuit is turned off.

[0091] The sixth field-effect transistor M17 is initially turned on upon power-up. The seventh field-effect transistor M18 limits the voltage V2. Under the action of the twelfth field-effect transistor M20, the voltage V2 is limited. P The voltage limits the current of the power transistor Mp. After startup, the OUTP voltage changes from low to high, M17 shuts down, and the current limiting effect disappears.

[0092] Under the influence of the current from the eleventh field-effect transistor M19, the eighth field-effect transistor M21 and the fifth resistor R5 increase the drain voltage of the twelfth field-effect transistor M20, thus increasing V. P Voltage is used to limit current and simultaneously reduce the current of the twelfth MOSFET M20, ensuring that the currents of the fifth MOSFET M5 and the ninth MOSFET M22 are within a reasonable matching range when the transistor is on. This prevents fluctuations in the current of the twelfth MOSFET M20 from causing voltage fluctuations. P Changes in voltage and power transistor current.

[0093] Figure 3 The diagram shows the simulation results of an LDO circuit with a current-limiting circuit. The LDO power-on time is 4.06ms, and the maximum current of the power supply voltage during power-on is 5.88mA. After power-on, the current-limiting circuit is turned off, and the LDO can drive a 30mA current load without a drastic drop in output voltage. This demonstrates that the present invention can effectively improve the current driving capability of the LDO output and reduce the requirements of the high-voltage LDO circuit on the DC-DC power supply.

[0094] In summary, the current limiting circuit for low dropout regulators of the present invention can improve the current driving capability of the LDO output while realizing current limiting of the high voltage LDO circuit, and reduce the requirements of the high voltage LDO circuit for the DC-DC power supply.

[0095] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A current-limiting circuit for a low-dropout voltage regulator, characterized in that, include: A first field-effect transistor (M1) is used to respond to the first voltage signal (V) at the sixth node (N6). p This switches the current path between the positive voltage signal (VDD) and the first node (N1); A second field-effect transistor (M2) is used to switch the current path between the first node (N1) and the second node (N2) in response to the voltage signal of the second voltage signal (Vctrl); A third field-effect transistor (M3) is used to switch the current path between the second node (N2) and the first ground terminal (GND1) in response to the voltage signal of the second node (N2); A fourth field-effect transistor (M4) is used to switch the current path between the third node (N3) and the first ground terminal (GND1) in response to the voltage signal of the second node (N2); A fifth field-effect transistor (M5) is used to respond to the voltage signal at the third node (N3), for the positive voltage signal (VDD) and the first voltage signal (V). p The third node (N3) switches the current path between the nodes, and generates a current-limiting voltage (V). C ); A sixth field-effect transistor (M17) is used to switch the current path between the positive voltage signal (VDD) and the fourth node (N4) in response to the voltage signal of the third voltage signal (OUTP); A seventh field-effect transistor (M18) is used to switch the current path between the fourth node (N4) and the fifth node (N5) in response to the voltage signal of the fifth node (N5); An eighth field-effect transistor (M21) is used to switch the current path between the seventh node (N7) and the first ground terminal (GND1) in response to the voltage signal of the seventh node (N7); A ninth field-effect transistor (M22) is used to respond to the third voltage signal (V). BP The voltage signal of the device switches the current path between the eighth node (N8) and the ninth node (N9); A tenth field-effect transistor (M23) is used to switch the current path between the ninth node (N9) and the sixth node (N6) in response to the voltage signal of the fourth voltage signal (OUTN); An eleventh field-effect transistor (M19) is used to respond to the third voltage signal (V). BP The voltage signal of the signal is used to switch the current path between the eighth node (N8) and the sixth node (N6); A twelfth field-effect transistor (M20) is used to switch the current path between the sixth node (N6) and the seventh node (N7) in response to the voltage signal of the fifth node (N5); A thirteenth field-effect transistor (Mp) is used to switch the current path between the positive voltage signal (VDD) and the tenth node (N10) in response to the first voltage signal (Vp) at the sixth node (N6). The tenth node (N10) generates the output voltage (V) of the low-dropout regulator. OUT ); An error amplifier (Amp) is connected to the second proportional voltage (V) at the output of the low dropout regulator. BK The negative input terminal is connected to a reference voltage (V). REF The output is connected to the fifth node (N5); A comparator, the positive input of which is connected to the output voltage (V). OUT The first proportional voltage (V) BK1 The negative input terminal is connected to a reference voltage (V). REF ); A D flip-flop (D1) is provided, the input of which is connected to the output of the comparator to store and synchronize signals. as well as A level shifter, the input of which is connected to the output of the D flip-flop (D1), is used to switch to different voltage domains to generate a second voltage signal (Vctrl), a third voltage signal (OUTP), and a fourth voltage signal (OUTN).

2. The current limiting circuit for a low-dropout voltage regulator as described in claim 1, characterized in that, Also includes: The first resistor (R1), the second resistor (R2), and the third resistor (R3) are connected in series between the tenth node (N10) and the second ground terminal (GND2). The first proportional voltage (V) is generated between the first resistor (R1) and the second resistor (R2). BK1 The second resistor (R2) and the third resistor (R3) generate a second proportional voltage (V) at the output terminal. BK ).

3. The current limiting circuit for a low-dropout voltage regulator as described in claim 2, characterized in that, Also includes: A fourth resistor (R4) is connected in series between the positive voltage signal (VDD) and the third node (N3).

4. The current limiting circuit for a low-dropout regulator as described in claim 3, characterized in that, Also includes: The fifth resistor (R5) is connected in series between the eighth field-effect transistor (M21) and the first ground terminal (GND1).

5. The current limiting circuit for a low-dropout regulator as described in claim 2, characterized in that, Also includes: A first capacitor (C1) is connected in series between the fifth node (N5) and the eleventh node (N11), and the eleventh node (N11) receives the output voltage (V). OUT ).

6. The current limiting circuit for a low-dropout regulator as described in claim 5, characterized in that, Also includes: A second capacitor (C2) is connected in series between the eleventh node (N11) and the twelfth node (N12), wherein the twelfth node (N12) receives the second proportional voltage (V). BK ).

7. The current limiting circuit for a low-dropout regulator as described in claim 6, characterized in that, Also includes: Third capacitor (C) L The third capacitor (C) L One end of the terminal is connected to the tenth node (N10), and the other end is connected to the second ground terminal (GND2).

8. The current limiting circuit for a low dropout voltage regulator as described in claim 1, characterized in that, When the current limiting voltage (V) C If the current exceeds the threshold voltage of the fifth field-effect transistor (M5), then the fifth field-effect transistor (M5) turns on. As the current flowing through the thirteenth field-effect transistor (Mp) increases, the current-limiting voltage (V) increases. C The first voltage signal (V) decreases. p The current is increased to limit the current of the low-dropout regulator.

9. The current limiting circuit for a low-dropout regulator as described in claim 1, characterized in that, When the output voltage (V) OUT The first proportional voltage (V) satisfies a preset percentage of a predetermined voltage. BK1 ) and reference voltage (V REF The comparison is performed, and the comparison result generates a rising edge from low to high, causing the output voltage (V1) of the D flip-flop (D1) to become high. After passing through the level shifter, the second voltage signal (Vctrl) is generated to drive the second field-effect transistor (M2) and the sixth field-effect transistor (M17) to be cut off, while the tenth field-effect transistor (M23) is turned on to turn off the current limiting circuit.

10. The current limiting circuit for a low dropout voltage regulator as described in claim 1, characterized in that, The first field-effect transistor (M1) is a PMOS field-effect transistor, the second field-effect transistor (M2) is an NMOS field-effect transistor, the third field-effect transistor (M3) is an NMOS field-effect transistor, the fourth field-effect transistor (M4) is an NMOS field-effect transistor, the fifth field-effect transistor (M5) is a PMOS field-effect transistor, the sixth field-effect transistor (M17) is a PMOS field-effect transistor, the seventh field-effect transistor (M18) is a PMOS field-effect transistor, the eighth field-effect transistor (M21) is an NMOS field-effect transistor, the ninth field-effect transistor (M22) is a PMOS field-effect transistor, the tenth field-effect transistor (M23) is a PMOS field-effect transistor, and the eleventh field-effect transistor (M19) is a PMOS field-effect transistor. It is a PMOS field-effect transistor, and the twelfth field-effect transistor (M20) is a PMOS field-effect transistor. The thirteenth field-effect transistor (Mp) is a PMOS field-effect transistor.

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