A multi-bit low-cost current trimming method

Abstract

The application discloses a kind of multi-bit low-cost current trimming methods, including multi-bit trimming current circuit;The multi-bit trimming current circuit includes A1 operational amplifier circuit, bit number control circuit, trimming TRIM circuit;In the trimming TRIM circuit, a primary switch array and a secondary multiplexing switch array are constructed by introducing MOS switch, the on or off of each MOS switch in the primary switch array and the secondary multiplexing switch array is passed through, the access resistance of series resistance circuit in trimming TRIM circuit is changed;The bit number control circuit outputs control signal to control the on or off of each MOS switch in the primary switch array and the secondary multiplexing switch array, so that trimming TRIM circuit outputs multi-way feedback signal;The multi-way feedback signal is input to the inverting input terminal of AI operational amplifier circuit, and the output current of AI operational amplifier circuit is trimmed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and particularly to a low-cost, multi-digit current adjustment method. Background Technology

[0002] In the design of modern high-performance analog integrated circuits (such as voltage reference sources, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs), a high-precision current or voltage reference is the core guarantee of system performance. However, due to the non-ideal nature of semiconductor manufacturing processes, chip manufacturing inevitably involves process deviations. Combined with temperature drift and power supply voltage fluctuations in the operating environment, this often causes the actual circuit parameters to deviate from the design target. Therefore, to improve chip yield and consistency, trimming techniques must be introduced after chip manufacturing or during operation to calibrate circuit parameters.

[0003] Currently, mainstream on-chip integrated calibration methods mainly include fuse calibration, laser calibration, and digital calibration technology based on switched resistor networks; among them, digital calibration technology is widely used due to its programmability and flexibility. Traditional current calibration circuits typically employ a multi-way selector switch combined with a series resistor network architecture. By controlling the on / off state of the switch, the voltage division ratio of the resistor network or the resistance value connected can be changed, thereby achieving fine-tuning of the bias current or reference voltage. However, to achieve N-bit calibration accuracy, at least 2N resistor units with different resistance values ​​are usually required. For multi-bit circuits, the layout area is too large, which is not conducive to layout design. Therefore, for 8-bit and above circuits, the traditional trimming structure has an excessively large layout area, and the switch array scheme needs to be optimized to reduce the layout area while ensuring trimming linearity. This structure is often affected by the switches. The switches connected in series in the resistor path have non-zero on-resistance. This on-resistance is connected in parallel with the trimming resistor, and its value will drift with the power supply voltage, temperature and process angle, introducing nonlinear error. This makes the trimmed current value inaccurate and unpredictable, and also reduces the trimming accuracy. Summary of the Invention

[0004] Purpose of the invention: In order to overcome the shortcomings of the existing technology, the present invention provides a multi-digit, low-cost current adjustment method. By introducing MOS switches to construct a primary main switch array and a secondary multiplexed switch array, the connection of the resistor is controlled by the on / off state of the MOS switches in the primary main switch array and the secondary multiplexed switch array, thereby achieving high-precision current adjustment.

[0005] Technical Solution: To achieve the above objectives, the present invention provides a low-cost multi-digit current adjustment method, comprising a multi-digit current adjustment circuit; the multi-digit current adjustment circuit includes an A1 operational amplifier circuit, a bit-control circuit, and a adjustment TRIM circuit; the adjustment TRIM circuit constructs a primary main switch array and a secondary multiplexed switch array by introducing MOS switches, and changes the input resistance value of the series resistor circuit in the adjustment TRIM circuit by turning on or off each MOS switch in the primary main switch array and the secondary multiplexed switch array; the bit-control circuit outputs a control signal to control the turning on or off of each MOS switch in the primary main switch array and the secondary multiplexed switch array, causing the adjustment TRIM circuit to output multiple feedback signals; the multiple feedback signals are input to the inverting input terminal of the AI ​​operational amplifier circuit to adjust the output current of the AI ​​operational amplifier circuit.

[0006] Furthermore, when the multi-bit trimming current circuit is powered on, the non-inverting input terminal of the A1 operational amplifier circuit receives the Vref reference voltage, and the output terminal of the A1 operational amplifier circuit outputs the Vout voltage. At this time, the trimming TRIM circuit starts to work. The bit control circuit outputs CTRL_AMP<3:0> and CTRL_RES<3:0> control signals to the control terminals of the first-stage main switch array and the second-stage multiplexed switch array, respectively. Through the CTRL_AMP<3:0> and CTRL_RES<3:0> control signals, the circuit controls the conduction or disconnection of each MOS switch in the first-stage main switch array and the second-stage multiplexed switch array, so that the trimming TRIM circuit outputs DIV. <4> To DIV <0> Multiple feedback signals; DIV <4> To DIV <0> The multiple feedback signals are input to the inverting input terminal of the A1 op-amp circuit, and the A1 op-amp circuit adjusts the output Iout current according to the received multiple feedback signals.

[0007] Furthermore, the A1 operational amplifier circuit includes an operational amplifier input circuit; the operational amplifier input circuit includes an MP11 transistor, a non-inverting input circuit, and an inverting input circuit; the non-inverting input circuit includes an MP1 transistor, an MP2 transistor, an MP3 transistor, an MP4 transistor, and an MP5 transistor; the gates of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor all serve as the IN_P non-inverting input terminal; the sources of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor are all electrically connected to the drain of the MP11 transistor.

[0008] Furthermore, the inverting input circuit includes MP6 transistor, MP7 transistor, MP8 transistor, MP9 transistor, and MP10 transistor; the gates of the MP6 transistor, MP7 transistor, MP8 transistor, MP9 transistor, and MP10 transistor are respectively used as IN_N. <4> IN_N <3> IN_N <2> IN_N <1> and IN_N <0> Five inverting input terminals; the sources of the MP6, MP7, MP8, MP9 and MP10 transistors are all electrically connected to the drain of the MP11 transistor.

[0009] Furthermore, the drains of the MP1, MP2, MP3, MP4, and MP5 transistors are electrically connected to each other; the drains of the MP6, MP7, MP8, MP9, and MP10 transistors are electrically connected to each other.

[0010] Furthermore, the series resistor circuit of the adjustment TRIM circuit includes resistors R0 to R16; one end of resistor R0 serves as the input terminal of the adjustment TRIM circuit, and the other end of resistor R0 is electrically connected to one end of resistor R16 through resistors R1 to R15 connected in series, and the other end of resistor R16 is grounded.

[0011] Furthermore, the primary main switch array of the adjustment TRIM circuit includes transistors MN1 to MN17; the drains of transistors MN1 to MN17 are electrically connected to one end of resistors R0 to R16 respectively; the sources of transistors MN1, MN3, MN5, MN7, MN9, MN11, MN13, MN15, and MN17 are electrically connected to each other and serve as the first output terminal of the primary main switch array; the sources of transistors MN2, MN4, MN6, MN8, MN10, MN12, MN14, and MN16 are electrically connected to each other and serve as the second output terminal of the primary main switch array; the internal decoding logic circuit of the adjustment TRIM circuit converts the CTRL_AMP<3:0> control signal into control levels CTRL_16 to CTRL_0 that control the gates of transistors MN1 to MN17 respectively.

[0012] Furthermore, the secondary multiplexed switch array of the trimmed TRIM circuit includes transistors MN21 to MN30; the drains of transistors MN21, MN23, MN25, MN27, and MN29 are all electrically connected to the first output terminal of the primary main switch array, and the drains of transistors MN22, MN24, MN26, MN28, and MN30 are all electrically connected to the second output terminal of the primary main switch array; the source of transistor MN21 and the source of transistor MN22 are electrically connected, outputting DIV. <4> Feedback signal to IN_N <4> Inverting input terminal; the source of transistor MN23 and the source of transistor MN24 are electrically connected, outputting DIV. <3> Feedback signal to IN_N <3> Inverting input terminal; the source of transistor MN25 and the source of transistor MN26 are electrically connected, outputting DIV. <2> Feedback signal to IN_N <2> Inverting input terminal; the source of transistor MN27 and the source of transistor MN28 are electrically connected, outputting DIV. <1> Feedback signal to IN_N <1> Inverting input terminal; the source of transistor MN29 and the source of transistor MN30 are electrically connected, outputting DIV. <0> Feedback signal to IN_N <0> Inverting input terminal.

[0013] Furthermore, the internal decoding logic circuit of the trimming TRIM circuit converts the CTRL_RES<3:0> control signal into control levels H_4~H_0 for controlling the gates of transistors MN21, MN23, MN25, MN27 and MN29, respectively, and control levels L_4~L_0 for controlling the gates of transistors MN22, MN24, MN26, MN28 and MN30, respectively.

[0014] Beneficial Effects: This invention provides a low-cost, multi-bit current trimming method. By employing a segmented architecture of high-4-bit op-amp input trimming + low-4-bit resistor selection trimming, the required 256 resistor units are drastically reduced to approximately 32 resistor units. This architecture, while maintaining 8-bit high precision, significantly reduces the number of passive components, thereby significantly reducing the circuit layout area and effectively lowering chip manufacturing costs. Addressing the issue of nonlinear errors introduced by the switch on-resistance in traditional structures, this invention utilizes the virtual short and virtual open characteristics of operational amplifiers and a negative feedback mechanism. High-bit trimming is placed at the input of the op-amp circuit, while low-bit trimming is placed in the feedback network or output branch. This design effectively isolates or weakens the influence of the MOS switch on-resistance on the voltage division ratio of the trimming resistor network. Regardless of process angle or temperature variations, the circuit maintains high linearity and stability, ensuring precise controllability of the output current Iout. This is particularly suitable for reference current sources and high-precision ADC / DAC chip designs with stringent precision requirements. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of a multi-position adjustable current circuit.

[0016] Figure 2 This is the circuit diagram of the op-amp input circuit.

[0017] Figure 3 The circuit structure diagram for adjusting the TRIM circuit. Detailed Implementation

[0018] The invention will now be further described with reference to the accompanying drawings.

[0019] like Figure 1 As shown, a low-cost multi-digit current adjustment method includes a multi-digit current adjustment circuit. The multi-digit current adjustment circuit includes an A1 operational amplifier circuit 1, a bit-control circuit 2, and an adjustment TRIM circuit 3. The adjustment TRIM circuit 3 constructs a primary main switch array and a secondary multiplexed switch array by introducing MOS switches. The resistance value of the series resistor circuit in the adjustment TRIM circuit 3 is changed by turning on or off each MOS switch in the primary main switch array and the secondary multiplexed switch array. The bit-control circuit 2 outputs a control signal to control the on or off of each MOS switch in the primary main switch array and the secondary multiplexed switch array, causing the adjustment TRIM circuit 3 to output multiple feedback signals. These multiple feedback signals are input to the inverting input terminal of the A1 operational amplifier circuit 1 to adjust the output current of the A1 operational amplifier circuit 1.

[0020] When the multi-bit trimming current circuit is powered on, the non-inverting input terminal of the A1 operational amplifier circuit 1 receives the reference voltage Vref, and the output terminal of the A1 operational amplifier circuit 1 outputs the voltage Vout. At this time, the trimming TRIM circuit 3 starts to work. The bit control circuit 2 outputs CTRL_AMP<3:0> and CTRL_RES<3:0> control signals to the control terminals of the primary main switch array and the secondary multiplexed switch array, respectively. Through the CTRL_AMP<3:0> and CTRL_RES<3:0> control signals, the circuit controls the conduction or disconnection of each MOS switch in the primary main switch array and the secondary multiplexed switch array, so that the trimming TRIM circuit 3 outputs DIV. <4> To DIV <0> Multiple feedback signals; DIV <4> To DIV <0> The multiple feedback signals are input to the inverting input of the A1 op-amp circuit. The A1 op-amp circuit adjusts the output Iout current according to the received multiple feedback signals. The high four bits are controlled by the CTRL_AMP<3:0> control signal, and the low four bits are controlled by the decoded CTRL_RES<3:0> control signal. The switching on and off enables the configurability of the series resistor circuit. The entire circuit is controlled by MOS switches to control the connection of each resistor in the resistor array, changing the bias current path impedance to adjust the current value and ensure accuracy.

[0021] The multi-bit trimming current circuit also includes transistors M1 and M2; the output of the A1 operational amplifier circuit is electrically connected to the gate of transistor M1, the drain of transistor M1 is electrically connected to the input of the trimming TRIM circuit, and the source of transistor M1 is electrically connected to the power supply output; the output of the bit control circuit is electrically connected to the control terminal of the trimming TRIM circuit, the output of the trimming TRIM circuit is electrically connected to the inverting input of the A1 operational amplifier circuit, and the non-inverting input of the A1 operational amplifier circuit receives the reference voltage Vref; the output of the A1 operational amplifier circuit is electrically connected to the gate of transistor M2, the source of transistor M2 is electrically connected to the power supply output, and the drain of transistor M2 outputs Iout current. Both transistors M1 and M2 are PMOS transistors.

[0022] like Figure 2 As shown, the A1 operational amplifier circuit 1 includes an operational amplifier input circuit; the operational amplifier input circuit includes an MP11 transistor, a non-inverting input circuit, and an inverting input circuit; the non-inverting input circuit includes MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor; the gates of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor all serve as the IN_P non-inverting input terminal; the sources of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor are all electrically connected to the drain of the MP11 transistor. The MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor are all PMOS transistors.

[0023] The inverting input circuit includes MP6, MP7, MP8, MP9, and MP10 transistors; the gates of the MP6, MP7, MP8, MP9, and MP10 transistors are respectively used as IN_N. <4> IN_N <3> IN_N <2> IN_N <1> and IN_N <0> The circuit has five inverting input terminals; the sources of transistors MP6, MP7, MP8, MP9, and MP10 are all electrically connected to the drain of transistor MP11; the source of transistor MP11 is electrically connected to the VDD power supply output terminal, and transistor MP11 is the tail current transistor of the input terminal of the A1 operational amplifier circuit; the gate of transistor MP11 serves as the control terminal of the A1 operational amplifier circuit, receiving control signals to control the bias current of the input differential pair. Transistors MP6, MP7, MP8, MP9, MP10, and MP11 are all PMOS transistors.

[0024] The drains of transistors MP1, MP2, MP3, MP4, and MP5 are electrically connected to each other, serving as the first output terminal and electrically connected to the drain of the NMOS current mirror; the drains of transistors MP6, MP7, MP8, MP9, and MP10 are electrically connected to each other, serving as the second output terminal and electrically connected to the drain of the NMOS current mirror.

[0025] The operational amplifier input circuit is the core component for voltage comparison and precise control. It employs a differential pair structure. To achieve high-bit trimming without introducing additional input offset voltage, the control of the high four bits' input terminals is composed of multiple parallel MOS transistors arrayed according to a binary weight ratio: MP6, MP7, MP8, MP9, and MP10 transistors in a size ratio of 16:8:4:2:1. The operational amplifier input circuit works in conjunction with the trimming TRIM circuit and the bit-control circuit. By receiving multiple feedback signals and relying on a negative feedback mechanism, it maintains the voltage balance between the non-inverting input terminal's Vref reference voltage and the inverting input signal, thus providing a stable operational amplifier control basis for precise adjustment of the output current Iout and ensuring the accuracy requirements of the 8-bit current trimming.

[0026] like Figure 3As shown, the adjustment TRIM circuit 3 is the core execution component for implementing resistor configuration and reference distribution. A series resistor circuit consisting of multiple resistors serves as a voltage divider network, and a primary main switch array and a secondary multiplexed switch array consisting of multiple MOSFETs serve as a digital control switch array. The series resistor circuit of the adjustment TRIM circuit 3 includes resistors R0 to R16; one end of resistor R0 serves as the input terminal of the adjustment TRIM circuit 3, and the other end of resistor R0 is electrically connected to one end of resistor R16 through resistors R1 to R15 connected in series. The other end of resistor R16 is grounded. The other end of resistor R0 is electrically connected to one end of resistor R1. The other end of resistor R1 is electrically connected to one end of resistor R2. The other end of resistor R2 is electrically connected to one end of resistor R3. The other end of resistor R3 is electrically connected to one end of resistor R4. The other end of resistor R4 is electrically connected to one end of resistor R5. The other end of resistor R5 is electrically connected to one end of resistor R6. The other end of resistor R6 is electrically connected to one end of resistor R7. The other end of resistor R7 is electrically connected to one end of resistor R8. The other end of resistor R8 is electrically connected to one end of resistor R9. The other end of resistor R9 is electrically connected to one end of resistor R10. The other end of resistor R10 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to one end of resistor R12. The other end of resistor R12 is electrically connected to one end of resistor R13. The other end of resistor R13 is electrically connected to one end of resistor R14. The other end of resistor R14 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to one end of resistor R16.

[0027] The primary main switch array of the adjustment TRIM circuit 3 includes transistors MN1 to MN17; the drains of transistors MN1 to MN17 are electrically connected to one end of resistors R0 to R16 respectively; the sources of transistors MN1, MN3, MN5, MN7, MN9, MN11, MN13, MN15, and MN17 are electrically connected to each other and serve as the first output terminal of the primary main switch array; the sources of transistors MN2, MN4, MN6, MN8, MN10, MN12, MN14, and MN16 are electrically connected to each other and serve as the second output terminal of the primary main switch array; the internal decoding logic circuit of the adjustment TRIM circuit 3 converts the CTRL_AMP<3:0> control signal into control levels CTRL_16 to CTRL_0 that control the gates of transistors MN1 to MN17 respectively, for coarse adjustment point selection; the internal decoding logic circuit is a 4-16 line decoder. The drain of transistor MN1 is electrically connected to one end of resistor R0, the drain of transistor MN2 is electrically connected to one end of resistor R1, the drain of transistor MN3 is electrically connected to one end of resistor R2, and so on, with the drain of transistor MN17 electrically connected to one end of resistor R16. Control levels CTRL_16 to CTRL_0 are sequentially input to the gates of transistors MN1 to MN17. All transistors MN1 to MN17 are NMOS transistors.

[0028] The two-stage multiplexed switch array of the trimmed TRIM circuit 3 includes transistors MN21 to MN30; the drains of transistors MN21, MN23, MN25, MN27, and MN29 are all electrically connected to the first output terminal of the primary main switch array, and the drains of transistors MN22, MN24, MN26, MN28, and MN30 are all electrically connected to the second output terminal of the primary main switch array; the source of transistor MN21 and the source of transistor MN22 are electrically connected, outputting DIV. <4> Feedback signal to IN_N <4> Inverting input terminal; the source of transistor MN23 and the source of transistor MN24 are electrically connected, outputting DIV. <3> Feedback signal to IN_N <3> Inverting input terminal; the source of transistor MN25 and the source of transistor MN26 are electrically connected, outputting DIV. <2> Feedback signal to IN_N <2> Inverting input terminal; the source of transistor MN27 and the source of transistor MN28 are electrically connected, outputting DIV. <1> Feedback signal to IN_N <1> Inverting input terminal; the source of transistor MN29 and the source of transistor MN30 are electrically connected, outputting DIV. <0> Feedback signal to IN_N <0> Inverting input terminal. All transistors MN21 to MN30 are NMOS transistors.

[0029] The internal decoding logic circuit of the trimmed TRIM circuit 3 converts the CTRL_RES<3:0> control signal into control levels H_4~H_0 for controlling the gates of transistors MN21, MN23, MN25, MN27 and MN29, and control levels L_4~L_0 for controlling the gates of transistors MN22, MN24, MN26, MN28 and MN30, respectively, for fine node routing. The internal decoding logic circuit is a 4-16 line decoder. Control level H_4 is input to the gate of transistor MN21 to control the conduction or disconnection of transistor MN21; control level H_3 is input to the gate of transistor MN23 to control the conduction or disconnection of transistor MN23; control level H_2 is input to the gate of transistor MN25 to control the conduction or disconnection of transistor MN25; control level H_1 is input to the gate of transistor MN27 to control the conduction or disconnection of transistor MN27; control level H_0 is input to the gate of transistor MN29 to control the conduction or disconnection of transistor MN29; control level L_4 is input to the gate of transistor MN22 to control the conduction or disconnection of transistor MN22; control level L_3 is input to the gate of transistor MN24 to control the conduction or disconnection of transistor MN24; control level L_2 is input to the gate of transistor MN26 to control the conduction or disconnection of transistor MN26; control level L_1 is input to the gate of transistor MN28 to control the conduction or disconnection of transistor MN28; control level L_0 is input to the gate of transistor MN30 to control the conduction or disconnection of transistor MN30.

[0030] Through a two-stage switching network architecture, the trimming TRIM circuit 3 can accurately select specific voltage nodes on the resistor ladder and output them as multiple feedback signals. The two-stage switching network architecture cleverly combines the binary weighting of the op-amp input circuit, breaking through the limitation of 256 resistor arrays required for traditional 8-bit trimming. It can achieve the same high-precision trimming with only a very small number of segmented resistors and multiplexed switching networks, while ensuring good linearity and significantly reducing the layout area.

[0031] It also includes a control circuit, which collects the Iout current output by the A1 operational amplifier circuit, calculates the error ratio based on the output Iout current, and inputs the error ratio to the bit control circuit 2. The bit control circuit 2 converts the error ratio into a multi-bit digital control word, namely the CTRL_AMP<3:0> and CTRL_RES<3:0> control signals, according to the calculated error ratio. The settings of the control circuit enable the multi-bit current adjustment circuit to automatically detect the output current and automatically adjust the output current.

[0032] The current generation depends on the virtual short-circuit characteristic of the op-amp. The specific process of output current generation is as follows: The A1 op-amp circuit clamps the reference voltage across the equivalent resistor R, and the current generated across the equivalent resistor R is Iout = Vref / R. This current is mirrored and output through the current mirror structure. Since Iout is inversely proportional to R, adjusting the output current Iout is essentially changing the resistance value of the equivalent resistor R. The equivalent resistor R is the resistance value of the series resistor circuit.

[0033] An error ratio is calculated by dividing the ideal current value obtained through theoretical calculation or simulation by the actual measured current value, which determines the adjustment range. Based on the calculated error ratio, the adjustment system converts the error ratio into a multi-bit digital control word, namely the CTRL_AMP<3:0> and CTRL_RES<3:0> control signals. The internal decoding logic circuit converts the multi-bit digital control word into the control level for controlling each MOS switch.

[0034] In the design of the tuning resistor network, a MOS switch is connected in parallel across each resistor segment. When the output control level turns on a certain MOS switch, the corresponding part of the resistor is "short-circuited"; conversely, this part of the resistor is connected to the circuit. The resistor connection state changed by the on and off states of each MOS switch is the multi-channel feedback signal fed back to the A1 op-amp circuit. The multi-channel feedback signal directly changes the magnitude of the total equivalent resistance R, thereby changing the output current Iout.

[0035] Assuming a 4-bit controlled series resistor array is used, theoretical calculations and simulations show that the theoretical current at the SET pin is 10μA; however, in testing, the actual measured current at this pin is 5μA. This means the actual current is half the target value, implying that the equivalent resistance R needs to be reduced to 50% of its original value to double the current. Therefore, the control signal 1111 is modified to control signal 1000. After being converted by the internal decoding logic circuit, control signal 1000 provides the control level for each MOS switch, turning on the corresponding MOS switches and halving the equivalent resistance R. This allows the multi-bit current adjustment circuit to ultimately achieve the target current value.

[0036] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered within the scope of protection as understood by the present invention.

Claims

1. A low-cost, multi-digit current adjustment method, characterized in that: The circuit includes a multi-bit adjustment current circuit; the multi-bit adjustment current circuit includes an A1 operational amplifier circuit (1), a bit control circuit (2), and an adjustment TRIM circuit (3); the adjustment TRIM circuit (3) constructs a primary main switch array and a secondary multiplexed switch array by introducing MOS switches, and changes the input resistance value of the series resistor circuit in the adjustment TRIM circuit (3) by turning on or off each MOS switch in the primary main switch array and the secondary multiplexed switch array; the bit control circuit (2) outputs a control signal to control the turning on or off of each MOS switch in the primary main switch array and the secondary multiplexed switch array, so that the adjustment TRIM circuit (3) outputs a multi-channel feedback signal; the multi-channel feedback signal is input to the inverting input terminal of the AI ​​operational amplifier circuit (1) to adjust the output current of the AI ​​operational amplifier circuit (1).

2. The multi-digit, low-cost current adjustment method according to claim 1, characterized in that: When the multi-bit trimming current circuit is powered on, the non-inverting input terminal of the A1 operational amplifier circuit (1) receives the reference voltage Vref, and the output terminal of the A1 operational amplifier circuit (1) outputs the voltage Vout. At this time, the trimming TRIM circuit (3) starts to work, and the bit control circuit (2) outputs the CTRL_AMP<3:0> and CTRL_RES<3:0> control signals to the control terminals of the first-level main switch array and the second-level multiplexed switch array, respectively. The CTRL_AMP<3:0> and CTRL_RES<3:0> control signals control the conduction or disconnection of each MOS switch in the first-level main switch array and the second-level multiplexed switch array, so that the trimming TRIM circuit (3) outputs DIV. <4> To DIV <0> Multiple feedback signals; DIV <4> To DIV <0> The multiple feedback signals are input to the inverting input terminal of the A1 op-amp circuit, and the A1 op-amp circuit adjusts the output Iout current according to the received multiple feedback signals.

3. The multi-digit, low-cost current adjustment method according to claim 2, characterized in that: The A1 operational amplifier circuit (1) includes an operational amplifier input circuit; the operational amplifier input circuit includes an MP11 transistor, a non-inverting input circuit, and an inverting input circuit; the non-inverting input circuit includes an MP1 transistor, an MP2 transistor, an MP3 transistor, an MP4 transistor, and an MP5 transistor; the gates of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor are all used as the IN_P non-inverting input terminal; the sources of the MP1 transistor, MP2 transistor, MP3 transistor, MP4 transistor, and MP5 transistor are all electrically connected to the drain of the MP11 transistor.

4. The multi-digit, low-cost current adjustment method according to claim 3, characterized in that: The inverting input circuit includes MP6, MP7, MP8, MP9, and MP10 transistors; the gates of the MP6, MP7, MP8, MP9, and MP10 transistors are respectively used as IN_N. <4> IN_N <3> IN_N <2> IN_N <1> and IN_N <0> Five inverting input terminals; the sources of the MP6, MP7, MP8, MP9 and MP10 transistors are all electrically connected to the drain of the MP11 transistor.

5. The multi-digit, low-cost current adjustment method according to claim 4, characterized in that: The drains of the MP1, MP2, MP3, MP4 and MP5 transistors are electrically connected to each other; the drains of the MP6, MP7, MP8, MP9 and MP10 transistors are electrically connected to each other.

6. The multi-digit, low-cost current adjustment method according to claim 2, characterized in that: The series resistor circuit of the adjustment TRIM circuit (3) includes resistors R0 to R16; one end of resistor R0 serves as the input terminal of the adjustment TRIM circuit (3), and the other end of resistor R0 is electrically connected to one end of resistor R16 through resistors R1 to R15 connected in series. The other end of resistor R16 is grounded.

7. The multi-digit, low-cost current adjustment method according to claim 2, characterized in that: The primary main switch array of the trimming TRIM circuit (3) includes transistors MN1 to MN17; the drains of transistors MN1 to MN17 are electrically connected to one end of resistors R0 to R16 respectively; the sources of transistors MN1, MN3, MN5, MN7, MN9, MN11, MN13, MN15 and MN17 are electrically connected to each other and serve as the first output terminal of the primary main switch array; the sources of transistors MN2, MN4, MN6, MN8, MN10, MN12, MN14 and MN16 are electrically connected to each other and serve as the second output terminal of the primary main switch array; the internal decoding logic circuit of the trimming TRIM circuit (3) converts the CTRL_AMP<3:0> control signal into control levels CTRL_16 to CTRL_0 that control the gates of transistors MN1 to MN17 respectively.

8. The multi-digit, low-cost current adjustment method according to claim 2, characterized in that: The secondary multiplexed switch array of the trimmed TRIM circuit (3) includes transistors MN21 to MN30; the drains of transistors MN21, MN23, MN25, MN27, and MN29 are electrically connected to the first output terminal of the primary main switch array, and the drains of transistors MN22, MN24, MN26, MN28, and MN30 are electrically connected to the second output terminal of the primary main switch array; the source of transistor MN21 and the source of transistor MN22 are electrically connected, and the output DIV is... <4> Feedback signal to IN_N <4> Inverting input terminal; the source of transistor MN23 and the source of transistor MN24 are electrically connected, outputting DIV. <3> Feedback signal to IN_N <3> Inverting input terminal; the source of transistor MN25 and the source of transistor MN26 are electrically connected, outputting DIV. <2> Feedback signal to IN_N <2> Inverting input terminal; the source of transistor MN27 and the source of transistor MN28 are electrically connected, outputting DIV. <1> Feedback signal to IN_N <1> Inverting input terminal; the source of transistor MN29 and the source of transistor MN30 are electrically connected, outputting DIV. <0> Feedback signal to IN_N <0> Inverting input terminal.

9. A low-cost, multi-digit current adjustment method according to claim 8, characterized in that: The internal decoding logic circuit of the trimmed TRIM circuit (3) converts the CTRL_RES<3:0> control signal into control levels H_4~H_0 for the gates of transistors MN21, MN23, MN25, MN27 and MN29, and control levels L_4~L_0 for the gates of transistors MN22, MN24, MN26, MN28 and MN30, respectively.

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