Low dropout linear regulator with high power supply rejection ratio and method of operation thereof

Abstract

The application provides a low-drop linear voltage regulator with high power supply rejection ratio and a working method thereof. The low-drop linear voltage regulator comprises a folded common-source common-gate operational amplifier circuit, which amplifies the voltage difference between an output feedback voltage and a reference voltage and then outputs the voltage difference to a driving circuit; the driving circuit is used for separating a low-frequency pole due to its small output impedance; the low-drop linear voltage regulator further comprises a power stage, which comprises a power tube and a negative feedback resistor string connected in series, and the gate of the power tube is connected with the output end of the driving circuit; the low-drop linear voltage regulator further comprises a current sampling circuit, which is used for sampling the driving current of the power tube; and the low-drop linear voltage regulator further comprises an adaptive biasing circuit, which receives an adaptive voltage, mirrors the adaptive voltage through a current mirror, and then outputs an output current which is in a proportional coefficient with the driving current of the power tube. The application further provides a working method of the low-drop linear voltage regulator. The low-drop linear voltage regulator can have a power supply rejection ratio in a 300mA load range while having low power consumption, and the circuit has a relatively accurate overcurrent protection threshold.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to a low dropout linear regulator with a high power supply rejection ratio and a method for operating such a low dropout linear regulator. Background Technology

[0002] With the development of SOC technology, analog circuits, digital circuits, mixed-signal circuits, and radio frequency circuits can all be integrated onto a single chip. Each module has different power supply performance requirements. For example, image sensor chips have high requirements for power supply ripple in the 1kHz to 100kHz frequency range. This necessitates low dropout regulators (LDOs) with high power supply rejection ratios (PSRR) to mitigate power supply interference to sensitive modules.

[0003] The main sources of power supply noise at the output of a low-dropout linear regulator include: first, the gate-source parasitic capacitance coupling of the power transistor; second, the limited power supply noise suppression capability of the error amplifier (EA); third, the limited output impedance of the power transistor; and fourth, power supply noise from the reference voltage. To address these issues, existing technologies employ corresponding techniques to improve the power supply rejection ratio (PSRR) for different noise sources. These techniques include using a sampling NMOS transistor as the power transistor, employing a cascode current mirror in the error amplifier to enhance its own PSRR, inserting a low-pass filter between the reference voltage and the differential input transistor, feedforward ripple reduction, and widening the loop bandwidth. These methods can also be used in combination.

[0004] For example, Chinese invention patent application CN116301163A discloses a technical solution to improve loop bandwidth by inserting a buffer between the error amplifier and the power transistor. This solution has the disadvantage of high power consumption of the buffer. In the invention patent application CN117111665A, the high power supply rejection ratio and low dropout linear regulator is disclosed. The adaptive bias current is obtained by the field-effect transistor Mps, which is directly mirrored with MP, and then mirrored to the field-effect transistor M10 to adjust the tail current of the error amplifier. However, as the load increases to a certain extent, the replication current of the super-field-effect transistor Mps may be too large. Summary of the Invention

[0005] The first objective of this invention is to provide a low-dropout linear regulator with low quiescent power consumption and high power supply rejection ratio.

[0006] A second objective of the present invention is to provide a method for operating the aforementioned low-dropout linear regulator with high power supply rejection ratio.

[0007] To achieve the first objective of this invention, the high power supply rejection ratio low dropout linear regulator provided by this invention includes a folded cascode operational amplifier circuit. The folded cascode operational amplifier circuit includes an input differential pair, two cascode amplifiers, and a current mirror. The folded cascode operational amplifier circuit amplifies the voltage difference between the output feedback voltage and the reference voltage and outputs it to the drive circuit. The drive circuit includes a common-source amplifier and a load. The load includes a series-connected diode and a resistor. The output impedance of the drive circuit is less than the output impedance of the folded cascode operational amplifier circuit. The input terminal of the common-source amplifier is connected to the folded cascode operational amplifier circuit. The power stage includes a series-connected power transistor and a series of negative feedback resistors. The gate of the power transistor is connected to the output of the drive circuit. The negative feedback resistors divide the output signal through resistors to form a feedback voltage, which is then output to the input of the folded cascode operational amplifier circuit. The current sampling circuit includes a self-biased current mirror and a startup current bias circuit. It is used to sample the drive current of the power transistor and outputs a sampled current to the overcurrent protection circuit for comparison with a threshold. The adaptive bias circuit receives an adaptive voltage and outputs an output current that is proportional to the drive current of the power transistor after being mirrored by the current mirror. The output current flows into the bias current input of the cascode amplifier.

[0008] A preferred embodiment is that the adaptive bias circuit includes a pair of PMOS current mirrors and a pair of NMOS current mirrors, with the output PMOS transistor in the PMOS current mirror being connected in series with a current-limiting resistor.

[0009] A further solution is that the overcurrent protection circuit includes a current mirror circuit, the output MOSFET of the current mirror circuit is connected to a current limiting circuit, and the current limiting circuit is connected to the output of the folded common-source common-gate operational amplifier circuit.

[0010] A further solution is to include a current source in the current limiting circuit, which is connected in series with the output MOSFET.

[0011] An alternative approach is to include an NMOS common-source amplifier in the current limiting circuit, which is connected to the output MOS transistor.

[0012] A further embodiment involves connecting a compensation circuit between the output of the folded common-source cascode operational amplifier circuit and the driver circuit. This compensation circuit includes a parallel branch with fixed impedance and a branch with adjustable impedance. Preferably, the impedance of the adjustable branch varies with the load.

[0013] To achieve the second objective mentioned above, the operating method of the high power supply rejection ratio low dropout linear regulator provided by the present invention includes a folded cascode operational amplifier circuit receiving a reference voltage and an output feedback voltage, and outputting an amplified voltage drop to a drive circuit; the drive circuit outputs a drive current to the power transistor; a current sampling circuit samples the drive current and outputs a sampled current to an overcurrent protection circuit; an adaptive bias circuit receives an adaptive voltage, and outputs an output current proportional to the drive current of the power transistor after being mirrored by a current mirror; the output current flows into the bias current input terminal of the folded cascode operational amplifier circuit.

[0014] A preferred embodiment is that the adaptive bias circuit includes a pair of PMOS current mirrors and a pair of NMOS current mirrors, with the output PMOS transistor in the PMOS current mirror connected in series with a current-limiting resistor. When the load current increases, the voltage across the current-limiting resistor increases, the gate-source voltage of the output PMOS transistor is limited, and thus the current flowing through the output PMOS transistor is limited.

[0015] As can be seen from the above scheme, the current sampling circuit of the present invention uses current mirror feedback to make the drain voltage of the current sampling transistor closer to the drain voltage of the power transistor, thereby eliminating the error caused by the channel length effect and making the current sampling more accurate. The load current sampled by the current sampling circuit is scaled proportionally by the current mirror circuit and then fed back to the circuit bias current, thereby increasing the circuit bandwidth as the load increases. This optimizes the power supply rejection ratio under heavy load without increasing static power consumption. Connecting a resistor at the source of the current mirror output transistor can avoid the problem of excessive mirror current.

[0016] Furthermore, in the overcurrent protection circuit design of this invention, the current sampled by a current sampling circuit is compared with a fixed current. When the load current exceeds the set overcurrent protection threshold, the voltage at the gate of the power transistor increases, thereby limiting the current of the power transistor. The circuit compensation method is zero-point following compensation, which is achieved through a variable compensation resistor. The compensation circuit includes a parallel fixed impedance branch and an adjustable impedance branch. Under no-load conditions, the adjustable impedance branch is a megawatt-level resistor. As the load increases, the dominant pole shifts to higher frequencies, and the resistance of the adjustable impedance branch decreases with the increase of the load. The compensation zero point also shifts to higher frequencies with the increase of the load, thereby achieving zero-point following compensation and ensuring circuit stability. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the folded common-source common-gate operational amplifier circuit, drive circuit, compensation circuit and power stage in the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0018] Figure 2 This is a circuit diagram of the compensation circuit in the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0019] Figure 3 This is a circuit diagram of the voltage bias circuit in the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0020] Figure 4 This is a circuit diagram of the current sampling circuit and overcurrent protection circuit in the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0021] Figure 5 This is a circuit diagram of the adaptive bias circuit in the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0022] Figure 6 This is a simulation result of the power supply rejection ratio at room temperature for the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0023] Figure 7 This is a simulation result of the power supply rejection ratio of the first embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention at temperatures of -40°C and 125°C.

[0024] Figure 8 This is a circuit diagram of the current limiting circuit in the second embodiment of the high power supply rejection ratio low dropout linear regulator of the present invention.

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0026] The high power supply rejection ratio low dropout linear regulator of the present invention is used in electronic devices to power various modules and can output a stable voltage under various load conditions.

[0027] First embodiment: This embodiment includes a folded common-source cascode operational amplifier circuit, a driver circuit, a power stage, a current sampling circuit, an adaptive bias circuit, an overcurrent protection circuit, and a compensation circuit. See also... Figure 1 The folded cascode operational amplifier circuit 11 has multiple field-effect transistors (FETs). Specifically, it includes an input differential pair, two cascode amplifiers, and a current mirror. FETs Ep1 and Ep2 form one input differential pair, FETs Ep3, Ep4, Ep5, and Ep6 form one cascode amplifier, and FETs En1, En2, En3, and En4 form another cascode amplifier. FET Mbp3 serves as the current mirror. The folded cascode operational amplifier circuit 11 amplifies the voltage difference between the output feedback voltage Vfb and the reference voltage Vref and outputs it to the driver circuit 12.

[0028] Furthermore, the gate of field-effect transistor Mbp3 receives the voltage signal Vbp0, and the gate of field-effect transistor Ep2 receives the reference voltage Vref. The gate voltage of field-effect transistor Ep1 is Vfb, which is the feedback voltage of the feedback resistor string. The folded cascode operational amplifier circuit 11 of this embodiment has high gain, which can improve the power supply rejection ratio at low frequencies. In addition, since field-effect transistors Ep3, Ep4, Ep5, and Ep6 do not use self-biasing, this method helps to improve the power supply rejection ratio.

[0029] The driver circuit 12 includes a common-source amplifier and a load. The common-source amplifier includes a field-effect transistor M2, and the load includes a series-connected diode and a resistor R1. The diode is a field-effect transistor M4. The output impedance of the driver circuit is much smaller than the output impedance of the folded common-source cascode operational amplifier circuit 11, and the input terminal of the common-source amplifier is connected to the folded common-source cascode operational amplifier circuit 11.

[0030] from Figure 1 As can be seen, the gate of the field-effect transistor M2 is connected to the output terminal of the folded cascode operational amplifier circuit 11. Therefore, the folded cascode operational amplifier circuit 11 can output voltage to the drive circuit 12. Specifically, the gate of the field-effect transistor M2 is connected between the field-effect transistors Ep6 and En1, and a voltage VO1 is formed on the gate of the field-effect transistor M2.

[0031] from Figure 1 As can be seen, the driver stage consists of resistors R0 and R1 connected in parallel, and resistors R1, MOSFET M4, and MOSFET M2 connected in series. Therefore, the output impedance of the driver circuit 12 is R0 / / (R1+1 / gm4), where " / / " indicates the calculation method of the parallel resistor, and gm4 is the admittance of MOSFET M4.

[0032] Additionally, the gate of the field-effect transistor M4 is connected to the gate of the power transistor Mp, see [link / reference]. Figure 4 The field-effect transistor M4 also outputs a voltage Vg to the power transistor Mp. Therefore, the drive circuit 12 outputs a drive current to the power transistor Mp.

[0033] The power stage includes a power transistor Mp connected in series and a negative feedback resistor string. The feedback resistor string includes resistors R11 and R2 connected in series. The gate of the power transistor Mp is connected to the output terminal of the driver circuit 12. The negative feedback resistor string divides the output signal through resistors to form a feedback voltage Vfb, which is then output to the input terminal of the folded cascode operational amplifier circuit 11. The power transistor Mp is also connected to a compensation capacitor Cf and a load. The power transistor Mp also outputs a voltage Vout. The load includes an external capacitor, an ESR resistor, and a load resistor. The compensation capacitor Cf is connected in parallel with resistor R11.

[0034] When the low-dropout linear regulator is unloaded, the MOSFET M4 is almost off. At this time, the current of the drive circuit is provided by the resistor R0. When the load is large, since the resistor R1 is connected in series with the MOSFET M4, the resistor R1 can limit the current flowing through the MOSFET M4, thus preventing the voltage Vo1 from rising too high due to excessive current flowing through the MOSFET M4.

[0035] A compensation circuit is also connected between the output of the folded common-source cascode operational amplifier circuit 11 and the driver circuit 12. In this embodiment, the compensation circuit includes a capacitor Cc and an equivalent compensation resistor Rc. See [link to relevant documentation]. Figure 2 The compensation resistor Rc includes resistor R10 and parallel fixed-impedance branch and adjustable-impedance branch. The fixed-impedance branch includes a field-effect transistor (FET) Mfix with a fixed resistance value of Rfix. The adjustable-impedance branch includes an FET Mdap with an adjustable resistance value of Rdap. The resistance of FET Mdap is related to its gate voltage Vdap; therefore, the resistance Rdap of FET Mdap can be controlled by controlling the voltage Vdap applied to its gate. Preferably, the resistance Rdap of FET Mdap decreases as the current increases. Furthermore, the resistance Rfix of FET Mfix is ​​controlled by voltage Vbn3, which is generated by a voltage bias circuit.

[0036] See Figure 3 The voltage bias circuit includes a current source I3 and a field-effect transistor Mfix0 connected in series. The gate of the field-effect transistor Mfix0 forms a voltage Vbn3 and outputs it to the field-effect transistor Mfix. In this embodiment, by selecting a suitable bias current for the current source I3 and controlling the resistance Rfix of the field-effect transistor Mfix0 to be a megaohm level resistance, the adjustment of the compensation resistor Rc of the compensation circuit can be effectively achieved.

[0037] according to Figure 2 The resistance value of the compensation resistor Rc can be calculated using the following formula: Rc = R10 + Rdap / / Rfix, where " / / " indicates the calculation method for parallel resistance. When the low-dropout linear regulator is under no-load, since the resistance Rdap of the field-effect transistor Mdap is much larger than the resistance Rfix of the field-effect transistor Mfix, the compensation resistor is equivalent to Rc = R10 + Rfix. When the load increases, since the resistance Rdap of the field-effect transistor Mdap is much smaller than the resistance Rfix of the field-effect transistor Mdap, Rc = R10 + Rdap. In this way, the overall compensation resistor Rc decreases as the load increases, which is beneficial for achieving zero-point compensation of the folded cascode operational amplifier circuit 11.

[0038] See Figure 4 The current sampling circuit 13 samples the current of the power transistor MP. The current sampling circuit 13 includes a power transistor mirror Mir, three current mirror pairs, and a current source I1. The field-effect transistors Mi1, Mi2, Mi3, and Mi4 form a self-biased current mirror. The current source I1, along with the field-effect transistors Mbn1 and Mbn2, forms a startup current bias circuit. The current source I1 is input to the branches of the field-effect transistors Mi1 and Mi3 through the mirror formed by the field-effect transistors Mbn1 and Mbn2, avoiding the generation of degeneracy points. The power transistor mirror Mir and the power transistor MP also form a current mirror pair, which can proportionally replicate the current of the power transistor MP, equivalent to scaling the drive current sampling according to a certain ratio. Therefore, the current sampling circuit can sample the drive current of the power transistor MP and output a sampled current to the overcurrent protection circuit for comparison with a threshold.

[0039] Furthermore, in the three current mirror pairs, the first current mirror pair uses identical MOSFETs Mi1 and Mi2 with matched electrical parameters; the second current mirror pair uses identical MOSFETs Mi3 and Mi4; and the third current mirror pair includes MOSFETs Mbn1 and Mbn2. During normal operation, the negative feedback loop formed by MOSFETs Mi1, Mi2, Mi3, and Mi4 ensures that the voltage Vout output by power transistor Mp is equal to the voltage Vmir output by its mirror transistor Mir. At this point, the source-drain voltages of power transistor Mp and its mirror transistor Mir are equal, eliminating the influence of channel length modulation and making current replication more accurate. Additionally, the current sampling circuit 13 generates a voltage Vdap, specifically derived from the drain of MOSFET Mi4, and this voltage Vdap is positively correlated with the load current of the low-dropout linear regulator.

[0040] The current sampling circuit 13 outputs current to the overcurrent protection circuit 14. The overcurrent protection circuit 14 includes field-effect transistors Mi5, Mip6, Mip7, and Mi8, a current source I2, a resistor R4, and a capacitor C4. Among them, field-effect transistors Mip6 and Mip7 form a pair of current mirrors. Field-effect transistors Mi5 and Mip6 are connected in series. Field-effect transistor Mi5 replicates the current of field-effect transistor Mi4. The current flowing through field-effect transistor Mi5 is equal to the current of field-effect transistor Mip6. Since field-effect transistors Mip6 and Mip7 form a pair of current mirrors, the current output by field-effect transistor Mip7 is a scaled current of the load sampled current output by the current sampling circuit 13. Therefore, field-effect transistor Mip7 constitutes the output MOS transistor in this embodiment.

[0041] In this embodiment, the field-effect transistor Mi8, the current source I2, the resistor R4, and the capacitor C4 constitute a current-limiting circuit. The field-effect transistor Mi8 is an NMOS common-source amplifier transistor, which is connected to the output MOS transistor. The current source I2 is connected in series with the field-effect transistor Mip7. Therefore, the output MOS transistor Mip7 of the current mirror circuit is connected to the current-limiting circuit, which is connected to the voltage output terminal of the folded common-source common-gate operational amplifier circuit 11. That is, the drain of the field-effect transistor Mi8 is connected to the voltage Vo1 output by the folded common-source common-gate operational amplifier circuit 11.

[0042] In this embodiment, the rated current of current source I2 is 1uA. When the load current is greater than the overcurrent protection threshold, the current flowing through the field-effect transistor Mip7 is greater than 1uA. At this time, the current Imit at the upper end of current source I2 is raised. Correspondingly, the voltage Vo1 output by the folded common-source common-gate operational amplifier circuit 11 is pulled down, thereby turning off the field-effect transistor M2. At this time, the voltage Vg at the gate of the power transistor Mp is pulled up, that is, the voltage Vg at the gate of the power transistor Mp is raised to a higher level, thereby reducing the current of the power transistor Mp.

[0043] See Figure 5 The adaptive bias circuit receives the adaptive voltage and, after mirroring it through a current mirror, outputs an output current proportional to the drive current of the power transistor Mp. This output current flows into the bias current input terminal of the folded cascode operational amplifier circuit 11. The adaptive bias circuit includes a pair of PMOS current mirrors and a pair of NMOS current mirrors. The PMOS current mirrors include field-effect transistors Mdp1 and Mdp2, and the NMOS current mirrors include field-effect transistors Mdn1 and Mdn2. The output PMOS transistor Mdp2 in the PMOS current mirror pair is connected in series with the current-limiting resistor R3. Furthermore, the current-limiting resistor R3, field-effect transistors Mdp2 and Mdn2 are connected in series sequentially. The current flowing through the field-effect transistor Mi6 is proportional to the load current. The PMOS and NMOS current mirrors can scale the current flowing through Mi6 and apply it to the field-effect transistor Mbp1. Figure 5 As can be seen, MOSFETs Mbp1 and Mbp2 form a pair of current mirrors. Since the current-limiting resistor R3 is connected in series with MOSFET Mdp2, when the current flowing through MOSFET Mdp2 increases to a certain level, the voltage across the current-limiting resistor R3 increases. Therefore, the gate-source voltage Vgs of MOSFET Mdp2 is limited, which in turn limits the current of MOSFET Mdp2, thus avoiding the problem of excessive bias current.

[0044] The field-effect transistor Mbp1 is also connected in series with the current source I4, and Mbp1 and Mbp2 form a current mirror. The gate voltage Vbp0 of the field-effect transistor Mbp1 is the bias voltage, and the bias voltage Vbp0 is output to the folded common-source common-gate operational amplifier circuit 11. Specifically, the field-effect transistor Mbp3 receives the bias voltage Vbp0.

[0045] In this embodiment, the folded cascode operational amplifier circuit 11 provides high gain. The driving circuit can isolate the output pole of the error amplifier and the gate pole of the power transistor, which is beneficial for stability design. Furthermore, by adding a current mirror clamp to the load current sampling circuit, the influence of channel length modulation is reduced, making current sampling more accurate. Adaptive bias and overcurrent protection are achieved using the sampling current of the current sampling circuit. Therefore, the driving circuit isolates the folded cascode operational amplifier circuit 11 from the power stage, separating the originally lower-frequency output pole into two higher-frequency output poles.

[0046] In this embodiment, the load current sampled by the current sampling circuit is scaled by a current mirror and then fed back to the circuit bias current. This allows the circuit bandwidth to increase as the load increases, thereby optimizing the power supply rejection ratio under heavy load without increasing static power consumption. Adding a current limiting resistor can avoid the problem of excessive mirror current.

[0047] In addition, in the overcurrent protection circuit design of this embodiment, the current sampled by the current sampling circuit is compared with a fixed current. When the load current exceeds the set overcurrent protection threshold, the voltage at the gate of the power transistor can be increased, thereby limiting the current of the power transistor. The circuit compensation method is zero-point following compensation, which is achieved through a variable compensation resistor. Since the compensation circuit includes a parallel fixed impedance branch and an adjustable impedance branch, the adjustable impedance branch is a megawatt-level resistor under no-load conditions. As the load increases, the dominant pole shifts to higher frequencies, and the resistance of the adjustable impedance branch decreases with the increase of the load. The compensation zero point also shifts to higher frequencies with the increase of the load, thereby achieving zero-point following compensation and realizing a stable design.

[0048] See Figure 6 Table 1 shows the power supply suppression under different current loads at a TT process corner temperature of 25°C. Under this condition, the static power consumption is 63uA, while the static power consumption without the adaptive bias circuit is 100uA. Therefore, the static power consumption is reduced by 37% using the solution in this embodiment.

[0049] Table 1

[0050] Table 2 shows the power supply rejection (PSR) data for a load of 300mA, a temperature range of -40℃ to 125℃, a load current of 300mA, and process corners tt, ss, ff, sftt, and fstt. It can be seen that the PSR is greater than 86dB at a power supply frequency of 1kHz, greater than 82dB at a power supply frequency of 10kHz, and greater than 63dB at a power supply frequency of 100kHz. The simulated waveforms are shown below. Figure 7 As shown.

[0051] Table 2

[0052] Second embodiment: This embodiment includes a folded common-source common-gate operational amplifier circuit, a driver circuit, a current sampling circuit, an adaptive bias circuit, an overcurrent protection circuit, and a compensation circuit. Unlike the first embodiment, the overcurrent protection current in this embodiment is as follows: Figure 8 As shown.

[0053] The overcurrent protection circuit in this embodiment includes a current source I5 and a current limiting circuit. The current limiting circuit includes a field-effect transistor Mi5, a resistor R5, a capacitor C5, and a PMOS common-source amplifier transistor Moc8. The field-effect transistor Mi5 is a mirror field-effect transistor carrying load information. Figure 4 The current source I5 and the reference MOSFET Mi5 are connected in series. The current flowing through the MOSFET Mi5 is compared with the current flowing through the current source I5. When the current flowing through the MOSFET Mi5 is greater than the current flowing through the current source I5, the MOSFET Mi5 pulls down the node Imit, thereby turning on the PMOS common-source amplifier Moc8, pulling down the voltage Vo1, and increasing the gate voltage of the power transistor Mp, thus achieving current limiting. When the current flowing through the MOSFET Mi5 is less than the current flowing through the current source I5, the current Imit is pulled up, thereby turning off the PMOS common-source amplifier Moc8, which will not affect the normal operation of the low-dropout linear regulator.

[0054] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-dropout linear regulator with high power supply rejection ratio, characterized in that, include: A folded cascode operational amplifier circuit includes an input differential pair, two cascode amplifiers, and a current mirror. The folded cascode operational amplifier circuit amplifies the voltage difference between the output feedback voltage and the reference voltage and outputs it to the drive circuit. The driving circuit includes a common-source amplifier and a load. The load includes a series-connected diode and a resistor. The output impedance of the driving circuit is less than the output impedance of the folded common-source cascode operational amplifier circuit. The input terminal of the common-source amplifier is connected to the folded common-source cascode operational amplifier circuit. The power stage includes a series power transistor and a series of negative feedback resistors. The gate of the power transistor is connected to the output terminal of the driving circuit. The series of negative feedback resistors divides the output signal to form the feedback voltage and outputs it to the input terminal of the folded common-source common-gate operational amplifier circuit. The current sampling circuit, including a self-biased current mirror and a startup current biasing circuit, is used to sample the drive current of the power transistor and output a sampled current to the overcurrent protection circuit for comparison with a threshold. An adaptive bias circuit receives an adaptive voltage and, after mirroring it through a current mirror, outputs an output current that is proportional to the drive current of the power transistor. This output current flows into the bias current input terminal of the common-source cascode amplifier.

2. The low dropout linear regulator with high power supply rejection ratio according to claim 1, characterized in that: The adaptive bias circuit includes a pair of PMOS current mirrors and a pair of NMOS current mirrors, wherein the output PMOS transistor in the PMOS current mirror is connected in series with a current limiting resistor.

3. The low dropout linear regulator with high power supply rejection ratio according to claim 1 or 2, characterized in that, Also includes: The overcurrent protection circuit includes a current mirror circuit, the output MOS transistor of the current mirror circuit is connected to a current limiting circuit, and the current limiting circuit is connected to the output terminal of the folded common-source common-gate operational amplifier circuit.

4. The low dropout linear regulator with high power supply rejection ratio according to claim 3, characterized in that: The current limiting circuit includes a current source connected in series with the output MOS transistor.

5. The low dropout linear regulator with high power supply rejection ratio according to claim 3, characterized in that: The current limiting circuit includes an NMOS common-source amplifier transistor, which is connected to the output MOS transistor.

6. The low dropout linear regulator with high power supply rejection ratio according to claim 1 or 2, characterized in that: A compensation circuit is also connected between the output terminal of the folded common-source common-gate operational amplifier circuit and the driving circuit. The compensation circuit includes a parallel fixed impedance branch and an adjustable impedance branch.

7. The low dropout linear regulator with high power supply rejection ratio according to claim 6, characterized in that, include: The impedance of the adjustable branch changes with the load.

8. The operating method of a low-dropout linear regulator with high power supply rejection ratio, characterized in that: The folded common-source common-gate operational amplifier circuit receives a reference voltage and an output feedback voltage, and outputs an amplified voltage difference to the drive circuit, which in turn outputs a drive current to the power transistor. The current sampling circuit samples the drive current and outputs the sampled current to the overcurrent protection circuit; The adaptive bias circuit receives an adaptive voltage and outputs an output current that is proportional to the drive current of the power transistor after being mirrored by a current mirror. The output current flows into the bias current input terminal of the folded common-source common-gate operational amplifier circuit.

9. The operating method of the low dropout linear regulator with high power supply rejection ratio according to claim 8, characterized in that: The adaptive bias circuit includes a pair of PMOS current mirrors and a pair of NMOS current mirrors, wherein the output PMOS transistor in the PMOS current mirror is connected in series with a current limiting resistor. When the load current increases, the voltage across the current-limiting resistor increases, the gate-source voltage of the output PMOS transistor is limited, and thus the current flowing through the output PMOS transistor is limited.

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