Capacitor voltage adjustment circuit and method

Abstract

The application discloses a capacitor voltage adjustment circuit and method, and relates to the technical field of electronic circuits.The circuit comprises a conversion module, a comparison module, a logic control module, a level shift module and a charge-discharge module.The conversion module is connected with the comparison module, the comparison module is connected with the logic control module and the charge-discharge module, the logic control module is connected with the level shift module, the level shift module is connected with the charge-discharge module, and the charge-discharge module is also connected with an input voltage and a capacitor to be monitored.The comparison module is used for obtaining a reference voltage and an offset voltage amplitude, determining a voltage monitoring interval of the capacitor to be monitored according to the reference voltage and the offset voltage amplitude, obtaining a voltage value of the capacitor to be monitored, and controlling the logic control module to generate a logic signal when the voltage value of the capacitor to be monitored deviates from the voltage monitoring interval, so that the level shift module is driven by the logic signal to drive the charge-discharge module, and the voltage value of the capacitor to be monitored is corrected.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a capacitor voltage adjustment circuit and method. Background Technology

[0002] In integrated circuits such as power management and power drive systems, to improve overall circuit performance, the power supply voltage is often reduced before being applied to the corresponding circuit. This power supply voltage is stored in capacitors, and the charging and discharging of these capacitors needs to be monitored and adjusted in real time to ensure the stability of the power supply applied to the circuit. Typically, a window threshold voltage comparator circuit is used to detect the capacitor voltage, and a switch is used to switch the reference voltage to achieve the capacitor threshold switching. However, for multiple thresholds or a wider threshold selection window, the circuit needs to include a complex voltage divider network, which increases the circuit board area and cost. Therefore, there is an urgent need for a capacitor voltage adjustment circuit and method that can flexibly set the capacitor voltage detection range and adjust the capacitor voltage according to this detection range. Summary of the Invention

[0003] To address the problems mentioned in the background section, this application provides the following technical solutions: In a first aspect, a capacitor voltage adjustment circuit is provided, comprising: a conversion module, a comparison module, a logic control module, a level shifting module, and a charging / discharging module; The conversion module is connected to the comparison module, the comparison module is connected to the logic control module and the charge / discharge module, the logic control module is connected to the level shifting module, the level shifting module is connected to the charge / discharge module, and the charge / discharge module is also connected to the input voltage and the capacitor to be monitored. The conversion module is used to set the offset voltage amplitude; The comparison module is used to acquire the reference voltage and the offset voltage amplitude, and determine the voltage monitoring range of the capacitor to be monitored based on the reference voltage and the offset voltage amplitude. It is also used to acquire the voltage value of the capacitor to be monitored, and when the voltage value of the capacitor to be monitored deviates from the voltage monitoring range, the control logic module generates a logic signal, which controls the level shift module to drive the charging and discharging module to correct the voltage value of the capacitor to be monitored.

[0004] Secondly, a capacitor voltage adjustment method is provided, applied to the capacitor voltage adjustment circuit described in the first aspect, comprising: Set the voltage amplitude of the reference voltage source, and set the resistance values ​​of the first resistor, the second resistor, and the third resistor; Set the resistance values ​​of the fourth and fifth resistors; Obtain the input voltage and determine the reference voltage based on the amplitude of the input voltage, the resistance value of the fourth resistor, and the resistance value of the fifth resistor; The voltage monitoring range is determined based on the reference voltage, the voltage amplitude of the reference voltage source, the resistance of the first resistor, the resistance of the second resistor, and the resistance of the third resistor. Obtain the voltage of the capacitor to be monitored, and adjust the voltage of the capacitor to be monitored according to the voltage monitoring range.

[0005] By implementing the capacitor voltage adjustment circuit described in this application embodiment, the monitoring range of the capacitor voltage can be flexibly adjusted, allowing the same circuit architecture to adapt to different input voltage monitoring requirements by changing the external resistor value; hysteresis control is provided for the monitored capacitor voltage to prevent oscillation and frequent switching; the high-voltage and low-voltage regions in the circuit are isolated by a level shifting module, improving circuit reliability; and high-precision threshold voltage generation is achieved by utilizing the matching characteristics of analog integrated circuits, reducing the impact of process deviations and temperature drift on monitoring accuracy. By implementing the capacitor voltage adjustment method described in this application embodiment, the voltage monitoring range can be quantified and flexibly adjusted; the real-time and adaptive control strategy is achieved, ensuring that the system can instantly calculate the most suitable monitoring window under the current operating conditions regardless of input voltage fluctuations, without manual intervention; a complete closed-loop feedback control is formed, ensuring that the capacitor voltage is always maintained within a safe and efficient operating range, and maximizing the system's energy efficiency ratio through an "on-demand adjustment" strategy. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 This is a schematic diagram of the capacitor voltage adjustment circuit module provided in the embodiments of this application; Figure 2 This is a schematic diagram of the conversion module circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the comparison module circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the logic control module circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of the charging and discharging module circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the level shifting module circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of a capacitor voltage adjustment circuit module including a voltage setting module provided in an embodiment of this application; Figure 8 This is a schematic diagram of the voltage setting module circuit provided in an embodiment of this application; Figure 9 This is a schematic diagram of the capacitor voltage adjustment method provided in the embodiments of this application. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0009] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0010] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0011] In view of the problems of capacitor voltage detection and adjustment circuits mentioned in the background art, this application provides a capacitor voltage adjustment circuit to realize flexible setting of capacitor voltage detection range and adjust capacitor voltage according to the detection range.

[0012] In some embodiments, such as Figure 1As shown, a capacitor voltage adjustment circuit includes: a conversion module 100, a comparison module 200, a logic control module 300, a level shifting module 400, and a charge / discharge module 500; The conversion module 100 is connected to the comparison module, the comparison module is connected to the logic control module 300 and the charge / discharge module 500, the logic control module 300 is connected to the level shifting module 400, the level shifting module 400 is connected to the charge / discharge module 500, and the charge / discharge module 500 is also connected to the input voltage V. IN and the capacitor C to be monitored; The charging / discharging module 500 contains a capacitor to be monitored. Conversion module 100 is used to set the offset voltage amplitude; Comparison module 200 is used to obtain the reference voltage V. R And the offset voltage magnitude, and based on the reference voltage V R The system also uses the offset voltage amplitude to determine the voltage monitoring range of the capacitor to be monitored. It is also used to obtain the voltage value of the capacitor to be monitored. When the voltage value of the capacitor to be monitored deviates from the voltage monitoring range, the control logic module 300 generates a logic signal to control the level shift module 400 to drive the charging and discharging module 500 to correct the voltage value of the capacitor to be monitored.

[0013] The offset voltage amplitude includes the upper offset voltage amplitude and the lower offset voltage amplitude.

[0014] Reference voltage V R The sum of the upper offset voltage amplitude and the upper offset voltage amplitude is the maximum value of the voltage monitoring range, with the reference voltage V. R The difference between the capacitor voltage amplitude and the lower limit voltage amplitude is the minimum value of the voltage monitoring range. When the capacitor voltage is within the voltage monitoring range, no correction is needed; when the capacitor voltage is greater than the reference voltage V... R The sum of the voltage amplitude and the upper offset voltage amplitude requires discharging the capacitor to reduce its voltage; when the capacitor voltage is less than the reference voltage V... R The difference between the voltage level and the lower offset voltage requires charging the capacitor to increase its voltage. This ensures the capacitor voltage remains within the voltage monitoring range to suit the circuit design.

[0015] Maintaining the capacitor voltage within the voltage monitoring range rather than a precise voltage value avoids the frequent charging and discharging state where the capacitor charges when the voltage is below the target value and discharges when the voltage is above the target value. Since there is energy loss with each switch, high-frequency switching will bring unnecessary losses, generate serious electromagnetic interference, affect surrounding circuits, and shorten the lifespan of devices. Within this range, the capacitor can naturally cope with load changes through charging and discharging without the need for immediate intervention from the control circuit. The active control circuit will only intervene when the fluctuation exceeds this "safety buffer".

[0016] Specifically, the conversion module 100 has a first port 100a. The comparison module 200 has: a first comparison module port 200a, a second comparison module port 200b, a third comparison module port 200c, a fourth comparison module port 200d, a fifth comparison module port 200e, a sixth comparison module port 200f, a seventh comparison module port 200g, and an eighth comparison module port 200h; The logic control module 300 has: a first logic control port 300a, a second logic control port 300b, a third logic control port 300c, a fourth logic control port 300d, a fifth logic control port 300e, a sixth logic control port 300f, and a seventh logic control port 300g. The level shifting module 400 has: a first level shifting port 400a, a second level shifting port 400b, a third level shifting port 400c, and a fourth level shifting port 400d; The charging and discharging module 500 has: a first port 500a, a second port 500b, a third port 500c, and a fourth port 500d. The first port 100a of the conversion module is connected to the third port 200c of the comparison module. After the first port 200a of the comparison module is connected to the fourth port 500d of the charge / discharge module, it is used to connect one end of the capacitor C to be monitored. The other end of the capacitor C to be monitored is connected to the voltage reference point AGND. The second port 200b of the comparison module is used to obtain the reference voltage V. R The fourth port 200d of the comparator module is connected to the first port 300a of the logic control module; the fifth port 200e of the comparator module is connected to the second port 300b of the logic control module; the sixth port 200f of the comparator module is connected to the third port 300c of the logic control module; the seventh port 200g of the comparator module is connected to the fourth port 300d of the logic control module; the eighth port 200h of the comparator module is connected to the fifth port 300e of the logic control module; the sixth port 300f of the logic control module is connected to the first port 400a of the level shifter module; the seventh port 300g of the logic control module is connected to the second port 400b of the level shifter module; the third port 400c of the level shifter module is connected to the first port 500a of the charge / discharge module; the fourth port 400d of the level shifter module is connected to the second port 500b of the charge / discharge module; and the third port 500c of the charge / discharge module is used to connect the input voltage V. IN Wherein, the reference voltage V R According to the input voltage V IN Sure.

[0017] The conversion module 100 is capable of providing the offset voltage amplitude.

[0018] Comparison module 200 is capable of acquiring reference voltage V R And the offset voltage magnitude, and based on the reference voltage V R The voltage monitoring range of the capacitor to be monitored is determined by measuring the voltage amplitude and the offset voltage. The comparison module 200 acquires the voltage value of the capacitor to be monitored and compares it with the voltage monitoring range. When the voltage value of the capacitor to be monitored deviates from the voltage monitoring range, the control logic module 300 generates a logic signal, which controls the level shift module 400 to drive the charging and discharging module 500 to correct the voltage value of the capacitor to be monitored.

[0019] The logic control module 300 generates a control signal based on the comparison result between the voltage value of the capacitor to be monitored and the voltage monitoring range. The level shifting module 400 further generates a drive signal to drive the charging and discharging module 500 based on the control signal. The charging and discharging module 500 corrects the voltage value of the capacitor to be monitored based on the drive signal.

[0020] like Figure 2 As shown, the conversion module 100 includes: a reference voltage source V REF Operational amplifier OP, first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and first resistor R1; The inverting input of the operational amplifier OP is connected to the reference voltage source V. REF The positive terminal of the operational amplifier OP is connected to the gate and drain of the first transistor T1, the gate of the second transistor T2, and the drain of the third transistor T3. The output terminal of the operational amplifier OP is connected to the gate of the third transistor T3. The source of the third transistor T3 is connected to one end of the first resistor R1. The source of the first transistor T1 is connected to the source of the second transistor T2 and the gate of the fifth transistor T5, which is then used to connect to the operating voltage V. DD After the drain of the second transistor T2 is connected to the drain and gate of the fourth transistor T4, it serves as the first port 100a of the conversion module 100. The source of the fourth transistor T4 is connected to the drain of the fifth transistor T5, and the reference voltage source V... REF The negative terminal of the transistor is connected to the other end of the first resistor R1 and the source of the fifth transistor T5 at the voltage reference point AGND.

[0021] The operational amplifier OP is a unity-gain negative feedback operational amplifier.

[0022] The first transistor T1 and the second transistor T2 are P-channel MOSFETs, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are N-channel MOSFETs.

[0023] Preferably, the voltage reference point AGND is the grounding point.

[0024] Reference voltage source V REF The amplitude is used to set the offset voltage amplitude. Reference voltage source V REF The branch containing the first resistor R1 generates a value of V REF / R The current is 1, where, V REF Reference voltage source V REF voltage amplitude, R 1 represents the resistance value of the first resistor R1. This current mirror structure, consisting of the first transistor T1 and the second transistor T2, mirrors the current to the branch containing the second transistor T2, forming a mirrored current I. bias The mirror current I bias This is further mirrored to the current mirror structure in the comparator module 200. Therefore, by setting the reference voltage source V... REF The voltage amplitude can be set to determine the offset voltage amplitude. The specific setting of this amplitude will be explained in detail when discussing the comparison module 200 below.

[0025] like Figure 3 As shown, the comparison module 200 includes: a first comparator CMP1, a second comparator CMP2, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T1. 10 11th transistor T 11 Twelfth transistor T 12 Thirteenth transistor T 13 Fourteenth transistor T 14 The fifteenth transistor T 15 The sixteenth transistor T 16 The seventeenth transistor T 17 The eighteenth transistor T 18 The nineteenth transistor T 19 20th transistor T 20 Twenty-first transistor T 21 Twenty-second transistor T 22 Twenty-third transistor T 23 The second resistor R2 and the third resistor R3; After the gate and drain of the sixth transistor T6 are connected, it serves as the first port 200a of the comparator module 200. The source of the sixth transistor T6 is connected to the inverting input of the first comparator CMP1, the non-inverting input of the second comparator CMP2, and the fourteenth transistor T. 14 The drain of the seventh transistor T7 is connected to the source of the eighth transistor T8 and the eleventh transistor T8. 11 The gate of the fourteenth transistor T 14The gate of the sixteenth transistor T 16 The gate of the seventeenth transistor T 17 The gate of the transistor and the twenty-second transistor T 22 After the gate is connected, it is used to connect the operating voltage V. DD The gate and drain of the seventh transistor T7, the gate of the eighth transistor T8, and the eleventh transistor T 11 The drain of the eighth transistor T8 is connected to the non-inverting input of the first comparator CMP1 and one end of the second resistor R2. The gate of the ninth transistor T9 is connected to the gate of the tenth transistor T1. 10 After the gate and drain are connected, the tenth transistor T serves as the second port 200b of the comparator module 200. 10 The source of transistor T9 is connected to the drain of transistor T9. The source of transistor T9 is connected to the other end of the second resistor R2, one end of the third resistor R3, and the seventeenth transistor T1. 17 The drain and the twenty-third transistor T 23 The drain of the third resistor R3 is connected to the inverting input of the second comparator CMP2 and the twentieth transistor T. 20 The drain connection, the twentieth transistor T 20 The gate of the comparator module 200 is used as the sixth port 200f of the comparator module 200, and the twenty-third transistor T 23 The gate of the comparator module 200 serves as the seventh port 200g of the comparator module 200, and the twentieth transistor T 20 The source of the 21st transistor T 21 The drain and the twenty-third transistor T 23 The source connection, the eleventh transistor T 11 The source of the twelfth transistor T 12 The drain connection, the fourteenth transistor T 14 The source of the fifteenth transistor T 15 The drain connection, the seventeenth transistor T 17 The source and the eighteenth transistor T 18 The drain connection, the twelfth transistor T 12 The gate of the fifteenth transistor T 15 The gate of the eighteenth transistor T 18 The gate and the twenty-first transistor T 21 After the gate is connected, the twelfth transistor T serves as the third port 200c of the comparator module 200. 12 The source and the thirteenth transistor T 13 The drain connection, the fifteenth transistor T 15 The source of the sixteenth transistor T 16 The drain connection, the eighteenth transistor T 18The source of the nineteenth transistor T 19 The drain connection, the twenty-first transistor T 21 The source of the 22nd transistor T 22 The drain connection, the thirteenth transistor T 13 The gate of the nineteenth transistor T 19 After the gate is connected, the thirteenth transistor T serves as the eighth port 200h of the comparator module 200. 13 The source of the sixteenth transistor T 16 The source of the nineteenth transistor T 19 The source and the twenty-second transistor T 22 After the source is connected, it is connected to the voltage reference point AGND. The output of the first comparator CMP1 is used as the fourth port 200d of the comparator module 200, and the output of the second comparator CMP2 is used as the fifth port 200e of the comparator module 200.

[0026] Sixth transistor T6, ninth transistor T9, tenth transistor T 10 11th transistor T 11 Twelfth transistor T 12 Thirteenth transistor T 13 Fourteenth transistor T 14 The fifteenth transistor T 15 The sixteenth transistor T 16 The seventeenth transistor T 17 The eighteenth transistor T 18 The nineteenth transistor T 19 20th transistor T 20 Twenty-first transistor T 21 Twenty-second transistor T 22 And the twenty-third transistor T 23 It is an N-channel MOSFET.

[0027] The seventh transistor T7 and the eighth transistor T8 are P-channel MOSFETs.

[0028] To simplify the explanation, the working principle of the capacitor voltage adjustment circuit is described under the assumption that the transistors constituting each current mirror have the same width-to-length ratio. However, this application does not limit the specific dimensions of each transistor.

[0029] Combination Figure 2 , 3 The mirror current I mentioned above bias After passing through the fourth transistor T4 and the twelfth transistor T 12 The fifteenth transistor T 15 The eighteenth transistor T 18 Twenty-first transistor T21 The current mirrors formed are respectively mirrored to the twelfth transistor T. 12 The fifteenth transistor T 15 The eighteenth transistor T 18 And the twenty-first transistor T 21 The branch in which it is located. Among them, since the gate of the fifth transistor T5 is connected to a high potential and is normally open, the mirror current I... bias It always exists in the branch where the fourth transistor T4 is located. 11th transistor T 11 The gate of the fourteenth transistor T 14 The gate of the sixteenth transistor T 16 The gate of the seventeenth transistor T 17 The gate of the transistor and the twenty-second transistor T 22 The gate is connected to a high potential and is normally open.

[0030] The thirteenth transistor T 13 and the nineteenth transistor T 19 The on / off state is controlled by the logic signal transmitted by the eighth port 200h of the comparison module.

[0031] Twenty-third transistor T 23 The on / off state is controlled by the logic signal transmitted by the seventh port 200g of the comparator module.

[0032] The first is transistor T. 20 The on / off state is controlled by the logic signal transmitted by the sixth port 200f of the comparison module.

[0033] The voltage of the capacitor to be monitored is input from the first port 200a of the comparator module, and transmitted through the sixth transistor T6 connected by the diode to the inverting input of the first comparator CMP1 and the non-inverting input of the second comparator CMP2.

[0034] Reference voltage V R The current is input from the second port 200b of the comparator module and transmitted to the connection point of the second resistor R2 and the third resistor R3. For simplicity, it is assumed that the transistors constituting the current mirror structure have the same aspect ratio; therefore, the current flowing through the second resistor R2 and the third resistor R3 is the mirror current I. bias Therefore, the voltage at the non-inverting input of the first comparator is V R + I bias · R 2. The voltage at the inverting input of the second comparator is V R - I bias · R 3, of which, VR Reference voltage V R amplitude, I bias The current value is the mirror current. R 2 represents the resistance value of the second resistor R2. R 3 represents the resistance value of the third resistor, R3. This is assuming the resistance values ​​of the first, second, and third resistors are equal, i.e.: R 1= R 2= R In case 3, the voltage value at the non-inverting input of the first comparator is V R + V REF The voltage value at the inverting input of the second comparator is V R – V REF This allows for the comparison of the voltage value of the capacitor to be monitored with the voltage monitoring range.

[0035] When the voltage value of the capacitor to be monitored is less than V R + V REF When the voltage of the capacitor to be monitored is greater than 200d, the fourth port of the comparator module outputs a low level; when the voltage of the capacitor to be monitored is greater than 200d, the comparator outputs a low level. V R + V REF At that time, the fourth port 200d of the comparator module outputs a high level.

[0036] When the voltage value of the capacitor to be monitored is greater than V R - V REF When the voltage of the capacitor being monitored is less than 200e, the fifth port of the comparator module outputs a low level; when the voltage of the capacitor being monitored is less than 200e, the comparator outputs a low level. V R - V REF At that time, the fifth port 200e of the comparator module outputs a high level.

[0037] Those skilled in the art will understand that the magnitude of the mirrored current can be set by adjusting the aspect ratio of the transistors constituting the current mirror structure. By adjusting the values ​​of the first resistor R1, the second resistor R2, and the third resistor R3, the voltage input to the non-inverting input of the first comparator CMP1 and the voltage input to the inverting input of the second comparator CMP2 can be flexibly adjusted. This application does not limit the values ​​of the first resistor R1, the second resistor R2, and the third resistor R3.

[0038] like Figure 4 As shown, the logic control module 300 includes: a first NAND gate 310, a second NAND gate 320, a first inverter 330, a second inverter 340, and a third inverter 350; After the input terminal of the first inverter 330 is connected to one input terminal of the second NAND gate 320, it serves as the first logic control port 300a of the logic control module 300. The output terminal of the first inverter 330 is connected to one input terminal of the first NAND gate 310. After the other input terminal of the first NAND gate 310 is connected to the input terminal of the second inverter 340, it serves as the second logic control port 300b of the logic control module 300. The output terminal of the second inverter 340 is connected to the other input terminal of the second NAND gate 320. After the output terminal of the first NAND gate 310 is connected to the input terminal of the third inverter 350, it serves as the third logic control port 300c and the sixth logic control port 300f of the logic control module 300. The output terminal of the third inverter 350 serves as the fourth logic control port 300d of the logic control module 300. The output terminal of the second NAND gate 320 serves as the fifth logic control port 300e and the seventh logic control port 300g of the logic control module 300.

[0039] The logic level generated by the fourth port 200d of the comparison module is transmitted to the first logic control port 300a, and the logic level generated by the fifth port 200e of the comparison module is transmitted to the second logic control port 300b.

[0040] When both logic control port 300a and logic control port 300b receive a low level, it indicates that the voltage of the capacitor to be monitored is within the voltage monitoring range. At this time, logic control module 300 generates a high level at logic control port 300f, logic control port 300g, logic control port 300e, logic control port 300d, and logic control port 300c.

[0041] Correspondingly, the high level generated by the logic control third port 300c is transmitted to the sixth port 200f of the comparator module, controlling the twentieth transistor T. 20 When the circuit is turned on, the low-level signal generated by the logic control port 4 (300d) is transmitted to the comparator module port 7 (200g), controlling the 23rd transistor T. 23 When the logic control is turned off, the high-level signal generated at port 300e (the fifth port) is transmitted to port 200h (the eighth port) of the comparator module, controlling the thirteenth transistor T. 13 and the nineteenth transistor T 19 Conductive.

[0042] When logic control port 300a receives a high level and logic control port 300b receives a low level, it indicates that the voltage of the capacitor to be monitored is greater than 1. V R + V REF When the first logic control port 300a receives a low level and the second logic control port 300b receives a high level, it indicates that the voltage of the capacitor to be monitored is less than... V R - V REF In the above situation, based on the preceding text and... Figure 4 According to the description of the logic control module 300, the logic control third port 300c, logic control fourth port 300d, logic control fifth port 300e, logic control sixth port 300f, and logic control seventh port 300g will generate corresponding logic signals and transmit them to the corresponding connection ports.

[0043] like Figure 5 As shown, the charge / discharge module 500 includes: the twenty-fourth transistor T 24 And the twenty-fifth transistor T 25 ; Twenty-fourth transistor T 24 The gate of the charge / discharge module 500 serves as the first port 500a of the charge / discharge module 500, and the twenty-fourth transistor T 24 The source of the charge / discharge module 500 is used as the third port 500c of the charge / discharge module 500, and the twenty-fourth transistor T 24 The drain of the 25th transistor T 25 After the drain is connected, it serves as the fourth port 500d of the charge / discharge module 500, and the twenty-fifth transistor T 25 The gate of the charge / discharge module 500 serves as the second port 500b of the charge / discharge module 500, and the twenty-fifth transistor T 25 The source is connected to the voltage reference point AGND.

[0044] When the first port 500a of the charging / discharging module receives a high level, the twenty-fourth transistor T... 24 Shutdown; when the first port 500a of the charging / discharging module receives a low level, the twenty-fourth transistor T... 24 Conductive.

[0045] When the second port 500b of the charging / discharging module receives a high level, the twenty-fifth transistor T... 25 When the second port 500b of the charging / discharging module receives a low level, the twenty-fifth transistor T is activated. 25 Turn off.

[0046] When the voltage of the capacitor to be monitored is within the voltage monitoring range, the twenty-fourth transistor T... 24 And the twenty-fifth transistor T 25 Turn off; when the voltage of the capacitor to be monitored is greater than V R + V REF At that time, the twenty-fourth transistor T 24 Turn off, transistor T25 25 When the circuit is turned on, the capacitor to be monitored is discharged; when the voltage of the capacitor to be monitored is less than... V R - V REF At that time, the twenty-fourth transistor T 24 Turn on, transistor T25 25 Turn off and charge the capacitor to be monitored.

[0047] Twenty-fourth transistor T 24 It is a P-channel MOSFET, the twenty-fifth transistor T. 25 It is an N-channel MOSFET.

[0048] Preferably, the twenty-fourth transistor T 24 And the twenty-fifth transistor T 25 It is a power transistor.

[0049] The level shifting module 400 is configured to: in response to receiving a high level at the first level shifting port 400a and the second level shifting port 400b, output a high-level driving voltage at the third level shifting port 400c and output a low-level driving voltage at the fourth level shifting port 400d; When a high level is received at the first level shift port 400a and a low level is received at the second level shift port 400b, a high-level driving voltage is output at the third level shift port 400c and a high-level driving voltage is output at the fourth level shift port 400d. In response to receiving a low level at the first level shift port 400a and a high level at the second level shift port 400b, a low-level drive voltage is output at the third level shift port 400c and a low-level drive voltage is output at the fourth level shift port 400d.

[0050] The level shifting module 400 can convert the received logic level signal into a value that can drive the twenty-fourth transistor T. 24 And the twenty-fifth transistor T 25 The drive voltage signal that turns the circuit on or off.

[0051] This application does not limit the specific structure of the level shifting module 400 that can realize the above logic level input and output configuration.

[0052] Schematic diagram: The structure of the level shifting module 400 is as follows Figure 6 As shown, it includes: a first current source I1, a second current source I2, and a twenty-sixth transistor T. 26 Twenty-seventh transistor T 27 Twenty-eighth transistor T 28 And the twenty-ninth transistor T 29 ; Twenty-sixth transistor T 26 The gate and drain of the twenty-eighth transistor T 28 After the drain is connected, the 26th transistor T serves as the third port 400c of the level shifting module 400 for level shifting. 26 The source of transistor T is connected to one end of the first current source I1, and the other end of the first current source I1 is connected to the twenty-seventh transistor T. 27 The drain connection, the twenty-seventh transistor T 27 The gate of the level shift module 400 serves as the second level shift port 400b, and the twenty-seventh transistor T... 27 The source of the 29th transistor T 29 After the drain and gate are connected, the twenty-eighth transistor T serves as the fourth level shift port 400d of the level shift module 400. 28 The gate of the level shift module 400 serves as the first level shift port 400a, and the twenty-eighth transistor T... 28 The source of transistor T is connected to one end of the second current source I2, and the other end of the second current source I2 is connected to the twenty-ninth transistor T. 29 The source is connected to the voltage reference point AGND.

[0053] Optionally, such as Figure 7 As shown, the capacitor voltage adjustment circuit also includes a voltage setting module 600; The voltage setting module 600 has: a voltage setting input port 600a and a voltage setting output port 600b; The voltage setting input port 600a is connected to the third port 500c of the charge / discharge module of the charge / discharge module 500, and the voltage setting output port 600b is connected to the second port 200b of the comparison module of the comparison module 200.

[0054] Input voltage V IN The voltage setting module 600 is input via the voltage setting input port 600a, and the reference voltage V is input. R The output is set by the voltage setting port 600b.

[0055] like Figure 8As shown, the voltage setting module 600 includes: a fourth resistor R4 and a fifth resistor R5; One end of the fourth resistor R4 serves as the voltage setting input port 600a. The other end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and serves as the voltage setting output port 600b. The other end of the fifth resistor R5 is connected to the voltage reference point AGND.

[0056] Due to the reference voltage V R It is based on the input voltage V IN The reference voltage V is obtained by voltage division using the 600-volt voltage setting module. By adjusting the resistance values ​​of the fourth resistor R4 and the fifth resistor R5, the reference voltage V can be adjusted. R Relative to input voltage V IN The proportion.

[0057] Preferably, select R 4= R 5, of which, R 4 represents the resistance value of the fourth resistor, R4. R 5 represents the resistance value of the fifth resistor R5. Under this setting, the reference voltage V... R The amplitude is the input voltage V IN Half the amplitude.

[0058] By implementing the capacitor voltage adjustment circuit described in the embodiments of this application, the monitoring range of the capacitor voltage can be flexibly adjusted, allowing the same circuit architecture to adapt to different input voltage monitoring requirements by changing the external resistor value; hysteresis control is provided for the capacitor voltage to be monitored to prevent oscillation and frequent switching; the high-voltage region and low-voltage region in the circuit are isolated by the level shifting module to improve circuit reliability; and high-precision threshold voltage generation is achieved by utilizing the matching characteristics of analog integrated circuits, reducing the impact of process deviations and temperature drift on monitoring accuracy.

[0059] In other embodiments, such as Figure 9 As shown, a capacitor voltage adjustment method, applied to the capacitor voltage adjustment circuit described above, includes: S100: Set the voltage amplitude of the reference voltage source, and set the resistance values ​​of the first resistor, the second resistor, and the third resistor; S200: Sets the resistance values ​​of the fourth and fifth resistors; S300: Obtain the input voltage and determine the reference voltage based on the amplitude of the input voltage, the resistance value of the fourth resistor, and the resistance value of the fifth resistor; S400: Determine the voltage monitoring range based on the reference voltage, the voltage amplitude of the reference voltage source, the resistance value of the first resistor, the resistance value of the second resistor, and the resistance value of the third resistor; S500: Acquires the voltage of the capacitor to be monitored and adjusts the voltage of the capacitor to be monitored according to the voltage monitoring range.

[0060] Specifically, adjusting the voltage of the capacitor to be monitored according to the voltage monitoring range includes: S510: In response to the voltage of the capacitor to be monitored being within the voltage monitoring range, no correction is made to the voltage of the monitored capacitor. S520: Responds when the voltage of the capacitor being monitored is greater than... V R + I bias · R 2. Then, the capacitor to be monitored is discharged, where, V R The amplitude of the reference voltage. I bias The current value is the mirror current. R 2 represents the resistance value of the second resistor; S530: In response to the voltage of the capacitor being monitored being less than V R - I bias · R 3. Then, the capacitor to be monitored is charged, wherein... R 3 represents the resistance value of the third resistor.

[0061] By implementing the capacitor voltage adjustment method described in the embodiments of this application, the voltage monitoring range can be quantified and flexibly adjusted; the real-time and adaptive nature of the control strategy is realized, ensuring that no matter how the input voltage fluctuates, the system can instantly calculate the most suitable monitoring window under the current operating conditions without manual intervention; a complete closed-loop feedback control is formed, which not only ensures that the capacitor voltage is always maintained within a safe and efficient operating range, but also maximizes the system's energy efficiency ratio through the "adjust as needed" strategy.

[0062] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0063] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A capacitor voltage adjustment circuit, characterized in that, include: Conversion module (100), comparison module (200), logic control module (300), level shifting module (400), charging and discharging module (500); The conversion module (100) is connected to the comparison module, the comparison module is connected to the logic control module (300) and the charge / discharge module (500), the logic control module (300) is connected to the level shift module (400), the level shift module (400) is connected to the charge / discharge module (500), and the charge / discharge module (500) is also connected to the input voltage and the capacitor (C) to be monitored. The conversion module (100) is used to provide the offset voltage amplitude; The comparison module (200) is used to obtain the reference voltage (V). R ) and the magnitude of the offset voltage, and according to the reference voltage (V R The system determines the voltage monitoring range of the capacitor to be monitored (C) based on the offset voltage amplitude, and also obtains the voltage value of the capacitor to be monitored (C). When the voltage value of the capacitor to be monitored (C) deviates from the voltage monitoring range, the system controls the logic control module (300) to generate a logic signal, and uses the logic signal to control the level shift module (400) to drive the charging and discharging module (500) to correct the voltage value of the capacitor to be monitored (C).

2. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The conversion module (100) has a first port (100a); The comparison module (200) has: a first comparison module port (200a), a second comparison module port (200b), a third comparison module port (200c), a fourth comparison module port (200d), a fifth comparison module port (200e), a sixth comparison module port (200f), a seventh comparison module port (200g), and an eighth comparison module port (200h); The logic control module (300) has: a first logic control port (300a), a second logic control port (300b), a third logic control port (300c), a fourth logic control port (300d), a fifth logic control port (300e), a sixth logic control port (300f), and a seventh logic control port (300g). The level shifting module (400) has: a first level shifting port (400a), a second level shifting port (400b), a third level shifting port (400c), and a fourth level shifting port (400d). The charging and discharging module (500) has: a first port (500a), a second port (500b), a third port (500c), and a fourth port (500d). The first port (100a) of the conversion module is connected to the third port (200c) of the comparison module. The first port (200a) of the comparison module, after being connected to the fourth port (500d) of the charge / discharge module, is used to connect one end of the capacitor (C) to be monitored. The other end of the capacitor (C) to be monitored is connected to the voltage reference point (AGND). The second port (200b) of the comparison module is used to obtain the reference voltage (V). R The comparison module's fourth port (200d) is connected to the logic control first port (300a), the comparison module's fifth port (200e) is connected to the logic control second port (300b), the comparison module's sixth port (200f) is connected to the logic control third port (300c), the comparison module's seventh port (200g) is connected to the logic control fourth port (300d), and the comparison module's eighth port (200h) is connected to the logic control fifth port (300e). The sixth logic control port (300f) is connected to the first level shift port (400a), the seventh logic control port (300g) is connected to the second level shift port (400b), the third level shift port (400c) is connected to the first charging / discharging module port (500a), the fourth level shift port (400d) is connected to the second charging / discharging module port (500b), and the third charging / discharging module port (500c) is used to connect the input voltage, wherein the reference voltage (V) R It is determined based on the input voltage.

3. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The conversion module (100) includes: a reference voltage source (V REF The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the first resistor (R1) are operational amplifiers (OP), first transistors (T1), second transistors (T2), third transistors (T3), fourth transistors (T4), fifth transistors (T5), and first resistors (R1). The inverting input of the operational amplifier (OP) is connected to the reference voltage source (V). REF The positive terminal of the operational amplifier (OP) is connected to the first transistor (T1), the non-inverting input terminal of the operational amplifier (OP) is connected to the gate and drain of the first transistor (T1), the gate of the second transistor (T2), and the drain of the third transistor (T3). The output terminal of the operational amplifier (OP) is connected to the gate of the third transistor (T3). The source of the third transistor (T3) is connected to one end of the first resistor (R1). After the source of the first transistor (T1) is connected to the source of the second transistor (T2) and the gate of the fifth transistor (T5), it is used to connect the operating voltage (V). DD After the drain of the second transistor (T2) is connected to the drain and gate of the fourth transistor (T4), it serves as the first port (100a) of the conversion module (100). The source of the fourth transistor (T4) is connected to the drain of the fifth transistor (T5). The reference voltage source (V REF The negative terminal of the first resistor (R1) and the other end of the first resistor (R1) and the source of the fifth transistor (T5) are connected to the voltage reference point (AGND).

4. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The comparison module (200) includes: a first comparator (CMP1), a second comparator (CMP2), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), and a tenth transistor (T1). 10 ), eleventh transistor (T) 11 ), the twelfth transistor (T) 12 ), the thirteenth transistor (T) 13 ), the fourteenth transistor (T) 14 ), the fifteenth transistor (T) 15 ), the sixteenth transistor (T) 16 ), the seventeenth transistor (T) 17 ), the eighteenth transistor (T) 18 ), the nineteenth transistor (T) 19 ), the twentieth transistor (T) 20 ), Twenty-first transistor (T) 21 ), Twenty-second transistor (T) 22 ), Twenty-third transistor (T) 23 ), second resistor (R2) and third resistor (R3); After the gate and drain of the sixth transistor (T6) are connected, it serves as the first port (200a) of the comparison module (200). The source of the sixth transistor (T6) is connected to the inverting input of the first comparator (CMP1), the non-inverting input of the second comparator (CMP2), and the fourteenth transistor (T1). 14 The drain of the seventh transistor (T7) is connected to the source of the eighth transistor (T8), and the source of the eleventh transistor (T1) is connected to the drain of the eleventh transistor (T1). 11 The gate of the fourteenth transistor (T) 14 The gate of the sixteenth transistor (T) 16 The gate of the seventeenth transistor (T) 17 The gate of the 22nd transistor (T) and the gate of the 22nd transistor (T) 22 After the gate of the ) is connected, it is used to connect the operating voltage (V) DD The gate and drain of the seventh transistor (T7), the gate of the eighth transistor (T8), and the eleventh transistor (T... 11 The drain of the eighth transistor (T8) is connected to the non-inverting input of the first comparator (CMP1) and one end of the second resistor (R2). The gate of the ninth transistor (T9) is connected to the drain of the tenth transistor (T1). 10 After the gate and drain of the tenth transistor (T) are connected, it serves as the second port (200b) of the comparison module (200), and the tenth transistor (T) 10 The source of the transistor is connected to the drain of the ninth transistor (T9), and the source of the ninth transistor (T9) is connected to the other end of the second resistor (R2), one end of the third resistor (R3), and the seventeenth transistor (T7). 17 The drain of the 23rd transistor (T) and the drain of the 24th transistor (T) 23 The drain of the first transistor is connected to the second transistor (CMP2), and the other end of the third resistor (R3) is connected to the inverting input of the second comparator (CMP2) and the twentieth transistor (T). 20 The drain connection of the twentieth transistor (T) 20 The gate of the 23rd transistor (T) serves as the sixth port (200f) of the comparator module (200). 23 The gate of the twentieth transistor (T) serves as the seventh port (200g) of the comparator module (200), and the gate of the twentieth transistor (T) serves as the seventh port (200g) of the comparator module (200). 20 The source of ) and the twenty-first transistor (T) 21 The drain of the 23rd transistor (T) and the drain of the 24th transistor (T) 23 The source connection of the eleventh transistor (T) 11 The source of ) and the twelfth transistor (T) 12 The drain connection of the fourteenth transistor (T) 14 The source of ) and the fifteenth transistor (T) 15 The drain connection of the seventeenth transistor (T) 17 The source of ) and the eighteenth transistor (T) 18 The drain connection of the twelfth transistor (T) 12 The gate of the fifteenth transistor (T) and the gate of the fifteenth transistor (T) 15 The gate of the eighteenth transistor (T) 18 The gate of the 21st transistor and the gate of the 22nd transistor (T) 21 After the gate of the twelfth transistor (T) is connected, it serves as the third port (200c) of the comparator module (200), and the gate of the twelfth transistor (T) is connected. 12 The source of ) and the thirteenth transistor (T) 13 The drain connection of the fifteenth transistor (T) 15 The source of ) and the sixteenth transistor (T) 16 The drain connection of the eighteenth transistor (T) 18 The source of ) and the nineteenth transistor (T) 19 The drain connection of the 21st transistor (T) 21 The source of ) and the twentieth-second transistor (T) 22 The drain connection of the thirteenth transistor (T) 13 The gate of the nineteenth transistor (T) and the gate of the nineteenth transistor (T) 19 After the gate of the thirteenth transistor (T) is connected, it serves as the eighth port (200h) of the comparison module (200), and the thirteenth transistor (T) 13 The source of ) and the sixteenth transistor (T) 16 The source of the nineteenth transistor (T) 19 The source of the transistor and the twentieth-second transistor (T) 22 After the source of the first comparator (CMP1) is connected, it is connected to the voltage reference point (AGND). The output of the first comparator (CMP1) is used as the fourth port (200d) of the comparator module (200), and the output of the second comparator (CMP2) is used as the fifth port (200e) of the comparator module (200).

5. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The logic control module (300) includes: a first NAND gate (310), a second NAND gate (320), a first inverter (330), a second inverter (340), and a third inverter (350). After the input terminal of the first inverter (330) is connected to one input terminal of the second NAND gate (320), it serves as the first logic control port (300a) of the logic control module (300). The output terminal of the first inverter (330) is connected to one input terminal of the first NAND gate (310). After the other input terminal of the first NAND gate (310) is connected to the input terminal of the second inverter (340), it serves as the second logic control port (300b) of the logic control module (300). The output terminal of the second inverter (340) is connected to the input terminal of the second NAND gate (320). The other input terminal of the first NAND gate (310) is connected to the input terminal of the third inverter (350), which serves as the third logic control port (300c) and the sixth logic control port (300f) of the logic control module (300). The output terminal of the third inverter (350) serves as the fourth logic control port (300d) of the logic control module (300), and the output terminal of the second NAND gate (320) serves as the fifth logic control port (300e) and the seventh logic control port (300g) of the logic control module (300).

6. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The charging and discharging module (500) includes: a twenty-fourth transistor (T 24 ) and the twenty-fifth transistor (T 25 ); The 24th transistor (T) 24 The gate of the 24th transistor (T) serves as the first port (500a) of the charge / discharge module (500), and the gate of the 24th transistor (T) serves as the first port (500a) of the charge / discharge module (500). 24 The source of the 24th transistor (T) serves as the third port (500c) of the charge / discharge module (500), and the source of the 24th transistor (T) serves as the third port (500c) of the charge / discharge module (500). 24 The drain of the 25th transistor (T) and the 25th transistor (T) 25 After the drain of the ) is connected, it serves as the fourth port (500d) of the charge / discharge module (500), and the 25th transistor (T) 25 The gate of the 25th transistor (T) serves as the second port (500b) of the charge / discharge module (500), and the gate of the 25th transistor (T) serves as the second port (500b) of the charge / discharge module (500). 25 The source of the ) is connected to the voltage reference point (AGND).

7. The capacitor voltage adjustment circuit according to claim 1, characterized in that, The level shifting module (400) is configured to: In response to receiving a high level at the first level shift port (400a) and the second level shift port (400b), a high-level drive voltage is output at the third level shift port (400c), and a low-level drive voltage is output at the fourth level shift port (400d). In response to receiving a high level at the first level shift port (400a) and a low level at the second level shift port (400b), a high-level driving voltage is output at the third level shift port (400c) and a high-level driving voltage is output at the fourth level shift port (400d). In response to receiving a low level at the first level shift port (400a) and a high level at the second level shift port (400b), a low-level drive voltage is output at the third level shift port (400c) and a low-level drive voltage is output at the fourth level shift port (400d).

8. The capacitor voltage adjustment circuit according to any one of claims 1-7, characterized in that, The circuit also includes a voltage setting module (600). The voltage setting module (600) has: a voltage setting input port (600a) and a voltage setting output port (600b); The voltage setting input port (600a) is connected to the third port (500c) of the charging and discharging module (500), and the voltage setting output port (600b) is connected to the second port (200b) of the comparison module (200).

9. The capacitor voltage adjustment circuit according to claim 8, characterized in that, The voltage setting module (600) includes: a fourth resistor (R4) and a fifth resistor (R5); One end of the fourth resistor (R4) serves as the voltage setting input port (600a), and the other end of the fourth resistor (R4) is connected to one end of the fifth resistor (R5) to serve as the voltage setting output port (600b). The other end of the fifth resistor (R5) is connected to the voltage reference point (AGND).

10. A method for adjusting capacitor voltage, characterized in that, The capacitor voltage adjustment circuit according to any one of claims 1-9 comprises: Set the voltage amplitude of the reference voltage source, and set the resistance values ​​of the first resistor, the second resistor, and the third resistor; Set the resistance values ​​of the fourth and fifth resistors; Obtain the input voltage and determine the reference voltage based on the amplitude of the input voltage, the resistance value of the fourth resistor, and the resistance value of the fifth resistor; The voltage monitoring range is determined based on the reference voltage, the voltage amplitude of the reference voltage source, the resistance of the first resistor, the resistance of the second resistor, and the resistance of the third resistor. Obtain the voltage of the capacitor to be monitored, and adjust the voltage of the capacitor to be monitored according to the voltage monitoring range.

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