A fast-starting bandgap reference circuit

Abstract

The application relates to a fast-starting band-gap reference circuit. The band-gap reference circuit comprises a starting current generating module, a biasing branch, a current mirror copy branch, a reference voltage generating module, a current filling branch and a clamping operational amplifier module. The starting current generating module is used for providing a starting current for the reference voltage generating module. The biasing branch is used for providing a bias voltage for the current mirror copy branch. The current mirror copy branch is used for copying the branch current generated by the current mirror copy branch to the reference voltage generating module to form the starting current. The reference voltage generating module is used for generating a band-gap voltage. The current filling branch is used for injecting the mirror-copied starting current and an injection current controlled by a feedback loop of the clamping operational amplifier module into a band-gap generating branch. The clamping operational amplifier module is used for clamping the voltage of two connection nodes through the feedback loop to make the sum of the injection current and the starting current be the working current of the clamping operational amplifier module. The application can solve the problems that the current band-gap reference starting circuit has slow starting speed, large extra static power consumption in the starting process and large influence of the starting circuit on the power voltage, temperature and process deviation.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a fast-start bandgap reference circuit. Background Technology

[0002] The bandgap reference is a core module of an analog chip, providing a high-precision reference voltage that remains unchanged regardless of temperature or voltage, directly affecting the chip's accuracy and reliability. Bandgap reference circuits are suitable for analog or mixed-signal integrated circuits such as power management and digital-to-analog conversion. Because bandgap reference circuits exhibit a degeneracy point problem during startup—meaning they exist in both correct and other operating states—a startup circuit is needed to help the circuit enter its normal operating state upon startup.

[0003] Currently, integrated circuits are developing towards low voltage and low power consumption, miniaturization, wide voltage range, and high reliability. Traditional bandgap startup circuits suffer from problems such as slow startup, poor robustness, and high static power consumption. Therefore, a bandgap reference with fast power-up speed, strong stability, and low static power consumption is essential for improving the overall performance of the chip.

[0004] In analog circuit design, the circuit structures of bandgap reference sources mainly include the following: Widlar-type bandgap voltage reference source, Kuijk-type bandgap voltage reference source, and Banba current-mode bandgap voltage reference source. The reference voltage source structure in this invention is a Kuijk-type reference voltage source structure.

[0005] In 1973, KEKuijk proposed a precision reference voltage source. This circuit was the first to introduce a bandgap reference with an operational amplifier clamped current mirror structure, solving the current matching problem in early circuits. This type of bandgap reference is as follows: Figure 1 The diagram shows a Kuijk bandgap voltage reference source. This Kuijk bandgap voltage reference source includes a PTAT current generation circuit and a clamping operational amplifier. The Kuijk bandgap voltage reference source includes the clamping operational amplifier Amp, NPN transistors Q11-Q12, and resistors R11-R13. The clamping operational amplifier uses node voltage... and As input, the upper ends of R11 and R12 (R11=R12) are driven, clamping points X and Y at approximately equal voltages. The reference voltage Vref can be obtained at the output of the op-amp, based on the... Figure 1 Analysis of the Kuijk reference voltage source, we have ,in , These are the base-emitter voltages of NPN transistors Q11~Q12, respectively. Let n be the thermal voltage, and n be the emitter area ratio of Q11 to Q12; the output current of the left branch is obtained as follows. Therefore, the output voltage is .

[0006] The startup circuits used in the Kuijk reference voltage source mainly include the following types: startup circuits using capacitive coupling, current injection startup circuits, and startup circuits that detect voltage through a comparator.

[0007] like Figure 2 The diagram shows a typical soft-start circuit for a reference circuit. This circuit uses capacitor C1 for soft starting. When the system is powered on, the reference start-up module charges capacitor C1 through the signal line until C1 turns on transistors NM2 and NM3. The current is then copied to the outside through current mirrors PM1 and PM2, enabling the main bandgap reference circuit to operate. When the reference voltage reaches a certain value, the input level is flipped, and the start-up module is turned off.

[0008] Figure 2 Medium current sources Ibias1 and Ibias2 provide a relatively stable bias current for the circuit. The bandgap voltage Vref is converted into an output voltage through an inverter, controlling the state of NM1. When the chip is first powered on, the reference source has not yet started, and the reference source output voltage is low. After passing through the inverter, the output voltage is high, NM1 is turned on, and Ibias1 charges the capacitor C1 of the reference module. When the voltage on the capacitor reaches the threshold voltage of the subsequent NMOS transistor, the reference module starts to work, the voltage rises, and after Vref is established, the inverter output becomes low, causing NM1 to turn off and stop charging capacitor C1, thus completing the soft start.

[0009] Traditional bandgap reference startup circuits, such as the soft-start circuits using capacitors mentioned above, employ relatively small bias currents to reduce steady-state power consumption, resulting in long power-up times and instability. Power-up time and the operating state of the startup circuit are significantly affected by power supply voltage, temperature, and process variations, leading to poor startup reliability. Traditional bandgap reference sources often achieve fast startup by increasing power consumption, resulting in a trade-off between low quiescent power consumption and fast startup, making it difficult to meet the demands of modern reference circuits for both.

[0010] Therefore, there is an urgent need for this invention to propose a fast-start bandgap reference circuit to solve the above-mentioned technical problems. Summary of the Invention

[0011] The purpose of this invention is to provide a fast-start bandgap reference circuit. This invention can solve the problems of slow start-up speed, large additional static power consumption during start-up, and the significant impact of power supply voltage, temperature and process deviation on the start-up circuit of current bandgap reference start-up circuits.

[0012] To address the aforementioned technical problems, this invention provides a fast-start bandgap reference circuit, comprising: A startup current generation module is used to provide a startup current for the reference voltage generation module; it includes a bias branch and a current mirror copy branch; the bias branch provides a bias voltage to the current mirror copy branch, and the current mirror copy branch mirrors and copies the branch current it generates to the reference voltage generation module to form a startup current; A reference voltage generation module is used to generate a bandgap voltage Vref; it includes a current injection branch and a bandgap generation branch; the current injection branch injects the mirror-copied starting current and the injection current controlled by the feedback loop of the clamping operational amplifier module into the bandgap generation branch. The clamping operational amplifier module has its positive and negative input terminals connected to the two connection nodes of the bandgap generation branch, and its output terminal connected to the current injection branch. Through its feedback loop, it clamps the voltage of the two connection nodes so that the sum of the injected current and the starting current is always the operating current of the clamping operational amplifier module.

[0013] Preferably, the bias branch includes: a PMOS transistor string, an NMOS transistor N5, and a PNP transistor Q3; the gate of the PMOS transistor string is connected to an enable signal EN, and when the enable signal EN is low, the PMOS transistor string operates in the linear region to form a MOS resistor; one end of the PMOS transistor string's source is connected to the power supply VCC, and the other end's drain is connected to the drain and gate of the NMOS transistor N5 to generate a bias output node; the source of the NMOS transistor N5 is connected to the emitter of the PNP transistor Q3, and the base and collector of the PNP transistor Q3 are grounded to GND.

[0014] Preferably, the PMOS transistor string includes PMOS transistors P6 to P9; the source of PMOS transistor P6 serves as one end of the PMOS transistor string, the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8, the drain of PMOS transistor P8 is connected to the source of PMOS transistor P9, the drain of PMOS transistor P9 serves as the other end of the PMOS transistor string, and the gates of PMOS transistors P6 to P9 are connected to the enable signal EN.

[0015] Preferably, the current mirror copying branch includes: PMOS transistors P10~P11, NMOS transistors N6~N7, and resistor R4; the source of PMOS transistor P10 is connected to power supply VCC, and its drain and gate are connected to the drain of NMOS transistor N6 and the input terminal of the current sinking branch; the gates of NMOS transistors N6~N7 are connected to the bias voltage output by the bias branch, and the sources of NMOS transistors N6~N7 are connected to resistor R4 connected to ground GND; the drain of NMOS transistor N7 is connected to the drain and gate of PMOS transistor P11 and the input terminal of the current sinking branch; the source of PMOS transistor P11 is connected to power supply VCC.

[0016] Preferably, the current injection branch includes: PMOS transistors P1~P2 and PMOS transistors P12~P13; the sources of PMOS transistors P1 and P12 are connected to the power supply VCC, and the gates of PMOS transistors P12~P13 serve as input terminal one and input terminal two, respectively, and receive the branch current generated by the current mirror copy branch; the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, and the drains of PMOS transistors P13 and PMOS transistor P2 serve as output terminals connected to the current injection terminal of the bandgap generation branch; the gate of PMOS transistor P2 is connected to the bias voltage Vbias, the source is connected to the drain of PMOS transistor P1, and the gate of PMOS transistor P1 is connected to the output terminal of the clamping operational amplifier module.

[0017] Preferably, the bandgap generation branch includes: PNP transistors Q1~Q2 and resistors R1~R3; the base and collector of the PNP transistors Q1~Q2 are grounded to GND, the emitter of the PNP transistor Q1 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of resistor R2 and the positive input terminal of the clamping operational amplifier module, the other end of resistor R2 is connected to one end of resistor R1 and the output terminal of the current injection branch, and generates a bandgap voltage Vref; the other end of resistor R1 is connected to the emitter of the PNP transistor Q2 and the negative input terminal of the clamping operational amplifier module.

[0018] Preferably, the resistance ratio of resistors R1 to R2 is R1:R2=1:2; and the emitter area ratio of PNP transistors Q1 to Q2 is Q1:Q2=1:24.

[0019] Preferably, the clamping operational amplifier module includes: PMOS transistors P3-P5, NMOS transistors N1-N4, and PNP transistors Q4-Q5; the sources of PMOS transistors P3-P5 are connected to the power supply VCC; the gate and drain of PMOS transistor P3 are connected to the gate of PMOS transistor P4 and the drain of NMOS transistor N1; the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2 and generates a bias voltage Vbias1; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N3 and the collector of PNP transistor Q4; the gate of NMOS transistor N3 is connected to NMOS transistor N4... The gate of the PMOS transistor is connected to generate a bias voltage Vbias2; the source of the NMOS transistors N3-N4 is grounded to GND; the drain of the NMOS transistor N4 is connected to the source of the NMOS transistor N2 and the collector of the PNP transistor Q5; the drain of the NMOS transistor N2 is connected to the drain of the PMOS transistor P4 and serves as the output terminal of the clamping operational amplifier module; the bases of the PNP transistors Q4-Q5 serve as the positive and negative input terminals of the clamping operational amplifier module, respectively; the emitters of the PNP transistors Q4-Q5 are connected to the drain of the PMOS transistor P5, and the gate of the PMOS transistor P5 is connected to a bias voltage Vbias3.

[0020] The present invention also provides a power management circuit that employs a fast-start bandgap reference circuit as described above.

[0021] The present invention also provides a digital-to-analog conversion circuit, which employs a fast-start bandgap reference circuit as described above.

[0022] Compared with the prior art, the present invention has the following beneficial effects: This invention, by adding a startup current generation module, can break the degenerate bias point of the bandgap reference upon power-up, effectively avoiding the problem of traditional bandgap references failing to start due to zero current lockout. Simultaneously, because current is injected synchronously into the main bandgap reference circuit (i.e., the reference voltage generation module) and the clamping operational amplifier, the main bandgap reference circuit and the clamping operational amplifier start synchronously, significantly shortening the voltage settling time. Compared to traditional startup circuits, this invention's fast startup circuit does not require shutdown after the bandgap reference is operating normally. Therefore, it does not generate additional large currents during chip startup and does not increase additional static power consumption after startup. Furthermore, as part of the main bandgap reference circuit, this circuit improves the robustness of the startup circuit and is simpler and more reliable than traditional startup circuits. Attached Figure Description

[0023] Figure 1 Circuit diagram of the Kuijk bandgap reference voltage source provided for the prior art.

[0024] Figure 2 A circuit diagram of the soft-start equivalent circuit provided for the prior art.

[0025] Figure 3 The present invention provides a circuit diagram of a fast-start bandgap reference circuit.

[0026] Figure 4 The circuit diagram of the clamping operational amplifier module provided by this invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] like Figure 3 As shown, this embodiment of the invention specifically provides a fast-start bandgap reference circuit, including a startup current generation module, a reference voltage generation module, and a clamping operational amplifier module.

[0029] The startup current generation module includes constant voltage PMOS transistors P6, P7, P8, P9, P10, and P11, constant voltage NMOS transistors N5, N6, and N7, PNP transistor Q3, and resistor R4.

[0030] In the startup current generation module, the source of the constant-voltage PMOS transistor P6 is connected to the power supply VCC. The gate of constant-voltage PMOS transistor P6 is connected to the gates of constant-voltage PMOS transistors P7, P8, and P9. The drain of constant-voltage PMOS transistor P6 is connected to the source of constant-voltage PMOS transistor P7. The drain of constant-voltage PMOS transistor P7 is connected to the source of constant-voltage PMOS transistor P8. The drain of constant-voltage PMOS transistor P8 is connected to the source of constant-voltage PMOS transistor P9. The drain of constant-voltage PMOS transistor P9 is connected to the drain and gate of constant-voltage NMOS transistor N5, and the gates of constant-voltage NMOS transistors N6 and N7. The source of constant-voltage NMOS transistor N5 is connected to the emitter of PNP transistor Q3. The base and collector of transistor Q3 are connected to ground (GND). The upper end of resistor R4 is connected to the source of N6 and N7 of NMOS transistors at constant voltage, and the lower end of resistor R4 is connected to ground (GND). The source of PMOS transistor P10 at constant voltage is connected to power supply VCC. The gate and drain of PMOS transistor P10 at constant voltage are connected to the drain of NMOS transistor N6 at constant voltage. The source of PMOS transistor P11 at constant voltage is connected to power supply VCC. The gate and drain of PMOS transistor P11 at constant voltage are connected to the drain of NMOS transistor N7 at constant voltage. The gate of PMOS transistor P10 at constant voltage is connected to the gate of PMOS transistor P12 at constant voltage. The gate of PMOS transistor P11 at constant voltage is connected to the gate of PMOS transistor P13 at constant voltage.

[0031] The reference voltage generation module includes constant voltage PMOS transistors P1, P2, P12, and P13, PNP transistors Q1 and Q2, and resistors R1, R2, and R3; the clamping operational amplifier module uses an operational amplifier AMP_bandgap.

[0032] In the reference voltage generation module, the source of the constant voltage PMOS transistor P1 is connected to the power supply VCC, the gate of the constant voltage PMOS transistor P1 is connected to the output terminal AMP_Output of the operational amplifier AMP_bandgap, the drain of the constant voltage PMOS transistor P1 is connected to the source of the constant voltage PMOS transistor P2, and the gate of the constant voltage PMOS transistor P2 is connected to the bias voltage Vbias. The bias voltage Vbias is the voltage required for the circuit module to work and is generally generated by the bias circuit. The source of PMOS transistor P12 is connected to the power supply VCC. The gate of PMOS transistor P12 is connected to the gate of PMOS transistor P10. The drain of PMOS transistor P12 is connected to the source of PMOS transistor P13. The gate of PMOS transistor P13 is connected to the gate of PMOS transistor P11. The drain of PMOS transistor P13 is connected to the drain of PMOS transistor P2. The drain of PMOS transistor P2 is connected to the upper ends of resistors R1 and R2. The lower end of resistor R1 is connected to the negative input terminal INN of operational amplifier AMP_bandgap and the emitter of PNP transistor Q1. The lower end of resistor R2 is connected to the positive input terminal INP of operational amplifier AMP_bandgap and the upper end of resistor R3. The lower end of resistor R3 is connected to the emitter of PNP transistor Q2. The base and collector of PNP transistors Q1 and Q2 are connected to GND.

[0033] like Figure 4 As shown, the clamping operational amplifier AMP_bandgap includes constant voltage PMOS transistors P3, P4, and P5, constant voltage NMOS transistors N1, N2, N3, and N4, and PNP transistors Q4 and Q5.

[0034] In the clamping operational amplifier AMP_bandgap, the source of the constant-voltage PMOS transistor P5 is connected to the power supply VCC, the gate of P5 is connected to the bias voltage Vbias3 generated by the startup current, the drain of P5 is connected to the emitters of PNP transistors Q5 and Q4, the base of Q5 is the negative input terminal INN of the clamping operational amplifier, the collector of Q5 is connected to the source of constant-voltage NMOS transistors N2 and N4, the base of Q4 is the positive input terminal INP of the clamping operational amplifier, and the collector of Q4 is connected to the constant-voltage... The source of NMOS transistor N1 is connected to the drain of NMOS transistor N3 (normal voltage). The source of PMOS transistor P3 (normal voltage) is connected to power supply VCC. The gate of PMOS transistor P3 (normal voltage) is connected to the drain of PMOS transistor P3 (normal voltage) and the gate of PMOS transistor P4 (normal voltage). The drain of PMOS transistor P3 (normal voltage) is connected to the drain of NMOS transistor N1 (normal voltage). The source of PMOS transistor P4 (normal voltage) is connected to power supply VCC. The drain of PMOS transistor N3 (normal voltage) is connected to the drain of NMOS transistor N2 (normal voltage). The gate of NMOS transistor N3 (normal voltage) is connected to the gate of NMOS transistor N4 (normal voltage). The drain of NMOS transistor N3 (normal voltage) is connected to the drain of NMOS transistor N4 (normal voltage).

[0035] It also includes the following working principles: like Figure 3 The left bias branch of the startup current generation module shown consists of four series-connected PMOS transistors (P6, P7, P8, and P9) with their gates connected to the enable signal EN, plus diode N5 and PNP transistor Q3. When the enable signal EN is low, these four PMOS transistors operate in the linear region, forming a MOS resistor. Because the gate voltages are the same, the currents of N6 and N7 are determined by N5. The startup current generation module forms... current The current is copied outward through the current mirror formed by P10, P11, P12 and P13.

[0036] When the chip starts up, the copied startup current is injected into the reference voltage generation module and the clamping operational amplifier module, such as... Figure 3 As shown, when the bandgap reference circuit has not entered the normal operating point, this additional current injection branch will inject current into the bandgap generation branch (i.e., the bandgap reference main circuit) and the clamping operational amplifier module, so that the bandgap gets out of the degeneracy point of zero current.

[0037] Specifically, during the power-on process, the gate voltage of the constant-voltage PMOS transistor connected in series in the startup current generation module is controlled by the enable signal EN. Initially, the enable voltage is high; as the power supply voltage rises, the enable voltage decreases, turning on the series-connected PMOS transistor and injecting current downwards, thus obtaining the gate voltage of the constant-voltage NMOS transistor N5. , This is the base-emitter voltage of transistor Q3. Given the gate-source voltage of transistor N5, the gate-source voltages of constant voltage NMOS transistors N6 and N7 can be approximated as the same as the gate-source voltage of constant voltage NMOS transistor N5. Therefore, the dropout voltage across resistor R4 can be obtained as follows: The current generated by the right-side current mirror copy branch is Starting current Copy the branch current for the right-side current mirror.

[0038] By stabilizing the INP and INN terminals to approximately equal voltages using the clamping operational amplifier AMP_bandgap described above, and considering that the resistance of resistor R2 in this design is twice that of R1, we can obtain... The formula for the collector current of a transistor is: ,in For collector current, It is the reverse saturation current. This is the base-emitter voltage. This is the thermal voltage; in the design of this invention, the emitter area ratio of transistors Q1~Q2 is Q1:Q2=1:24, from which we can obtain: A temperature-dependent current can be obtained by using a clamping operational amplifier. :

[0039] During circuit operation, if the startup current exceeds the op-amp's operating current, the clamping op-amp will malfunction, resulting in zero current in the output branch. Therefore, it is necessary to ensure the startup current is within acceptable limits. Always less than the op-amp operating current This ensures the clamping operational amplifier is functioning correctly. The operational amplifier controls the current injected into the bandgap generation branch (bandgap reference main circuit) through a feedback loop. The sum of this injected current and the starting current is the operational amplifier's operating current.

[0040] In summary, this invention eliminates the zero-current degeneracy point by injecting current into the bandgap reference circuit and the clamping operational amplifier with a fixed bias current, thereby achieving synchronous and rapid startup of the bandgap reference circuit and the clamping operational amplifier. Moreover, the fixed bias current used for startup is always present during the normal operation of the bandgap reference circuit and, as part of the operating current, does not introduce additional static power consumption compared to startup circuits with other architectures.

[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A fast-start bandgap reference circuit, characterized in that, include: A startup current generation module is used to provide startup current for a reference voltage generation module; it includes a bias branch and a current mirror copy branch; the bias branch provides a bias voltage to the current mirror copy branch, and the current mirror copy branch mirrors and copies the branch current it generates to the reference voltage generation module to form a startup current; A reference voltage generation module is used to generate a bandgap voltage Vref; it includes a current injection branch and a bandgap generation branch; the current injection branch injects the mirror-copied starting current and the injection current controlled by the feedback loop of the clamping operational amplifier module into the bandgap generation branch. The clamping operational amplifier module has its positive and negative input terminals connected to the two connection nodes of the bandgap generation branch, and its output terminal connected to the current injection branch. Through its feedback loop, it clamps the voltage of the two connection nodes so that the sum of the injected current and the starting current is always the operating current of the clamping operational amplifier module. The bias branch includes: a PMOS transistor string, an NMOS transistor N5, and a PNP transistor Q3; the gate of the PMOS transistor string is connected to an enable signal EN. When the enable signal EN is low, the PMOS transistor string operates in the linear region, forming a MOS resistor; one end of the PMOS transistor string's source is connected to the power supply VCC, and the other end's drain is connected to the drain and gate of the NMOS transistor N5, generating a bias output node; the source of the NMOS transistor N5 is connected to the emitter of the PNP transistor Q3, and the base and collector of the PNP transistor Q3 are grounded to GND; The current mirror copying branch includes: PMOS transistors P10~P11, NMOS transistors N6~N7, and resistor R4; the source of PMOS transistor P10 is connected to power supply VCC, and its drain and gate are connected to the drain of NMOS transistor N6 and the input terminal of the current sinking branch; the gates of NMOS transistors N6~N7 are connected to the bias voltage output by the bias branch, and the sources of NMOS transistors N6~N7 are connected to resistor R4 connected to ground GND; the drain of NMOS transistor N7 is connected to the drain and gate of PMOS transistor P11 and the input terminal of the current sinking branch; the source of PMOS transistor P11 is connected to power supply VCC; The current injection branch includes PMOS transistors P1~P2 and PMOS transistors P12~P13; the sources of PMOS transistors P1 and P12 are connected to the power supply VCC, and the gates of PMOS transistors P12~P13 serve as input terminals one and two, respectively, and receive the branch current generated by the current mirror copy branch; the drain of PMOS transistor P12 is connected to the source of PMOS transistor P13, and the drains of PMOS transistors P13 and PMOS transistor P2 serve as output terminals connected to the current injection terminals of the bandgap generation branch; the gate of PMOS transistor P2 is connected to the bias voltage Vbias, and its source is connected to the drain of PMOS transistor P1; the gate of PMOS transistor P1 is connected to the output terminal of the clamping operational amplifier module.

2. The fast-start bandgap reference circuit as described in claim 1, characterized in that, The PMOS transistor string includes PMOS transistors P6 to P9; the source of PMOS transistor P6 serves as one end of the PMOS transistor string, the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8, the drain of PMOS transistor P8 is connected to the source of PMOS transistor P9, the drain of PMOS transistor P9 serves as the other end of the PMOS transistor string, and the gates of PMOS transistors P6 to P9 are connected to the enable signal EN.

3. The fast-start bandgap reference circuit as described in claim 1, characterized in that, The bandgap generation branch includes: PNP transistors Q1~Q2 and resistors R1~R3; the base and collector of the PNP transistors Q1~Q2 are grounded to GND, the emitter of the PNP transistor Q1 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of resistor R2 and the positive input terminal of the clamping operational amplifier module, the other end of resistor R2 is connected to one end of resistor R1 and the output terminal of the current injection branch, and generates a bandgap voltage Vref; the other end of resistor R1 is connected to the emitter of the PNP transistor Q2 and the negative input terminal of the clamping operational amplifier module.

4. The fast-start bandgap reference circuit as described in claim 3, characterized in that, The resistance ratio of resistors R1 to R2 is R1:R2=1:2; the emitter area ratio of PNP transistors Q1 to Q2 is Q1:Q2=1:

24.

5. The fast-start bandgap reference circuit as described in claim 1, characterized in that, The clamping operational amplifier module includes: PMOS transistors P3-P5, NMOS transistors N1-N4, and PNP transistors Q4-Q5; the sources of PMOS transistors P3-P5 are connected to the power supply VCC; the gate and drain of PMOS transistor P3 are connected to the gate of PMOS transistor P4 and the drain of NMOS transistor N1; the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2 and generates a bias voltage Vbias1; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N3 and the collector of PNP transistor Q4; the gate of NMOS transistor N3 is connected to the gate of NMOS transistor N4. The NMOS transistors N3-N4 are connected to ground (GND); the drain of NMOS transistor N4 is connected to the source of NMOS transistor N2 and the collector of PNP transistor Q5; the drain of NMOS transistor N2 is connected to the drain of PMOS transistor P4 and serves as the output terminal of the clamping operational amplifier module; the bases of PNP transistors Q4-Q5 serve as the positive and negative input terminals of the clamping operational amplifier module, respectively; the emitters of PNP transistors Q4-Q5 are connected to the drain of PMOS transistor P5, and the gate of PMOS transistor P5 is connected to the bias voltage Vbias3.

6. A power management circuit, characterized in that, The method employs a fast-start bandgap reference circuit as described in any one of claims 1 to 5.

7. A digital-to-analog converter circuit, characterized in that, The method employs a fast-start bandgap reference circuit as described in any one of claims 1 to 5.

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