A current source circuit and an integrated circuit

Abstract

This application provides a current source circuit and integrated circuit, applicable to the field of integrated circuit design technology. The circuit includes a detection circuit, a negative temperature coefficient current generation circuit, and a positive temperature coefficient current generation circuit. The detection circuit detects the changing trend of the reference voltage of the voltage-mode bandgap reference circuit and generates a control signal. The negative temperature coefficient current generation circuit responds to the control signal and generates a target negative temperature coefficient current based on the reference voltage. The positive temperature coefficient current generation circuit generates a target positive temperature coefficient current based on the bias voltage of the voltage-mode bandgap reference circuit. The target negative temperature coefficient current and the target positive temperature coefficient current are superimposed to output a zero-temperature drift current. Compared with related technologies that additionally introduce a current-mode bandgap reference circuit, this circuit makes full use of the existing voltage-mode bandgap reference circuit. While meeting the zero-temperature drift current requirements of some circuits in the integrated circuit, it avoids large-scale modifications to the overall circuit, which helps the product development proceed smoothly.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, specifically to a current source circuit and an integrated circuit. Background Technology

[0002] In the field of integrated circuit design, voltage-mode bandgap reference circuits are widely used as reference voltage sources and bias sources for systems due to their mature structure and stable output. In such systems powered by voltage-mode bandgap reference circuits, local circuits sometimes require zero-temperature drift current to achieve higher-precision signal processing or conversion functions.

[0003] In related technologies, to obtain zero-temperature drift current, a dedicated current-mode bandgap reference circuit can be configured inside the integrated circuit to generate it directly. However, for integrated circuits that already have a built-in voltage-mode bandgap reference circuit or must use one, an additional independent current-mode reference circuit must be integrated. Such a setup inevitably requires extensive modifications or adaptations to the original power supply architecture, extending the product development cycle. Summary of the Invention

[0004] In view of this, this application aims to provide a current source circuit and integrated circuit to solve the problem that adding a current mode bandgap reference circuit to an integrated circuit that already has a built-in voltage mode bandgap reference circuit requires extensive modifications to the original power supply architecture, thus extending the product development cycle.

[0005] In a first aspect, this application provides a current source circuit applied to an integrated circuit configured with a voltage-mode bandgap reference circuit, the voltage-mode bandgap reference circuit being used to provide a reference voltage and a bias voltage, the current source circuit comprising: The detection circuit is connected to the voltage-mode bandgap reference circuit to detect the trend of the reference voltage changing with the operating temperature of the integrated circuit, and generates a control signal based on the detection result. The negative temperature coefficient current generation circuit is connected to the voltage mode bandgap reference circuit and the detection circuit respectively, and generates a target negative temperature coefficient current based on the reference voltage in response to the control signal. A positive temperature coefficient current generation circuit is connected to the voltage-mode bandgap reference circuit and generates a target positive temperature coefficient current based on the bias voltage. The output terminal of the negative temperature coefficient current generating circuit is connected to the output terminal of the positive temperature coefficient current generating circuit, and the target negative temperature coefficient current and the target positive temperature coefficient current are superimposed to output a zero temperature drift current.

[0006] In one optional implementation, the negative temperature coefficient current generating circuit includes: A reference current generation circuit is connected to the voltage-mode bandgap reference circuit and the detection circuit respectively, and generates a reference negative temperature coefficient current based on the reference voltage in response to the control signal. The first current mirror circuit is connected to the reference current generation circuit and, in response to the reference negative temperature coefficient current, outputs the target negative temperature coefficient current according to a preset mirror ratio.

[0007] In one optional implementation, the control signal includes: a first control signal characterizing that the reference voltage increases as the operating temperature increases, and a second control signal characterizing that the reference voltage decreases as the operating temperature increases. The reference current generation circuit includes: The first current generation branch, in response to the first control signal, receives the reference voltage and generates a reference negative temperature coefficient current that decreases as the reference voltage increases based on the reference voltage. The second current generation branch, in response to the second control signal, receives the reference voltage and generates a reference negative temperature coefficient current that decreases as the reference voltage decreases.

[0008] In one optional implementation, the first current generating branch may be selectively connected to the second current generating branch; When the first current generating branch is connected to the second current generating branch, the reference negative temperature coefficient current, which decreases as the operating temperature increases, is transmitted through the second current generating branch.

[0009] In one optional implementation, the first current generation branch includes: a first controllable switch, a first PMOS transistor, a first NMOS transistor, and a second controllable switch, wherein, The input terminal of the first controllable switch is used to receive the reference voltage, the control terminal of the first controllable switch is used to receive the control signal, and the output terminal of the first controllable switch is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is used to receive the operating voltage, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain and gate of the first NMOS transistor are shorted, and the source of the first NMOS transistor is grounded; The input terminal of the second controllable switch is connected to the gate of the first NMOS transistor, the output terminal of the second controllable switch serves as the output terminal of the first current generation branch, and the control terminal of the second controllable switch is used to receive the control signal. The first controllable switch and the second controllable switch are turned on in response to the first control signal; The first controllable switch and the second controllable switch are turned off in response to the second control signal.

[0010] In one optional implementation, the second current generation branch includes: a second NMOS transistor and a third controllable switch, wherein, The input terminal of the third controllable switch is used to receive the reference voltage, the output terminal of the third controllable switch is connected to the gate of the second NMOS transistor, and the control terminal of the third controllable switch is used to receive the control signal. The drain of the second NMOS transistor is connected to the first current mirror circuit, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the first current generation branch.

[0011] In one optional embodiment, the second current generating branch further includes: a branch control switch, wherein, The branch control switch is connected between the second NMOS transistor and the first current mirror circuit, and the control terminal of the branch control switch is used to receive an enable signal or a de-enable signal. In response to the enable signal, the branch control switch is turned on; In response to the de-enable signal, the branch control switch is turned off.

[0012] In one optional implementation, the first current mirror circuit includes: a main power transistor and a first mirror branch, wherein, The main power transistor is connected to the reference current generation circuit, and the gate and drain of the main power transistor are shorted. In response to the reference negative temperature coefficient current, the main power transistor generates a drive voltage; The first mirror branch is connected to the gate of the main power transistor to form a current mirror with the main power transistor; In response to the driving voltage, the first mirror branch generates a negative temperature coefficient current according to a preset mirror ratio.

[0013] In one optional implementation, the first current mirror circuit further includes: at least one second mirror branch, wherein, Each of the second mirror branches is connected to the gate of the main power transistor to form a corresponding current mirror; In response to the driving voltage, any of the second mirror branches generates a negative temperature coefficient current according to its corresponding preset mirror ratio; The output terminal of the first mirror branch is connected to the output terminal of each of the second mirror branches, and the sum of the negative temperature coefficient currents output by the first mirror branch and each of the second mirror branches is taken as the target negative temperature coefficient current.

[0014] In one optional implementation, the first mirror branch and each of the second mirror branches are respectively provided with a branch control switch, which is turned on in response to an enable signal, or turned off in response to a de-enable signal.

[0015] In one optional embodiment, the positive temperature coefficient current generating circuit includes a second current mirror circuit, wherein, The second current mirror circuit includes a third mirror branch, wherein, The third mirror branch receives the bias voltage of the voltage-mode bandgap reference circuit and forms a current mirror with the voltage-mode bandgap reference circuit. In response to the bias voltage, the third mirror branch generates a positive temperature coefficient current according to a preset mirror ratio.

[0016] In one optional implementation, the second current mirror circuit further includes: at least one fourth mirror branch, wherein, Each of the fourth mirror branches is connected to the voltage-mode bandgap reference circuit to form a corresponding current mirror; In response to the bias voltage, any of the fourth mirror branches generates a positive temperature coefficient current according to its corresponding preset mirror ratio; The output terminal of the third mirror branch is connected to the output terminal of each of the fourth mirror branches, and the sum of the positive temperature coefficient currents output by the third mirror branch and each of the fourth mirror branches is used as the target positive temperature coefficient current.

[0017] In one optional implementation, the third mirror branch and each of the fourth mirror branches are respectively provided with a branch control switch, which is turned on in response to an enable signal, or turned off in response to a de-enable signal.

[0018] In one optional implementation, the detection circuit includes: a delay module and an operational amplifier, wherein, The input terminal of the delay module is used to receive the reference voltage, and the output terminal of the delay module is connected to the inverting input terminal of the operational amplifier. The delay module is used to output the reference voltage to the operational amplifier after delaying it by a preset time. The non-inverting input of the operational amplifier is used to receive the reference voltage, and the output of the operational amplifier serves as the output of the detection circuit. In response to the reference voltage obtained at the non-inverting input being greater than the reference voltage obtained at the inverting input, the operational amplifier outputs a first control signal characterizing the increase of the reference voltage as the operating temperature increases. In response to the reference voltage obtained at the non-inverting input being less than the reference voltage obtained at the inverting input, the operational amplifier outputs a second control signal to characterize the decrease of the reference voltage as the operating temperature increases.

[0019] Secondly, this application provides an integrated circuit, comprising: a voltage-mode bandgap reference circuit and a current source circuit as described in any embodiment of the first aspect of this application, wherein... The voltage-mode bandgap reference circuit is used to output reference voltage and bias voltage; The current source circuit is connected to the voltage-mode bandgap reference circuit, and outputs a zero-temperature drift current based on the reference voltage and the bias voltage.

[0020] Based on the above, the current source circuit provided in this application is applied to an integrated circuit configured with a voltage-mode bandgap reference circuit. This voltage-mode bandgap reference circuit provides a reference voltage and a bias voltage. The current source circuit provided in this application includes a detection circuit, a negative temperature coefficient current generation circuit, and a positive temperature coefficient current generation circuit. The detection circuit detects the trend of the reference voltage following the operating temperature change of the integrated circuit and generates a control signal based on the detection result. The negative temperature coefficient current generation circuit responds to the control signal and generates a target negative temperature coefficient current based on the reference voltage. The positive temperature coefficient current generation circuit generates a target positive temperature coefficient current based on the bias voltage. The target negative temperature coefficient current and the target positive temperature coefficient current are superimposed to output a zero-temperature-drift current. The current source circuit provided in this application generates a zero-temperature-drift current based on the reference voltage and bias voltage provided by the existing voltage-mode bandgap reference circuit in the integrated circuit. Compared to related technologies that additionally introduce a current-mode bandgap reference circuit, this solution can fully utilize the existing voltage-mode bandgap reference circuit. While meeting the zero-temperature-drift current requirements of some circuits in the integrated circuit, it avoids large-scale modifications to the overall circuit, which helps product development proceed smoothly and ensures that the R&D cycle is not extended. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a structural block diagram of a current source circuit provided in an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of a voltage-mode bandgap reference circuit provided by related technologies.

[0024] Figure 3 This is a schematic diagram of another voltage-mode bandgap reference circuit provided by related technologies.

[0025] Figure 4a It is a graph showing the relationship between reference voltage and operating temperature for a voltage-mode bandgap reference circuit provided by related technologies.

[0026] Figure 4b This is a graph showing the relationship between the reference voltage and operating temperature for a voltage-mode bandgap reference circuit provided by related technologies.

[0027] Figure 5 This is a block diagram of another current source circuit provided in the embodiments of this application.

[0028] Figure 6 This is a circuit topology diagram of a current source circuit provided in an embodiment of this application.

[0029] Figure 7 This is a circuit topology diagram of another current source circuit provided in the embodiments of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the field of integrated circuit design, to provide stable bias or reference signals to the internal functional modules of an integrated circuit, the common approach is to use a bandgap reference circuit to generate a reference voltage or current that is theoretically independent of temperature and power supply voltage. Voltage-mode bandgap reference circuits, due to their mature structure, ease of design, and strong driving capability, are widely used in various analog and mixed-signal integrated circuits as reference voltage and bias sources. Of course, in such systems powered by voltage-mode bandgap reference circuits, some local circuits may sometimes require zero-temperature drift current to achieve higher-precision signal processing or conversion functions.

[0032] To provide a stable current that does not change with temperature to the internal functional modules of an integrated circuit, i.e., a zero-temperature-drift current, the common approach is to introduce a dedicated current-mode bandgap reference circuit. The current-mode bandgap reference circuit utilizes the ratio between the base-emitter voltage difference of a bipolar transistor and the thermal voltage, combined with an operational amplifier and a resistor network, to compensate for and superimpose positive and negative temperature coefficients in the form of current, ultimately outputting a theoretically zero-temperature-drift current.

[0033] Current-mode bandgap reference circuits can meet the application requirements of integrated circuits for zero temperature drift current. However, for integrated circuits that have built-in or must use voltage-mode bandgap reference circuits, the introduction of current-mode reference circuits to obtain the zero temperature drift current required by local circuits will inevitably require extensive modifications or adaptations to the original power supply architecture, and may even lead to extended design iteration cycles and increased reliability risks.

[0034] To address the aforementioned technical issues, this application provides a current source circuit that generates a negative temperature coefficient current (TTC current) that is opposite to the temperature change by detecting and utilizing the trend of the reference voltage output from the voltage-mode bandgap reference circuit as a function of temperature. Simultaneously, a positive temperature coefficient current is generated using the bias voltage provided by the same voltage-mode reference circuit. Finally, the two types of currents are superimposed to generate a zero-temperature drift current without altering the original power supply core architecture of the integrated circuit. This fully utilizes the existing voltage-mode bandgap reference circuit, meeting the zero-temperature drift current requirements of some circuits in the integrated circuit while avoiding large-scale modifications to the overall circuit. This facilitates smooth product development and ensures that the R&D cycle is not extended.

[0035] Based on the above, see Figure 1 This application provides a current source circuit, including: a detection circuit 10, a negative temperature coefficient current generation circuit 20, and a positive temperature coefficient current generation circuit 30.

[0036] Combination Figure 1 As shown, the integrated circuit includes a voltage-mode bandgap reference circuit 40, which has a first output terminal and a second output terminal. The first output terminal provides a reference voltage V1, and the second output terminal provides a bias voltage V2. The reference voltage V1 is theoretically designed to have zero temperature drift, but in actual integrated circuit manufacturing processes and operating temperature ranges, its voltage-temperature characteristic exhibits a parabolic shape, which will be discussed in detail later. The bias voltage V2 is output from the output node or equivalent node of the operational amplifier inside the voltage-mode bandgap reference circuit 40. The current source circuit provided in this embodiment utilizes the bias voltage provided by the voltage-mode bandgap reference circuit 40 to generate a current with a positive temperature coefficient.

[0037] In one alternative implementation, the basic architecture of the voltage-mode bandgap reference circuit 40 can be found in [reference needed]. Figure 2 As shown, it includes operational amplifier A1, bipolar transistors Q1 and Q2, and resistors R1 and R2, wherein the emitter junction area ratio of bipolar transistors Q1 and Q2 is 1:N.

[0038] Combination Figure 2 As shown, the voltage at point X is That is, the base-emitter voltage of bipolar transistor Q1, the voltage at point Y is ,in, This represents the base-emitter voltage of the bipolar transistor Q2. This represents the current flowing through resistor R1. According to the virtual short principle of operational amplifiers, we can obtain... Since R1 and R2 have the same resistance, .

[0039] Based on the above, assuming the ratio of Q1 to Q2 is 1:N, then according to the PN junction voltage calculation formula, we can obtain: V be1 = ; V be2 = ; N; in, , q is Boltzmann's constant, T represents the operating temperature of the integrated circuit, and q is the electron charge. It is the saturation current of a single PN junction.

[0040] From the above derivation, it can be seen that ,because It has a positive temperature coefficient. Assuming that resistor R1 is an ideal resistor with zero temperature coefficient, the current passing through resistor R1 also has a positive temperature coefficient, which is called positive temperature coefficient current.

[0041] In another alternative implementation, the voltage-mode bandgap reference circuit 40 can also be as follows: Figure 3 In the circuit topology shown, the W / L (width-to-length ratio) of PMOS transistors M1, M2, and M3 is 1:1:1, thus satisfying the current... Therefore, the voltage across resistor R1 is ,at the same time, , where V Y express Figure 3 Voltage at point Y, V Q2 The emitter voltage of bipolar transistor Q2 can be obtained from the virtual short and virtual open characteristics of operational amplifier A1 and the voltage and current relationship of the PN junction: ; ; Based on the above formula ,so, The voltage across R2 is Reference voltage , where V be3This represents the base-emitter voltage of the bipolar transistor Q3, because It is a voltage with a negative temperature coefficient. It is a voltage with a positive temperature coefficient. The reference voltage V1 obtained by superimposing the two is theoretically a zero temperature drift voltage, that is, the voltage value remains unchanged or undergoes a very small change with temperature.

[0042] However, in practical applications, due to various process factors, the voltage curve of the reference voltage V1 output by the voltage-mode bandgap reference circuit 40 in related technologies is parabolic, rather than an ideal horizontal straight line. (See also...) Figure 4a As shown, the reference voltage V1 provided by the voltage-mode bandgap reference circuit 40 follows an upward parabola. The reference voltage V1 reaches its maximum value at T0. In other words, before T0, the reference voltage V1 gradually increases with increasing temperature, and after T0, the reference voltage V1 gradually decreases with increasing temperature. Further details can be found in [reference 1]. Figure 4b As shown, the reference voltage V1 provided by the voltage mode bandgap reference circuit 40 is a downward parabola. The reference voltage V1 reaches its minimum value at T0. That is, before T0, the reference voltage V1 gradually decreases with increasing temperature, and after T0, the reference voltage V1 gradually increases with increasing temperature.

[0043] The voltage-mode bandgap reference circuit 40 also provides a bias voltage V2. The specific method by which the voltage-mode bandgap reference circuit 40 provides the bias voltage V2 can be found in conjunction with... Figure 3 The diagram and related technical implementation are shown, but will not be detailed here.

[0044] It should be noted that in practical applications, the voltage-mode bandgap reference circuit 40 can also be implemented in other optional ways. Any implementation that can provide the reference voltage and bias voltage required by the various embodiments of this application is optional. This application does not limit the specific selection of the voltage-mode bandgap reference circuit 40.

[0045] The detection circuit 10 is connected to the first output terminal of the voltage-mode bandgap reference circuit 40. It receives the reference voltage V1 and detects the trend of the reference voltage V1 changing with the operating temperature of the integrated circuit. Based on the detection result, it generates a control signal to indicate whether the reference voltage V1 increases or decreases with the increase of the operating temperature. The optional implementation of the detection circuit 10 will be elaborated in detail in subsequent embodiments and will not be described here.

[0046] The negative temperature coefficient current generating circuit 20 is connected to both the voltage-mode bandgap reference circuit 40 and the detection circuit 10. Specifically, the input terminal of the negative temperature coefficient current generating circuit 20 is connected to the first output terminal of the voltage-mode bandgap reference circuit 40 to receive the reference voltage V1. Simultaneously, the control terminal of the negative temperature coefficient current generating circuit 20 is connected to the output terminal of the detection circuit 10 to receive the control signal output by the detection circuit 10. The negative temperature coefficient current generating circuit 20 is configured to generate a target negative temperature coefficient current I- based on the received reference voltage V1 in response to the control signal provided by the detection circuit 10. That is, when the reference voltage V1 increases with increasing temperature (the control signal indicates an upward trend) or decreases with increasing temperature (the control signal indicates a downward trend), it generates a target negative temperature coefficient current whose amplitude decreases with increasing temperature.

[0047] The positive temperature coefficient current generation circuit 30 is connected to the second output terminal of the voltage-mode bandgap reference circuit 40 and receives the bias voltage V2. The positive temperature coefficient current generation circuit 30 is configured to generate a target positive temperature coefficient current I+ based on the received bias voltage V2. Since the bias voltage V2 itself originates from the positive temperature coefficient current branch inside the voltage-mode bandgap reference circuit 40, the current I+ obtained by mirroring or converting it naturally inherits the positive temperature coefficient characteristics.

[0048] The output terminal of the negative temperature coefficient current generating circuit 20 is connected to the output terminal of the positive temperature coefficient current generating circuit 30. The resulting connection point serves as the output terminal of the current source circuit. This connection structure can superimpose the target negative temperature coefficient current I- and the target positive temperature coefficient current I+. By configuring the amplitude ratio of I- and I+, the increases and decreases of their values ​​with temperature changes are mutually canceled out, thereby outputting the final zero-temperature-drift current I0 at the output terminal of the current source circuit. For example, if the temperature coefficient of I- is approximately -1000 ppm / ℃ and the temperature coefficient of I+ is approximately +1000 ppm / ℃, and both are designed to have a current value of 10μA at room temperature, then the superimposed I0 will ideally have a temperature coefficient close to 0 ppm / ℃, i.e., zero temperature drift.

[0049] In summary, the current source circuit provided in this application generates zero-temperature drift current based on the reference voltage and bias voltage provided by the existing voltage-mode bandgap reference circuit in the integrated circuit. Compared with the related technologies that additionally introduce a current-mode bandgap reference circuit, this solution can make full use of the existing voltage-mode bandgap reference circuit. While meeting the zero-temperature drift current requirements of some circuits in the integrated circuit, it avoids large-scale modifications to the overall circuit, which helps the product development proceed smoothly and ensures that the R&D cycle is not extended.

[0050] This application also provides another current source circuit, see [link to example]. Figure 5As shown, in the current source circuit provided in this application embodiment, the negative temperature coefficient current generation circuit 20 includes a reference current generation circuit 210 and a first current mirror circuit 220.

[0051] Specifically, the reference current generation circuit 210 is connected to the voltage mode bandgap reference circuit 40 and the detection circuit 10 respectively. It receives the reference voltage V1 output by the voltage mode bandgap reference circuit 40 and the control signal C0 output by the detection circuit 10. In response to the control signal C0, the reference current generation circuit 210 generates a reference negative temperature coefficient current based on the reference voltage V1.

[0052] The first current mirror circuit 220 is connected to the reference current generation circuit 210. In response to the reference negative temperature coefficient current provided by the reference current generation circuit 210, the first current mirror circuit 220 outputs the final target negative temperature coefficient current I- according to a preset mirror ratio. This configuration decouples the generation and amplitude scaling functions of the negative temperature coefficient current. The reference current generation circuit 210 focuses on accurately generating a small-amplitude reference current with the correct temperature coefficient direction based on the trend of the reference voltage V1, while the first current mirror circuit 220 is responsible for amplifying or replicating this reference current as needed to obtain the final output target negative temperature coefficient current I-. This improves the modularity and flexibility of the circuit architecture. The reference negative temperature coefficient current can be designed to be very small to save power consumption and area, and through the scaling of the current mirror, target negative temperature coefficient currents of different amplitudes can be flexibly obtained to meet the needs of matching with positive temperature coefficient currents of different sizes.

[0053] As for the operation of the positive temperature coefficient current generation circuit 30 and the final output of zero temperature drift current, please refer to the relevant content of the aforementioned embodiments, which will not be repeated here.

[0054] As mentioned earlier, the reference voltage provided by the voltage-mode bandgap reference circuit exhibits two different trends of change. The control signal output by the detection circuit based on the trend of the reference voltage change should be able to clearly characterize the trend of the reference voltage change, so that the negative temperature coefficient current generation circuit can generate the target negative temperature coefficient current based on the trend of the reference voltage change.

[0055] Based on this, in one optional implementation, the control signal generated by the detection circuit includes: a first control signal characterizing that the reference voltage V1 increases with increasing operating temperature, and a second control signal characterizing that the reference voltage V1 decreases with increasing operating temperature.

[0056] Accordingly, the reference current generation circuit includes a first current generation branch and a second current generation branch. The first current generation branch, activated in response to a first control signal, receives a reference voltage V1 and generates a reference negative temperature coefficient current (i.e., decreasing as the reference voltage V1 increases) based on the reference voltage V1. The second current generation branch, activated in response to a second control signal, receives the reference voltage V1 and generates a reference negative temperature coefficient current (i.e., decreasing as the reference voltage V1 decreases) based on the reference voltage V1. Figure 4a as well as Figure 4b As shown, this configuration provides optimized current generation paths on both sides of the monotonic intervals of the parabola corresponding to the reference voltage V1, enabling the circuit to adaptively select the best conversion path and thus obtain good negative temperature coefficient current throughout the entire temperature range of the reference voltage.

[0057] Based on the above, this application provides an embodiment of the present invention. Figure 5 For a detailed implementation of the current source generation circuit shown in the embodiment, please refer to [link to specific implementation details]. Figure 6 As shown, the detection circuit 10 includes a delay module 110 and an operational amplifier U1, the negative temperature coefficient current generation circuit 20 includes a reference current generation circuit 210 and a first current mirror circuit 220, wherein the reference current generation circuit 210 includes a first current generation branch 2101 and a second current generation branch 2102, and the positive temperature coefficient current generation circuit 30 includes a second current mirror circuit.

[0058] Understandably, in practical applications, the first and second control signals provided by the detection circuit can be output through two independent signal lines, or through two logic levels on a single signal line. For example, a high level could represent the first control signal, and a low level could represent the second control signal. Figure 6 The illustrated embodiment uses two logic levels on a single signal line to represent the aforementioned first control signal and second control signal, respectively. Specifically, the input terminal of the delay module 110 is connected to the first output terminal of the voltage-mode bandgap reference circuit 40 to receive the reference voltage V1. The output terminal of the delay module 110 is connected to the inverting input terminal of the operational amplifier U1, and the non-inverting input terminal of the operational amplifier U1 is also connected to the first output terminal of the voltage-mode bandgap reference circuit 40 to receive the reference voltage V1. The output terminal of the operational amplifier U1 serves as the output terminal of the detection circuit 10, used to output the control signal C0.

[0059] The delay module 110 delays the received reference voltage V1 by a preset time Δt before outputting it to the inverting input of the operational amplifier U1. The non-inverting input of the operational amplifier U1 directly receives the current, undelayed reference voltage V1. It is understood that due to the delay effect of the delay module 110, the reference voltage received at the inverting input of the operational amplifier U1 lags behind the reference voltage received at the non-inverting input of the operational amplifier U1 in time. The specific interval is the aforementioned preset time. Within this preset time, the amplitude of the reference voltage output by the voltage-mode bandgap reference circuit 40 will change, resulting in different amplitudes of the reference voltage received at the non-inverting and inverting inputs of the operational amplifier U1.

[0060] Based on this, if the current reference voltage V1(t) is greater than the voltage V1(t-Δt) at the previous moment, it indicates that the reference voltage V1 is on an upward trend. Therefore, the reference voltage obtained at the non-inverting input of operational amplifier U1 is greater than the reference voltage obtained at the inverting input, and operational amplifier U1 outputs a high level, i.e., the first control signal. Conversely, if the current reference voltage V1(t) is less than the delayed reference voltage V1(t-Δt), it indicates that the reference voltage V1 is on a downward trend. Therefore, the reference voltage obtained at the non-inverting input of operational amplifier U1 is less than the reference voltage obtained at the inverting input, and operational amplifier U1 outputs a low level, i.e., the second control signal. In practical applications, the preset duration Δt of the delay module 110 should be much smaller than the characteristic time constant of temperature change to ensure timely detection of trend changes. Simultaneously, the preset duration Δt should enable operational amplifier U1 to identify the difference between the non-inverting and inverting inputs, thereby outputting the corresponding control signal. Furthermore, the preset duration Δt should be greater than the period of circuit noise and the short-term fluctuations of the reference voltage V itself to avoid false triggering. This application does not specifically limit the value of the aforementioned preset duration.

[0061] The first current generation branch 2101 includes a first controllable switch K1, a first PMOS transistor MP1, a first NMOS transistor MN1, and a second controllable switch K2. Specifically, the input terminal of the first controllable switch K1 is used to receive a reference voltage V1, its control terminal is used to receive a control signal C0 (a first control signal or a second control signal), and its output terminal is connected to the gate of the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is used to receive the operating voltage VDD, and its drain is connected to the drain of the first NMOS transistor MN1. The drain and gate of the first NMOS transistor MN1 are shorted (i.e., connected by a diode), and the source of the first NMOS transistor MN1 is grounded. The input terminal of the second controllable switch K2 is connected to the gate of the first NMOS transistor MN1, and its output terminal serves as the output terminal of the first current generation branch 2101 (connected to the gate of the second NMOS transistor MN2 in the subsequent second current generation branch 2102). The control terminal of the second controllable switch K2 is also used to receive the control signal C0 (a first control signal or a second control signal). The first controllable switch K1 and the second controllable switch K2 are configured to be turned on in response to a first control signal and to be turned off in response to a second control signal.

[0062] Furthermore, the second current generation branch 2102 includes a second NMOS transistor MN2 and a third controllable switch K3, combined with Figure 6 As shown, the input terminal of the third controllable switch K3 is connected to the first output terminal of the voltage-mode bandgap reference circuit 40 to receive the reference voltage V1. The output terminal of the third controllable switch K3 is connected to the gate of the second NMOS transistor MN2. The control terminal of the third controllable switch K3 is used to receive a control signal (either a first control signal or a second control signal). The drain of the second NMOS transistor MN2 is connected to the input node of the first current mirror circuit 220. The source of the second NMOS transistor MN2 is grounded. The gate of the second NMOS transistor MN2 is connected to the output terminal of the first current generation branch 2101. The third controllable switch K3 is configured to turn off in response to the first control signal and turn on in response to the second control signal.

[0063] It should be noted that, as an optional implementation, the first controllable switch K1 and the third controllable switch K3 can be integrated. For example, a single-pole double-throw switch can be used instead of the first controllable switch K1 and the third controllable switch K3. The input terminal of this single-pole double-throw switch is connected to the first output terminal of the voltage-mode bandgap reference circuit 40. The first output terminal is connected to the gate of the first PMOS transistor MP1, and the second output terminal is connected to the gate of the second NMOS transistor MN2. In response to the first control signal, the single-pole double-throw switch connects the input terminal and the first output terminal. In response to the second control signal, the single-pole double-throw switch connects the input terminal and the second output terminal. With this configuration, it is possible to achieve... Figure 6 The functions that can be achieved by the first controllable switch K1 and the third controllable switch K3 in the embodiment shown are.

[0064] It should also be noted that the specific implementation of the first controllable switch K1, the second controllable switch K2, and the third controllable switch K3 involved in this embodiment can all be implemented with reference to relevant technologies, and will not be described in detail here.

[0065] The first current mirror circuit 220 includes a main power transistor P0 and a first mirror branch, wherein the first mirror branch includes a PMOS transistor PM, combined with Figure 6 As shown, the source of the main power transistor P0 is used to receive the operating voltage VDD. The gate and drain of the main power transistor P0 are shorted together, and the drain of the main power transistor P0 is connected to the output terminal of the reference current generation circuit 210. The source of the PMOS transistor PM is used to receive the operating voltage VDD. The drain of the PMOS transistor PM serves as the output terminal of the negative temperature coefficient current generation circuit 20. The gate of the PMOS transistor PM is connected to the gate of the main power transistor P0, thus forming a current mirror with the main power transistor P0.

[0066] The positive temperature coefficient current generation circuit 30 includes a second current mirror circuit, in Figure 6 In the illustrated embodiment, the second current mirror circuit further includes a third mirror branch. Specifically, the third mirror branch is implemented based on a PMOS transistor PG, combined with... Figure 6 As shown, the source of PMOS transistor PG serves as the power supply terminal of the third mirror branch, receiving the operating voltage VDD. The drain of PMOS transistor PG serves as the output terminal of the positive temperature coefficient current generation circuit 30. The gate of PMOS transistor PG is connected to the second output terminal of the voltage-mode bandgap reference circuit 40, receiving the bias voltage V2. More importantly, when the gate of PMOS transistor PG is connected to the voltage-mode bandgap reference circuit 40, it can form a current mirror with the internal circuit of the voltage-mode bandgap reference circuit 40, realizing the current mirror function of the current mirror. As for the current mirror formed by PMOS transistor PG and the internal circuit of the voltage-mode bandgap reference circuit 40, it can be specifically combined with... Figure 2 The diagram and related technical implementation are shown, but will not be detailed here.

[0067] The following is combined Figure 4a The reference voltage variation curve shown is for Figure 6 The working process of the current source circuit provided in the illustrated embodiment is described in detail below: Before the integrated circuit reaches its operating temperature T0, the reference voltage V1 is on an upward trend.

[0068] Based on the aforementioned detection process, the detection circuit 10 outputs a first control signal.

[0069] The first controllable switch K1 and the second controllable switch K2 are turned on, and the third controllable switch K3 is turned off.

[0070] When the first current generation branch 2101 is powered on, a reference voltage V1 is applied to the gate of the first PMOS transistor MP1, generating current that flows through the first PMOS transistor MP1 and the first NMOS transistor MN1. Furthermore, when the second controllable switch K2 is turned on, the first NMOS transistor MN1 and the second NMOS transistor MN2 in the second current generation branch 2102 form a current mirror, thereby replicating the current image generated by the first current generation branch 2101 to the second NMOS transistor MN2, outputting a reference negative temperature coefficient current.

[0071] In the first current mirror circuit 220, the main power transistor, namely PMOS transistor P0, is connected in series with the second NMOS transistor MN2. When the second NMOS transistor MN2 is turned on, PMOS transistor P0 is also turned on, and the current flowing through them is equal. PMOS transistor P0 generates a drive voltage V0 in response to the aforementioned reference negative temperature coefficient current. Since PMOS transistor P0 and the first mirror branch, namely PMOS transistor PM, constitute a current mirror, PMOS transistor PM generates a negative temperature coefficient current according to a preset mirror ratio in response to the drive voltage V0.

[0072] Understandably, with the reference voltage V1 trending upwards, as the operating temperature of the integrated circuit increases, the reference voltage V1 applied to the gate of the first PMOS transistor MP1 becomes increasingly higher. Assuming the operating voltage VDD remains constant, the voltage between the gate and source of the first PMOS transistor MP1 will decrease. Since the current generated by the PMOS transistor is positively correlated with the gate-source voltage, the decrease in the voltage between the gate and source of the first PMOS transistor MP1 leads to a decrease in the current flowing through it, resulting in a negative temperature coefficient current that moves in the opposite direction to the operating temperature change. Furthermore, using a current mirror composed of the first NMOS transistor MN1 and the second NMOS transistor MN2, the negative temperature coefficient current generated by the first PMOS transistor MP1 is mirrored and replicated according to a preset mirror ratio. This mirrored current is then output as a reference negative temperature coefficient current to the first current mirror circuit 220, which mirrors and replicates it according to the preset mirror ratio, ultimately outputting the target negative temperature coefficient current I-.

[0073] After the operating temperature of the integrated circuit reaches T0 (greater than T0), the reference voltage V1 is on a downward trend.

[0074] Based on the aforementioned detection process, the detection circuit 10 outputs a second control signal.

[0075] The first controllable switch K1 and the second controllable switch K2 are turned off, and the third controllable switch K3 is turned on.

[0076] The first current generation branch 2101 is powered down and stops working. The third controllable switch K3 is turned on, and the reference voltage V1 provided by the voltage-mode bandgap reference circuit 40 is directly applied to the gate of the second NMOS transistor MN2. The second NMOS transistor MN2 directly generates current as a common-source amplifier. When the reference voltage V1 is decreasing, as the operating temperature of the integrated circuit increases, the reference voltage V1 applied to the gate of the second NMOS transistor MN2 becomes lower and lower. The voltage between the gate and source of the second NMOS transistor MN2 will become smaller and smaller. Since the current generated by the NMOS transistor is positively correlated with the gate-source voltage, the voltage between the gate and source of the second NMOS transistor MN2 decreases, and the current flowing through the second NMOS transistor MN2 also decreases. This results in a reference negative temperature coefficient current that is opposite to the trend of operating temperature change.

[0077] In the first current mirror circuit 220, the main power transistor, namely PMOS transistor P0, is connected in series with the second NMOS transistor MN2. When the second NMOS transistor MN2 is turned on, PMOS transistor P0 is also turned on, and the current flowing through them is equal. PMOS transistor P0 generates a drive voltage V0 in response to the aforementioned reference negative temperature coefficient current. Since PMOS transistor P0 and the first mirror branch, namely PMOS transistor PM, constitute a current mirror, PMOS transistor PM responds to the drive voltage V0 and mirrors the current according to a preset mirror ratio, ultimately outputting the target negative temperature coefficient current I-.

[0078] Based on the above, it can be seen that the current source circuit provided in this embodiment can selectively connect the first current generation branch 2101 and the second current generation branch 2102 by controlling the conduction state of the second controllable switch K2. When the first current generation branch 2101 is connected to the second current generation branch 2102, the negative temperature coefficient current generated by it is transmitted to the subsequent first current mirror circuit 220 through the second current generation branch 2102. When the first current generation branch 2101 and the second current generation branch 2102 are disconnected, the negative temperature coefficient current is output by the second current generation branch 2102. It can be seen that no matter which branch is working, the current flowing to the first current mirror circuit 220 is ultimately through the same output transistor, which can simplify the circuit connection, save area overhead, and potentially reduce parasitic parameters. This is especially important for large-scale integration and high-frequency applications.

[0079] This application embodiment also provides another current source circuit. Based on the aforementioned embodiment, the second current generation branch of the reference current generation circuit in the negative temperature coefficient current generation circuit further includes a branch control switch. This branch control switch is connected between the second NMOS transistor and the first current mirror circuit. The control terminal of the branch control switch is used to receive an enable signal or a de-enable signal. When an enable signal is received, the branch control switch is turned on, so that the second current branch is in a conducting state and can operate normally. When a de-enable signal is received, the branch control switch is turned off, and the second current branch is prohibited from operating. By setting an independent branch control switch, the negative temperature coefficient compensation function can be independently turned on or off without changing the trend detection results provided by the detection circuit, thereby improving the flexibility of the system.

[0080] Furthermore, the first current mirror circuit in the negative temperature coefficient current generation circuit also includes at least one second mirror branch. Each second mirror branch is connected to the gate of the main power transistor to form a corresponding current mirror. In practical applications, any second mirror branch generates a negative temperature coefficient current according to its own preset mirror ratio in response to the driving voltage of the main power transistor. The output terminal of the first mirror branch is connected to the output terminal of each second mirror branch. The negative temperature coefficient currents output by the first mirror branch and each second mirror branch are superimposed, and the sum is the target negative temperature coefficient current. As an optional implementation, the first mirror branch and each second mirror branch in the negative temperature coefficient current generation circuit are also respectively provided with branch control switches. Any branch control switch is turned on in response to an enable signal or turned off in response to a de-enable signal. The operating state of each mirror branch can be independently controlled through the branch control switches. Mirror branches that do not need to work can be directly turned off, which helps to reduce the operating power consumption of the integrated circuit and improve the flexibility of system control.

[0081] The second current mirror circuit in the positive temperature coefficient current generation circuit, in addition to configuring the third mirror branch, also includes at least one fourth mirror branch. Each fourth mirror branch is connected to a voltage-mode bandgap reference circuit to form a corresponding current mirror. Furthermore, each fourth mirror branch, in response to the bias voltage provided by the voltage-mode bandgap reference circuit, can generate a positive temperature coefficient current according to its corresponding preset mirror ratio. The output terminal of the third mirror branch is connected to the output terminals of each fourth mirror branch, and the positive temperature coefficient currents output by the third mirror branch and each fourth mirror branch are superimposed, resulting in the target positive temperature coefficient current. Referring to the aforementioned configuration of the negative temperature coefficient current generation circuit, the third mirror branch and each fourth mirror branch in the positive temperature coefficient current generation circuit can also be equipped with branch control switches. The branch control switches are turned on in response to an enable signal or turned off in response to a de-enable signal, thereby controlling the conduction state of their respective mirror branches.

[0082] For example, the specific circuit topology of the current source circuit provided in this embodiment can be found in [reference needed]. Figure 7 As shown.

[0083] The first current mirror circuit 220 includes a main power transistor (i.e., a PMOS transistor P0), a first mirror branch SMM, and n second mirror branches, represented in the figure as SMG0, SMG1, ..., SMGn. Combined with... Figure 7 As shown, the gates of the PMOS transistor PM in the first mirror branch SMM and the PMOS transistors (PM0-PMn) in each of the second mirror branches are connected to the gates of the main power transistors to form corresponding current mirrors. The sources of the PMOS transistors PM0-PMn and PM are used to receive the operating voltage VDD. The first mirror branch SMM and each of the second mirror branches are also equipped with branch control switches. Among them, PMOS transistor SM serves as the branch control switch of the first mirror branch SMM, with its source connected to the drain of PMOS transistor PM. The drain of PMOS transistor SM serves as the output terminal of the first current mirror circuit 220, and the gate of PMOS transistor SM serves as the enable terminal of the branch control switch, used to receive the enable signal EN. Of course, it is also used to receive the de-enable signal (not shown in the figure). Correspondingly, PMOS transistor SM0 serves as the branch control switch of the second mirror branch SMG0, with its source connected to the drain of PMOS transistor PM0. The drain of PMOS transistor SM0 serves as the output terminal of the first current mirror circuit 220, and the gate of PMOS transistor SM0 serves as the enable terminal of the branch control switch, used to receive the enable signal S0. Of course, it is also used to receive the de-enable signal (not shown in the figure). The structure and connection method of the other second mirror branches can be referred to the second mirror branch SMG0, and will not be described in detail here.

[0084] Combination Figure 7 As shown, any second mirror branch in the first current mirror circuit 220, responding to the same driving voltage V0, generates a corresponding negative temperature coefficient current according to its own preset mirror ratio (determined by the width-to-length ratio of its transistor). The output terminal of the first mirror branch SMM is connected to the output terminal of each second mirror branch. The currents output by all mirror branches are superimposed, and the result is the target negative temperature coefficient current I-. In practical applications, any second mirror branch can be turned on or off by sending an enable signal or a de-enable signal, thereby controlling the number of mirror branches and the specific current mirror ratio of the actual output negative temperature coefficient circuit. By connecting multiple mirror branches with different mirror ratios in parallel and controlling their on / off states, digital step adjustment of the target negative temperature coefficient current can be achieved.

[0085] In one optional implementation, the aspect ratio of transistors (PM0-PMn) in each second mirror branch and transistor PM in the first mirror branch can be designed with binary weights (e.g., 1:2:4:8…), or customized according to specific process corner compensation requirements, so that each mirror branch can mirror the reference negative temperature coefficient current according to its corresponding preset mirror ratio. By configuring these enable signals, the effective branch combination participating in the current mirroring can be changed, thereby finely adjusting the amplitude of the target negative temperature coefficient current I- digitally over a wide range, so that the current source circuit can adapt to the possible changes in the positive temperature coefficient current under different process corners, and ensure that zero temperature drift output is always obtained after the two are superimposed. In addition, the branch control switch is not limited to a single MOS transistor switch; a transmission gate can also be used to improve linearity. As long as it does not exceed the core idea of ​​this application, it also falls within the protection scope of this application.

[0086] Correspondingly, the positive temperature coefficient current generation circuit 30 can also adopt a similar programmable mirror structure to achieve matched adjustment of the amplitude of the target positive temperature coefficient current I+. Combined with Figure 7 As shown, the third mirror branch SPP includes a PMOS transistor PG, which is used to form a current mirror with the internal components in the voltage-mode bandgap reference circuit 40. The branch control switch selects the PMOS transistor SG. The specific connection method can be referred to the aforementioned content and Figure 7 As shown, details will not be elaborated here. The third mirror branch SPP receives the bias voltage V2 from the voltage-mode bandgap reference circuit 40. In response to the bias voltage V2, the third mirror branch SPP generates a portion of the positive temperature coefficient current according to a preset mirror ratio. To adjust the target positive temperature coefficient current I+, the second current mirror circuit also includes at least n fourth mirror branches, i.e., SPG0-SPGn. Combined with... Figure 7 As shown, each fourth mirror branch includes a PMOS transistor (PG0-PGn) for forming a current mirror and a PMOS transistor (SG0-SGn) for controlling the conduction state of its respective fourth mirror branch. PMOS transistors PG0-PGn are connected to the voltage-mode bandgap reference circuit 40 to form corresponding current mirrors. Each fourth mirror branch generates a portion of the positive temperature coefficient current according to its preset mirror ratio in response to the bias voltage V2. The output terminal of the third mirror branch SPP is connected to the output terminals of each fourth mirror branch. The sum of the positive temperature coefficient currents output by all branches is the target positive temperature coefficient current I+. Similarly, the third mirror branch SPP and each fourth mirror branch are equipped with branch control switches (SG0-SGn). These branch control switches are turned on in response to an enable signal (S1-Sn) or turned off in response to a de-enable signal (not shown in the figure), thereby realizing the digital programming of the target positive temperature coefficient current I+.

[0087] The sum of the target positive temperature coefficient current I+ and the target negative temperature coefficient current I- is the zero-temperature drift current I0. By independently controlling the mirrored branch arrays of the negative temperature coefficient current I- and the positive temperature coefficient current I+, the temperature drift of the superimposed total current I0 can be minimized very precisely across all process corners and temperature ranges of the integrated circuit. In practical applications, the enable signals (including de-enable signals) of the control switches of the above-mentioned branches can come from the fixed configuration after the integrated circuit is powered on (such as fuses, antifuses, EEPROM), or from the registers dynamically configured by the digital control core during runtime. This application does not limit the specific source of the enable and de-enable signals.

[0088] Furthermore, to more flexibly control whether the second current generating branch 2102 participates in operation, the second current generating branch 2102 may also include a branch control switch. Figure 7 In the illustrated embodiment, a PMOS transistor MP0 is used. Specifically, the branch control switch is connected between the drain of the second NMOS transistor MN2 and the first current mirror circuit 220. The control terminal of the branch control switch is used to receive an independent enable signal EN or de-enable signal (not shown in the figure). In response to the enable signal EN, the branch control switch is turned on, allowing current to flow; correspondingly, in response to the de-enable signal, the branch control switch is turned off, completely shutting down the negative temperature coefficient current generation path.

[0089] As for Figure 7 The specific configuration and operation of the remaining circuits in the illustrated embodiments can be referred to the relevant content of the foregoing embodiments, and will not be repeated here.

[0090] Generally, after an integrated circuit is powered on, it typically operates under a pre-configured typical process corner. In other words, the integrated circuit operates according to the typical process corner for most of the time. Based on this, by configuring the first current mirror circuit 220 and the second current mirror circuit in the positive temperature coefficient current generation circuit 30, the mirrored current output through the first mirror branch SMM and the third mirror branch SPP can meet the operating requirements of the typical process corner. Correspondingly, when it is necessary to operate in other process corners besides the typical process corner, the branch control switches in different mirror branches can be controlled to conduct, and the zero-temperature drift current that meets the requirements of other process corners can be output, as described above. Based on this, Figure 7 The difference between the enable signal EN and the enable signals S0-Sn is that the enable signal EN is sent to the relevant branch control switch when the integrated circuit is powered on to maintain the basic operation of the current source circuit and can provide zero temperature drift current to the subsequent circuit under typical process corners. As for the enable signals S0-Sn, they need to be flexibly adjusted according to specific operating requirements and actual process corner parameters.

[0091] It is understood that in the current source circuit provided in the aforementioned embodiment, the first current generation branch 2101 can be selectively connected to the second current generation branch 2102. When the two are connected, the current generated by the first current generation branch 2101 is transmitted to the subsequent circuit through the second current generation branch 2102. When the two are disconnected, the current generated by the second current generation branch 2102 is transmitted to the subsequent circuit. It can be seen that the first current generation branch 2101 and the second current generation branch 2102 share some transistors. This arrangement can reduce the overall area overhead of the current source circuit and simplify the circuit structure.

[0092] It should be noted that the operating voltage VDD mentioned in any of the foregoing embodiments can be provided by the power supply network of the integrated circuit. This application does not limit the specific source or value of the operating voltage VDD.

[0093] This application also provides an integrated circuit, including a voltage-mode bandgap reference circuit and a current source circuit as provided in any of the preceding embodiments. The voltage-mode bandgap reference circuit is used to output a reference voltage and a bias voltage. The current source circuit is connected to the voltage-mode bandgap reference circuit and, based on the received reference voltage and bias voltage, ultimately outputs a zero-temperature-drift current.

[0094] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0095] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0096] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0097] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0098] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0099] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0100] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0101] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A current source circuit, characterized in that, An integrated circuit configured with a voltage-mode bandgap reference circuit, the voltage-mode bandgap reference circuit being used to provide a reference voltage and a bias voltage, the current source circuit comprising: The detection circuit is connected to the voltage-mode bandgap reference circuit to detect the trend of the reference voltage changing with the operating temperature of the integrated circuit, and generates a control signal based on the detection result. The negative temperature coefficient current generation circuit is connected to the voltage mode bandgap reference circuit and the detection circuit respectively, and generates a target negative temperature coefficient current based on the reference voltage in response to the control signal. A positive temperature coefficient current generation circuit is connected to the voltage-mode bandgap reference circuit and generates a target positive temperature coefficient current based on the bias voltage. The output terminal of the negative temperature coefficient current generating circuit is connected to the output terminal of the positive temperature coefficient current generating circuit, and the target negative temperature coefficient current and the target positive temperature coefficient current are superimposed to output a zero temperature drift current.

2. The current source circuit according to claim 1, characterized in that, The negative temperature coefficient current generating circuit includes: A reference current generation circuit is connected to the voltage-mode bandgap reference circuit and the detection circuit respectively, and generates a reference negative temperature coefficient current based on the reference voltage in response to the control signal. The first current mirror circuit is connected to the reference current generation circuit and, in response to the reference negative temperature coefficient current, outputs the target negative temperature coefficient current according to a preset mirror ratio.

3. The current source circuit according to claim 2, characterized in that, The control signal includes: a first control signal characterizing that the reference voltage increases as the operating temperature increases, and a second control signal characterizing that the reference voltage decreases as the operating temperature increases; The reference current generation circuit includes: The first current generation branch, in response to the first control signal, receives the reference voltage and generates a reference negative temperature coefficient current that decreases as the reference voltage increases based on the reference voltage. The second current generation branch, in response to the second control signal, receives the reference voltage and generates a reference negative temperature coefficient current that decreases as the reference voltage decreases.

4. The current source circuit according to claim 3, characterized in that, The first current generating branch can be selectively connected to the second current generating branch; When the first current generating branch is connected to the second current generating branch, the reference negative temperature coefficient current, which decreases as the operating temperature increases, is transmitted through the second current generating branch.

5. The current source circuit according to claim 4, characterized in that, The first current generation branch includes: a first controllable switch, a first PMOS transistor, a first NMOS transistor, and a second controllable switch, wherein, The input terminal of the first controllable switch is used to receive the reference voltage, the control terminal of the first controllable switch is used to receive the control signal, and the output terminal of the first controllable switch is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is used to receive the operating voltage, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain and gate of the first NMOS transistor are shorted, and the source of the first NMOS transistor is grounded; The input terminal of the second controllable switch is connected to the gate of the first NMOS transistor, the output terminal of the second controllable switch serves as the output terminal of the first current generation branch, and the control terminal of the second controllable switch is used to receive the control signal. The first controllable switch and the second controllable switch are turned on in response to the first control signal; The first controllable switch and the second controllable switch are turned off in response to the second control signal.

6. The current source circuit according to claim 4, characterized in that, The second current generation branch includes: a second NMOS transistor and a third controllable switch, wherein, The input terminal of the third controllable switch is used to receive the reference voltage, the output terminal of the third controllable switch is connected to the gate of the second NMOS transistor, and the control terminal of the third controllable switch is used to receive the control signal. The drain of the second NMOS transistor is connected to the first current mirror circuit, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the first current generation branch.

7. The current source circuit according to claim 6, characterized in that, The second current generating branch further includes: a branch control switch, wherein, The branch control switch is connected between the second NMOS transistor and the first current mirror circuit, and the control terminal of the branch control switch is used to receive an enable signal or a de-enable signal. In response to the enable signal, the branch control switch is turned on; In response to the de-enable signal, the branch control switch is turned off.

8. The current source circuit according to claim 2, characterized in that, The first current mirror circuit includes: a main power transistor and a first mirror branch, wherein, The main power transistor is connected to the reference current generation circuit, and the gate and drain of the main power transistor are shorted. In response to the reference negative temperature coefficient current, the main power transistor generates a drive voltage; The first mirror branch is connected to the gate of the main power transistor to form a current mirror with the main power transistor; In response to the driving voltage, the first mirror branch generates a negative temperature coefficient current according to a preset mirror ratio.

9. The current source circuit according to claim 8, characterized in that, The first current mirror circuit further includes: at least one second mirror branch, wherein, Each of the second mirror branches is connected to the gate of the main power transistor to form a corresponding current mirror; In response to the driving voltage, any of the second mirror branches generates a negative temperature coefficient current according to its corresponding preset mirror ratio; The output terminal of the first mirror branch is connected to the output terminal of each of the second mirror branches, and the sum of the negative temperature coefficient currents output by the first mirror branch and each of the second mirror branches is taken as the target negative temperature coefficient current.

10. The current source circuit according to claim 9, characterized in that, The first mirror branch and each of the second mirror branches are respectively provided with a branch control switch, which is turned on in response to an enable signal, or turned off in response to a de-enable signal.

11. The current source circuit according to claim 1, characterized in that, The positive temperature coefficient current generating circuit includes a second current mirror circuit, wherein... The second current mirror circuit includes a third mirror branch, wherein, The third mirror branch receives the bias voltage of the voltage-mode bandgap reference circuit and forms a current mirror with the voltage-mode bandgap reference circuit. In response to the bias voltage, the third mirror branch generates a positive temperature coefficient current according to a preset mirror ratio.

12. The current source circuit according to claim 11, characterized in that, The second current mirror circuit further includes: at least one fourth mirror branch, wherein, Each of the fourth mirror branches is connected to the voltage-mode bandgap reference circuit to form a corresponding current mirror; In response to the bias voltage, any of the fourth mirror branches generates a positive temperature coefficient current according to its corresponding preset mirror ratio; The output terminal of the third mirror branch is connected to the output terminal of each of the fourth mirror branches, and the sum of the positive temperature coefficient currents output by the third mirror branch and each of the fourth mirror branches is used as the target positive temperature coefficient current.

13. The current source circuit according to claim 12, characterized in that, Each of the third mirror branch and each of the fourth mirror branches is provided with a branch control switch, which is turned on in response to an enable signal, or turned off in response to a de-enable signal.

14. The current source circuit according to any one of claims 1 to 13, characterized in that, The detection circuit includes: a delay module and an operational amplifier, wherein, The input terminal of the delay module is used to receive the reference voltage, and the output terminal of the delay module is connected to the inverting input terminal of the operational amplifier. The delay module is used to output the reference voltage to the operational amplifier after delaying it by a preset time. The non-inverting input of the operational amplifier is used to receive the reference voltage, and the output of the operational amplifier serves as the output of the detection circuit. In response to the reference voltage obtained at the non-inverting input being greater than the reference voltage obtained at the inverting input, the operational amplifier outputs a first control signal characterizing the increase of the reference voltage as the operating temperature increases. In response to the reference voltage obtained at the non-inverting input being less than the reference voltage obtained at the inverting input, the operational amplifier outputs a second control signal to characterize the decrease of the reference voltage as the operating temperature increases.

15. An integrated circuit, characterized in that, include: The voltage-mode bandgap reference circuit and the current source circuit as described in any one of claims 1 to 14, wherein, The voltage-mode bandgap reference circuit is used to output reference voltage and bias voltage; The current source circuit is connected to the voltage-mode bandgap reference circuit, and outputs a zero-temperature drift current based on the reference voltage and the bias voltage.

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