A low temperature drift reference current source circuit based on mos resistors

Abstract

The application relates to a low-temperature drift reference current source circuit based on a MOS resistor. The circuit comprises a starting circuit, a PTAT current generation circuit, a MOS resistor gate voltage generation circuit and a reference current generation circuit. The PTAT current generation circuit generates a positive temperature coefficient voltage through a triode cross-coupling module and superimposes the voltage on a resistor to generate a PTAT current. The MOS resistor gate voltage generation circuit is used for injecting the PTAT current and the reference current into a resistor string to generate a superimposed compensation voltage, superimposing the compensation voltage and the gate-source voltage of an NMOS tube to control the gate voltage of the MOS resistor working in a deep linear region, so as to realize the MOS resistor with a positive temperature coefficient. The reference current generation circuit generates a positive temperature coefficient voltage through a triode cross-coupling module two and superimposes the voltage on the MOS resistor with the positive temperature coefficient to generate a zero temperature coefficient reference current. The application realizes compensation of the absolute temperature negative first-order term and the negative second-order term of the electron mobility, and obtains the reference current with a lower temperature coefficient.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a low-temperature drift reference current source circuit based on a MOS resistor. Background Technology

[0002] Reference current sources are widely used in operational amplifiers, A / D converters, D / A converters, oscillators, and other applications to provide a reference current for other modules in analog circuits. Since the accuracy of the current source directly affects the temperature and stability of the entire system, a high-performance reference current source is essential for improving overall circuit performance. Therefore, researching high-precision reference current sources is of great significance in meeting the demands of high-performance analog circuits.

[0003] In analog circuit design, the circuit structure and temperature compensation of a reference current source mainly include: (1) Voltage-controlled reference current source; such as Figure 1 As shown, a reference current is generated by applying a voltage with zero temperature coefficient across a resistor. This includes a reference voltage with zero temperature coefficient. The negative feedback circuit formed by the operational amplifier. Zero-temperature coefficient reference voltage. It can be generated through a bandgap voltage reference circuit. The negative feedback circuit includes operational amplifier GM1, NMOS transistor N11, resistors R11 and R12, and a current mirror, used to generate a stable zero-temperature coefficient reference voltage. A reference current is obtained by applying it across resistors R11 and R12. And the reference current is obtained through a current mirror. It provides power to other modules in the circuit. Based on the negative feedback principle of the op-amp, we can derive: The temperature coefficient of this current reference depends on the temperature coefficient of the bandgap reference and the temperature coefficient of the resistance. The zero-temperature coefficient voltage generated for the bandgap reference, to ensure the reference current To ensure that the resistors' accuracy remains unchanged with temperature, the common practice is to choose a positive temperature coefficient (PTC) resistor for R11 and a negative temperature coefficient (NTC) resistor for R12. However, in standard CMOS integrated circuit manufacturing processes, the accuracy of resistors is very low, with deviations exceeding 20%. In many applications, such deviations are unacceptable, often necessitating the use of trimming (fuse adjustment) to adjust the resistance. .

[0004] (2) Traditional summation-type reference current source; such as Figure 2As shown, its basic principle is to obtain a reference current by weighted summing of currents with a positive temperature coefficient and currents with a negative temperature coefficient. Specifically, it includes operational amplifiers A1 and A2, resistors R21 and R22, transistors Q21 and Q22, and a summing circuit. Operational amplifier A1 clamps the potentials at points A and B, and operational amplifier A2 clamps the potentials at points B and C. The ratio of the emitter areas of transistors Q22 and Q21 is N. The voltage difference across resistor R21 is VBE1, and the voltage difference across resistor R22 is VBE1 - VBE2, thereby obtaining the negative temperature coefficient current I1 and the positive temperature coefficient current I2. Figure 2 The summing circuit produces a current with zero temperature coefficient after weighted summation: .

[0005] In the formula, , Here, k is a constant, q is the Boltzmann constant, and q is the electron charge. This current reference, like the voltage-controlled current reference, has its output current directly affected by the resistance. Manufacturing deviations can introduce significant errors. Furthermore, due to… Due to its nonlinearity, the temperature coefficient of the reference current is too high without higher-order compensation.

[0006] (3) Oguey current source (micro-current source); In 1997, Oguey proposed a resistorless reference current source. This circuit uses a MOSFET operating in the linear region instead of a resistor, and the output current is independent of the MOSFET threshold voltage, offering advantages such as small chip area and small process deviation. The Oguey current source is described below. Figure 3 As shown, the array includes PMOS transistors M1, M2, and M5, and NMOS transistors M3, M4, M6, and M7. PMOS transistors M1, M2, and M5 operate in the saturation region, forming a current mirror structure and creating a 1:1:1 current mirror. Within the dashed box, NMOS transistors M3 and M4 operate in the subthreshold region, NMOS transistor M6 operates in the linear region as a linear resistor, and NMOS transistor M7 operates in the saturation region. Figure 3 The reference current generated by the structure is as follows:

[0007] in, , , , It is a quantity that is only related to the aspect ratio of the device. It is electron mobility, and Cox is the gate oxide capacitance per unit area.

[0008] Known electron mobility :

[0009] The relationship between the reference current and temperature can be derived as follows:

[0010] In the formula, Reference temperature electron mobility at that point Right now All are reference temperatures. The thermal voltage at room temperature, m is a constant between 1.5 and 2, and T is the thermodynamic temperature. Right now Both are thermal voltages at temperature T, so the output current of the Oguey current source exhibits the characteristic of increasing with increasing temperature, which is difficult to meet the requirements of some high-precision applications.

[0011] Given the above situation, the main drawbacks of existing technologies are as follows: Traditional voltage-controlled reference current sources and summation-type current sources require additional operational amplifiers, and the resistance value typically deviates by more than 20% due to process variations, resulting in a large variation in the reference current with process deviations. Furthermore, the Oguey current source approximates the square of temperature T to compensate for the electron mobility μ of the MOSFET, causing the output current to increase with temperature. However, changes in carrier mobility due to process variations still have a certain impact on the output current. Therefore, the aforementioned traditional reference current sources are insufficient to meet the requirements of high-precision applications. Summary of the Invention

[0012] The purpose of this invention is to provide a low-temperature drift reference current source circuit based on MOS resistors. This invention aims to solve the problems of existing reference current sources being directly affected by the temperature coefficient of the resistor and the difficulty in compensating for carrier mobility μ, thereby achieving a high-precision reference current source.

[0013] To address the aforementioned technical problems, this invention provides a low-temperature drift reference current source circuit based on a MOS resistor, comprising: A startup circuit is used to provide a startup signal to the PTAT current generating circuit during power-on and to mirror the positive temperature coefficient PTAT current IP generated by the PTAT current generating circuit. The PTAT current generation circuit generates a positive temperature coefficient voltage through a transistor cross-coupling module and superimposes it on resistor R3 to generate a positive temperature coefficient PTAT current IP. The PTAT current IP is then mirrored onto the startup circuit, the MOS resistor gate voltage generation circuit, and the reference current generation circuit. A MOS resistor gate voltage generation circuit is used to inject the PTAT current IP and the reference current Iref into the resistor string to generate a superimposed compensation voltage Vb. An NMOS transistor N1 operating in the subthreshold region is connected to the end of the resistor string. By superimposing the compensation voltage Vb and the gate-source voltage of the NMOS transistor N1, the gate voltage of the MOS resistor operating in the deep linear region is controlled, thereby realizing a MOS resistor with a positive temperature coefficient. The reference current generation circuit generates a positive temperature coefficient voltage through the transistor cross-coupling module 2 and superimposes it on the MOS resistor with a positive temperature coefficient to generate a reference current Iref with zero temperature coefficient. The reference current Iref is then mirrored onto the MOS resistor gate voltage generation circuit, and the PTAT current IP is mirrored at the same time.

[0014] Preferably, the startup circuit includes: The bias branch includes: a constant voltage PMOS transistor P1, a high voltage PMOS transistor HVP1, and a resistor R1; the source of the constant voltage PMOS transistor P1 is connected to the power supply VDD, the drain is connected to the source of the high voltage PMOS transistor HVP1, and the drain of the high voltage PMOS transistor HVP1 is connected to the resistor R1 connected to ground GND; the gates of the constant voltage PMOS transistor P1 and the high voltage PMOS transistor HVP1 are respectively connected to bias voltages Vb1~Vb2; The startup branch includes: a high-voltage PMOS transistor HVP2; the gate of the high-voltage PMOS transistor HVP2 is connected to the drain of the high-voltage PMOS transistor HVP1, the source of the high-voltage PMOS transistor HVP2 is connected to the power supply VDD, and the drain of the high-voltage PMOS transistor HVP2 outputs a disturbance current Ib as the startup signal.

[0015] Preferably, the PTAT current generating circuit includes: Bias module one is used to mirror the PTAT current IP to the startup circuit, the MOS resistor gate voltage generation circuit and the reference current generation circuit; A transistor cross-coupling module 1 includes: high-voltage NMOS transistors HVN1~HVN2, NPN transistors Q1~Q4, and resistor R3; the drain and gate of the high-voltage NMOS transistors HVN1~HVN2 are connected to the bias module 1; the source of the high-voltage NMOS transistor HVN1 is connected to the collector and base of NPN transistor Q1 and the base of NPN transistor Q2; the emitter of NPN transistor Q1 is connected to the collector of NPN transistor Q3 and the base of NPN transistor Q1; the base of NPN transistor Q3 is connected to the emitter of NPN transistor Q2 and the collector of NPN transistor Q4; the collector of NPN transistor Q2 is connected to the source of the high-voltage NMOS transistor HVN2; the emitter of NPN transistor Q3 is connected to ground (GND) at one end of resistor R3; and the other end of resistor R3 is connected to the emitter of NPN transistor Q4.

[0016] Preferably, the bias module includes: constant voltage PMOS transistors P2~P3, high voltage PMOS transistors HVP3~HVP4, and resistor R2; the source of constant voltage PMOS transistors P2~P3 is connected to power supply VDD, and the gate is connected to the drain of high voltage PMOS transistor HVP4 and one end of resistor R2 to generate a bias voltage Vb1; the drain of constant voltage PMOS transistor P2 is connected to the source of high voltage PMOS transistor HVP3, the drain of constant voltage PMOS transistor P3 is connected to the source of high voltage PMOS transistor HVP4, the gate of high voltage PMOS transistors HVP3~HVP4 is connected to the other end of resistor R2 to generate a bias voltage Vb2; the drain of high voltage PMOS transistor HVP3 is connected to the drain and gate of high voltage NMOS transistor HVN1 and the gate of high voltage NMOS transistor HVN2, and the other end of resistor R2 is connected to the drain of high voltage NMOS transistor HVN2.

[0017] Preferably, the MOS resistor gate voltage generation circuit includes: constant voltage PMOS transistors P4~P5, high voltage PMOS transistors HVP5~HVP6, a resistor string, and a constant voltage NMOS transistor N1; the source of the constant voltage PMOS transistors P4~P5 is connected to the power supply VDD, the gate of the constant voltage PMOS transistor P4 is connected to the bias voltage Vb1, the drain of the constant voltage PMOS transistor P4 is connected to the source of the high voltage PMOS transistor HVP5, the gate of the high voltage PMOS transistor HVP5 is connected to the bias voltage Vb2, the drain of the high voltage PMOS transistor HVP5 is connected to the beginning of the resistor string, the end of the resistor string is connected to the gate and drain of the constant voltage NMOS transistor N1, the source of the constant voltage NMOS transistor N1 is grounded to GND, the drain of the constant voltage PMOS transistor P5 is connected to the source of the high voltage PMOS transistor HVP6, the drain of the high voltage PMOS transistor HVP6 is connected to the series connection point of the resistor string, and the gates of the constant voltage PMOS transistor P5 and the high voltage PMOS transistor HVP6 are connected to the reference current generation circuit.

[0018] Preferably, the resistor string consists of two resistors R4 to R5 connected in series.

[0019] Preferably, the reference current generating circuit includes: Bias module two is used to mirror the reference current Iref onto the MOS resistor gate voltage generation circuit and to mirror the PTAT current IP. The second transistor cross-coupling module includes: a constant-voltage NMOS transistor N2, a high-voltage NMOS transistor HVN3, and NPN transistors Q5~Q8; the gate of the constant-voltage NMOS transistor N2 is connected to the superimposed compensation voltage Vb and the gate-source voltage of the NMOS transistor N1; the source of the constant-voltage NMOS transistor N2 and the emitter of the NPN transistor Q8 are grounded to GND; the drain of the constant-voltage NMOS transistor N2 is connected to the emitter of the NPN transistor Q7 to form a drain voltage Vd; and the base of the NPN transistor Q7 is connected to the NPN transistor... The emitter of Q6 and the collector of NPN transistor Q8 are connected. The base of NPN transistor Q8 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q6. The base of NPN transistor Q5 is connected to the base and collector of NPN transistor Q6, as well as the bias module two. The collector of NPN transistor Q5 is connected to the source of high-voltage NMOS transistor HVN3. The gate of high-voltage NMOS transistor HVN3 is connected to the bias voltage Vb2. The drain of high-voltage NMOS transistor HVN3 is connected to the bias module two.

[0020] Preferably, the second bias module includes: constant voltage PMOS transistors P6~P8, high voltage PMOS transistors HVP7~HVP8, and resistor R6; the source of constant voltage PMOS transistors P6~P8 is connected to power supply VDD, the gate of constant voltage PMOS transistors P6~P7 is connected to the drain of high voltage PMOS transistor HVP7 and one end of resistor R6 to generate bias voltage Vb3, the drain of constant voltage PMOS transistor P6 is connected to the source of high voltage PMOS transistor HVP7, the gate of high voltage PMOS transistor HVP7 is connected to the other end of resistor R6 and the drain of high voltage NMOS transistor HVN3, the gate of constant voltage PMOS transistor P8 is connected to bias voltage Vb1, the drain of constant voltage PMOS transistors P7~P8 is connected to the source of high voltage PMOS transistor HVP8, the gate of high voltage PMOS transistor HVP8 is connected to bias voltage Vb2, and the drain of high voltage PMOS transistor HVP8 is connected to the base and collector of NPN transistor Q6.

[0021] Preferably, the emitter areas of NPN transistors Q1 and Q4 are equal, the emitter areas of NPN transistors Q2 and Q3 are equal, and the emitter areas of NPN transistors Q1 and Q4 are N times the emitter areas of NPN transistors Q2 and Q3. The emitter areas of NPN transistors Q6 and Q7 are equal, and the emitter areas of NPN transistors Q5 and Q8 are equal. Furthermore, the emitter areas of NPN transistors Q6 and Q7 are N times the emitter areas of NPN transistors Q5 and Q8.

[0022] Preferably, the formula for the reference current Iref is:

[0023] in, , The capacitance per unit area of ​​the gate oxide layer. The aspect ratio of the NMOS transistor N2 at ambient voltage; Let R3 be the resistance value. Let be the resistance of the resistor string, k be Boltzmann's constant, and q be the electron charge. Reference temperature electron mobility at that point The coefficients of the polynomial for the second-order fitting of the mobility temperature characteristics are used as constant terms.

[0024] Compared with the prior art, the present invention has the following beneficial effects: This invention relates to a low-temperature drift reference current source. A positive temperature coefficient (PTC) current flowing through a resistor generates a PTC voltage, a zero temperature coefficient (ZTC) current flowing through a resistor generates a ZTC voltage, and this is superimposed with the gate-source voltage of an NMOS transistor operating in the subthreshold region. This biases the gate of the NMOS resistor operating in the deep linear region, giving the NMOS resistor a positive temperature coefficient characteristic with good linearity. A temperature-proportional voltage is then generated through transistor cross-coupling, and this voltage is superimposed on the temperature-proportional MOS resistor to produce a reference current that does not change with temperature. Compared to traditional voltage-controlled and summation-type reference current sources, this invention reduces the impact of resistor manufacturing variations on the current source magnitude because the resistor value is only related to the negative first-order term of the electron mobility μ expansion. Compared to traditional resistorless reference current sources, this invention uses a PTAT current proportional to the absolute temperature and the reference current superimposed through different resistors to generate a bias voltage on the NMOS resistor. This achieves compensation for the negative first and negative second-order terms of the absolute temperature after the second-order approximation of the electron mobility μ, thus obtaining a reference current with a lower temperature coefficient. Attached Figure Description

[0025] Figure 1 A circuit diagram of a conventional voltage-controlled reference current source provided for existing technology.

[0026] Figure 2 Circuit diagram of a conventional summing-type reference current source provided for existing technology.

[0027] Figure 3 Circuit diagram of a conventional Oguey current source provided for existing technology.

[0028] Figure 4 The circuit diagram provided by this invention is a low-temperature drift reference current source circuit based on a MOS resistor. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0030] like Figure 4 As shown, this embodiment of the invention specifically provides a low-temperature drift reference current source circuit based on a MOS resistor, including: A startup circuit is used to provide a startup signal to the PTAT current generating circuit during power-on and to mirror the positive temperature coefficient PTAT current IP generated by the PTAT current generating circuit. The PTAT current generation circuit generates a positive temperature coefficient voltage through a transistor cross-coupling module and superimposes it on resistor R3 to generate a positive temperature coefficient PTAT current IP. The PTAT current IP is then mirrored onto the startup circuit, the MOS resistor gate voltage generation circuit, and the reference current generation circuit. A MOS resistor gate voltage generation circuit is used to inject the PTAT current IP and the reference current Iref into the resistor string to generate a superimposed compensation voltage Vb. An NMOS transistor N1 operating in the subthreshold region is connected to the end of the resistor string. By superimposing the compensation voltage Vb and the gate-source voltage of the NMOS transistor N1, the gate voltage of the MOS resistor operating in the deep linear region is controlled, thereby realizing a MOS resistor with a positive temperature coefficient. The reference current generation circuit generates a positive temperature coefficient voltage through the transistor cross-coupling module 2 and superimposes it on the MOS resistor with a positive temperature coefficient to generate a reference current Iref with zero temperature coefficient. The reference current Iref is then mirrored onto the MOS resistor gate voltage generation circuit, and the PTAT current IP is mirrored at the same time.

[0031] Continue reading Figure 4As shown, the startup circuit includes: The bias branch includes: a constant voltage PMOS transistor P1, a high voltage PMOS transistor HVP1, and a resistor R1; the source of the constant voltage PMOS transistor P1 is connected to the power supply VDD, the drain is connected to the source of the high voltage PMOS transistor HVP1, and the drain of the high voltage PMOS transistor HVP1 is connected to the resistor R1 connected to ground GND; the gates of the constant voltage PMOS transistor P1 and the high voltage PMOS transistor HVP1 are respectively connected to bias voltages Vb1~Vb2; The startup branch includes: a high-voltage PMOS transistor HVP2; the gate of the high-voltage PMOS transistor HVP2 is connected to the drain of the high-voltage PMOS transistor HVP1, the source of the high-voltage PMOS transistor HVP2 is connected to the power supply VDD, and the drain of the high-voltage PMOS transistor HVP2 outputs a disturbance current Ib as the startup signal.

[0032] Continue reading Figure 4 As shown, the PTAT current generating circuit includes: Bias module one is used to mirror the PTAT current IP to the startup circuit, the MOS resistor gate voltage generation circuit and the reference current generation circuit; A transistor cross-coupling module 1 includes: high-voltage NMOS transistors HVN1~HVN2, NPN transistors Q1~Q4, and resistor R3; the drain and gate of the high-voltage NMOS transistors HVN1~HVN2 are connected to the bias module 1; the source of the high-voltage NMOS transistor HVN1 is connected to the collector and base of NPN transistor Q1 and the base of NPN transistor Q2; the emitter of NPN transistor Q1 is connected to the collector of NPN transistor Q3 and the base of NPN transistor Q1; the base of NPN transistor Q3 is connected to the emitter of NPN transistor Q2 and the collector of NPN transistor Q4; the collector of NPN transistor Q2 is connected to the source of the high-voltage NMOS transistor HVN2; the emitter of NPN transistor Q3 is connected to ground (GND) at one end of resistor R3; and the other end of resistor R3 is connected to the emitter of NPN transistor Q4.

[0033] Continue reading Figure 4As shown, the bias module includes: constant voltage PMOS transistors P2~P3, high voltage PMOS transistors HVP3~HVP4, and resistor R2; the source of constant voltage PMOS transistors P2~P3 is connected to power supply VDD, and the gate is connected to the drain of high voltage PMOS transistor HVP4 and one end of resistor R2 to generate a bias voltage Vb1; the drain of constant voltage PMOS transistor P2 is connected to the source of high voltage PMOS transistor HVP3, the drain of constant voltage PMOS transistor P3 is connected to the source of high voltage PMOS transistor HVP4, the gate of high voltage PMOS transistors HVP3~HVP4 is connected to the other end of resistor R2 to generate a bias voltage Vb2; the drain of high voltage PMOS transistor HVP3 is connected to the drain and gate of high voltage NMOS transistor HVN1 and the gate of high voltage NMOS transistor HVN2, and the other end of resistor R2 is connected to the drain of high voltage NMOS transistor HVN2.

[0034] Continue reading Figure 4 As shown, the MOS resistor gate voltage generation circuit includes: constant voltage PMOS transistors P4~P5, high voltage PMOS transistors HVP5~HVP6, a resistor string, and a constant voltage NMOS transistor N1. The sources of the constant voltage PMOS transistors P4~P5 are connected to the power supply VDD, the gate of the constant voltage PMOS transistor P4 is connected to the bias voltage Vb1, the drain of the constant voltage PMOS transistor P4 is connected to the source of the high voltage PMOS transistor HVP5, the gate of the high voltage PMOS transistor HVP5 is connected to the bias voltage Vb2, the drain of the high voltage PMOS transistor HVP5 is connected to the beginning of the resistor string, the end of the resistor string is connected to the gate and drain of the constant voltage NMOS transistor N1, the source of the constant voltage NMOS transistor N1 is grounded to GND, the drain of the constant voltage PMOS transistor P5 is connected to the source of the high voltage PMOS transistor HVP6, the drain of the high voltage PMOS transistor HVP6 is connected to the series connection point of the resistor string, and the gates of the constant voltage PMOS transistor P5 and the high voltage PMOS transistor HVP6 are connected to the reference current generation circuit. The resistor string consists of two resistors R4 and R5 connected in series.

[0035] Continue reading Figure 4 As shown, the reference current generating circuit includes: Bias module two is used to mirror the reference current Iref onto the MOS resistor gate voltage generation circuit and to mirror the PTAT current IP. The second transistor cross-coupling module includes: a constant-voltage NMOS transistor N2, a high-voltage NMOS transistor HVN3, and NPN transistors Q5~Q8; the gate of the constant-voltage NMOS transistor N2 is connected to the superimposed compensation voltage Vb and the gate-source voltage of the NMOS transistor N1; the source of the constant-voltage NMOS transistor N2 and the emitter of the NPN transistor Q8 are grounded to GND; the drain of the constant-voltage NMOS transistor N2 is connected to the emitter of the NPN transistor Q7 to form a drain voltage Vd; and the base of the NPN transistor Q7 is connected to the NPN transistor... The emitter of Q6 and the collector of NPN transistor Q8 are connected. The base of NPN transistor Q8 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q6. The base of NPN transistor Q5 is connected to the base and collector of NPN transistor Q6, as well as the bias module two. The collector of NPN transistor Q5 is connected to the source of high-voltage NMOS transistor HVN3. The gate of high-voltage NMOS transistor HVN3 is connected to the bias voltage Vb2. The drain of high-voltage NMOS transistor HVN3 is connected to the bias module two.

[0036] Continue reading Figure 4 As shown, the bias module two includes: constant voltage PMOS transistors P6~P8, high voltage PMOS transistors HVP7~HVP8, and resistor R6; the source of constant voltage PMOS transistors P6~P8 is connected to power supply VDD, the gate of constant voltage PMOS transistors P6~P7 is connected to the drain of high voltage PMOS transistor HVP7 and one end of resistor R6 to generate bias voltage Vb3, the drain of constant voltage PMOS transistor P6 is connected to the source of high voltage PMOS transistor HVP7, the gate of high voltage PMOS transistor HVP7 is connected to the other end of resistor R6 and the drain of high voltage NMOS transistor HVN3, the gate of constant voltage PMOS transistor P8 is connected to bias voltage Vb1, the drain of constant voltage PMOS transistors P7~P8 is connected to the source of high voltage PMOS transistor HVP8, the gate of high voltage PMOS transistor HVP8 is connected to bias voltage Vb2, and the drain of high voltage PMOS transistor HVP8 is connected to the base and collector of NPN transistor Q6.

[0037] Continue reading Figure 4 As shown, the low-temperature drift reference current source circuit based on MOS resistor of the present invention includes a reference current generation circuit. By generating a reference current through the reference current generation circuit and passing it through a resistor to generate a zero temperature coefficient voltage, and generating a positive temperature coefficient current through the PTAT current generation circuit and passing it through a resistor to generate a positive temperature coefficient voltage, the reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generates a reference current generation circuit generated ...

[0038] As a further description of an embodiment of the present invention, during the power-on process, the gate voltage of the high-voltage PMOS transistor HVP2 in the startup circuit is pulled low through resistor R1. As the power supply voltage VDD rises, the high-voltage PMOS transistor HVP2 turns on, providing a startup signal to the PTAT current generation circuit, which then begins normal operation. Then, the branch containing the constant-voltage PMOS transistor P1 and the high-voltage PMOS transistor HVP1 mirrors the PTAT current IP, pulling the gate voltage of the high-voltage PMOS transistor HVP2 high, turning it off, and shutting down the startup circuit.

[0039] In the PTAT current generation circuit, the MOS resistor gate voltage generation circuit, and the reference current generation circuit, the constant voltage PMOS transistors P2, P3, P4, and P8, the high voltage PMOS transistors HVP3, HVP4, HVP5, and HVP8, and resistor R2 form a self-biased current mirror to mirror the PTAT current IP generated by the PTAT current generation circuit in the branch containing resistor R3. The constant voltage PMOS transistors P5, P6, and P7, the high voltage PMOS transistors HVP6 and HVP7, and resistor R6 form another self-biased current mirror to mirror the reference current generated by the branch containing the constant voltage NMOS transistor N2 in the reference current generation circuit.

[0040] Furthermore, in the PTAT current generation circuit, the high-voltage NMOS transistors HVN1 and HVN2 act as a barrier to block high voltage, protecting the normal-voltage NPN transistors Q1, Q2, Q3, and Q4 from breakdown. The positive temperature coefficient current IP is obtained through the cross-coupled NPN transistors Q1, Q2, Q3, and Q4 and resistor R3.

[0041] The working principle of this PTAT current generation circuit is: when the transistors operate at different current densities, the difference between their base-emitter voltages... The voltage difference is proportional to absolute temperature, and a current is generated across the resistor using this voltage difference. The base-emitter voltage VBE1 of transistor Q1, the base-emitter voltage VBE4 of transistor Q4, and the voltage difference across resistor R3 are equal to the base-emitter voltage VBE2 of transistor Q2 and the base-emitter voltage VBE3 of transistor Q3. Where, the base-emitter voltage... The calculation formula is:

[0042] In the formula, For unit saturation current, , This is the collector current of the transistor.

[0043] Furthermore, the disturbance current introduced by the startup circuit is Ib, and its core bias branch current is IP. Ignoring the influence of the transistor base current, it can be seen that during circuit startup, the collector currents of NPN transistors Q2 and Q4 are equal to IP, and the collector currents of NPN transistors Q1 and Q3 are equal to... Assuming that NPN transistors Q1 and Q4 have equal areas, and NPN transistors Q2 and Q3 have equal areas, and the area of ​​Q1 and Q4 is N times the area of ​​Q2 and Q3, then:

[0044]

[0045]

[0046] Therefore, the positive temperature coefficient current can be obtained. .

[0047] In the reference current generation circuit, the high-voltage NMOS transistor HVN3 acts as a high-voltage shield; the collector currents of NPN transistors Q6 and Q8 are equal to... The collector current of NPN transistors Q5 and Q7 is equal to Iref. Transistors Q6 and Q7 have the same area, while transistors Q5 and Q8 have the same area. The area of ​​transistors Q6 and Q7 is N times the area of ​​transistors Q5 and Q8. The NMOS transistor N2 operates in the linear region under normal voltage and is used as a MOS resistor. Following the same PTAT current generation principle, the drain voltage of MOS resistor N2 can be obtained. The voltage is proportional to the thermodynamic temperature T.

[0048] The NMOS transistor N2 operating in the linear region is equivalent to a resistor, and its equivalent resistance is given by the following formula:

[0049] in It represents electron mobility, Cox is the gate oxide capacitance per unit area, and W / L is the width-to-length ratio of N2 in the NMOS transistor. It is the gate-source voltage of NMOS transistor N2. This is the threshold voltage of NMOS transistor N2.

[0050] In the above formula, mobility and threshold voltage Temperature changes affect the temperature characteristics of NMOS resistors. This invention addresses this by adjusting the gate-source voltage. Temperature characteristics are compensated for by the temperature characteristics of the MOS resistor.

[0051] (1) First, a voltage value of the gate-source voltage is generated. The bias voltage, through To eliminate the above formula Then the equivalent resistance becomes:

[0052] (2) Generate another voltage value Bias voltage to compensate for mobility The changes.

[0053] Due to electron mobility The relationship with temperature is as follows:

[0054] In the formula, Reference temperature electron mobility at that point It is the thermodynamic temperature, and m is a constant between 1.5 and 2 in the normal temperature range.

[0055] In order to obtain the thermodynamic temperature The proportional resistance generates a compensation voltage. Approximately proportional to Within a temperature range of -60 to 120℃, The voltage value is expressed by a second-order approximation as: ; , , This is a constant term.

[0056] In circuit design, compensation voltage The voltage value can be proportional to the thermodynamic temperature. The IP current and the reference current Iref are generated by voltage superposition through different resistors.

[0057] (3) Based on the above analysis, the gate-source voltage of the NMOS resistor Approximately expressed as That is, it can generate resistance that is proportional to temperature.

[0058] Specifically, the gate voltage of the MOS resistor N2 is determined by resistors R4 and R5 and the constant voltage NMOS transistor N1. The positive temperature coefficient current IP and the reference current Iref are mirrored across resistor R4 through two sets of current mirror circuits to generate a compensation voltage. The gate and drain of the constant voltage NMOS transistor N1 are connected, and it operates in the subthreshold region. Therefore, the gate-source voltage of the constant voltage NMOS transistor N1 is... Approximately equal to the threshold voltage of N2 in the NMOS transistor. This is used to compensate for the threshold voltage of the MOS resistor N2. Therefore, the gate-source voltage of the MOS resistor N2 is... By selecting appropriate resistors R4 and R5, a resistance proportional to the absolute temperature can be generated.

[0059] By changing the drain voltage of NMOS transistor N2 Divide by the resistance value of the MOS resistor N2 The reference current can then be obtained:

[0060] make ,but

[0061] Since m is a constant between 1.5 and 2 at room temperature, it can be... The second-order approximation yields... , These are all polynomial coefficients from the second-order fitting of the mobility-temperature characteristics, used as constant terms. Substituting them into the above equation yields:

[0062] in Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the electron charge. Substituting these values ​​into the above equation yields:

[0063] Adjust resistor R5 to meet the requirements. At this time, a reference current that does not change with temperature can be obtained:

[0064] By generating a positive temperature coefficient voltage through a resistor with a positive temperature coefficient current and a zero temperature coefficient voltage through a resistor, and then superimposing this voltage on the gate-source voltage of an NMOS transistor operating in the subthreshold region, the gate of the NMOS resistor operating in the deep linear region is biased, thus enabling the NMOS transistor resistor to exhibit a positive temperature coefficient characteristic with good linearity.

[0065] In summary, this invention designs a low-temperature drift reference current source based on a MOS resistor. A temperature-proportional voltage is generated through transistor cross-coupling. This voltage is superimposed on the temperature-proportional MOS resistor to produce a reference current that does not change with temperature. The resistance value of the temperature compensation resistor R5 is only related to the electron mobility. The expansion of the negative first-order term reduces the impact of resistor process variations on the magnitude of the current source current; the temperature-proportional current and the reference current are superimposed through different resistors to generate the bias voltage of the NMOS resistor, thereby controlling the electron mobility. Compensation for the negative first and negative second terms of absolute temperature resulted in a reference current with a lower temperature coefficient.

[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-temperature drift reference current source circuit based on a MOS resistor, characterized in that, include: A startup circuit is used to provide a startup signal to the PTAT current generating circuit during power-on and to mirror the positive temperature coefficient PTAT current IP generated by the PTAT current generating circuit. The PTAT current generation circuit generates a positive temperature coefficient voltage through a transistor cross-coupling module and superimposes it on resistor R3 to generate a positive temperature coefficient PTAT current IP. The PTAT current IP is then mirrored onto the startup circuit, the MOS resistor gate voltage generation circuit, and the reference current generation circuit. A MOS resistor gate voltage generation circuit is used to inject the PTAT current IP and the reference current Iref into the resistor string to generate a superimposed compensation voltage Vb. An NMOS transistor N1 operating in the subthreshold region is connected to the end of the resistor string. By superimposing the compensation voltage Vb and the gate-source voltage of the NMOS transistor N1, the gate voltage of the MOS resistor operating in the deep linear region is controlled, thereby realizing a MOS resistor with a positive temperature coefficient. The reference current generation circuit generates a positive temperature coefficient voltage through the transistor cross-coupling module 2 and superimposes it on the MOS resistor with a positive temperature coefficient to generate a reference current Iref with zero temperature coefficient. The reference current Iref is then mirrored onto the MOS resistor gate voltage generation circuit, and the PTAT current IP is mirrored at the same time.

2. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 1, characterized in that, The startup circuit includes: The bias branch includes: a constant voltage PMOS transistor P1, a high voltage PMOS transistor HVP1, and a resistor R1; the source of the constant voltage PMOS transistor P1 is connected to the power supply VDD, the drain is connected to the source of the high voltage PMOS transistor HVP1, and the drain of the high voltage PMOS transistor HVP1 is connected to the resistor R1 connected to ground GND; the gates of the constant voltage PMOS transistor P1 and the high voltage PMOS transistor HVP1 are respectively connected to bias voltages Vb1~Vb2; The startup branch includes: a high-voltage PMOS transistor HVP2; the gate of the high-voltage PMOS transistor HVP2 is connected to the drain of the high-voltage PMOS transistor HVP1, the source of the high-voltage PMOS transistor HVP2 is connected to the power supply VDD, and the drain of the high-voltage PMOS transistor HVP2 outputs a disturbance current Ib as the startup signal.

3. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 1, characterized in that, The PTAT current generating circuit includes: Bias module one is used to mirror the PTAT current IP to the startup circuit, the MOS resistor gate voltage generation circuit and the reference current generation circuit; A transistor cross-coupling module 1 includes: high-voltage NMOS transistors HVN1~HVN2, NPN transistors Q1~Q4, and resistor R3; the drain and gate of the high-voltage NMOS transistors HVN1~HVN2 are connected to the bias module 1; the source of the high-voltage NMOS transistor HVN1 is connected to the collector and base of NPN transistor Q1 and the base of NPN transistor Q2; the emitter of NPN transistor Q1 is connected to the collector of NPN transistor Q3 and the base of NPN transistor Q4; the base of NPN transistor Q3 is connected to the emitter of NPN transistor Q2 and the collector of NPN transistor Q4; the collector of NPN transistor Q2 is connected to the source of the high-voltage NMOS transistor HVN2; the emitter of NPN transistor Q3 and one end of resistor R3 are grounded to GND; the other end of resistor R3 is connected to the emitter of NPN transistor Q4.

4. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 3, characterized in that, The bias module includes: constant voltage PMOS transistors P2~P3, high voltage PMOS transistors HVP3~HVP4, and resistor R2; the source of constant voltage PMOS transistors P2~P3 is connected to power supply VDD, and the gate is connected to the drain of high voltage PMOS transistor HVP4 and one end of resistor R2 to generate a bias voltage Vb1; the drain of constant voltage PMOS transistor P2 is connected to the source of high voltage PMOS transistor HVP3, the drain of constant voltage PMOS transistor P3 is connected to the source of high voltage PMOS transistor HVP4, the gate of high voltage PMOS transistors HVP3~HVP4 is connected to the other end of resistor R2 to generate a bias voltage Vb2; the drain of high voltage PMOS transistor HVP3 is connected to the drain and gate of high voltage NMOS transistor HVN1 and the gate of high voltage NMOS transistor HVN2, and the other end of resistor R2 is connected to the drain of high voltage NMOS transistor HVN2.

5. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 4, characterized in that, The MOS resistor gate voltage generation circuit includes: constant voltage PMOS transistors P4~P5, high voltage PMOS transistors HVP5~HVP6, a resistor string, and constant voltage NMOS transistor N1. The sources of constant voltage PMOS transistors P4~P5 are connected to power supply VDD, the gate of constant voltage PMOS transistor P4 is connected to bias voltage Vb1, the drain of constant voltage PMOS transistor P4 is connected to the source of high voltage PMOS transistor HVP5, the gate of high voltage PMOS transistor HVP5 is connected to bias voltage Vb2, the drain of high voltage PMOS transistor HVP5 is connected to the beginning of the resistor string, the end of the resistor string is connected to the gate and drain of constant voltage NMOS transistor N1, the source of constant voltage NMOS transistor N1 is grounded to GND, the drain of constant voltage PMOS transistor P5 is connected to the source of high voltage PMOS transistor HVP6, the drain of high voltage PMOS transistor HVP6 is connected to the series connection point of the resistor string, and the gates of constant voltage PMOS transistor P5 and high voltage PMOS transistor HVP6 are connected to the reference current generation circuit.

6. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 5, characterized in that, The resistor string consists of two resistors R4 and R5 connected in series.

7. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 5, characterized in that, The reference current generating circuit includes: Bias module two is used to mirror the reference current Iref onto the MOS resistor gate voltage generation circuit and to mirror the PTAT current IP. The second transistor cross-coupling module includes: a constant-voltage NMOS transistor N2, a high-voltage NMOS transistor HVN3, and NPN transistors Q5~Q8; the gate of the constant-voltage NMOS transistor N2 is connected to the superimposed compensation voltage Vb and the gate-source voltage of the NMOS transistor N1; the source of the constant-voltage NMOS transistor N2 and the emitter of the NPN transistor Q8 are grounded to GND; the drain of the constant-voltage NMOS transistor N2 is connected to the emitter of the NPN transistor Q7 to form a drain voltage Vd; and the base of the NPN transistor Q7 is connected to the NPN transistor... The emitter of Q6 and the collector of NPN transistor Q8 are connected. The base of NPN transistor Q8 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q7. The base of NPN transistor Q5 is connected to the base and collector of NPN transistor Q6, as well as the bias module two. The collector of NPN transistor Q5 is connected to the source of high-voltage NMOS transistor HVN3. The gate of high-voltage NMOS transistor HVN3 is connected to the bias voltage Vb2. The drain of high-voltage NMOS transistor HVN3 is connected to the bias module two.

8. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 7, characterized in that, The bias module two includes: constant voltage PMOS transistors P6~P8, high voltage PMOS transistors HVP7~HVP8, and resistor R6; the sources of the constant voltage PMOS transistors P6~P8 are connected to the power supply VDD, the gates of the constant voltage PMOS transistors P6~P7 are connected to the gate of the constant voltage PMOS transistor P5, the drain of the high voltage PMOS transistor HVP7, and one end of resistor R6 to generate a bias voltage Vb3, and the drain of the constant voltage PMOS transistor P6 is connected to the source of the high voltage PMOS transistor HVP7, and the high voltage P... The gate of MOSFET HVP7 is connected to the gate of high-voltage PMOS transistor HVP6, the other end of resistor R6, and the drain of high-voltage NMOS transistor HVN3. The gate of the constant-voltage PMOS transistor P8 is connected to the bias voltage Vb1. The drains of the constant-voltage PMOS transistors P7~P8 are connected to the source of high-voltage PMOS transistor HVP8. The gate of high-voltage PMOS transistor HVP8 is connected to the bias voltage Vb2. The drain of high-voltage PMOS transistor HVP8 is connected to the base and collector of NPN transistor Q6.

9. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 7, characterized in that, The emitter areas of NPN transistors Q1 and Q4 are equal, the emitter areas of NPN transistors Q2 and Q3 are equal, and the emitter areas of NPN transistors Q1 and Q4 are N times the emitter areas of NPN transistors Q2 and Q3. The emitter areas of NPN transistors Q6 and Q7 are equal, and the emitter areas of NPN transistors Q5 and Q8 are equal. Furthermore, the emitter areas of NPN transistors Q6 and Q7 are N times the emitter areas of NPN transistors Q5 and Q8.

10. The low-temperature drift reference current source circuit based on a MOS resistor as described in claim 9, characterized in that, The formula for the reference current Iref is: in, , The capacitance per unit area of ​​the gate oxide layer. The aspect ratio of the NMOS transistor N2 at ambient voltage; Let R3 be the resistance value. Let be the resistance of the resistor string, k be Boltzmann's constant, and q be the electron charge. Reference temperature electron mobility at that point The coefficients of the polynomial for the second-order fitting of the mobility temperature characteristics are used as constant terms.

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