Analog-to-digital-to-analog conversion channel extended photonic computing device and method

Abstract

The application relates to a photonic computing device and method with an analog-digital-digital conversion channel expansion. The device comprises an FPGA master module, an analog-digital-digital conversion module, an input-output interface module, a switch switching delay adjustment module, a clock module, a memory module, a photonic computing module and a power module. The FPGA master module is used for outputting a timing control signal to control and manage the analog-digital-digital conversion module and the switch switching delay adjustment module to work cooperatively; the analog-digital-digital conversion module is used for providing multi-channel analog-digital-digital conversion; the input-output interface module is used for interface expansion of the FPGA master module and interaction of a multi-channel synchronous signal with the photonic computing module; the switch switching delay adjustment module is used for expanding the channel number of the analog-digital-digital conversion module and synchronously sending the data of all channels to the input-output interface module; and the photonic computing module is used for performing photonic computing on the multi-channel synchronous signal. The device can realize multi-channel expansion with higher parallelism, and reduce hardware cost and power consumption.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a photonic computing device and method with extended analog-to-digital and digital-to-analog conversion channels. Background Technology

[0002] With the development of the field of electronic circuits, photonic computing devices have emerged. In traditional technology, photonic computing devices mostly use FPGAs with fixed-channel analog-to-digital and digital-to-analog converter modules to complete data interaction. Conventionally, only a four-channel structure is used for signal processing. If it is necessary to increase the number of channels and improve parallel performance, multiple analog-to-digital and digital-to-analog converter chips are generally connected in parallel or cascaded.

[0003] However, current traditional methods have the problem of a limited number of basic channels, which cannot meet the needs of high-parallelism optical computing. Summary of the Invention

[0004] Therefore, it is necessary to provide a photonic computing device and method that can meet the requirements of high parallelism for analog-to-digital and digital-to-analog conversion channel expansion, addressing the aforementioned technical problems.

[0005] In a first aspect, this application also provides a photonic computing device with extended analog-to-digital and digital-to-analog conversion channels, comprising:

[0006] The FPGA main control module is used to output timing control signals and manage the coordinated operation of the analog-to-digital and digital-to-analog conversion modules and the switch switching delay adjustment module.

[0007] The analog-to-digital (ADC) and digital-to-analog (DAC) conversion modules are connected to the FPGA main control module, clock module, and switch switching delay adjustment module, respectively, to provide multi-channel ADC and DAC conversion.

[0008] The input / output interface module is connected to the FPGA main control module and the switch switching delay adjustment module, respectively, and is used to expand the interface of the FPGA main control module and exchange multiple synchronization signals with the optical computing module.

[0009] The switch-to-delay adjustment module is connected to the FPGA main control module, the analog-to-digital and digital-to-analog converter module, and the input / output interface module, respectively. It is used to expand the number of channels of the analog-to-digital and digital-to-analog converter module and to ensure that all data arrives at the input / output interface module synchronously.

[0010] The clock module is connected to the FPGA main control module and the analog-to-digital and digital-to-analog converter module respectively, and is used to provide the working clock.

[0011] The memory module is connected to the FPGA main control module and is used to exchange stored data with the FPGA main control module.

[0012] The optical computing module, connected to the input / output interface module, is used to perform photonic computing on the input multi-channel synchronous signals;

[0013] The power supply module is used to provide operating voltage to each module.

[0014] In one embodiment, the analog-to-digital and digital-to-analog conversion module has 16 physical channels, and the switch switching delay adjustment module includes 16 multiplexed switch circuits and 16 delay adjustment circuits;

[0015] Each multiplexer circuit has an input connected to one physical channel of the analog-to-digital and digital-to-analog converter module, and each multiplexer circuit has three outputs. The input of each delay adjustment circuit is connected to the three outputs of the corresponding multiplexer circuit, and the output of each delay adjustment circuit is connected to the input / output interface module.

[0016] In one embodiment, the multiplexing switch circuit is a single-pole triple-throw switch, which is used to time-division switch one physical channel input signal into three output branch signals.

[0017] The delay adjustment circuit is used to perform timing calibration on the three output signals of the multiplexed switching circuit.

[0018] In one embodiment, the device includes:

[0019] The FPGA main control module establishes control connections with each multiplexer circuit to perform timing switching control on the multiplexer circuits.

[0020] In one embodiment, the FPGA main control module is used to control the time-division switching timing of the multiplexing switch circuit, including:

[0021] At the initial moment, the 16 multiplexed switching circuits are simultaneously turned on to the first output branch; after a preset time interval, they are sequentially and synchronously turned on to the second output branch and the third output branch.

[0022] In one embodiment, the device further includes:

[0023] The 16 physical channels of the analog-to-digital and digital-to-analog converter module output signals under the control of the FPGA main control module;

[0024] The multiplexing switch circuit sequentially switches to three output branches, and the 16 physical channels correspond to the time-division transmission of signals for each output branch.

[0025] Secondly, this application provides a method for extending analog-to-digital and digital-to-analog conversion channels, including:

[0026] The FPGA main control module sends the switching timing to each multiplexer circuit, controlling the 16 multiplexer circuits to sequentially connect the first output branch, the second output branch, and the third output branch.

[0027] The 16 physical channels of the analog-to-digital and digital-to-analog converter module transmit signals in a time-division manner via three output branches, following the branch switching sequence of the multiplexing switch circuit; among them, the branch transmission signals are delivered to the corresponding delay adjustment circuit within a preset time period.

[0028] The delay adjustment circuit performs uniform delay processing on signals input at different times to complete timing calibration.

[0029] In one embodiment, the multiplexing switch circuit sequentially maintains the first output branch, the second output branch, and the third output branch in an on state according to a preset time interval.

[0030] In one embodiment, the 16 physical channels of the analog-to-digital and digital-to-analog converter module output a set of channel signals synchronously when switching one output branch.

[0031] In one embodiment, the delay adjustment circuit performs uniform delay processing on signals input at different times, including:

[0032] The time delay adjustment circuit configures a corresponding delay amount for signals input at different times and performs uniform delay processing.

[0033] The aforementioned photonic computing device and method with extended analog-to-digital (ADC) and digital-to-analog (DAC) conversion channels includes an FPGA main control module, an ADC module, an input / output interface module, a switch delay adjustment module, a clock module, a memory module, an optical computing module, and a power supply module. The FPGA main control module outputs timing control signals to manage the collaborative operation of the ADC module and the switch delay adjustment module. The ADC module is connected to the FPGA main control module, the clock module, and the switch delay adjustment module, respectively, to provide multi-channel ADC / DAC conversion. The input / output interface module is connected to the FPGA main control module, the switch delay adjustment module, and the optical computing module, respectively, to control the ADC / DAC and the switch delay adjustment module. The PGA main control module expands the interface and interacts with the optical computing module to exchange multiple synchronization signals; the switch-to-delay adjustment module is connected to the FPGA main control module, the analog-to-digital (ADC) / digital-to-analog (DAC) module, and the input / output interface module, respectively, to expand the number of channels of the ADC module and ensure that data from each channel arrives synchronously at the input / output interface module; the clock module is connected to the FPGA main control module and the ADC module, respectively, to provide the working clock; the memory module is connected to the FPGA main control module to exchange stored data with the FPGA main control module; the optical computing module is connected to the input / output interface module to perform photonic computing on the multiple synchronization signals; the power supply module provides the working voltage for each module. This device achieves expanded channel count for the analog-to-digital (ADC) and digital-to-analog (DMA) conversion modules through coordinated management of the FPGA main control module and the switch-switching delay adjustment module. This eliminates the need for additional hardware channel resources for the ADC, effectively reducing hardware costs and design complexity. Simultaneously, the timing calibration function of the switch-switching delay adjustment module ensures that all extended data streams arrive synchronously at the input / output interface modules and are stably transmitted to the optical computing module for computational interaction. This guarantees the synchronization and consistency of multi-channel data transmission, improving the reliability and efficiency of data processing. It provides a low-cost, highly synchronized, and reliable solution for multi-channel ADC in photonic computing scenarios. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a structural block diagram of a photonic computing device with an extended analog-to-digital (ADC) to digital-to-analog (DAC) conversion channel in one embodiment.

[0036] Figure 2This is a flowchart illustrating an analog-to-digital (ADC) to digital-to-analog (DAC) channel expansion method in one embodiment.

[0037] Figure 3 This is a block diagram of the circuit implementation for channel expansion in one embodiment;

[0038] Figure 4 This is a block diagram illustrating the implementation of the timing workflow and control logic algorithm in another embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0041] In one embodiment, such as Figure 1 As shown, a photonic computing device with extended analog-to-digital and digital-to-analog conversion channels is provided, comprising:

[0042] The FPGA main control module 101 is used to output timing control signals and control the analog-to-digital and digital-to-analog conversion module 102 and the switch switching delay adjustment module 104 to work together.

[0043] For example, after power-on, the FPGA main control module 101 first loads the configuration file from internal or external non-volatile memory such as configuration Flash or memory module 106 to complete the configuration of its own logic resources. Subsequently, the FPGA main control module 101 writes an initialization register to the analog-to-digital and digital-to-analog converter module 102 via SPI or parallel bus interface to set its operating mode, such as conversion accuracy, sampling rate, and input / output range; at the same time, it writes an initial channel mapping table and delay parameters to the switch switching delay adjustment module 104 to put it in a standby state.

[0044] The FPGA main control module 101 detects the reference clock from the clock module 105 and outputs a synchronization clock signal to the analog-to-digital (ADC) and digital-to-analog (DAC) conversion module 102 to ensure that all modules operate in the same clock domain. Successful clock synchronization is confirmed by reading the LOCK pin status. Subsequently, the FPGA main control module 101 generates timing control signals according to a preset channel expansion strategy, including a conversion start signal to trigger the ADC to begin conversion, a channel selection signal to control the switch array to map channels sequentially, and a delay adjustment enable signal to enable the programmable delay line to perform fine delay compensation for each data path.

[0045] During continuous operation, the FPGA main control module 101 continuously monitors the data synchronization flag returned by the input / output interface module 103. If the arrival time of a certain data channel deviates from the preset window, the delay step of the corresponding channel is adjusted in real time until all data arrives synchronously. When abnormalities such as clock lockout, conversion module overflow, or switch switching timeout are detected, the FPGA main control module 101 automatically triggers a partial reset, re-executes the initialization configuration, and reports the error code to the host computer. After the system recovers, it continues to work collaboratively, thereby achieving synchronous arrival of multi-channel data.

[0046] The analog-to-digital and digital-to-analog conversion module 102 is connected to the FPGA main control module 101, the clock module 105, and the switch switching delay adjustment module 104, respectively, and is used to provide multi-channel analog-to-digital and digital-to-analog conversion.

[0047] For example, the physical channels of the analog-to-digital and digital-to-analog converter module 102 are respectively connected to multiple multiplexed switch circuits in the switch switching delay adjustment module 104. Each multiplexed switch circuit is a single-pole multi-throw structure with multiple output branches. The FPGA main control module 101 controls the multiplexed switch circuits to switch each output branch in a time-division manner, so that the signals of each physical channel of the analog-to-digital and digital-to-analog converter module 102 are transmitted to the corresponding delay adjustment circuits in a time-division manner through each output branch. Then, the delay adjustment circuits perform timing calibration on the signals input at different times, and finally output the extended multiple logic channel signals, realizing the expansion from physical channels to logic channels.

[0048] The input / output interface module 103 is connected to the FPGA main control module 101 and the switch switching delay adjustment module 104 respectively, and is used to expand the interface of the FPGA main control module 101 and interact with the optical computing module with multiple synchronization signals.

[0049] Among them, interface expansion refers to providing the FPGA main control module 101 with various types of external communication interfaces through the input / output interface module 103 to support high-speed data exchange with external devices (such as host computers, optical computing modules, etc.).

[0050] The switch switching delay adjustment module 104 is connected to the FPGA main control module 101, the analog-to-digital-to-analog converter module 102, and the input / output interface module 103 respectively. It is used to expand the number of channels of the analog-to-digital-to-analog converter module 102 and to ensure that all data arrives at the input / output interface module synchronously.

[0051] Among them, channel expansion refers to expanding the limited number of physical input and output channels of the analog-to-digital and digital-to-analog conversion module 102 into a larger number of logical channels through time-division multiplexing or switching.

[0052] For example, the switch-switching delay adjustment module 104 is composed of multiple identical unit circuits. Each unit circuit includes a multiplexed switch circuit and a delay adjustment circuit, corresponding to one physical channel of the analog-to-digital and digital-to-analog converter module 102, respectively. Each multiplexed switch circuit is a single-pole multi-throw structure. Its input terminal is connected to one physical channel of the analog-to-digital and digital-to-analog converter module 102, and its multiple output branches are connected to the corresponding delay adjustment circuits. Under the timing control of the FPGA main control module 101, the circuits switch each output branch in a time-division manner, distributing the signals of the same physical channel to different transmission paths according to the time sequence. The delay adjustment circuit receives the multiple signals output by the corresponding multiplexed switch circuits and applies matching delay compensation to the signals arriving at different times through a programmable delay unit to achieve timing calibration. Finally, each unit circuit outputs multiple logic channel signals, and the multiple unit circuits output the extended multiple logic channel signals, completing the expansion from physical channel to logic channel.

[0053] The clock module 105 is connected to the FPGA main control module 101 and the analog-to-digital and digital-to-analog conversion module 102 respectively, and is used to provide the working clock;

[0054] The working clock refers to the periodic clock signal that provides a reference time for the FPGA main control module 101 and the analog-to-digital and digital-to-analog conversion module 102, and is used to synchronize the sampling, conversion and data transmission timing of each module.

[0055] For example, after power-on, the clock module 105 generates a stable reference clock signal through an internal crystal oscillator or an external clock source, and outputs it to the FPGA main control module 101 and the analog-to-digital (ADC) to digital-to-analog (DAC) module 102, respectively. The FPGA main control module 101 receives the reference clock and generates multiple synchronous clock signals through an internal phase-locked loop or clock management unit, which are then distributed to the ADC module 102 and other modules that require clocks. The ADC module 102 receives the synchronous clock signal as its own sampling and conversion clock, ensuring that it works in the same clock domain as the FPGA main control module 101. After its internal clock circuit locks the synchronous clock signal, it feeds back the lock status to the FPGA main control module 101 through the lock indicator pin. The FPGA main control module 101 starts the subsequent data conversion and transmission process only after confirming that the clock synchronization is successful. When the FPGA main control module 101 detects an abnormal lock indicator, it determines that the clock is abnormal, triggers the clock module 105 to reset or reconfigure, and reports a clock error code to the host computer. It continues to work after the clock stabilizes.

[0056] The memory module 106 is connected to the FPGA main control module 101 and is used to exchange stored data with the FPGA main control module 101.

[0057] Among them, data exchange refers to the FPGA main control module 101 writing data that needs to be temporarily stored, buffered or stored for a long time into the memory module 106, or reading stored data from the memory module 106 for subsequent processing during the data processing process.

[0058] For example, after power-on, the FPGA main control module 101 reads the configuration file from the memory module 106 or non-volatile memory through the memory interface to complete the configuration of its own logic resources. It also reads the pre-stored channel mapping table and delay parameters from the memory module 106 and writes them to the switch switching delay adjustment module 104 through the bus interface, so that it initializes and stands by according to the preset parameters. During operation, when the FPGA main control module 101 receives conversion data from the analog-to-digital and digital-to-analog conversion module 102 or external data from the input / output interface module 103, it temporarily stores the data in the memory module 106 for rate matching or data packaging. When data needs to be sent or subsequent processing is required, it reads the cached data from the memory module 106 and forwards it to the target module. When the FPGA main control module 101 adjusts the delay parameters according to the closed-loop monitoring results, it writes the updated delay parameters into the memory module 106 for storage and simultaneously updates the switch switching delay adjustment module 104 to ensure that the latest parameter configuration can be restored after power failure.

[0059] The optical computing module 107 is connected to the input / output interface module and is used to perform photonic computing on the multi-channel synchronization signals;

[0060] Among them, performing photonic computing refers to relying on the internal photonic computing architecture to receive multiple synchronous electrical signals after channel expansion and timing calibration, convert the electrical signals into optical signals, and then use the photonic transmission and computing characteristics to complete parallel computing processing.

[0061] For example, the optical computing module 108 integrates an electro-optical conversion unit, a photonic computing core unit, and an optoelectronic feedback unit. The electro-optical conversion unit receives multiple synchronous electrical signals transmitted from the input / output interface module 103, converts them into parallel optical signals at a preset rate, and sends them to the photonic computing core unit. The photonic computing core unit performs various photonic computing tasks, such as logic operations and feature operations, on multiple parallel optical signals simultaneously according to the computing instructions issued by the FPGA main control module 101. After the computation is completed, the optical signals are converted back into electrical signals by the optoelectronic feedback unit and then fed back to the input / output interface module 103, realizing the entire process of multi-channel synchronous signal photonic computing and result feedback.

[0062] Power module 108 is used to provide operating voltage to each module.

[0063] The operating voltage refers to the specific voltage value required for each module to operate normally; different modules may require different voltages.

[0064] For example, the power supply module 108 receives external input power and converts it into various operating voltages required by each module through an internal voltage conversion circuit (such as a DC-DC converter or a low-dropout linear regulator). According to a preset power-on sequence, it sequentially provides operating voltages to the FPGA main control module 101, clock module 105, analog-to-digital / digital-to-analog converter module 102, switch-to-delay adjustment module 104, memory module 106, and input / output interface module 103, ensuring that each module starts up in the correct order. During device operation, the power supply module 108 continuously monitors each output voltage; when it detects a certain output voltage... When the circuit voltage is abnormal (such as overvoltage, undervoltage, or short circuit), a power failure signal is sent to the FPGA main control module 101, which then performs corresponding protection operations (such as cutting off the output or reporting an error). When the external input power is abnormally interrupted, the power module 108 maintains power supply briefly through its internal energy storage element and sends a power failure warning to the FPGA main control module 101. The FPGA main control module 101 uses this brief period to save key configuration parameters (such as the current channel mapping table and dynamically adjusted delay parameters) to the memory module 106 or non-volatile memory so that they can be restored on the next power-on.

[0065] The aforementioned photonic computing device with extended analog-to-digital (ADC) and digital-to-analog (DAC) conversion channels includes an FPGA main control module 101, an ADC module 102, an input / output interface module 103, a switch-to-delay adjustment module 104, a clock module 105, a memory module 106, a photonic computing module 107, and a power supply module 108. The FPGA main control module 101 outputs timing control signals to manage the coordinated operation of the ADC module 102 and the switch-to-delay adjustment module 104. The ADC module 102 is connected to the FPGA main control module 101, the clock module 105, and the switch-to-delay adjustment module 104, providing multi-channel ADC / DAC conversion. The input / output interface module 103 is connected to the FPGA main control module 101, the switch-to-delay adjustment module 103, and the photonic computing module 107, providing multi-channel ADC / DAC conversion. The FPGA main control module 101 is interface-expanded and interacts with the optical computing module 107 to exchange multiple synchronization signals; the switch-switching delay adjustment module 101 is connected to the FPGA main control module 101, the analog-to-digital-to-analog converter module 102, and the input / output interface module 103 respectively, to expand the number of channels of the analog-to-digital-to-analog converter module 102 and to ensure that all data arrives at the input / output interface module 103 synchronously; the clock module 105 is connected to the FPGA main control module 101 and the analog-to-digital-to-analog converter module 102 respectively, to provide the working clock; the memory module 106 is connected to the FPGA main control module 101, to exchange stored data with the FPGA main control module 101; the optical computing module 107 is connected to the input / output interface module 103, to perform photonic computing on the multiple synchronization signals; and the power supply module 108 is used to provide working voltage to each module. This device achieves the expansion of the number of channels in the analog-to-digital (ADC) and digital-to-analog (DMA) conversion modules 102 and 104 through the coordinated management of the FPGA main control module 101. This eliminates the need to add additional hardware channel resources to the ADC 102, effectively reducing hardware costs and design complexity. Simultaneously, through the timing calibration function of the switch-to-digital (DMA) delay adjustment module 104, the extended data from each channel can arrive synchronously at the input / output interface module 103 and be stably transmitted to the optical computing module 107 to complete the computational interaction. This ensures the synchronization and consistency of multi-channel data transmission, improves the reliability and efficiency of data processing, and provides a low-cost, highly synchronous, and reliable implementation solution for multi-channel ADC in photonic computing scenarios.

[0066] In one embodiment, the multiplexing switch circuit is a single-pole triple-throw switch, which is used to time-division switch one physical channel input signal into three output branch signals.

[0067] The delay adjustment circuit is used to perform timing calibration on the three output signals of the multiplexed switching circuit.

[0068] Specifically, the FPGA main control module 101 controls all single-pole three-throw switches to switch synchronously: at time T0, all switches are simultaneously connected to the first output branch; at time T0+10ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output the first batch of 16 signals S1~S16, which are transmitted to the delay adjustment circuit via branch 1; at time T0+15ns, all switches are simultaneously switched to the second output branch; at time T0+25ns, the analog-to-digital and digital-to-analog converter module 102 outputs the second batch of 16 signals S17~S32, which are transmitted to the delay adjustment circuit via branch 2; at time T0+30ns, all switches are simultaneously switched to the third output branch; at time T0+40ns, the analog-to-digital and digital-to-analog converter module 102 outputs the third batch of 16 signals S33~S48, which are transmitted to the delay adjustment circuit via branch 3. Within 40ns, all 48 signals arrive at the delay adjustment circuit in three batches. The delay adjustment circuit applies matching delay compensation to the signals arriving at different times through three programmable delay lines—applying a larger delay to the signals that arrive first and a smaller delay or no delay to the signals that arrive later—so that the three batches of signals are aligned to the same time window. Finally, the 48 signals are synchronously output to the input / output interface module 103, thereby realizing the expansion from 16 physical channels to 48 logical channels.

[0069] In the above embodiments, the time-division switching of the single-pole triple-throw switch and the timing calibration of the three programmable delay lines can achieve a three-fold increase in the number of channels with only one analog-to-digital and digital-to-analog converter chip in conjunction with the switch and the delay circuit. Compared with the traditional solution of using multiple analog-to-digital and digital-to-analog converter chips in parallel, it significantly reduces hardware costs and system power consumption, while avoiding complex synchronization problems between multiple chips and improving the system's synchronization performance and anti-interference capability.

[0070] In one embodiment, the device includes:

[0071] The FPGA main control module establishes control connections with each multiplexer circuit to perform timing switching control on the multiplexer circuits.

[0072] Specifically, the FPGA main control module 101 outputs first, second, and third channel selection signals sequentially according to preset nanosecond time intervals, controlling all multiplexed switching circuits to switch synchronously: in the first time period, all switches are simultaneously turned on to the first output branch, allowing the first batch of physical channel signals output by the analog-to-digital and digital-to-analog converter module 102 to be transmitted to the delay adjustment circuit via the first branch; in the second time period, all switches are simultaneously switched to the second output branch, allowing the second batch of signals to be transmitted via the second branch; in the third time period, all switches are simultaneously switched to the third output branch, allowing the third batch of signals to be transmitted via the third branch. Furthermore, the FPGA main control module 101 also dynamically adjusts the switching timing or sends delay step adjustment commands based on the data synchronization flag returned by the input / output interface module 103, forming a closed-loop control to ensure that each batch of signals arrives at the delay adjustment circuit in a preset order and time interval, providing a precise time reference for subsequent timing calibration and channel expansion.

[0073] In the above embodiments, the control logic and wiring complexity are greatly simplified by using a unified control connection and synchronous switching mechanism, avoiding the additional interface resources and control overhead required to independently control each switch; the nanosecond-level timing control accuracy of the FPGA main control module ensures that each batch of signals arrives at the delay adjustment circuit in sequence at a strictly preset time interval, providing stable and predictable input conditions for subsequent timing calibration.

[0074] In one embodiment, the FPGA main control module 101 is used to control the time-division switching timing of the multiplexing switch circuit, including:

[0075] At the initial moment, the 16 multiplexed switching circuits are simultaneously turned on to the first output branch; after a preset time interval, they are sequentially and synchronously turned on to the second output branch and the third output branch.

[0076] Specifically, the FPGA main control module 101 controls all single-pole three-throw switches to switch synchronously: at time T0, all switches are simultaneously connected to the first output branch; at time T0+10ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output the first batch of 16 signals S1~S16, which are transmitted to the delay adjustment circuit via branch 1; at time T0+15ns, all switches are simultaneously switched to the second output branch; at time T0+25ns, the analog-to-digital and digital-to-analog converter module 102 outputs the second batch of 16 signals S17~S32, which are transmitted to the delay adjustment circuit via branch 2; at time T0+30ns, all switches are simultaneously switched to the third output branch; at time T0+40ns, the analog-to-digital and digital-to-analog converter module 102 outputs the third batch of 16 signals S33~S48, which are transmitted to the delay adjustment circuit via branch 3.

[0077] In the above embodiments, the synchronous switching mechanism greatly simplifies the control logic, eliminating the need for independent and complex phase control of each switch, thus reducing the FPGA's interface resource consumption and control algorithm complexity. The nanosecond-level precision interval ensures that each batch of signals arrives at the delay adjustment circuit in strict timing order, providing stable and predictable input conditions for subsequent unified timing calibration. At the same time, this time-division switching strategy, combined with the differentiated compensation of the delay adjustment circuit, enables the limited physical channels of the analog-to-digital and digital-to-analog conversion modules to be time-division multiplexed, ultimately achieving multiple channel expansion and ensuring synchronous output of all expanded channel signals. This achieves a balance between high parallelism and high synchronization performance with extremely low control overhead.

[0078] In one embodiment, the device further includes:

[0079] The 16 physical channels of the analog-to-digital and digital-to-analog converter module output signals under the control of the FPGA main control module;

[0080] The multiplexing switch circuit sequentially switches to three output branches, and the 16 physical channels correspond to the time-division transmission of signals for each output branch.

[0081] Specifically, the FPGA main control module 101 controls all single-pole three-throw switches to switch synchronously: at time T0, all switches are simultaneously connected to the first output branch; at time T0+10ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output the first batch of 16 signals S1~S16, which are transmitted to the delay adjustment circuit via branch 1; at time T0+15ns, all switches are simultaneously switched to the second output branch; at time T0+25ns, the analog-to-digital and digital-to-analog converter module 102 outputs the second batch of 16 signals S17~S32, which are transmitted to the delay adjustment circuit via branch 2; at time T0+30ns, all switches are simultaneously switched to the third output branch; at time T0+40ns, the analog-to-digital and digital-to-analog converter module 102 outputs the third batch of 16 signals S33~S48, which are transmitted to the delay adjustment circuit via branch 3. Within 40ns, all 48 signals arrive at the delay adjustment circuit in three batches. The delay adjustment circuit applies matching delay compensation to the signals arriving at different times through three programmable delay lines—applying a larger delay to the signals that arrive first and a smaller delay or no delay to the signals that arrive later—so that the three batches of signals are aligned to the same time window. Finally, the 48 signals are synchronously output to the input / output interface module 103, thereby realizing the expansion from 16 physical channels to 48 logical channels.

[0082] In the above embodiment, the 16 physical channels of the analog-to-digital (ADC) and digital-to-analog (DAC) conversion module output three batches of signals in a time-division manner under the control of the FPGA main control module. These signals are then sequentially switched to the three output branches for time-division transmission using a multiplexer switch circuit. The advantages are: only one ADC chip is needed to achieve a three-fold increase in the number of channels, reducing hardware costs by approximately two-thirds and system power consumption by approximately two-thirds compared to the traditional solution using multiple chips in parallel. Simultaneously, since all switches switch synchronously and each batch of signals is transmitted sequentially according to a strict timing sequence, the complex synchronization design between multiple chips is avoided. The delay adjustment circuit only needs to perform differentiated delay compensation on the three batches of signals that are from the same source and have predictable timing to achieve accurate alignment, significantly reducing the synchronization difficulty and the complexity of the calibration circuit. Ultimately, while ensuring the synchronous output of 48 extended signals, the system's integration, reliability, and anti-interference capability are significantly improved.

[0083] In one exemplary embodiment, such as Figure 2 As shown, an analog-to-digital (ADC) to digital-to-analog (DAC) channel extension method is provided, including steps 202 to 206. Wherein:

[0084] Step 202: The FPGA main control module 101 sends the switching timing sequence to each multiplexer circuit, controlling the 16 multiplexer circuits to sequentially connect the first output branch, the second output branch, and the third output branch.

[0085] The switching timing refers to the FPGA main control module 101 outputting different channel selection signals sequentially according to a preset time interval, which is used to control the multiplexing switch circuit to connect to different output branches at different time periods; the first output branch, the second output branch, and the third output branch refer to the three output channels of each multiplexing switch circuit, which correspond to three different signal transmission paths, and are used to distribute the signal of the same physical channel to different logic channels in a time-division manner.

[0086] For example, the FPGA main control module 101 integrates timing control logic to generate three sets of channel selection signals according to a preset channel expansion strategy. In the first time period, the first channel selection signal is output to control all 16 multiplexed switch circuits to be simultaneously turned on to their respective first output branches. After a first preset time interval, the second channel selection signal is output to control all switches to their respective second output branches. After another second preset time interval, the third channel selection signal is output to control all switches to their respective third output branches.

[0087] Step 204: The 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 transmit signals in a time-division manner via three output branches, following the branch switching sequence of the multiplexing switch circuit; wherein, the branch transmission signals are delivered to the corresponding delay adjustment circuit within a preset time period.

[0088] Among them, the multiplexing switch circuit refers to an analog switch device with a single-pole multi-throw structure, which, under the control of the FPGA main control module 101, switches one physical channel signal to multiple output branches in a time-division multiplexing manner. The delay adjustment circuit refers to a circuit module with a programmable delay line, which is used to perform timing calibration on signals input at different times and compensate for delay deviations introduced by factors such as switch switching and differences in signal transmission paths.

[0089] For example, after the FPGA main control module 101 controls the multiplexing switch circuit to complete the branch switching, it waits for a preset stabilization time to ensure that the switch is fully turned on, and then sends a conversion start signal to the analog-to-digital and digital-to-analog converter module 102. After receiving the start signal, the analog-to-digital and digital-to-analog converter module 102 outputs a batch of signals simultaneously through its 16 physical channels. This batch of signals is transmitted to the corresponding delay adjustment circuit within a preset time period through the currently connected output branch of the multiplexing switch circuit. The above process is repeated three times, corresponding to the first, second and third output branches respectively, so that the three batches of signals arrive at the delay adjustment circuit in a time-division manner.

[0090] Step 206: The delay adjustment circuit performs uniform delay processing on the signals input at different times to complete the timing calibration.

[0091] Timing calibration refers to eliminating the inherent time difference between different batches of signals through differential delay compensation, so that multiple signals are aligned to the same time window at the output end.

[0092] Optionally, the delay adjustment circuit includes multiple programmable delay lines, with each input signal corresponding to one programmable delay line. When three batches of signals arrive at the delay adjustment circuit in a time-division manner, the first batch of signals is subject to a larger delay, the second batch is subject to a medium delay, and the third batch is subject to a smaller delay or no delay. Each delay is pre-calculated and configured based on the actual time difference between each batch of signals. In addition, the delay adjustment circuit also supports dynamic calibration. The FPGA main control module 101 adjusts the step value of each programmable delay line in real time according to the data synchronization flag returned by the input / output interface module 103 until all signals arrive synchronously, and finally outputs the calibrated multiple signals synchronously to the input / output interface module 103.

[0093] In the above-mentioned analog-to-digital (ADC) and digital-to-analog (DAC) channel expansion method, the FPGA main control module sends switching timing sequences to each multiplexer circuit, controlling the 16 multiplexer circuits to sequentially connect the first output branch, the second output branch, and the third output branch. The 16 physical channels of the ADC module follow the branch switching timing sequence of the multiplexer circuits, transmitting signals through the three output branches in a time-division manner, and sending the signals of each branch to the corresponding delay adjustment circuit within a preset time period. The delay adjustment circuit performs unified delay processing on the signals input at different times, eliminates the time difference between batches of signals through differentiated delay compensation, completes timing calibration, and finally outputs the expanded multi-channel logic channel signals synchronously. Only one analog-to-digital and digital-to-analog converter chip is needed to achieve the channel scale of multiple chips connected in parallel, reducing hardware costs by about two-thirds and system power consumption by about two-thirds; all switches switch synchronously and each batch of signals is transmitted sequentially according to strict timing, avoiding complex synchronization design between multiple chips, and greatly reducing the synchronization difficulty and circuit implementation complexity; the delay adjustment circuit aligns the time-division signals arriving at the same time to the same time window through unified delay calibration, ensuring the synchronous output of multiple signals after expansion, and significantly improving the system's synchronization performance, reliability and anti-interference capability.

[0094] In one embodiment, the multiplexing switch circuit sequentially maintains the first output branch, the second output branch, and the third output branch in an on state according to a preset time interval.

[0095] For example, the FPGA main control module 101 integrates timing control logic to generate three sets of channel selection signals according to a preset channel expansion strategy. In the first time period, the first channel selection signal is output to control all 16 multiplexed switch circuits to be simultaneously turned on to their respective first output branches. After a first preset time interval, the second channel selection signal is output to control all switches to their respective second output branches. After another second preset time interval, the third channel selection signal is output to control all switches to their respective third output branches.

[0096] In the above embodiments, by time-division multiplexing each output branch and ensuring that each branch has sufficient conduction duration, the entire batch of signals output by the analog-to-digital and digital-to-analog converter modules can be transmitted completely and stably to the delay adjustment circuit through the current branch, avoiding signal truncation or incomplete transmission caused by excessively fast switching. The conduction states of each branch are maintained sequentially and without overlap, ensuring that different batches of signals are naturally separated in time, providing the delay adjustment circuit with three batches of input signals that are clearly distinguishable and have a fixed timing sequence. At the same time, all switches are switched synchronously and the conduction duration is uniformly controlled by the FPGA main control module. The control logic is simple and reliable, achieving multiple channel expansion with extremely low hardware overhead, and ensuring the integrity and synchronization of each signal after expansion.

[0097] In one embodiment, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output a set of channel signals each time one output branch is switched.

[0098] Specifically, the FPGA main control module 101 works in concert with the analog-to-digital and digital-to-analog converter module 102 and the multiplexing switch circuit to ensure that the output action of the analog-to-digital and digital-to-analog converter module 102 and the branch switching action of the multiplexing switch circuit maintain a strict following relationship: whenever the multiplexing switch circuit completes a branch switching and is stably turned on, the analog-to-digital and digital-to-analog converter module 102 immediately outputs a set of channel signals, which contain the sampling data of its 16 physical channels at the current moment.

[0099] According to the preset timing sequence, the multiplexing switch circuit switches to the first output branch, the second output branch, and the third output branch in sequence. After each switch, the analog-to-digital and digital-to-analog converter module 102 synchronously outputs a set of 16-channel signals, for a total of three sets of signals, each with 16 channels, for a total of 48 signals.

[0100] In the above embodiments, by binding the output action with the branch switching action, it is ensured that each group of signals accurately enters the preset transmission path, avoiding signal misalignment or crosstalk problems; the output is immediately after each switch without additional waiting time, maximizing the utilization of the conduction window of each output branch and improving signal transmission efficiency; the three groups of signals are generated and transmitted in a time-division manner, providing the delay adjustment circuit with three batches of input signals with clear timing and fixed intervals, reducing the complexity of subsequent timing calibration; at the same time, this "switching as output" collaborative control method only requires the FPGA main control module to issue a unified conversion start signal, the control logic is simple and reliable, and the efficient expansion from 16 physical channels to 48 logic channels is achieved with extremely low hardware overhead, while ensuring the integrity and transmission accuracy of each signal after expansion.

[0101] In one embodiment, the delay adjustment circuit performs uniform delay processing on signals input at different times, including:

[0102] The time delay adjustment circuit configures a corresponding delay amount for signals input at different times and performs uniform delay processing.

[0103] Specifically, because the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 output signals in three batches, and each batch of signals arrives at the time delay adjustment circuit at different times after being transmitted through different output branches (the first batch arrives earliest, the second batch later, and the third batch latest), there is a fixed time interval between the three batches of signals. The time delay adjustment circuit configures a corresponding delay dose for each batch of signals according to the time difference of arrival of each batch of signals, so that all signals are ultimately output at the same time.

[0104] In the above embodiments, by applying a differential compensation strategy that applies a larger delay to the first-arriving signal and a smaller delay to the later-arriving signal, the inherent time difference between batches of signals caused by time-division transmission can be accurately eliminated, so that all signals are aligned to the same time window for synchronous output.

[0105] In one embodiment, a photonic computing device with an extended analog-to-digital-to-analog conversion channel is provided, comprising: an FPGA main control module 101, an analog-to-digital-to-analog conversion module 102, an input / output interface module 103, a switch-to-delay adjustment module 104, a clock module 105, a memory module 106, an optical computing module 107, and a power supply module 108.

[0106] The FPGA main control module 101 is used to output timing control signals and manage the coordinated operation of the analog-to-digital (ADC) and digital-to-analog (DAC) conversion module 102 and the switch-to-interchange delay adjustment module 104. The ADC module 102 is connected to the FPGA main control module 101, the clock module 105, and the switch-to-interchange delay adjustment module 104, respectively, and is used to provide multi-channel ADC / DAC / DAC conversion. The input / output interface module 103 is connected to the FPGA main control module 101 and the switch-to-interchange delay adjustment module 104, respectively, and is used to expand the interface of the FPGA main control module 101 and interact with the optical computing module 107 to exchange multiple synchronization signals. The switch-to-interchange delay adjustment module 104 is connected to the FPGA main control module 101, clock module 105, and switch-to-interchange delay adjustment module 104, respectively. The control module 101, analog-to-digital (ADC) to digital-to-analog (DAC) module 102, and input / output interface module 103 are connected to each other to expand the number of channels in the ADC module 102 and to ensure that all data streams arrive at the input / output interface module 103 synchronously. The clock module is connected to the FPGA main control module 101 and the ADC module 102 respectively to provide the working clock. The memory module 106 is connected to the FPGA main control module 101 to exchange stored data with the FPGA main control module. The optical computing module 107 is connected to the input / output interface module 103 to perform photonic computing on multiple synchronous signals. The power supply module 108 is used to provide the working voltage for each module.

[0107] The analog-to-digital (ADC) and digital-to-analog (DAC) converter module 102 uses a Xilinx XCZU49DR chip, which integrates 16 ADC units and an FPGA interconnect interface, reducing the number of external interconnect interfaces between the ADC module 102 and the FPGA main control module 101. The multiplexing switch circuit uses an Analog Devices (ADI) ADG904 chip, which can achieve 1:4 switching multiplexing with a switching time of 10ns. In this embodiment, it is used as a 1:3 switch, with the extra channel shorted to ground to shield its function. The switching of the multiplexing switch circuit is achieved through the high-speed I / O of the FPGA main control module 101. The delay adjustment circuit uses an ADI AD8120 chip, which can automatically align the output of three input signals within a 50ns delay. The circuit block diagram is shown below. Figure 3 As shown.

[0108] Figure 3 In the analog-to-digital and digital-to-analog conversion module 102, the 16 physical channels (CH1~CH16) are respectively connected to the 16 multiplexed switch circuits in the switch switching delay adjustment module 104. Each multiplexed switch circuit is a single-pole triple-throw structure with three output branches. The FPGA main control module 101 controls the multiplexed switch circuits to switch the three output branches in a time-division manner, so that the 16 physical channel signals of the analog-to-digital and digital-to-analog conversion module 102 are transmitted to the corresponding delay adjustment circuits in a time-division manner through the three output branches. Then, the delay adjustment circuits perform timing calibration on the signals input at different times, and finally output 48 extended logic channel signals (CH1~CH48), realizing the expansion from 16 physical channels to 48 logic channels.

[0109] To extend the signal from the analog-to-digital and digital-to-analog converter module 102 from 16 physical channels to 48 logic channels, and to ensure that these 48 signals with different content arrive synchronously at the input / output interface module 103, it is also necessary to coordinate with the control logic algorithm of the FPGA main control module 101. The timing workflow and control logic algorithm implementation block diagram are shown below. Figure 4 As shown.

[0110] At time T0, the FPGA main control module 101 controls 16 multiplexed switching circuits to connect the first output branch; at time T0+10ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S1~S16; at time T0+15ns, the FPGA main control module 101 controls the multiplexed switching circuits to switch to the second output branch; at time T0+25ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S17~S32; at time T0+30ns, the FPGA main control module 101... 01 controls the multiplexing switch circuit to switch to the third output branch; at time T0+40ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S33~S48; within 40ns, all S1~S48 are sent to the corresponding time delay adjustment circuit in the switch switching time delay adjustment module 104. The time delay adjustment circuit applies a uniform delay processing to the signals input at different times, so that all signals are synchronously output to the input / output interface module 103, completing the expansion and timing calibration from 16 physical channels to 48 logic channels.

[0111] At time T0, the FPGA main control module 101 controls 16 multiplexed switching circuits to connect the first output branch; at time T0+10ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S1~S16, each signal segment occupying a duration ≤5ns; at time T0+15ns, the FPGA main control module 101 controls the multiplexed switching circuits to switch to the second output branch; at time T0+25ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S17~S32, each signal segment occupying a duration ≤5ns; at time T0+30ns, the FPGA main control module 101... 01 controls the multiplexing switch circuit to switch to the third output branch; at T0+40ns, the 16 physical channels of the analog-to-digital and digital-to-analog converter module 102 synchronously output signals S33~S48, each signal segment occupies a duration of ≤5ns; within 40ns, all S1~S48 are sent to the corresponding delay adjustment circuit in the switch switching delay adjustment module 104. The delay adjustment circuit applies a uniform delay processing to the signals input at different times, so that all signals are synchronously output to CH1~CH48 and synchronously arrive at the input / output interface module 103, completing the expansion and timing calibration from 16 physical channels to 48 logic channels.

[0112] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0113] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0115] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A photonic computing device with extended analog-to-digital and digital-to-analog conversion channels, characterized in that, The device includes: The FPGA main control module is used to output timing control signals and manage the coordinated operation of the analog-to-digital and digital-to-analog conversion modules and the switch switching delay adjustment module. The analog-to-digital and digital-to-analog conversion module is connected to the FPGA main control module, the clock module, and the switch switching delay adjustment module, respectively, and is used to provide multi-channel analog-to-digital and digital-to-analog conversion. The input / output interface module is connected to the FPGA main control module, the switch switching delay adjustment module, and the optical computing module, respectively, and is used to expand the interface of the FPGA main control module and exchange multiple synchronization signals with the optical computing module. The switch-to-delay adjustment module is connected to the FPGA main control module, the analog-to-digital-to-analog converter module, and the input / output interface module, respectively. It is used to expand the number of channels of the analog-to-digital-to-analog converter module and to ensure that all data arrives at the input / output interface module synchronously. The clock module is connected to the FPGA main control module and the analog-to-digital and digital-to-analog converter module respectively, and is used to provide the working clock; The memory module is connected to the FPGA main control module and is used to exchange stored data with the FPGA main control module; An optical computing module, connected to the input / output interface module, is used to perform photonic computing on the multi-channel synchronization signals; The power supply module is used to provide operating voltage to each module.

2. The apparatus according to claim 1, characterized in that, The analog-to-digital and digital-to-analog conversion module has 16 physical channels, and the switch switching delay adjustment module includes 16 multiplexed switch circuits and 16 delay adjustment circuits; The input of each multiplexer circuit is connected to one physical channel of the analog-to-digital and digital-to-analog converter module, and each multiplexer circuit has three outputs; the input of each delay adjustment circuit is connected to the three outputs of the corresponding multiplexer circuit, and the output of each delay adjustment circuit is connected to the input / output interface module.

3. The apparatus according to claim 2, characterized in that, The multiplexing switch circuit is a single-pole triple-throw switch, used to time-division switch one physical channel input signal into three output branch signals. The delay adjustment circuit is used to perform timing calibration on the three output signals of the multiplexed switching circuit.

4. The apparatus according to claim 2, characterized in that, The device includes: The FPGA main control module establishes a control connection with each multiplexer circuit to perform timing switching control on the multiplexer circuit.

5. The apparatus according to claim 4, characterized in that, The FPGA main control module is used to control the time-division switching sequence of the multiplexing switch circuit, including: At the initial moment, the 16 multiplexed switching circuits are simultaneously turned on to the first output branch; after a preset time interval, they are sequentially and synchronously turned on to the second output branch and the third output branch.

6. The apparatus according to claim 5, characterized in that, The device further includes: The 16 physical channels of the analog-to-digital and digital-to-analog converter module output signals under the control of the FPGA main control module; The multiplexing switch circuit sequentially switches to three output branches, and the 16 physical channels correspond to the time-division transmission of signals for each output branch.

7. A method for extending an analog-to-digital (ADC) and digital-to-analog (DAC) conversion channel, characterized in that, The method includes: The FPGA main control module sends the switching timing to each multiplexer circuit, controlling the 16 multiplexer circuits to sequentially connect the first output branch, the second output branch, and the third output branch. The 16 physical channels of the analog-to-digital and digital-to-analog converter module transmit signals in a time-division manner via three output branches, following the branch switching sequence of the multiplexing switch circuit; among them, the branch transmission signals are delivered to the corresponding delay adjustment circuit within a preset time period. The delay adjustment circuit performs uniform delay processing on signals input at different times to complete timing calibration.

8. The method according to claim 7, characterized in that, The multiplexing switch circuit sequentially maintains the conduction state of the first output branch, the second output branch, and the third output branch according to a preset time interval.

9. The method according to claim 7, characterized in that, The analog-to-digital and digital-to-analog converter module has 16 physical channels, and each time one output branch is switched, a set of channel signals is output synchronously.

10. The method according to claim 7, characterized in that, The time delay adjustment circuit performs uniform delay processing on signals input at different times, including: The time delay adjustment circuit configures a corresponding delay amount for signals input at different times and performs uniform delay processing.

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