A multi-bus cooperative intelligent platform integrated management and control system

Abstract

The application discloses a kind of multi-bus coordination intelligent platform integrated management and control systems, it is related to platform processing equipment control technical field.The application includes VPX case, VPX case has a plurality of slot on backplane, interconnection is achieved by multi-bus coordination communication mode between slot;Backplane is inserted with CPU interface card, CPU processing card, FPGA processing card, radio frequency transceiver card, ADDA card, CPU interface card is used to realize IP configuration and network configuration management and control, platform state acquisition management and control, extension control management and control and automation operation and maintenance management and control.The application can solve the problems of single platform management and control bus, untimely state reporting, difficult fault positioning and high artificial dependence.

Description

Technical Field

[0001] The present invention relates to the technical field of platform processing equipment control, and particularly relates to an intelligent platform integrated control system with multi-bus collaboration, which is applicable to the real-time monitoring, parameter configuration and resource management of complex electronic platforms composed of multiple types of boards, and particularly focuses on the improvement of intelligent and automated control capabilities to achieve autonomous operation and efficient control throughout the life cycle of the platform. Background Art

[0002] With the rapid development of electronic technology, the processing capabilities and operating speeds of complex electronic platforms have been continuously improved, the required software and hardware resources have increased day by day, and the platform composition has become more complex, usually composed of various types of boards with different frequency bands combined as needed. Existing platform control solutions have obvious defects: the bus type is single, the types of monitorable states are limited, the platform status query depends on the manual operation of the "self-check" button, the status reporting is not timely, which is likely to affect the normal operation of the platform; and when the platform fails, the fault information cannot be automatically recorded, resulting in difficulties in later problem location.

[0003] With the upgrade of platform processing requirements, the parallel operation of multiple software and hardware resources has greatly increased the difficulty of comprehensive control. The detection of any link is not timely or the configuration is incorrect, which may affect the smooth execution of the entire task. At the same time, the existing control systems have low levels of intelligence and automation, and a large number of operations rely on manual intervention, which not only increases the workload of operation and maintenance personnel, but also easily causes control loopholes due to human operation errors, resulting in a decrease in the operating stability of the platform. Therefore, there is an urgent need for a comprehensive control system with comprehensive functions, strong real-time performance, user-friendly interface, high intelligence and automation to achieve integrated control of platform parameter configuration, resource management, status detection, permission setting, online update, and log management, and solve the deficiencies of the existing technology. Summary of the Invention

[0004] In view of the defects existing in the prior art, the present invention provides an intelligent platform integrated control system with multi-bus collaboration to achieve full-dimensional, automated and real-time control of complex electronic platforms, reduce manual intervention, improve the operating stability and maintainability of the platform, and solve the problems of untimely status reporting, difficult fault location, low control efficiency, and high manual dependence.

[0005] The technical solution adopted by the present invention is as follows:

[0006] An intelligent platform integrated control system with multi-bus collaboration includes a VPX chassis. The backplane of the VPX chassis has multiple slots, and the slots are interconnected through a multi-bus collaborative communication method; a CPU interface card, a CPU processing card, an FPGA processing card, a radio frequency transceiver card, and an ADDA card are inserted on the backplane. Among them, the CPU interface card is used to implement IP configuration and network configuration control, platform status acquisition control, expansion control, and automated operation and maintenance control.

[0007] Furthermore, the CPU interface card implements IP configuration and network configuration management in the following way:

[0008] After receiving IP configuration commands from an external host, the CPU interface card automatically verifies the legality and completeness of the commands and parameters, and automatically provides error messages for commands with missing parameters or incorrect formats. Subsequently, it identifies the types of boards and slot distributions with configurable IPs within the platform, matches the corresponding IP network segments and configuration parameters, sends the IP configuration information to the target board via the IIC bus, controls the board to complete the local IP modification, and then receives the board's response signal. It verifies the validity of the IP configuration through communication, synchronously records the configuration log, and sends the verification result back to the external host. If three consecutive communication verifications fail, an audible and visual alarm is triggered.

[0009] Furthermore, the CPU interface card implements platform status acquisition and control in the following way:

[0010] The CPU interface card automatically scans all boards through the IIC bus, collects basic information, health data and proprietary status information of the boards, sorts out the composition relationship of the boards and generates a visual deployment topology diagram.

[0011] The CPU interface card sends routing query commands to the CPU processing card via gigabit network, receives and parses the platform routing information returned by the CPU processing card, and updates the routing topology map. The basic information of the board includes the board number, board manufacturer, board temperature, chip temperature, voltage, and current.

[0012] The CPU interface card determines whether to perform online function loading based on the platform load. After issuing the loading command, the CPU processing card completes the FPGA or DSP program loading. If loading fails, the routing is automatically repaired and reloaded. If it fails three times in a row, an anomaly is reported and the cause of the fault is analyzed.

[0013] Furthermore, the CPU interface card implements extended control and management in the following ways:

[0014] The CPU interface card can select three time synchronization modes: external time synchronization, built-in time synchronization, and self-generated time information. It can detect the stability of the time synchronization in real time. If the current time synchronization mode is abnormal, it will automatically switch to the backup mode and send the time synchronization information to the CPU processing card for RTC synchronization.

[0015] The CPU interface card collects temperature data from each board in real time and dynamically adjusts the platform fan speed to achieve a balance between heat dissipation and noise control. Specifically, when the temperature is ≤50℃, the platform fan speed is adjusted to 3000r / min; when the temperature is >50℃ and ≤70℃, the platform fan speed is adjusted to 5100r / min; and when the temperature is >70℃, the platform fan speed is adjusted to 7200r / min.

[0016] The CPU interface card automatically sets the clock mode of the RF transceiver card via the SPI bus and automatically detects the clock synchronization status. When an external clock anomaly occurs, it automatically switches to the internal clock.

[0017] Furthermore, the CPU interface card achieves automated operation and maintenance management in the following way:

[0018] The CPU interface card collects real-time data on platform resource usage and allocates resources accordingly.

[0019] The CPU interface card provides a web interface, through which multiple users and devices can log in to the system. The system automatically identifies the identity and permission level of each user, assigns corresponding operation permissions, and records the operation logs of each user.

[0020] The CPU interface card obtains the status of each board through periodic detection. When a fault is diagnosed, it automatically triggers a repair mechanism including SRIO routing and online loading. If the repair fails, the faulty board is locked, the faulty link is disconnected, and the fault situation is reported.

[0021] Furthermore, the VPX chassis back panel adopts a front-to-back 6-slot configuration, with reserved interfaces for Gigabit Ethernet, 10 Gigabit Ethernet, IIC, MLVDS, SRIO, GTH, LVDS, SPI, and PCIe. The front 4 to 6 slots of the back panel are compatible with various types of cards. Slot 4 supports the insertion of high-speed memory cards, GPU processing cards, and AI inference cards. Slot 5 supports the insertion of GPU processing cards, AI inference cards, CPU processing cards, FPGA processing cards, and DSP processing cards. Slot 6 supports the insertion of CPU processing cards, FPGA processing cards, and DSP processing cards. The CPU interface card is fixedly installed in the rear 2 slots of the VPX chassis back panel.

[0022] Furthermore, the multi-bus collaborative communication method employs a hybrid application of IIC bus, Gigabit Ethernet, SRIO bus, MLVDS bus, SPI bus, and IO bus, with each bus having the following function:

[0023] 1) Gigabit Ethernet: Enables interconnection of all boards, monitors and sets board IP addresses through the web interface of the CPU interface card, and realizes 10 Gigabit Ethernet data forwarding and status management through the 1820 chip;

[0024] 2) IIC Bus: Adopts the standard IIC protocol to collect basic information, health information and proprietary status information of all boards;

[0025] 3) SRIO bus: Obtain platform SRIO routing, online loading status, and address information of CPU, DSP, and FPGA chips;

[0026] 4) MLVDS bus: Acquires time, latitude and longitude, and satellite count information;

[0027] 5) SPI bus: Used to obtain the local oscillator status of the RF transceiver card;

[0028] 6) IO bus: Obtain internal and external time system and antenna connection status information of the platform.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The design adopts a multi-bus hybrid application and multi-protocol collaboration, which breaks through the limitation of the single bus type of the traditional platform and realizes accurate and real-time collection of platform information in all dimensions, covering board basic information, health status, proprietary parameters, time statistics information, etc., with a comprehensive control scope.

[0031] 2. By using an automated data collection and real-time reporting mechanism to replace the traditional manual self-inspection method, the timeliness of platform status reporting is greatly improved, avoiding the impact of status lag on the normal operation of the platform; at the same time, it can automatically record fault-related information, providing strong support for later problem localization.

[0032] 3. It integrates functions such as IP configuration, status monitoring, online loading, time control, and temperature control, realizing intelligent and centralized management and control of the platform, reducing the management complexity of multiple software and hardware running in parallel, and improving the platform's operational stability and maintenance efficiency.

[0033] 4. The hardware architecture adopts a modular design and a symmetrical disaster recovery design. The boards can be combined as needed, with good scalability and compatibility to adapt to the application requirements of different scenarios. The SRIO mesh topology enables high-speed interconnection between boards, ensuring efficient data transmission.

[0034] 5. Enhance intelligent and automated functions, add automatic fault diagnosis and repair functions, access control, automated resource optimization and other functions to significantly reduce manual intervention, reduce the workload of operation and maintenance personnel, avoid human operation errors, and improve the intelligent level of platform management and autonomous operation and maintenance capabilities. Attached Figure Description

[0035] Figure 1 This is a hardware architecture block diagram of the platform integrated management and control system in an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the multi-bus cooperative communication mechanism in an embodiment of the present invention.

[0037] Figure 3 This is a flowchart of the IP configuration processing in an embodiment of the present invention.

[0038] Figure 4 This is a flowchart illustrating the platform status acquisition process in an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of the SRIO bus mesh topology in an embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0041] A multi-bus collaborative intelligent platform integrated management and control system includes a hardware architecture and software management and control logic. The hardware architecture consists of a VPX chassis, a power module, and various functional boards. The software management and control logic is based on multi-bus collaborative communication, integrating intelligent algorithms and automated control strategies to realize automated collection, configuration, analysis, early warning, and operation and maintenance of platform information. The specific technical solution is as follows:

[0042] (a) Hardware Architecture

[0043] It includes 11 different types of boards in different frequency bands, such as VPX chassis, power modules, CPU processing cards, CPU interface cards, FPGA processing cards, RF transceiver cards, ADDA cards, DVB demodulation cards, DSP processing cards, AI inference cards, GPU processing cards, memory cards, and 10 Gigabit transmission cards. The front-mounted slots 4 to 6 are compatible with multiple types of boards. Slot 4 supports high-speed memory cards, GPU processing cards, and AI inference cards. Slot 5 supports GPU processing cards, AI inference cards, CPU processing cards, FPGA processing cards, and DSP processing cards. Slot 6 supports CPU processing cards, FPGA processing cards, and DSP processing cards.

[0044] The VPX chassis features a 6-slot backplane design with front and rear plug-in ports, providing interfaces for various types and speeds, including Gigabit Ethernet, 10 Gigabit Ethernet, IIC, MLVDS, SRIO, GTH, LVDS, SPI, and PCIe. The SRIO bus uses a mesh topology to enable interconnection between the boards in each slot.

[0045] Each independent board is equipped with sensors and switching chips, employing a processor-symmetrical design for post-disaster recovery. The CPU interface card, located in two slots on the backplane, serves as the initiator and final receiver of the entire platform's management and control. It undertakes global management functions such as IP configuration, status monitoring, timing settings, function reset, and online updates. The CPU interface card supports full-process platform management via a web interface, with a built-in web service module that supports simultaneous access by multiple users and devices. Each user obtains corresponding management and operation permissions based on their own permission level, ensuring that operations are independent and do not interfere with each other. The AI ​​inference card works in collaboration with the GPU processing card, providing hardware computing power support for the system's intelligent analysis and decision-making, enabling real-time data processing and intelligent judgment. Its working status can be displayed in real time through the web interface.

[0046] (ii) Multi-bus cooperative communication mechanism

[0047] The system employs a hybrid application of multiple bus types, including IIC bus, Gigabit Ethernet, SRIO bus, MLVDS bus, SPI bus, and IO bus, working in conjunction with multiple protocols to achieve comprehensive information acquisition and control of the platform. The specific division of labor is as follows:

[0048] Gigabit Ethernet: Enables interconnection of all internal cards within the extension unit, providing stable network support for CPU interface card web interface access and simultaneous management of multiple users and devices. Gigabit network management is achieved by monitoring and setting the card IP address through the CPU interface card's web interface; 10 Gigabit network management is achieved through the 1820 chip, ensuring data transmission efficiency when multiple users access the network simultaneously.

[0049] IIC Bus: Adopting the standard and comprehensive IIC protocol, it obtains basic information such as slot number, board type, board manufacturer, program version number, and version production time of all boards. At the same time, it collects health information such as temperature, humidity, voltage, and current of each board, as well as proprietary information such as CPU board resource usage, FPGA and DSP SRIO port status, DVB board signal lock status, and ADDA card and RF card clock lock status.

[0050] SRIO bus: Obtain platform SRIO routing, online loading status, and address information of multiple CPU chips, DSP chips, and FPGA chips;

[0051] MLVDS bus: Acquires time, latitude and longitude, number of stars and other time-related information;

[0052] SPI bus: Obtain the local oscillator status of the RF card;

[0053] IO bus: Acquires information such as internal and external timing systems and antennas of the platform.

[0054] (III) Core control processes (including intelligent and automated functions)

[0055] 1. IP Configuration Processing Flow (Automated Configuration)

[0056] The CPU interface card receives the platform IP configuration field from the external host through the external network port, automatically identifies the legality and completeness of the configuration command, and automatically returns an error message and marks the problem point if there are missing parameters or incorrect format, without the need for manual verification.

[0057] The CPU interface card automatically reads the platform's internal composition information, obtains the specific model and slot distribution of the board, and intelligently filters out boards with configurable IPs (where gigabit network interface boards include CPU processing cards, FPGA processing cards, DSP processing cards, 10-gigabit transmission cards, high-speed storage cards, and DVB demodulation cards; 10-gigabit network interface boards include CPU processing cards, high-speed storage cards, and 10-gigabit transmission cards), and automatically matches the corresponding IP network segment and configuration parameters according to the board type;

[0058] The CPU interface card automatically sends IP information to the corresponding board via the IIC bus. After receiving the IP value, the board automatically modifies the local IP and returns a confirmation message to the CPU interface card after the modification is complete. The whole process requires no manual intervention.

[0059] 2. Platform Status Acquisition Process (Intelligent Data Collection, Analysis, and Early Warning)

[0060] The CPU interface card performs automated communication verification of the modified IP. If the communication is successful, the modification is considered successful, and the connection is successful and the corresponding IP value is displayed on the web interface. Multiple users and devices can view the result through the web interface simultaneously, and configuration logs are automatically recorded. If the verification fails, the modification command is automatically initiated again. If the verification fails three times in a row, the connection is automatically reported to the web interface, triggering an audible and visual alarm. At the same time, troubleshooting suggestions are generated (such as checking the board connection and verifying the IP network segment). The fault information is synchronously pushed to the web access interface of all authorized users.

[0061] The platform uses both direct acquisition via the IIC bus and indirect acquisition via gigabit network to achieve automated collection, intelligent analysis, and anomaly early warning of status information, obtaining overall platform information, board status information, and working resource information, as detailed below:

[0062] 1) IIC bus direct acquisition process (automated acquisition + intelligent analysis and early warning):

[0063] After the CPU interface card is powered on, it automatically reads the configuration file to obtain the platform name, type, manufacturer and platform number, without the need for manual input.

[0064] The system automatically scans all boards via the IIC bus to obtain board names and slot numbers, intelligently sorts out the board composition relationship of the platform, generates a visual board deployment topology diagram, updates it to the web interface in real time, supports multiple users and multiple devices to view at the same time, and displays topology information of corresponding level of detail according to user permissions.

[0065] The CPU interface card automatically sends timed status query commands to each board. After receiving the command, each board automatically reports its current status at regular intervals, including basic information (board number, board manufacturer, board temperature, chip temperature, voltage, current, etc.) and proprietary information (which varies depending on the board type, including SRIO switch interface status, network connection status, chip type, chip program version number, program generation time, storage capacity, CPU resource utilization, RF local oscillator lock status, CPU / FPGA / DSP address, etc.).

[0066] The CPU interface card updates the acquired status information, intelligent analysis results, and early warning information to the web interface in real time, supporting simultaneous access and viewing by multiple users and devices. It also automatically records status logs to form a historical data ledger, which authorized users can query through the web interface for easy traceability and analysis later.

[0067] 2) Gigabit network indirect data acquisition process (automated loading + intelligent scheduling):

[0068] The CPU interface card automatically sends a route acquisition command to the CPU processing card (the sending frequency can be intelligently adjusted). After receiving the command, the CPU processing card automatically collects the current routing information of the platform (including the route ID, connection status, chip information, etc. of each slot), packages it, and sends it to the CPU interface card. The CPU interface card automatically displays and updates the routing topology map and pushes it to the Web interface simultaneously for multiple users and devices to view at the same time.

[0069] The CPU interface card automatically identifies the current platform load based on application operation requirements and intelligently determines whether online function loading is required. If so, it automatically sends an online function loading command to the CPU processing card. After receiving the command, the CPU processing card automatically selects the FPGA or DSP program to be loaded and sends it to the corresponding board to complete the loading.

[0070] If loading fails, the CPU processing card automatically repairs the route and reloads. If loading fails three times in a row, the failure status is sent back to the CPU interface card. The AI ​​inference card automatically analyzes the reasons for the loading failure (such as routing failure, program corruption, board abnormality, etc.) and generates a troubleshooting plan. If loading is successful, the loading time is automatically returned, and the resource status of the currently running function (including the boards and chips running the function, the total number of chip logic channels, the amount of data used, the link transmission rate, etc.) is reported to the CPU interface card. The CPU interface card automatically summarizes and displays the data, and intelligently schedules board resources based on resource usage to avoid resource waste.

[0071] (iv) Expanded control functions (intelligent adjustment, automated operation and maintenance)

[0072] The CPU interface card can be controlled via the board's parameters to intelligently select the platform's time synchronization mode (external time synchronization, built-in time synchronization, and self-generated time information modes), monitor time synchronization stability in real time, and automatically switch to backup mode in case of anomalies, sending time synchronization information to the CPU processing card for RTC synchronization; it also supports authorized users to manually switch time synchronization modes, adjust fan speeds, and configure RF card clock modes via a web interface, ensuring no interference between multiple users; by collecting temperature information from each board, it automatically adjusts the platform fan speed to achieve a dynamic balance between noise control and heat dissipation control (300 RPM when temperature ≤ 50℃). The fan speed is 0 r / min. When the temperature is 50℃ to 70℃, the fan speed is 5100 r / min. When the temperature is >70℃, the fan speed is 7200 r / min. The fan speed is adjusted in advance according to the temperature change trend to avoid sudden temperature rise. The fan speed and board temperature data are displayed in real time on the web interface, which supports multiple users to view at the same time. The RF card clock mode is automatically set via the SPI bus (including three modes: 10MHz external clock, 10MHz internal clock and 25MHz clock), and the clock synchronization status is automatically detected. When the external clock is abnormal, it automatically switches to the internal clock. The clock status is synchronized and fed back on the web interface.

[0073] The intelligent and automated operation and maintenance functions are as follows:

[0074] Automatic fault diagnosis and self-healing: The CPU interface card obtains its current status through periodic detection. When a fault is diagnosed, it will automatically trigger a repair mechanism that includes SRIO routing and online loading. In case of a serious fault, the faulty board will be locked and the fault status will be reported.

[0075] Intelligent permission management: Supports multiple users and devices to log in to the system simultaneously through the web interface. The system automatically identifies the identity and permission level of each logged-in user and automatically assigns operation permissions according to the permission level (e.g., administrators can perform full-function operations, maintenance personnel can only view status and perform simple configurations, and visitors can only view basic status). Each user's permissions are independent and their operations do not interfere with each other. The system automatically records the operation logs of each user. Authorized administrators can query the operation logs of all users through the web interface to quickly locate problems.

[0076] Automated resource optimization: Real-time collection of resource usage of each board on the platform, automatic adjustment of resource allocation strategy, allocation of idle resources to high-load boards, improving the overall processing efficiency of the platform; at the same time, automatic cleanup of redundant data and release of idle resources to avoid resource waste.

[0077] Here is a more specific example:

[0078] A multi-bus collaborative intelligent platform integrated management and control system, its hardware architecture consists of a VPX chassis, a 220V AC power supply module, a CPU interface card, a CPU processing card, an FPGA processing card, an RF transceiver card, an ADDA card, a DVB demodulation card, a DSP processing card, an AI inference card, a GPU processing card, a high-speed storage card, and a 10 Gigabit transmission card, totaling 10 different types of functional boards, which are inserted into the 6 slots of the VPX chassis as needed, with the CPU interface card fixedly installed in the second rear slot (corresponding to...). Figure 1 ). Figure 1 The system hardware composition and connection relationships are demonstrated, the deployment location of each board and the connection method of the backplane interface are clearly defined, the core control position of the CPU interface card is highlighted, and the hardware modular design concept is presented.

[0079] The VPX chassis back panel has reserved interfaces for Gigabit Ethernet, 10 Gigabit Ethernet, IIC, MLVDS, SRIO, GTH, LVDS, SPI, and PCIe. The SRIO bus uses a mesh topology to achieve high-speed interconnection between all boards in the six slots. Figure 5 Each board is equipped with a temperature sensor, voltage sensor, current sensor, and switching chip. It adopts a dual-processor symmetrical design to ensure rapid switching in the event of a single processor failure, thus achieving disaster recovery backup. Figure 5 This design demonstrates the mesh topology of the SRIO bus connection between the VPX chassis slots. Since only the CPU, FPGA, and DSP processing cards have SRIO buses, based on the backplane connection relationships, SRIO routing is only available in slots 1, 5, and 6. Slots 4-6 are compatible with various types of cards. Slot 4 supports high-speed storage cards, GPU processing cards, and AI inference cards; slot 5 supports GPU processing cards, AI inference cards, CPU processing cards, FPGA processing cards, and DSP processing cards; and slot 6 supports CPU processing cards, FPGA processing cards, and DSP processing cards. The connection nodes are labeled according to this design, showcasing the high-speed interconnection structure between the cards and clearly demonstrating the advantages of the mesh topology and data transmission paths.

[0080] The system's multi-bus cooperative communication mechanism operates as follows (corresponding to...) Figure 2 ):

[0081] Gigabit Ethernet interconnects all boards via a switch, providing stable network support for simultaneous access by multiple users and devices via the CPU interface card's web interface. The CPU interface card's web interface can display the IP addresses of each board in real time and supports simultaneous manual modification by multiple authorized users without conflict. The 1820 chip connects to the 10 Gigabit Ethernet port, responsible for data forwarding and status management of the 10 Gigabit network. The IIC bus scans all boards periodically (every 100ms), collecting basic board information and health data, while also receiving dedicated status feedback from each board. The SRIO bus uses the SRIO v3.0 protocol with a transmission rate of 5Gbps, acquiring the platform's SRIO routing topology and chip address information in real time. The MLVDS bus uses the LVDS-2 protocol to collect time, latitude, longitude, and satellite information output by the GPS module. The SPI bus communicates with the RF transceiver card to obtain parameters such as local oscillator frequency and lock status. The IO bus connects the platform's timing module and antenna interface, collecting internal and external timing synchronization status and antenna connection status.

[0082] Figure 2 It demonstrates the connection relationships, communication objects, and data transmission directions of each bus (IIC, Gigabit Ethernet, etc.), clarifies the multi-bus division of labor logic, and presents the complete path of platform information collection and transmission.

[0083] The IP configuration process is as follows (corresponding to...) Figure 3 External access points can send IP configuration commands to the CPU interface card via Ethernet. Authorized users can also manually input IP configuration commands through the web interface (supporting multiple authorized users initiating configuration requests simultaneously, with the system executing them sequentially according to permission priority). The CPU interface card automatically identifies the validity of the configuration commands. If an IP network segment conflict exists, it automatically returns a "IP network segment conflict, please reconfigure" prompt and displays it simultaneously on the web interface. The CPU interface card automatically reads the board configuration file, identifies boards with configurable IPs, automatically matches the corresponding IP network segment, and sends IP configuration commands one by one through the IIC bus. Upon receiving the command, the local network card IP address is automatically modified, and a response signal is sent to the CPU interface card. The CPU interface card automatically verifies IP connectivity via the ping command. If the verification is successful, "Connection normal + IP address" is displayed on the web interface, supporting simultaneous viewing by multiple users and devices, and configuration logs are automatically recorded. If the verification fails, the command is automatically resent. After three consecutive failures, the web interface displays "Link disconnected" and triggers an audible and visual alarm. At the same time, troubleshooting suggestions such as "Check board IIC bus connection and verify IP network segment" are generated, and the fault information is synchronously pushed to the web access interface of all authorized users.

[0084] Figure 3 The entire IP configuration process is demonstrated, clearly defining the execution order, triggering conditions, and feedback mechanisms of each step, which corresponds to the actual operation process of IP configuration in specific embodiments.

[0085] In the platform status acquisition process (corresponding to) Figure 4 The IIC bus collects the health management status of each board every 100ms. When the board temperature reaches 65℃, a pre-warning is automatically triggered, indicating "temperature is too high and the threshold is about to be reached". When the temperature exceeds 70℃, a severe warning is automatically triggered, with an audible and visual alarm, and the fan speed is automatically adjusted to 7200r / min. When a voltage fluctuation exceeding ±0.5V is detected, it is automatically judged as a voltage abnormality, the abnormal board is locked, and the information is recorded in the log. The basic information includes board number, manufacturer, board temperature (range -40℃~85℃), chip temperature, power supply voltage (±3.3V, ±12V), and operating current. Specific information includes: the CPU processing card reports memory usage and CPU utilization; the FPGA processing card reports SRIO port connection status and logic resource utilization; the DVB demodulation card reports signal strength and lock status; and the RF transceiver card reports local oscillator lock status and power output value. The CPU interface card updates this information, analysis results, and warning information to the web interface in real time, supporting simultaneous access and viewing by multiple users and devices. It also automatically records status logs to form a historical data ledger, which authorized users can query through the web interface.

[0086] In the indirect data collection process of gigabit network (corresponding to) Figure 4 The CPU interface card sends a route query command to the CPU processing card every 500ms. The CPU processing card scans the routing nodes of each board through the SRIO bus, collecting information such as route ID, connection status, and chip model. When the status is incorrect, it automatically repairs it and packages the final status and transmits it back through the gigabit network. When it is necessary to load FPGA or DSP programs, the CPU interface card issues a loading command. The CPU processing card reads the corresponding program from the hard drive and sends it to the target FPGA or DSP board through the SRIO bus. After loading is completed, it returns the loading time (usually ≤2s). If loading fails, it automatically repairs the routing link and reloads. If it fails 3 times in a row, it reports "loading abnormality" and reports a fault.

[0087] Figure 4 The corresponding platform status acquisition process distinguishes between two methods: direct acquisition via IIC bus and indirect acquisition via Gigabit network. It demonstrates each acquisition step, clarifies the logical differences and collaborative relationship between the two methods, and matches the status acquisition parameters and frequency in specific embodiments.

[0088] In the extended control functions, the time synchronization mode can be manually switched via the web interface, supporting simultaneous viewing by multiple authorized users, but only the administrator can perform the switching operation; the default is to use an external time synchronization system (GPS time synchronization), and the system automatically checks the stability of the time synchronization system every 100ms. If the external time synchronization signal is lost for more than 3 seconds, it automatically switches to the onboard time synchronization system, and the switching status is updated in real time on the web interface; the CPU interface card controls the fan speed based on the highest temperature of each board, and the fan speed and board temperature data are displayed in real time on the web interface, supporting simultaneous viewing by multiple users; the RF card clock mode can be selected via the web interface, and the default is to use a 10MHz external clock. The system automatically detects the clock synchronization status, and if an external clock failure occurs, it will automatically switch to the internal clock, and the clock status is synchronously fed back on the web interface for multiple users to view.

[0089] The intelligent and automated operation and maintenance functions operate as follows: When a temporary interruption of the SRIO link is detected, the system automatically reconnects the link and restores normal operation within 10 seconds without manual intervention. The fault repair status is updated in real time on the Web interface, which supports multiple users to view simultaneously. Multiple users and multiple devices can log in to the system simultaneously through the Web interface. After the administrator logs in, the system automatically assigns full-function operation permissions. After the operation and maintenance personnel log in, they can only view the status and perform simple configurations. Visitors can only view the basic status. Each user's operation is independent and does not interfere with each other.

[0090] In this embodiment, the system can achieve full-dimensional control over 11 types of boards, with status acquisition latency ≤200ms, IP configuration success rate ≥99%, online program loading success rate ≥99%, fault reporting response time ≤1s, and automatic fault repair success rate ≥90%. This significantly reduces manual intervention and effectively solves the problems of low management efficiency, status lag, difficulty in fault location, and high dependence on manual intervention in traditional platforms, thereby improving the stability and ease of operation and maintenance of the platform.

[0091] In summary, this invention uses a CPU interface card as the core of control, coordinating hardware architecture and software control logic. The hardware architecture consists of a VPX chassis, a power module, and 11 functional boards. The VPX chassis backplane has multiple reserved interfaces, and the SRIO bus uses a mesh topology to achieve board interconnection. The software control logic is based on multi-bus collaborative communication such as IIC and Gigabit Ethernet, integrating intelligent algorithms and automated control strategies. Core control is performed through the CPU interface card: automatically completing IP and network configuration, intelligently selecting configurable IP boards and verifying connectivity; automatically collecting platform status, and using the CPU interface card to perform intelligent data analysis and anomaly warning; realizing extended control such as intelligent switching of time synchronization mode, automatic fan speed adjustment, and RF card clock calibration, while integrating automated operation and maintenance functions. This invention achieves centralized, multi-dimensional, automated real-time control of complex electronic platforms through the CPU interface card, reducing manual intervention, improving platform stability, maintainability, and operation and maintenance efficiency, and has good scalability and compatibility. It can solve the problems of existing platforms such as single control bus, untimely status reporting, difficult fault location, and high dependence on manual intervention.

[0092] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-bus collaborative intelligent platform integrated management and control system, comprising a VPX chassis, wherein the back panel of the VPX chassis has multiple slots, and the slots are interconnected through a multi-bus collaborative communication method; characterized in that, The backplane contains a CPU interface card, a CPU processing card, an FPGA processing card, an RF transceiver card, and an ADDA card. The CPU interface card is used to implement IP configuration and network configuration management, platform status acquisition and management, expansion control management, and automated operation and maintenance management.

2. The multi-bus collaborative intelligent platform integrated management and control system according to claim 1, characterized in that, The CPU interface card implements IP configuration and network configuration management in the following ways: After receiving IP configuration commands from external interfaces, the CPU interface card automatically verifies the legality of the commands and the completeness of the parameters, and automatically provides error messages for commands with missing parameters or incorrect formats. Subsequently, the system identifies the types of configurable IP cards and their slot distribution within the platform, matches the corresponding IP network segments and configuration parameters, sends IP configuration information to the target card via the IIC bus, controls the card to complete the local IP modification, receives the card's response signal, verifies the validity of the IP configuration through communication, synchronously records the configuration log, and feeds back the verification results to external seats. If three consecutive communication verification attempts fail, an audible and visual alarm will be triggered.

3. The intelligent platform integrated management and control system with multi-bus collaboration according to claim 1, characterized in that, The CPU interface card implements platform status acquisition and management in the following way: The CPU interface card automatically scans all boards through the IIC bus, collects basic information, health data and proprietary status information of the boards, sorts out the composition relationship of the boards and generates a visual deployment topology diagram. The CPU interface card sends routing query commands to the CPU processing card via gigabit network, receives and parses the platform routing information returned by the CPU processing card, and updates the routing topology map. The basic information of the board includes the board number, board manufacturer, board temperature, chip temperature, voltage, and current. The CPU interface card determines whether to perform online function loading based on the platform load. After issuing the loading command, the CPU processing card completes the FPGA or DSP program loading. If loading fails, the routing is automatically repaired and reloaded. If it fails three times in a row, an anomaly is reported and the cause of the fault is analyzed.

4. The multi-bus collaborative intelligent platform integrated management and control system according to claim 1, characterized in that, The CPU interface card implements extended control and management in the following way: The CPU interface card can select three time synchronization modes: external time synchronization, built-in time synchronization, and self-generated time information. It can detect the stability of the time synchronization in real time. If the current time synchronization mode is abnormal, it will automatically switch to the backup mode and send the time synchronization information to the CPU processing card for RTC synchronization. The CPU interface card collects temperature data from each board in real time and dynamically adjusts the platform fan speed to achieve a balance between heat dissipation and noise control. Specifically, when the temperature is ≤50℃, the platform fan speed is adjusted to 3000r / min; when the temperature is >50℃ and ≤70℃, the platform fan speed is adjusted to 5100r / min; and when the temperature is >70℃, the platform fan speed is adjusted to 7200r / min. The CPU interface card automatically sets the clock mode of the RF transceiver card via the SPI bus and automatically detects the clock synchronization status. When an external clock anomaly occurs, it automatically switches to the internal clock.

5. The multi-bus collaborative intelligent platform integrated management and control system according to claim 1, characterized in that, The CPU interface card achieves automated operation and maintenance management in the following way: The CPU interface card collects real-time data on platform resource usage and allocates resources accordingly. The CPU interface card provides a web interface, through which multiple users and devices can log in to the system. The system automatically identifies the identity and permission level of each user, assigns corresponding operation permissions, and records the operation logs of each user. The CPU interface card obtains the status of each board through periodic detection. When a fault is diagnosed, it automatically triggers a repair mechanism including SRIO routing and online loading. If the repair fails, the faulty board is locked, the faulty link is disconnected, and the fault situation is reported.

6. The multi-bus collaborative intelligent platform integrated management and control system according to claim 1, characterized in that, The VPX chassis features a 6-slot backplate with front and rear plug-in ports, providing interfaces for Gigabit Ethernet, 10 Gigabit Ethernet, IIC, MLVDS, SRIO, GTH, LVDS, SPI, and PCIe. The front 4-6 slots are compatible with various types of cards. Slot 4 supports high-speed memory cards, GPU processing cards, and AI inference cards; slot 5 supports GPU processing cards, AI inference cards, CPU processing cards, FPGA processing cards, and DSP processing cards; and slot 6 supports CPU processing cards, FPGA processing cards, and DSP processing cards. The CPU interface card is fixedly installed in the rear 2 slots of the VPX chassis backplate.

7. The intelligent platform integrated management and control system with multi-bus collaboration according to claim 1, characterized in that, The multi-bus collaborative communication method adopts a mixed application of IIC bus, Gigabit Ethernet, SRIO bus, MLVDS bus, SPI bus, and IO bus, with the following division of labor among the buses: 1) Gigabit Ethernet: Enables interconnection of all boards, monitors and sets board IP addresses through the web interface of the CPU interface card, and realizes 10 Gigabit Ethernet data forwarding and status management through the 1820 chip; 2) IIC Bus: Adopts the standard IIC protocol to collect basic information, health information and proprietary status information of all boards; 3) SRIO bus: Obtain platform SRIO routing, online loading status, and address information of CPU, DSP, and FPGA chips; 4) MLVDS bus: Acquires time, latitude and longitude, and satellite count information; 5) SPI bus: Used to obtain the local oscillator status of the RF transceiver card; 6) IO bus: Obtain internal and external time system and antenna connection status information of the platform.

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