A power-on timing optimization circuit for an adapted single motherboard firewall

Abstract

This invention discloses a power-on timing optimization circuit adapted for single-motherboard firewalls, comprising: an FPGA timing control module, a DC-DC power supply module, and a CPU module; the FPGA timing control module outputs an enable signal and receives a PowerGood signal from the DC-DC power supply module; then, based on built-in programmable timing parameters, it controls the output sequence and time interval of the enable signal of the DC-DC power supply module to obtain the startup timing control result of the DC-DC power supply module; and, based on the received PowerGood signal, it determines the power supply status of the corresponding power rail to obtain a power status judgment result. This invention uses FPGA to precisely control the power-on timing of multiple DC-DC power supplies, adapts to the multi-power rail requirements of the CPU, and allows for flexible adjustment of timing parameters. Combined with the PowerGood signal, it achieves power status monitoring, improving the startup reliability and versatility of the firewall solution.

Description

Technical Field

[0001] This invention belongs to the field of cybersecurity hardware design technology, and in particular relates to a power-on timing optimization circuit adapted to a single-motherboard firewall. Background Technology

[0002] With the advancement of domestic substitution, domestic CPU platforms such as Phytium and Hygon have been widely used in network security firewall equipment. Among them, the 1U / 2U single-motherboard form factor has become the mainstream design form of firewalls due to its small size and flexible deployment. As a core network security device, the startup reliability of the firewall directly determines the effectiveness of network protection, and the rationality of the CPU power-on sequence is a key prerequisite for ensuring the normal startup of the device. At present, most power-on sequence solutions provided by suppliers on the market are based on x86 platform design. Their power-on sequence and time intervals are optimized for x86 CPUs, without fully considering the power supply requirements of multiple power rails (core rail, I / O rail, memory rail) of domestic CPUs such as Phytium and Hygon. At the same time, existing power-on sequence solutions adapted to domestic CPUs mostly use fixed hardware circuits, and the timing parameters cannot be flexibly adjusted. Moreover, the power status judgment mostly relies on the PowerGood signal of the DC-DC power chip itself, but traditional solutions do not effectively combine this signal with the timing control logic.

[0003] However, the aforementioned existing technologies still have the following problems: First, the supplier's general solution does not match the strict specifications of Phytium / Hygon CPUs for the power-on sequence of each power rail. If the sequence is disordered or the time interval deviation is too large, it is very easy to cause CPU startup failure, interface abnormality, or even damage to the chip, which seriously affects the reliability of firewall operation. Second, the timing solution with fixed hardware circuit cannot flexibly adapt to the timing differences of different Phytium and Hygon CPU models. It has poor universality. When changing the CPU model, the hardware needs to be redesigned, which increases the design cost and cycle and is not conducive to mass production and product iteration. Third, the traditional solution can only simply determine whether the power supply is outputting normally. It cannot respond in time to power abnormalities caused by timing deviations and cannot actively stop the power-on process when the power state is abnormal, thus failing to effectively avoid CPU startup failure or chip damage. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a power-on timing optimization circuit adapted for single-motherboard firewalls, comprising: FPGA timing control module, DC-DC power supply module, and CPU module; The FPGA timing control module is electrically connected to the enable terminal and the PowerGood signal output terminal of the DC-DC power module, and is used to output an enable signal and receive the PowerGood signal fed back by the DC-DC power module. The power output terminals of the DC-DC power module are electrically connected to the power rails corresponding to the CPU module, respectively, to provide power to the CPU module. The FPGA timing control module is used to control the output sequence and time interval of the enable signal of the DC-DC power module according to the built-in programmable timing parameters, so as to obtain the startup timing control result of the DC-DC power module; and to determine the power supply status of the corresponding power rail according to the received PowerGood signal, so as to obtain the power status judgment result.

[0005] Preferably, the FPGA timing control module includes: Programmable logic unit (PLU) is used to store and configure timing parameters; A clock management unit, electrically connected to the programmable logic unit, is used to provide a clock reference for timing control; The enable signal output terminal is electrically connected to the enable terminal of the DC-DC power module and is used to output an enable signal according to the configuration of the programmable logic unit. The PowerGood signal input terminal is electrically connected to the PowerGood signal output terminal of the DC-DC power module and is used to receive the PowerGood signal.

[0006] Preferably, the FPGA timing control module further includes: The status judgment unit is electrically connected to the PowerGood signal input terminal. It is used to determine whether the output of the corresponding DC-DC power module is stable based on the level status of the received PowerGood signal, and obtain a stability judgment result. The enable control unit is electrically connected to the state judgment unit and the enable signal output terminal, and is used to control the enable signal output or stop the output of the corresponding DC-DC power module according to the stability judgment result.

[0007] Preferably, the DC-DC power module includes: The core rail DC-DC power module has its power output terminal electrically connected to the core rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. An IO rail DC-DC power supply module is provided, wherein the power output terminal of the IO rail DC-DC power supply module is electrically connected to the IO rail of the CPU module, the enable terminal of the IO rail DC-DC power supply module is electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and the PowerGood signal output terminal of the IO rail DC-DC power supply module is electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. The memory rail DC-DC power supply module has its power output terminal electrically connected to the memory rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module.

[0008] Preferably, the core rail DC-DC power module, the IO rail DC-DC power module, and the memory rail DC-DC power module are all DC-DC power chips with integrated PowerGood signal output terminals.

[0009] Preferably, the CPU module includes: The core rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive core rail power supply. The IO rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive IO rail power supply. The memory rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive power from the memory rail.

[0010] Preferably, the FPGA timing control module is further configured to: when the power supply status of any DC-DC power module is determined to be abnormal according to the PowerGood signal, stop outputting the enable signal to the corresponding DC-DC power module and obtain the enable stop control result.

[0011] Preferably, the FPGA timing control module is further configured to: after stopping the output of enable signals to the DC-DC power supply module with abnormal power supply status, and after the fault is cleared, output enable signals to the corresponding DC-DC power supply module again according to the preset startup sequence to obtain the restart control result.

[0012] Preferably, the programmable timing parameters built into the FPGA timing control module, for the Phytium D2000 / 8 CPU module, are preset to power on in the following order: core rail DC-DC power supply module, memory rail DC-DC power supply module, and IO rail DC-DC power supply module, with a time interval of 5-10ms.

[0013] Preferably, the programmable timing parameters built into the FPGA timing control module are used to modify them through programming to adapt to different models of Phytium CPU modules or Hygon CPU modules, thereby obtaining timing parameter modification and adaptation results.

[0014] Compared with the prior art, the present invention has the following advantages and technical effects: First, this invention precisely controls the output sequence and time interval of the enable signals of each DC-DC power module through the FPGA timing control module, and receives the PowerGood signal in real time to determine the power supply status of each power rail. This solves the problem of CPU startup failure, interface abnormality or even chip damage caused by disordered power-on sequence or time interval deviation, and significantly improves the startup reliability of the firewall.

[0015] Secondly, this invention utilizes the programmable characteristics of FPGAs, allowing for flexible adjustment of timing parameters to adapt to different Phytium / Hygon CPU models without modifying the hardware circuit. This solves the problems of poor versatility and high replacement costs of fixed hardware solutions, reducing design cycle and mass production failure rate.

[0016] Third, this invention effectively combines the PowerGood signal of the DC-DC power chip itself with timing control logic, and promptly stops the corresponding enable output when an abnormal power state is detected. This solves the problem that traditional solutions cannot actively respond to power abnormalities caused by timing deviations, prevents the CPU from starting under abnormal power supply conditions, and further ensures device safety. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the method flow according to an embodiment of the present invention. Detailed Implementation

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0020] like Figure 1As shown, this embodiment provides a power-on timing optimization circuit adapted for a single-motherboard firewall, including: FPGA timing control module, DC-DC power supply module, and CPU module; The FPGA timing control module is electrically connected to the enable terminal and the PowerGood signal output terminal of the DC-DC power module. It is used to output the enable signal and receive the PowerGood signal fed back from the DC-DC power module. The power output terminals of the DC-DC power module are electrically connected to the corresponding power rails of the CPU module to provide power to the CPU module. The FPGA timing control module is used to control the output sequence and time interval of the enable signal of the DC-DC power module according to the built-in programmable timing parameters, so as to obtain the startup timing control result of the DC-DC power module; and to determine the power supply status of the corresponding power rail according to the received PowerGood signal, so as to obtain the power status judgment result.

[0021] Furthermore, the FPGA timing control module includes: Programmable logic unit (PLU) is used to store and configure timing parameters; The clock management unit, electrically connected to the programmable logic unit, is used to provide a clock reference for timing control; The enable signal output terminal is electrically connected to the enable terminal of the DC-DC power module and is used to output an enable signal according to the configuration of the programmable logic unit. The PowerGood signal input terminal is electrically connected to the PowerGood signal output terminal of the DC-DC power supply module and is used to receive the PowerGood signal.

[0022] Furthermore, the FPGA timing control module also includes: The status judgment unit is electrically connected to the PowerGood signal input terminal. It is used to determine whether the output of the corresponding DC-DC power module is stable based on the level status of the received PowerGood signal, and obtain a stability judgment result. The enable control unit is electrically connected to the status judgment unit and the enable signal output terminal. It is used to control the enable signal output or stop the output of the corresponding DC-DC power module according to the stability judgment result.

[0023] Furthermore, the DC-DC power module includes: The core rail DC-DC power module has its power output terminal electrically connected to the core rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. The IO rail DC-DC power module has its power output terminal electrically connected to the IO rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. The memory rail DC-DC power supply module has its power output terminal electrically connected to the memory rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module.

[0024] Furthermore, the core rail DC-DC power module, the IO rail DC-DC power module, and the memory rail DC-DC power module are all DC-DC power chips with integrated PowerGood signal output terminals.

[0025] Furthermore, the CPU module includes: The core rail power input terminal is electrically connected to the power output terminal of the DC-DC power module to receive core rail power. The IO rail power input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive power from the IO rail. The memory rail power supply input is electrically connected to the power output of the DC-DC power module to receive power from the memory rail.

[0026] Furthermore, the FPGA timing control module is also used to: when the power supply status of any DC-DC power module is determined to be abnormal based on the PowerGood signal, stop outputting the enable signal to the corresponding DC-DC power module and obtain the enable stop control result.

[0027] Furthermore, the FPGA timing control module is also used to: after stopping the output of enable signals to the DC-DC power supply module with abnormal power supply status, and after the fault is cleared, to output enable signals to the corresponding DC-DC power supply module again according to the preset startup sequence, so as to obtain the restart control result.

[0028] Furthermore, the programmable timing parameters built into the FPGA timing control module, for the Phytium D2000 / 8 CPU module, have a preset power-on sequence of core rail DC-DC power supply module, memory rail DC-DC power supply module, and IO rail DC-DC power supply module, with a time interval of 5-10ms.

[0029] Furthermore, the programmable timing parameters built into the FPGA timing control module can be modified through programming to adapt to different models of Phytium CPU modules or Hygon CPU modules, thereby obtaining the timing parameter modification and adaptation results.

[0030] Furthermore, the power-on timing optimization circuit provided in this embodiment takes the FPGA timing control module as its core, outputs an enable signal to control the startup timing of the three DC-DC power modules, each DC-DC power module supplies power to the corresponding power rail of the CPU, and feeds back the power supply status to the FPGA through the PowerGood signal.

[0031] Specifically, the FPGA timing control module, as the core control unit, is electrically connected to each DC-DC power module to output precise enable signals, control the startup sequence and time interval of each DC-DC power module, and precisely match the power-on sequence requirements of the Phytium / Hygon CPU module's multiple power rails. Specifically, multiple DC-DC power modules correspond to the core rail, I / O rail, and memory rail of the Phytium / Hygon CPU module, respectively, to provide stable power supply to each power rail of the CPU. Each DC-DC power module integrates a PowerGood signal output terminal, which is electrically connected to the FPGA timing control module to provide real-time feedback on the power supply status of the corresponding power rail. Specifically, the Phytium / Hygon CPU module is electrically connected to each DC-DC power module and receives power from each power rail. Its startup timing is precisely controlled by the FPGA timing control module through the enable signal of the DC-DC power module. Specifically, the FPGA timing control module has built-in programmable timing parameters, which can flexibly adjust the enable signal output timing of each DC-DC power module according to the timing requirements of different Phytium / Hygon CPU models without modifying the hardware circuit. At the same time, the FPGA timing control module receives the PowerGood signal of each DC-DC power module in real time to determine whether the power supply of the corresponding power rail is normal. If an abnormality is detected, the enable output of the corresponding DC-DC power module is stopped in time to avoid CPU startup failure.

[0032] In the above implementation, the power-on timing of the supplier's general-purpose power supply is adapted to the x86 platform but does not match the power-on sequence requirements of Phytium / Hygon CPUs with multiple power rails, easily leading to CPU startup failure and interface abnormalities. Furthermore, existing adaptation solutions mostly use fixed timing control, which cannot flexibly adapt to different models of domestic CPUs, resulting in poor versatility. To address this, this embodiment uses an FPGA as the timing control core. It controls the startup timing of each DC-DC power module by outputting precise enable signals, matching the power-on requirements of domestic CPUs with multiple power rails. Simultaneously, it utilizes the DC-DC chip's own PowerGood signal to provide real-time feedback on the power status, preventing startup failures. Moreover, the FPGA's programmable nature allows for flexible adaptation to different models of Phytium / Hygon CPUs without modifying the hardware circuitry. This solves the problems of poor compatibility, inaccurate timing control, and low startup reliability of the supplier's general-purpose solution, achieving precise timing control of Phytium / Hygon CPUs with multiple power rails, improving firewall startup reliability and solution versatility, and adapting to the miniaturized design requirements of 1U / 2U single-motherboard systems.

[0033] This embodiment solves the pain points of startup failure and interface abnormality caused by the power-on timing mismatch of the firewall on the Phytium / Hygon CPU platform. By precisely controlling the DC-DC power enable through FPGA and monitoring the power status with PowerGood signal, the reliability of device startup is greatly improved and CPU chip damage is avoided. This embodiment of FPGA programmable design can be adapted to different models of Phytium / Hygon CPUs without modifying the hardware, improving the versatility of the solution, reducing the design cost and cycle during CPU iteration, and facilitating mass production and upgrades of products; The circuit structure of this embodiment is simple and the layout is optimized, which can meet the miniaturization requirements of 1U / 2U single motherboard, reduce the complexity of hardware design, and reduce the timing-related failure rate during mass production. This embodiment utilizes the PowerGood signal of the DC-DC chip itself, eliminating the need for additional power-on anomaly detection circuitry. It aligns with practical design, reduces hardware costs, and improves the feasibility of the solution. This embodiment is precisely adapted to domestic CPU platforms, meets the needs of domestic cybersecurity equipment, enhances product market competitiveness, and conforms to the trend of domestic substitution.

[0034] As a preferred implementation, this embodiment provides a power-on timing optimization circuit adapted to Phytium / Hygon single-motherboard firewalls, applied to a 1U single-motherboard firewall, adapted to Phytium D2000 / 8 CPUs, with the specific structure as follows: The circuit includes an FPGA timing control module, three DC-DC power supply modules, and a Phytium D2000 / 8 CPU module. The three DC-DC power supply modules correspond to the CPU's core rail (Vcore), I / O rail (Vio), and memory rail (Vmem), respectively, and utilize DC-DC chips from domestic manufacturers such as Changgong Microelectronics and Jiewat. Each chip integrates a PowerGood signal output terminal. The use of domestically produced DC-DC chips aligns with the trend of domestic substitution, ensures supply chain security, meets compliance requirements for cybersecurity equipment, and offers advantages such as high cost-effectiveness and stable supply. It is compatible with the power supply parameters of domestic CPUs, meets the firewall's 24 / 7 uninterrupted operation requirements, and fits the compact 1U single-motherboard layout.

[0035] The FPGA timing control module uses the Anlogic EF2L45BG256B low-power FPGA chip. Its core performance advantages and reasons for selection are as follows: First, it boasts low power consumption and high integration, employing advanced low-power technology with static power consumption as low as microwatts, meeting the long-term operation requirements of firewalls. Its compact 256-pin BGA package perfectly fits a 1U single-motherboard layout. Second, it offers precise timing control, with a built-in high-precision clock management unit (clock jitter ≤50ps), meeting the timing control accuracy requirements of domestic CPUs (error ≤10ms). Its strong signal driving capability eliminates the need for additional driver circuits, simplifying the design. Third, it offers strong programmability, supporting online programming and allowing flexible modification of timing parameters. It adapts to different models of domestic CPUs without hardware changes, reducing iteration costs. Fourth, it offers excellent compatibility and stability, with rich I / O interfaces, perfectly synchronized with the domestic DC-DC chip PowerGood, a wide operating temperature range (-40℃~85℃), and strong anti-interference capabilities, making it suitable for complex data center environments. Fifth, it is compatible with domestically produced equipment, with a self-sufficient and controllable supply chain, meeting the requirements for domestic production of cybersecurity equipment. The FPGA has built-in programmable timing parameters. According to the Phytium D2000 / 8 CPU specification, the preset power-on sequence is core rail → memory rail → IO rail, with a time interval of 5-10ms and an error of ≤10ms. Its output terminal is electrically connected to the enable terminal of each DC-DC power module, and the timing is started by the high and low level control module.

[0036] The PowerGood signal output of each DC-DC power module is electrically connected to the input of the FPGA timing control module to provide real-time feedback on the power rail status: a high level is output when the output voltage is stable, and a low level is output when there is overvoltage or undervoltage.

[0037] The FPGA timing control module receives each PowerGood signal in real time. If a low level is detected, it immediately stops the corresponding DC-DC power module's enable output. After the fault is cleared, it restarts according to the preset timing to avoid CPU startup failure or damage.

[0038] When adapting to the Hygon 3490 CPU, no hardware modification is required. Simply modify the FPGA timing parameters through programming and adjust the power-on sequence and time interval to meet the requirements, achieving flexible adaptation.

[0039] In this embodiment, the Anlogic EF2L45BG256B FPGA and the domestic DC-DC power module are compactly arranged to fit the 1U single motherboard space limitation, reduce line loss, improve timing control accuracy, and take into account both equipment reliability and the need for domestic production.

[0040] The improvement in this embodiment focuses on "FPGA-controlled DC-DC enable to achieve timing adaptation of multiple power rails for Phytium / Hygon CPUs". Instead of adding an additional power-on anomaly detection circuit, it uses the PowerGood signal of the DC-DC chip itself to determine the power status, which fits the actual hardware design and avoids being out of touch with the actual implementation. At the same time, it has the advantage of FPGA programmable adaptation, which is different from the existing fixed timing general solution from suppliers.

[0041] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power-on timing optimization circuit adapted for a single-motherboard firewall, characterized in that, include: FPGA timing control module, DC-DC power supply module, and CPU module; The FPGA timing control module is electrically connected to the enable terminal and the PowerGood signal output terminal of the DC-DC power module, and is used to output an enable signal and receive the PowerGood signal fed back by the DC-DC power module. The power output terminals of the DC-DC power module are electrically connected to the power rails corresponding to the CPU module, respectively, to provide power to the CPU module. The FPGA timing control module is used to control the output sequence and time interval of the enable signal of the DC-DC power module according to the built-in programmable timing parameters, so as to obtain the startup timing control result of the DC-DC power module; and to determine the power supply status of the corresponding power rail according to the received PowerGood signal, so as to obtain the power status judgment result.

2. The power-on timing optimization circuit according to claim 1, characterized in that, The FPGA timing control module includes: Programmable logic unit (PLU) is used to store and configure timing parameters; A clock management unit, electrically connected to the programmable logic unit, is used to provide a clock reference for timing control; The enable signal output terminal is electrically connected to the enable terminal of the DC-DC power module and is used to output an enable signal according to the configuration of the programmable logic unit. The PowerGood signal input terminal is electrically connected to the PowerGood signal output terminal of the DC-DC power supply module, and is used to receive the PowerGood signal.

3. The power-on timing optimization circuit according to claim 1, characterized in that, The FPGA timing control module also includes: The status judgment unit is electrically connected to the PowerGood signal input terminal. It is used to determine whether the output of the corresponding DC-DC power module is stable based on the level status of the received PowerGood signal, and obtain a stability judgment result. The enable control unit is electrically connected to the state judgment unit and the enable signal output terminal, and is used to control the enable signal output or stop the output of the corresponding DC-DC power module according to the stability judgment result.

4. The power-on timing optimization circuit according to claim 1, characterized in that, The DC-DC power module includes: The core rail DC-DC power module has its power output terminal electrically connected to the core rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. An IO rail DC-DC power supply module is provided, wherein the power output terminal of the IO rail DC-DC power supply module is electrically connected to the IO rail of the CPU module, the enable terminal of the IO rail DC-DC power supply module is electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and the PowerGood signal output terminal of the IO rail DC-DC power supply module is electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module. The memory rail DC-DC power supply module has its power output terminal electrically connected to the memory rail of the CPU module, its enable terminal electrically connected to the corresponding enable signal output terminal of the FPGA timing control module, and its PowerGood signal output terminal electrically connected to the corresponding PowerGood signal input terminal of the FPGA timing control module.

5. The power-on timing optimization circuit according to claim 4, characterized in that, The core rail DC-DC power module, IO rail DC-DC power module, and memory rail DC-DC power module are all DC-DC power chips with integrated PowerGood signal output terminals.

6. The power-on timing optimization circuit according to claim 1, characterized in that, The CPU module includes: The core rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive core rail power supply. The IO rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive IO rail power supply. The memory rail power supply input terminal is electrically connected to the power output terminal of the DC-DC power module and is used to receive power from the memory rail.

7. The power-on timing optimization circuit according to claim 1, characterized in that, The FPGA timing control module is also used to: when the power supply status of any DC-DC power module is determined to be abnormal according to the PowerGood signal, stop outputting the enable signal to the corresponding DC-DC power module and obtain the enable stop control result.

8. The power-on timing optimization circuit according to claim 1, characterized in that, The FPGA timing control module is also used to: after stopping the output of enable signals to the DC-DC power module with abnormal power supply status, and after the fault is cleared, output enable signals to the corresponding DC-DC power module again according to the preset startup sequence to obtain the restart control result.

9. The power-on timing optimization circuit according to claim 1, characterized in that, The programmable timing parameters built into the FPGA timing control module, for the Phytium D2000 / 8 CPU module, have a preset power-on sequence of core rail DC-DC power supply module, memory rail DC-DC power supply module, and IO rail DC-DC power supply module, with a time interval of 5-10ms.

10. The power-on timing optimization circuit according to claim 1, characterized in that, The programmable timing parameters built into the FPGA timing control module are used to modify them through programming to adapt to different models of Phytium CPU modules or Hygon CPU modules, thereby obtaining timing parameter modification and adaptation results.

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