Transaction order optimization for improved channel utilization

Abstract

The present disclosure relates to transaction order optimization for improved lane utilization. To achieve efficient operation, a data storage device can optimize the use of a link between the data storage device and a host device. The data storage device can change the lane configuration such that there are more transmit (Tx) lanes than receive (Rx) lanes within the link. Similarly, the data storage device can change the lane configuration such that there are more receive lanes than transmit lanes within the link. Additionally, the data storage device can activate and deactivate lanes within the link as needed. In doing so, the resulting lane configuration can be asymmetric such that there are unequal numbers of transmit lanes and receive lanes within the link. The lane configuration can be changed and asymmetric in order to optimize power consumption and reduce latency.

Description

Background Technology Invention Field

[0001] The implementation plan disclosed herein generally involves optimizing channel distribution.

[0002] Description of related technologies

[0003] Peripheral Component Interconnect (PCIe) / Non-Volatile Memory (NVM) Fast (NVMe) commands use a series of queues for submission and completion. When an input / output (I / O) command is executed, the data storage device performs a Direct Memory Access (DMA) transfer across the PCIe bus, and then completes the command by writing to a completion queue in host memory. DMA transfers utilize all available PCIe bandwidth.

[0004] Recent innovations in power management allow for the selective optimization of PCIe bandwidth by reducing channel width and speed when storage devices are not actively using bandwidth. These innovations include PCIe Gen6 L0p features, as well as previous implementations of features such as AMD's PCIe Speed ​​Power Policy (PSPP). However, current technology does not selectively allow for asymmetric bandwidth modification; instead, it prioritizes the desired ratio between direction (read or write) and transmit (Tx) to receive (Rx) to achieve maximum efficiency within a limited power envelope.

[0005] Regarding channel reconfiguration latency, once the reduction in link width with L0p is determined, the data storage device waits until the next SKP ordered set boundary (the next preset window), which in the worst case will be 1.5 microseconds away. During the upconfiguration process, latency depends on the amount of aggressive power savings implemented by the design and device. The PCIe specification anticipates these amounts to be in the microsecond range. Therefore, while channel reconfiguration has benefits, latency can be a concern.

[0006] Therefore, there is a need in this field to optimize channel configuration. Summary of the Invention

[0007] To achieve efficient operation, data storage devices can optimize the use of the link between the data storage device and the host device. The data storage device can change the channel configuration so that there are more transmit (Tx) channels than receive (Rx) channels within the link. Similarly, the data storage device can change the channel configuration so that there are more receive channels than transmit channels within the link. Additionally, the data storage device can activate and deactivate channels within the link as needed. In doing so, the resulting channel configuration can be asymmetric, resulting in unequal numbers of transmit and receive channels within the link. The channel configuration can be changed and is asymmetric to optimize power consumption and reduce latency.

[0008] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine the current and future workload of the data storage device; determine an optimal number of active channels for the workload; determine an optimal orientation of the optimal number of active channels for the workload; and modify one or more of the following: the number of active channels; or the orientation of the active channels.

[0009] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a completion queue order that is out of order of retrieval from one or more submission queues, wherein the completion queue order reduces power consumption or latency, or both, compared to the retrieval order; change one or more channels in a link between a host device and a data storage device, wherein the link includes multiple channels, and wherein the change results in an asymmetric number of transmit and receive channels; and execute commands that retrieve data in the retrieval order and execute data in the completion queue order.

[0010] In another embodiment, a data storage device includes: a component for storing data; and a controller coupled to the component for storing data, wherein the controller is configured to: change the order of command execution; change the channel configuration between the data storage device and a host device, wherein the channel configuration is changed to an asymmetric arrangement of a transmit channel and a receive channel; and execute commands, wherein the controller includes a completion queue control module, a workload analysis module, and an LOP modification control module. Attached Figure Description

[0011] To gain a more detailed understanding of the features of this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0012] Figure 1 This is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device for a host device, according to certain embodiments.

[0013] Figure 2 It is a block diagram of a system based on an implementation plan.

[0014] Figure 3 It is a block diagram of a system based on another implementation scheme.

[0015] Figure 4This is a flowchart illustrating the channel modification determined according to an implementation scheme.

[0016] Figure 5 This is a flowchart illustrating the channel modification determined according to an implementation scheme.

[0017] Figure 6 This is a flowchart illustrating the channel modification determined according to an implementation scheme.

[0018] Figure 7 This is a flowchart illustrating the channel modification determined according to an implementation scheme.

[0019] Figure 8 This is a flowchart illustrating the channel modification determined according to an implementation scheme.

[0020] Figure 9 This is a schematic diagram of a memory system with a four-channel link according to one implementation scheme.

[0021] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0022] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the features and elements described below, whether or not they relate to different embodiments, is contemplated for implementation and practice of this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit this disclosure. Therefore, the following aspects, features, embodiments, and advantages are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0023] To achieve efficient operation, data storage devices can optimize the use of the link between the data storage device and the host device. The data storage device can change the channel configuration so that there are more transmit (Tx) channels than receive (Rx) channels within the link. Similarly, the data storage device can change the channel configuration so that there are more receive channels than transmit channels within the link. Additionally, the data storage device can activate and deactivate channels within the link as needed. In doing so, the resulting channel configuration can be asymmetric, resulting in unequal numbers of transmit and receive channels within the link. The channel configuration can be changed and is asymmetric to optimize power consumption and reduce latency.

[0024] Figure 1 This is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104, according to certain embodiments. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / disk-only (RAID) that collectively serve as a large-capacity storage device for the host device 104.

[0025] Host device 104 can store data in one or more storage devices, such as data storage device 106, and / or retrieve data from said one or more storage devices. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a wide range of devices, including: computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, telephone receivers (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.

[0026] Host DRAM 138 may optionally include a host memory buffer (HMB) 150. HMB 150 is a portion of host DRAM 138 allocated to data storage device 106 for the dedicated use of controller 108 of data storage device 106. For example, controller 108 may store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, etc., in HMB 150. In other words, HMB 150 may be used by controller 108 to store data that would typically be stored in volatile memory 112, buffer 116, or internal memory of controller 108 such as static random-access memory (SRAM). In an example where data storage device 106 does not include DRAM (i.e., optional DRAM 118), controller 108 may utilize HMB 150 as DRAM for data storage device 106.

[0027] Data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and optional DRAM 118. In some examples, data storage device 106 may include additional components, not shown for clarity. Figure 1 Additional components are shown. For example, data storage device 106 may include a printed circuit board (PCB) to which components of data storage device 106 are mechanically attached, and the PCB includes conductive traces that enable isoelectric interconnection of components of data storage device 106. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDDs or SSDs), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), extended PCI (PCI-X), and fast PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini-cards, mini PCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of host device 104.

[0028] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, High Speed ​​Non-Volatile Memory (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to controller 108, providing an electrical connection between host device 104 and controller 108, enabling data exchange between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0029] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data from controller 108 and a message instructing the memory cell to store data. Similarly, a memory cell may receive a message from controller 108 instructing the memory cell to retrieve data. In some examples, each memory cell in the memory cell may be referred to as a die. In some examples, NVM 110 may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0030] In some examples, each memory cell may include any type of non-volatile memory device such as: flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.

[0031] NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory device may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor in each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into multiple dies, each of which includes multiple physical blocks or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each page may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-cell (SLC), multi-cell (MLC), three-cell (TLC), or four-cell (QLC) device. Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0032] Power supply 111 can provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device such as host device 104 to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 may include one or more power storage components configured to provide power to one or more components when operating in a shutdown mode, such as when power reception from external devices is stopped. In this way, power supply 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the electrical energy that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the electrical energy stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0033] Controller 108 may use volatile memory 112 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 before it is written to NVM 110. Figure 1As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, optional DRAM 118 can be used to store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. In some examples, data storage device 106 does not include optional DRAM 118, making data storage device 106 DRAM-free. In other examples, data storage device 106 includes optional DRAM 118.

[0034] Controller 108 can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from and / or writing data to NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data to NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operating characteristic of storage system 100 and store at least one operating characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores the data associated with the write command in internal memory or write buffer 116 before sending the data associated with the write command to NVM 110. Controller 108 may include circuitry or a processor configured to execute programs for operating data storage device 106.

[0035] Controller 108 may include optional second volatile memory 120. Optional second volatile memory 120 may be similar to volatile memory 112. For example, optional second volatile memory 120 may be SRAM. Controller 108 may allocate a portion of the optional second volatile memory to host device 104 as a controller memory buffer (CMB) 122. CMB 122 may be directly accessed by host device 104. For example, host device 104 may utilize CMB 122 to store one or more submission queues that are normally maintained in host device 104, rather than maintaining those one or more submission queues in host device 104. In other words, host device 104 may generate commands and store the generated commands, with or without associated data, in CMB 122, wherein controller 108 accesses CMB 122 to retrieve the stored generated commands and / or associated data.

[0036] As described above, the link between the data storage device and the host device can be configured differently to improve performance. For example, the data storage device can enter a low-power state to provide better power on the link. Using L0p, the data storage device can dynamically adjust according to the number of active channels in the system.

[0037] This paper addresses the problem of optimizing performance and power while considering both the current state of the link and the data to be transmitted on the link, resulting in better power and performance outcomes. Previously, there was no command reordering based on link state. This disclosure relates to command reordering in execution and data transmission, taking into account both the current state of the link and pending commands in the system. Based on both state and pending commands, better power and performance outcomes are achieved.

[0038] Currently, the L0p feature is defined in the PCIe standard and can have the same number of active channels for Tx and Rx. For example, if the maximum number of channels is four, there are up to four channels for Tx and up to four channels for Rx. If the data storage device decides to reduce the number of channels, the data storage device cannot have, for example, four channels for Tx and only two channels for Rx. This would be an asymmetric mode, which is not currently supported by the PCIe standard but is expected to be supported by the PCIe standard in the near future. Before the PCIe standard supports asymmetric channels, if the data storage device decides to reduce the number of channels to two, the number of channels will be the same for Tx and Rx. For the purposes of this disclosure, it is assumed that the PCIe standard supports asymmetric modes.

[0039] As an example, if a read workload is running in the system, such as for artificial intelligence (AI) purposes, there is an intensive read workload. Due to the intensive read workload, the data storage device needs to read large amounts of data from the storage device and write the read data to the host device. Therefore, it would be beneficial to increase the number of Tx channels and decrease the number of Rx channels, since most of the business will be Tx on the link interface.

[0040] In most cases, the data storage device needs to write large amounts of data to the host device and therefore only needs to handle read commands. Assume that, for this example, handling read commands is the workload, and the host device also occasionally handles write commands. Furthermore, assume a single active channel is configured for Rx and a channel with one pending command.

[0041] If the data storage device needs to write data to the memory device, the controller needs to read some content from the host interface. In the current example, there is only one port with one channel on the host interface used for the Rx side. However, there are pending write commands and many other pending read commands in the system. Therefore, in a specific example, the controller might decide to reorder command execution and prioritize read commands until another write command is available, then execute the write command for better performance. For write commands, the controller will need to increase the number of channels used for Rx, and it's best to aggregate write commands rather than frequently switching channel configurations, as switching takes time. Therefore, the idea at a very high level is to support the workload in the system, but consider the state of the channels and minimize the number of channel switches. The motivation is to minimize switching for better performance, better power, etc. This process involves considering the current state of the links, pending commands in the device controller, and expectations or predictions about when the host device will transmit the next read or write command in the system. The controller will thus determine the optimal timing, for example, to increase the number of active channels and / or switch channels from Rx to Tx, or vice versa.

[0042] This paper discusses methods for improving the order of completion queues to optimize power consumption and reduce latency overhead from active channel polarity modification. As part of the implementation, a system is described comprising a data storage device and a host device that introduces novel PCIe asymmetric L0p features, allowing unequal numbers of active channels per Rx and Tx. More specifically, the number of channels in a link can be modified based on the expected workload to optimize performance, power consumption, and reconfiguration latency.

[0043] As an example, if a "burst" throughput boost is used when reading AI models from a memory device (e.g., NAND), redirecting most channels to Tx will improve performance at the cost of power consumption. Previously, the order in which storage commands were executed did not take into account the number and direction of active channels. Additionally, Rx and Tx require an equal number of channels, making a reduction in the number of channels possible, but it will be the same for both Rx and Tx. The primary goal of this feature reduction is to reduce power consumption when the data storage device is not in full interaction.

[0044] This disclosure relates to improving transmission sequencing to optimize asymmetric channel counting for a given power envelope for optimized transmission. The controller sequences transactions in the NVMe completion queue to optimize power consumption and reduce latency overhead from modifications to the number of active channels. As part of this disclosure, a system comprising storage devices and host devices is also described, utilizing and extending new PCIe 6.0 L0p features to modify the number of channels based on the expected workload to optimize performance, power consumption, and latency. It should be noted that asymmetric L0p is a feature under discussion in the standard, and this disclosure assumes that this feature will eventually be developed and standardized. The proposed system estimates the current completion rate and the expected completion queue population in the completion queue control module and reorders command execution and completion in a manner that reduces the number of switches to the number of active channels and their corresponding polarities.

[0045] Figure 2 It is a block diagram of a system based on an implementation plan. Figure 3 It's for adding add-ons. Figure 2 A block diagram of the system. (e.g.) Figure 2 and Figure 3 As shown, there is a host device 202 and a storage controller 204. Figure 2 and Figure 3 The completion queue 206 is shown in the accompanying image. Figure 2 Also shown is a completion queue control module 208 located in storage controller 204. The completion queue 206 is used when the controller needs to send completion information to host device 202. Controller 204 can determine to reorder command execution based on the current state of the link and the anticipated next workload in system 200.

[0046] In one implementation, reconfiguration latency is also taken into account, allowing modification of command execution order and completion, as well as the number of active channels, based on workload, power consumption, and requested throughput. Figure 3 The workload analysis module 308 is shown. A L0p modification control module 310 is present in the storage controller 204, and another L0p modification control module 312 is present in the host device. The workload analysis module 308 predicts what the next workload might be, leading to the optimal aggregation of increasingly more commands, especially write commands, before executing write commands. There will be interaction with the L0p modification control module 310, which determines when to increase or possibly decrease the number of channels on the interface. The number of channels will depend on the current workload in system 300.

[0047] exist Figure 3In the storage controller 204, the workload analysis module 308 monitors the current and expected workload, power consumption, and requested throughput. The workload analysis module 308 then transmits the determined information to the L0p modification control module 310 in the storage controller 204. The workload and configuration can then be considered to order transactions accessing host memory.

[0048] The L0p modification control module 310 analyzes overall conditions that do not include the workload (i.e., power consumption, host throughput requirements, and / or special priority conditions). The L0p modification control module 310 also considers reconfiguration latency and determines whether changes to the channel configuration are beneficial. Based on this decision, the L0p modification control module 310 initiates a handshake with host device 202 and L0p modification control module 312, and schedules the changes to the next switching window.

[0049] Figure 4 This is a flowchart 400 illustrating channel modification determination according to one implementation. Initially, the passage of time or a change in workload is detected. The workload analysis module will check the current and future workloads in the queue at box 402 and interact with the L0p modification control module, which takes the current conditions into account, at box 404. At box 406, the output will be the optimal number and direction of active channels best suited for use given the asymmetric characteristics of L0p. In this case, the controller may decide to wait on the switch for a period of time and not to make the modification now, but rather, for example, within one second from now. Simultaneously, the controller will reorder command execution to maximize the window. If modification is needed at box 408, the controller will interact with the host device to make a switchover at box 410.

[0050] The original goal of L0p was to reduce the number of active channels in order to save power when channels are not needed. However, the number of Tx channels is equal to the number of Rx channels. This disclosure utilizes the proposed extension to L0p, which enables the asymmetric use of Tx and Rx channels to optimize bandwidth while saving power. For example, when reading a large language model (LLM) from a memory device (i.e., flash memory) via host DRAM for inference, the read volume is very large, and it is necessary to use the LLM as quickly as possible.

[0051] In another example, for an LLM serving as a write-intensive AI workload, the controller will periodically have write-backs for updates. Therefore, it is more advantageous to handle existing writes by aggregating them and then performing them all at once, in order to minimize the number of exchanges in the link. If additional power consumption is permitted, the system can utilize this disclosure and thus increase the number of active Tx channels.

[0052] Figure 5This is a flowchart 500 illustrating channel modification determination according to one implementation. Initially, the controller determines at block 502 that multiple commands exist in one or more submission queues, and modifies the channel configuration in at least one link 504 based on the contents of the submission queues. The controller also determines at block 506 whether the commands should be reordered for execution, then executes the commands at block 508 and delivers the results to the completion queue, and subsequently repeats the process.

[0053] Figure 6 This is a flowchart 600 illustrating channel modification determination according to one implementation. Initially, the controller determines at block 602 that multiple commands exist in one or more submission queues, and then at block 604 determines whether the current channel configuration is optimal. If not, the channel configuration is changed at block 608; but if it is optimal, the command is executed at block 606 and the result is delivered to the completion queue, after which the process is repeated.

[0054] Figure 7 This is a flowchart 700 illustrating channel modification determination according to one implementation. Initially, at block 702, the controller determines the current and expected workload. If reconfiguring the channel in the link at block 704 is not beneficial, then at block 708 it is determined whether reordering commands is beneficial. If reconfiguring the channel in the link at block 704 is beneficial, then the channel is reconfigured at block 706, followed by the determination at block 708. If there is benefit at block 708, then commands are reordered at block 710, followed by command execution at block 712 and the repetition of this process. If reordering commands at block 708 is not beneficial, the process continues to block 712. Note that blocks 704 and 708, and therefore blocks 706 and 710, can occur in any order or even simultaneously.

[0055] Figure 8 This is a flowchart 800 illustrating a channel modification determined according to an implementation scheme. Figure 8 In this scenario, channel modifications can be scheduled to occur at a later time point because the expected workload is altered due to future commands in the queue, taking into account conditions such as power consumption and read latency. The L0p modification block will set a timer to transmit the channel modification command at a later time, most likely within a few microseconds or tens of microseconds. More specifically, the channel modification timing may ideally be switched to increase, for example, the number of channels later, as the controller detects a point where the workload will increase and writes will be more intensive. Therefore, based on this, the controller will determine the timing of the modification.

[0056] At box 802, the controller predicts a workload change and then determines at box 804 whether the workload change will require a channel configuration change. If no, no change is made at box 806. If yes at box 804, a timer is set at box 808, and the controller waits for the timer to expire at box 810. Once the timer expires, the channel configuration is changed at box 812.

[0057] Figure 9 This is a schematic diagram of a memory system 900 with a four-channel link 914 according to one embodiment. In the memory system 900, there is a host device 902 coupled to a data storage device 904. Figure 9 The diagram shows a single link 914 with four channels 906, 908, 910, and 912. Based on the asymmetric channel configuration, any combination of channels is possible, such as channel 906 being Rx and channels 908, 910, and 912 being Tx, and vice versa. A symmetric channel configuration is also possible.

[0058] In operation, the controller in data storage device 904 retrieves commands from one or more submission queues, which may reside within host device 902 or data storage device 904, such as within a CMB. Based on this retrieval, the commands will be in a retrieved or fetched order, which is the default expected execution order. The controller then analyzes the retrieved commands and performs several actions. One of these actions is to determine or predict what additional commands will follow. For example, whether more read or write commands will follow. Additionally, the controller will determine the power consumption of executing the commands, when the channel configuration should be changed to execute commands in the retrieved order, and the latency of the channel configuration change. The controller will then decide whether to begin executing commands, reorder commands in a more efficient order, or wait for commands to be executed. Based on this decision, the controller will set the optimal channel configuration for the link, which may be asymmetric between Rx and Tx, and begin execution or wait (and then execute).

[0059] By reordering the execution of host transfers, power consumption is reduced while maintaining throughput.

[0060] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine the current and future workload of the data storage device; determine an optimal number of active channels for the workload; determine an optimal direction for the optimal number of active channels for the workload; and modify one or more of the following: the number of active channels; or the direction of the active channels. The direction of the active channels is asymmetric in number. The controller is configured to reorder commands retrieved from a submission queue. The controller is configured to determine the time to perform the modification. The controller is configured to set a timer after the determined time. The controller includes a completion queue control module, a workload analysis module, and an LOP modification control module. The controller is configured to return executed commands to the completion queue out of order of the order in which commands are received in the submission queue. The controller is configured to determine that the read volume will exceed a threshold, and wherein the controller is configured to increase the number of transmit channels based on the determination. The number of transmit channels in the link is asymmetric to the number of receive channels. The controller is configured to sort transactions in the completion queue to optimize power consumption and reduce latency.

[0061] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine a completion queue order out of order of retrieval from one or more submission queues, wherein the completion queue order reduces power consumption or latency, or both, compared to the retrieval order; change one or more channels in a link between a host device and the data storage device, wherein the link includes multiple channels, and wherein the change results in an asymmetric number of transmit and receive channels; and execute commands for retrieval in the retrieval order and execution in the completion queue order. The controller is configured to monitor the current and expected workload of the data storage device. The controller includes a L0p modification control module configured to initiate a handshake with a host device L0p modification control module. The controller L0p modification control module analyzes overall conditions excluding workload. Overall conditions excluding workload include the expected power consumption and throughput of the host device. Overall conditions excluding workload include reconfiguration latency and are configured to determine whether to change the channel configuration of the link. The controller is configured to estimate the current completion rate and the expected completion queue population in the completion queue control module.

[0062] In another embodiment, a data storage device includes: a component for storing data; and a controller coupled to the component for storing data, wherein the controller is configured to: change the order of command execution; change the channel configuration between the data storage device and a host device, wherein the channel configuration is changed to an asymmetric arrangement of transmit and receive channels; and execute commands, wherein the controller includes a completion queue control module, a workload analysis module, and a LOP modification control module. The LOP modification control module determines the channel configuration based on the changed order of command execution. The workload analysis module examines the current and future workloads in one or more submission queues, and wherein the completion queue control module estimates the current completion rate and the expected completion queue population.

[0063] While the foregoing describes an embodiment of this disclosure, other and additional embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: Memory devices; and A controller, coupled to the memory device, wherein the controller is configured to: Determine the current and future workload of the data storage device; Determine the optimal number of active channels for the workload; Determine the optimal orientation of the optimal number of active channels for the workload; and Modify one or more of the following: The number of activity channels; or The direction of the activity passage.

2. The data storage device according to claim 1, wherein the directions of the active channels are asymmetrical in number.

3. The data storage device of claim 1, wherein the controller is configured to reorder commands retrieved from the submission queue.

4. The data storage device of claim 1, wherein the controller is configured to determine the time for performing the modification.

5. The data storage device of claim 4, wherein the controller is configured to set a timer after a determined time.

6. The data storage device according to claim 1, wherein the controller includes a queue control module, a workload analysis module, and an LOP modification control module.

7. The data storage device of claim 1, wherein the controller is configured to return executed commands to the completion queue out of order of receiving commands in the submission queue.

8. The data storage device of claim 1, wherein the controller is configured to determine that the number of reads will be greater than a threshold, and wherein the controller is configured to increase the number of transmission channels based on the determination.

9. The data storage device according to claim 8, wherein the number of transmitting channels within the link is asymmetrical to the number of receiving channels.

10. The data storage device of claim 1, wherein the controller is configured to sort transactions in the completion queue to optimize power consumption and reduce latency.

11. A data storage device, the data storage device comprising: Memory devices; and A controller, coupled to the memory device, wherein the controller is configured to: Determine a completion queue order that is out of order of retrieval from one or more submission queues, wherein the completion queue order reduces power consumption or latency, or both, compared to the retrieval order. Change one or more channels in the link between the host device and the data storage device, wherein the link includes multiple channels, and wherein the change results in an asymmetric number of transmit channels and receive channels; as well as Execute commands that retrieve data in the stated retrieval order and execute data in the stated completion queue order.

12. The data storage device of claim 11, wherein the controller is configured to monitor the current and expected workload of the data storage device.

13. The data storage device of claim 11, wherein the controller includes an LOP modification control module, the LOP modification control module being configured to initiate a handshake with the host device's LOP modification control module.

14. The data storage device of claim 13, wherein the controller L0p modifies the overall conditions of the control module, excluding the workload.

15. The data storage device of claim 14, wherein the overall conditions excluding the workload include the power consumption and throughput expected by the host device.

16. The data storage device of claim 15, wherein the overall condition excluding the workload includes reconfiguration latency and is configured to determine whether to change the channel configuration of the link.

17. The data storage device of claim 11, wherein the controller is configured to estimate the current completion rate and the expected completion queue population in the completion queue control module.

18. A data storage device, the data storage device comprising: Components used for storing data; and A controller, coupled to the component for storing data, wherein the controller is configured to: Change the order in which commands are executed; The channel configuration between the data storage device and the host device is changed, wherein the channel configuration is changed to an asymmetric arrangement of the transmit channel and the receive channel; as well as The controller executes commands, including a queue control module, a workload analysis module, and an LOP modification control module.

19. The data storage device of claim 18, wherein the L0p modification control module determines the channel configuration based on the order in which commands are executed.

20. The data storage device of claim 18, wherein the workload analysis module examines current and future workloads in one or more submission queues, and wherein the completion queue control module estimates the current completion rate and the expected completion queue population.

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