A solid state disk reconstruction method, test fixture and host link verification system

Abstract

This application relates to the field of solid-state drive (SSD) technology, and discloses an SSD reconstruction method, a test fixture, and a host link verification system. The method configures test firmware on the controller chip when the non-volatile storage medium of the target SSD fails or is unreliable, but the controller chip and PCIe interface are still functional. During the power-on initialization phase, the test firmware enters the test endpoint startup process, generates a logical test namespace that does not correspond to the actual physical storage blocks, establishes an isolation table, and prohibits host-side commands from establishing data mapping relationships with the non-volatile storage medium. Host-side PCIe / NVMe test commands are diverted to the internal test data path to generate or verify test data, enabling the retired SSD to run as a test endpoint for server link verification. This application utilizes test firmware to reuse retired SSDs whose non-volatile storage medium has failed, but whose controller and interface functions are intact, achieving resource reuse of electronic waste.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and in particular to an SSD reconstruction method, a test fixture, and a host link verification system. Background Technology

[0002] Enterprise-grade solid-state drives (SSDs) typically consist of a controller chip, a PCIe interface, and non-volatile storage media such as NAND flash memory. As the number of erase and write cycles increases or the operating environment changes, the non-volatile storage media will gradually exhibit problems such as an increase in bad blocks, a decrease in data retention capability, an increase in uncorrectable errors, read / write timeouts, error verification failures, or an increase in media integrity errors. Ultimately, this makes the SSD unsuitable for continued use as a reliable storage device.

[0003] On the other hand, during the production verification of server motherboards, hard drive backplanes, PCIe slots, cables, retimers, switches, or complete systems, it is usually necessary to connect PCIe / NVMe endpoints capable of performing link training, device enumeration, command response, and data transmission to verify link speed, link width, read / write stress, data consistency, hot-plug recovery, and link reset recovery. Currently, the industry typically uses fully functional NVMe SSDs or dedicated PCIe / NVMe testing equipment to achieve the above verification: using fully functional SSDs will continuously consume usable media lifespan during high-intensity stress testing; using dedicated testing equipment requires additional procurement, maintenance, and calibration.

[0004] Therefore, there is an urgent need for a technical solution that can separate the still-functioning controller chip and PCIe / NVMe communication endpoint capabilities in a retired solid-state drive from the failed storage path when the non-volatile storage medium has failed or become unreliable, and stably reconstruct it into a test fixture for server link verification. Summary of the Invention

[0005] This application provides a method, test fixture, and system for reconstructing a solid-state drive into a test fixture.

[0006] Firstly, this application provides a solid-state drive reconstruction method, including:

[0007] Obtain a target solid-state drive, the target solid-state drive including a main controller chip, a PCIe interface and a non-volatile storage medium, the main controller chip and the PCIe interface being in a working state; The main control chip is configured with test firmware, which is configured to: block data access between host-side conventional storage commands and the non-volatile storage medium, and divert host-side PCIe / NVMe test commands to an internal test data path; the internal test data path generates or verifies test data so that the target solid-state drive can be used as a test fixture to verify the host-side PCIe link.

[0008] In conjunction with the first aspect, in one possible implementation, the shielding of data access between conventional storage commands on the host side and the non-volatile storage medium includes: During the power-on initialization phase of the target solid-state drive, the test endpoint startup process begins. In the test endpoint startup process, the test firmware generates a logical test namespace that does not correspond to the real physical storage block, and establishes an isolation table for the non-volatile storage medium. The real physical storage block is the smallest operating unit inside the non-volatile storage medium. The test firmware uses the isolation table to block the data mapping relationship between the host-side regular storage commands and the non-volatile storage medium.

[0009] In conjunction with the first aspect, in one possible implementation, the test firmware blocks the data mapping relationship between the host-side regular storage commands and the non-volatile storage medium based on the isolation table, including: The isolation table records the channel number, chip select number, logic cell number, bare die number, plane number, and corresponding isolation status of the non-volatile storage medium. The test firmware blocks storage access requests at the command scheduling layer based on the isolation table, prohibits the corresponding channel or chip select from entering a valid access state at the channel control layer, and prohibits read retry, bad block remapping, or erase recovery processes for the non-volatile storage medium at the anomaly recovery layer.

[0010] In conjunction with the first aspect, in one possible implementation, the logical test namespace has a preset capacity, a preset block size, a preset queue depth, or a preset namespace identifier, and the preset capacity is not mapped to the actual physical storage block of the non-volatile storage medium; for formatting commands, erase commands, secure erase commands, or commands that change the actual storage state sent by the host side, the test firmware returns a state of prohibiting execution, not supporting, or refusing execution in test endpoint mode.

[0011] In conjunction with the first aspect, in one possible implementation, the endpoint availability screening of retired solid-state drives is further included before the step of obtaining the target solid-state drive; The endpoint availability screening includes determining whether the non-volatile storage medium is in a failed or unreliable state based on health information logs, media error logs, vendor logs, erase / write cycles, number of bad blocks, number of uncorrectable errors, read / write timeouts, remaining lifetime information, or data retention test results.

[0012] In conjunction with the first aspect, in one possible implementation, the entry conditions for the test endpoint startup process include one or more of the following: endpoint mode flag, fixture identification information, test firmware version flag, non-volatile storage medium status, main control chip working status, PCIe interface working status, or host-side entry instruction; when the entry conditions are met, the test firmware skips or terminates the normal storage startup process and establishes the test endpoint configuration before flash conversion layer initialization, mapping table loading, and standard storage namespace mounting.

[0013] In conjunction with the first aspect, one possible implementation involves offloading host-side PCIe / NVMe test commands to an internal test data path, including: The test firmware establishes a test command context for PCIe / NVMe test commands issued by the host side, and selects the corresponding internal test data path based on the test command context. The internal test data path includes one or more of the following: the main control chip internal buffer, volatile memory, fixed test data generation module, address-related test data generation module, pseudo-random test data generation module, DMA loopback path, circular read / write buffer path, or error injection module.

[0014] Secondly, this application provides a solid-state drive (SSD) test fixture, including an SSD circuit board, a main control chip disposed on the SSD circuit board, a PCIe interface connected to the main control chip, a non-volatile storage medium in a failed or unreliable state, and test firmware configured on the main control chip; the test firmware is configured to block data access between host-side conventional storage commands and the non-volatile storage medium, and to divert host-side PCIe / NVMe test commands to an internal test data path.

[0015] Thirdly, this application provides a host link verification system, a server to be verified, and the solid-state drive test fixture described in the second aspect, wherein the solid-state drive test fixture is inserted into the communication interface of the server to be verified; the server to be verified runs a test control program to verify the host link via the solid-state drive test fixture.

[0016] In conjunction with the third aspect, in one possible implementation, the test control program performs link training, continuous read / write, mixed read / write, queue depth stress, link reset, hot-plug recovery, server restart recovery, or error injection tests according to the test case table, and generates a link verification report; the link verification report records endpoint mode information, isolation status information, logical test namespace parameters, test case parameters, link negotiation results, data consistency results, or link error statistics.

[0017] Compared with the prior art, the beneficial effects of this application are as follows: by testing the firmware to isolate the failed storage medium in the power-on initialization, command routing and data response paths, retired solid-state drives whose non-volatile storage media has failed or become unreliable, but whose main control chip and PCIe interface can still work, can be reused and reconstructed into test fixtures for host-side PCIe link verification, which solves the problem of electronic waste disposal and is in line with the development trend of green computing and circular economy. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a method for reconstructing a retired solid-state drive into a test fixture according to the present invention; Figure 2 This is a schematic diagram of the system architecture for the solid-state drive test fixture connected to the server in this invention. Figure 3 This is a schematic diagram of the test process for the host link verification system of the present invention.

[0019] Explanation of reference numerals in the attached figures: 100. Server to be verified; 110. Server motherboard; 120. PCIe slot or backplane; 130. Server-side PCIe link; 200. Target solid-state drive; 210. Solid-state drive circuit board; 220. PCIe interface; 230. Controller chip; 240. Non-volatile storage medium. Detailed Implementation

[0020] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that the solid-state drive (SSD) in this application is not limited to NVMe SSDs, but can also be any type of SSD device that uses a PCIe interface, is equipped with a controller chip, and uses non-volatile storage media. The non-volatile storage media 240 is not limited to NAND flash memory, but can also be other non-volatile storage media uniformly managed by the controller chip 230. This application uses NAND flash memory as an example for illustrative purposes, and this description does not constitute a limitation on the type of non-volatile storage media in this application. Furthermore, the test endpoint in this application refers to an endpoint device that can be enumerated, identified, and accessed as a host-side PCIe / NVMe communication object, and can normally respond to host test commands. Its core feature is that the test interaction and data response process does not rely on the non-volatile storage media 240 to achieve reliable data storage function, does not require restoring the SSD's regular storage services, and only reuses the native communication endpoint capabilities of the controller chip 230 and the PCIe interface 220 to complete the link test.

[0022] Example 1 Combination Figure 1 As shown in the figure, this embodiment details the complete implementation method of reconstructing a retired solid-state drive (SSD) into a test fixture. The overall transformation scheme consists of two core steps: endpoint availability screening of the retired SSD and test firmware reconstruction configuration. The specific steps are as follows: S1. Perform endpoint availability screening on retired solid-state drives to obtain target solid-state drives 200; the target solid-state drive 200 includes a main controller chip, a PCIe interface and a non-volatile storage medium, the non-volatile storage medium is in an invalid or unreliable state, and the main controller chip and the PCIe interface are in a working state. S2. Clear the original storage firmware inside the main control chip 230 and configure test firmware on the main control chip 230. The test firmware is configured to: block data access between the host-side conventional storage commands and the non-volatile storage medium, and divert host-side PCIe / NVMe test commands to the internal test data path; the internal test data path generates or verifies test data so that the target solid-state drive can be used as a test fixture to verify the host-side PCIe link.

[0023] In the screening process of step S1 above, the retired solid-state drives (SSDs) undergo dual endpoint availability screening. Firstly, it determines whether the non-volatile storage medium 240 is in a failed or unreliable state. Secondly, it verifies whether the controller chip 230 and PCIe interface 220 are capable of normal operation. Only retired SSDs whose non-volatile storage medium 240 is in a failed or unreliable state, and whose controller chip 230 and PCIe interface 220 are in a working state, are considered target SSDs 200.

[0024] The failure and unreliability determination of the non-volatile storage medium 240 can be achieved by reading the solid-state drive's health information log, media error log, manufacturer log, write / erase cycles, number of bad blocks, number of uncorrectable errors, number of media integrity errors, read / write timeouts, remaining lifetime information, or data retention test results. Based on these parameters, it can be determined whether the non-volatile storage medium has failed or is no longer suitable for use as a reliable storage medium. When the write / erase cycles exceed the design lifetime, uncorrectable errors continue to increase, read / write timeouts occur frequently, media integrity failures occur repeatedly, or data retention time does not meet the standard, the non-volatile storage medium 240 can be considered to have failed or is no longer suitable for use as a reliable storage medium. It should be noted that the failure determination of the non-volatile storage medium does not require a uniform fixed threshold. The determination rules can be customized according to the main control platform, NAND flash memory type, and enterprise business scenario. The rules can adopt single-indicator threshold determination or multi-indicator joint determination.

[0025] After determining the media status, it is necessary to further determine whether the main control chip 230 and the PCIe interface 220 are still in a working state. A working state can be confirmed in the following ways: the target solid-state drive 200 can complete PCIe link training, can be enumerated by the host as a PCIe or NVMe device, can respond to at least one management command, can return basic device information, or can reach the preset link speed and link width. Only when the non-volatile storage medium 240 is in a failed or unreliable state, and the main control chip 230 and the PCIe interface 220 are in a working state, can the retired solid-state drive be identified as the target solid-state drive 200 and enter the subsequent reconstruction and transformation process.

[0026] In the firmware reconstruction process of step S2 above, after obtaining the target solid-state drive 200, the original factory-stored firmware in the main controller chip 230 is first cleared, and test firmware is then burned into the main controller chip 230. During the reconstruction process, the test firmware can be written to the main controller chip 230 through firmware burning tools, maintenance tools, debugging interfaces, bootloaders, remote firmware update mechanisms, or other permitted configuration methods. After the firmware burning is completed, fixture identification information can be written to or associated with the target solid-state drive 200. This fixture identification information may include the original solid-state drive model, serial number, main controller chip model, test firmware version, media failure level, supported link speed, supported link width, modification batch, and the most recent warehouse entry test result, etc., which facilitates subsequent batch management and status traceability of fixtures.

[0027] In large-scale production and equipment maintenance scenarios, multiple retired solid-state drives (SSDs) can be screened and reconstructed to obtain multiple SSD test fixtures. Each SSD test fixture can be written with or associated with fixture identification information. The fixture identification information may include the original SSD model, serial number, controller chip model, non-volatile storage media failure level, test firmware version, supported PCIe link speed, supported link width, modification batch, calibration results, cumulative test time, hot-plug count, and the most recent test result, enabling fine-grained management of the fixture's usage status.

[0028] To ensure the consistency and reliability of batch test fixtures, this application establishes a two-tier batch management mechanism of inbound testing and periodic review. Inbound testing is the core step for fixture admission, encompassing power-on enumeration testing, endpoint mode confirmation testing, isolation table activation testing, internal test data path consistency testing, continuous read / write stress testing, link reset recovery testing, and hot-swap recovery testing. Only when the main control chip 230, PCIe interface 220, logical test namespace, isolation table, and internal test data path all meet preset conditions is a retired solid-state drive (SSD) marked as a usable test fixture. Retired SSDs that cannot complete PCIe link training, cannot stably respond to management commands, cannot establish a logical test namespace, or cannot block access from non-volatile storage media 240 are not included in the usable fixture library.

[0029] Periodic review is a routine maintenance step for the fixture. Before each use, the test control program reads the fixture identification information, endpoint mode information, and the most recent test results. Based on the cumulative test time, changes in error statistics, hot-plug counts, link degradation records, and endpoint logs, it determines whether recalibration or decommissioning is required. Periodic review records can be stored on the server where the test control program resides, in an external database, or in the fixture management system, and do not rely on non-volatile storage media.

[0030] Furthermore, the step of shielding data access between the host-side conventional storage commands and the non-volatile storage medium 240 includes: During the power-on initialization phase of the target solid-state drive 200, the test endpoint startup process is initiated. In the test endpoint startup process, the test firmware generates a logical test namespace that does not correspond to the real physical storage block, and establishes an isolation table for the non-volatile storage medium 240. The real physical storage block is the smallest operating unit inside the non-volatile storage medium 240. The test firmware, based on the isolation table, blocks the data mapping relationship between the host-side regular storage commands and the non-volatile storage medium 240.

[0031] After the target SSD is powered on, the test firmware automatically enters the power-on initialization process and reads information such as endpoint mode flag, fixture identifier, firmware version, media status, and master controller communication status. Based on preset conditions, it determines whether to enter the test endpoint startup process. When the test endpoint access conditions are met, the test firmware starts the test endpoint initialization process, generates a logical test namespace that does not map to real flash physical blocks, and establishes an isolation table for managing failed storage media. Subsequently, in the command processing stage, the test firmware blocks the host's access path to the non-volatile storage media according to the isolation table and uniformly diverts the host-side PCIe / NVMe test commands to the internal test data path. Finally, the accompanying test control program reads the endpoint status according to the test case table, performs server-side PCIe link 130 verification, and generates a link verification report.

[0032] In one boot sequence, the test firmware first initializes the basic operating environment of the main control chip 230, and then initializes the PCIe interface 220 and the minimum functional set of the NVMe controller capable of supporting host enumeration. Subsequently, the test firmware reads the endpoint mode flag and media status record; if the endpoint mode is valid, it does not enter the real namespace loading state, but instead enters the test namespace establishment state. After the test namespace is established, the test firmware enters the isolation table establishment state and writes the access status of the non-volatile storage medium 240 to the endpoint log. Only after the logical test namespace, isolation table, and internal test data path are all initialized does the test firmware present the test endpoint availability status to the host side.

[0033] In another startup sequence, the test firmware allows an initial attempt to read the minimum status information of the non-volatile storage medium 240 to confirm the media failure level or channel anomaly location. If the read is completed within a preset timeout window, the test firmware establishes an isolation table based on the read result; if the read exceeds the preset timeout window, the test firmware does not continue to wait for a media response, but instead marks the corresponding channel or media object as an access timeout isolation state and continues to initialize the logical test namespace and internal test data path. This process ensures that the media status confirmation step does not become a blocking condition for test endpoint startup.

[0034] The logical test namespace is a logical access object presented to the host side in test endpoint mode. The logical test namespace can have a preset capacity and preset block size, allowing the host driver or test control program to initiate read / write stress tests according to standard block device or NVMe command methods. However, this preset capacity does not correspond to a real physical block in the non-volatile storage medium 240, nor does it require the target solid-state drive 200 to have a corresponding amount of reliable NAND space. When the host side sends an identification command, the test firmware returns the test capability information of the logical test namespace; when the host side sends a read / write command, the test firmware redirects the read / write command to the internal test data path; when the host side sends format, erase, secure erase, or commands that change the actual storage state, the test firmware can return a completion status indicating that it is not supported, prohibited, or refused to execute in test endpoint mode.

[0035] The purpose of the aforementioned startup chain is not to create a reliable storage disk, but to provide the server-side PCIe link 130 with a test endpoint that can be recognized by the host and stably accessed by the tested program. Since the logical test namespace does not depend on the actual physical blocks in the non-volatile storage medium 240, bad blocks in the failed medium, retention failures, or read / write timeouts are not necessary conditions for the establishment of the logical test namespace.

[0036] The test endpoint configuration includes endpoint mode flags, non-volatile storage media access prohibition flags, logical test namespace parameters, test command set, internal test data path selection parameters, error response strategy, and log reporting strategy. The endpoint mode flags instruct the main control chip 230 not to enter normal storage operation mode. The access prohibition flags restrict the command scheduling layer, channel control layer, and exception recovery layer from translating host-side test commands into actual storage access for the non-volatile storage media 240. The logical test namespace parameters define the namespace capacity, block size, queue depth, and namespace identifier that the host side can recognize.

[0037] The isolation table records the channel number, chip select number, logic cell number, plane number, die number, isolation reason, isolation time, most recent error type, timeout count, and current isolation state corresponding to the non-volatile storage medium 240. Isolation states can include logic mask state, chip select disabled state, reset hold state, clock off state, or access timeout isolation state. A logic mask state means the command scheduling layer does not dispatch an actual storage access command to the corresponding medium object. A chip select disabled state means no valid chip select is issued to the corresponding chip or channel. A reset hold state means the corresponding channel or medium object is held in a reset state. A clock off state means the operating clock of the corresponding channel is turned off. An access timeout isolation state means that after detecting a reset, identification, status read, or access command timeout, the corresponding object is marked as isolated and subsequent access is prevented.

[0038] Isolation processing can be performed in order from high-level to low-level. The test firmware first sets a logical mask flag at the command scheduling layer to prevent upper-level commands from generating new NAND access requests; then, at the channel control layer, it disables chip select, reset release, or clock enable, preventing existing lower-level access requests from entering the corresponding channel; subsequently, at the error recovery layer, it disables read retry, bad block remapping, erase recovery, or media scan processes for the non-volatile storage medium 240. This sequence reduces the probability of prolonged firmware waiting, repeated resets, or repeated entry into error recovery due to media abnormalities during the startup phase.

[0039] The test firmware can also set a timeout window for isolation processing. If a NAND channel or media object cannot complete reset, identification, or status reading within a preset time, the test firmware will no longer wait for the channel to recover, but will write the channel into the isolation table and continue to complete the PCIe / NVMe test endpoint initialization. The timeout window can be determined based on the startup timing of the main control chip 230, the PCIe enumeration time limit, or the wait time limit of the test control program. Through this process, abnormal responses from the non-volatile storage medium 240 will not block the target solid-state drive 200 from being identified by the host side.

[0040] The isolation table can also be used as a log reporting object. The test control program can read the isolation reason, isolation object, isolation time, current endpoint mode, and most recent error type through the log acquisition command. In this way, the test control program can confirm that the target solid-state drive 200 is in a non-storage access state and distinguish between "test endpoint with isolated media" and "ordinary storage device" in the link verification report.

[0041] Furthermore, the test firmware categorizes and processes host-side PCIe / NVMe commands. Identification commands are redirected to the endpoint information response path, returning device information, firmware version, supported command set, logical test namespace parameters, and fixture identification information for the test endpoint. Log retrieval commands are redirected to the log response path, returning link status information, isolation status information, command statistics, error statistics, or endpoint mode information. Read and write commands are redirected to the internal test data path. Formatting, erasing, secure erasing, firmware commit, or other commands that may alter the actual storage state can be redirected to a rejection path and return a preset completion status.

[0042] To ensure traceability of command processing, the test firmware establishes a test command context for test commands submitted in the host-side queue. The test command context can include a command identifier, queue identifier, command type, namespace identifier, data length, data offset, logical address, test data generation method, checksum seed, completion status, error injection flag, submission time, completion time, and statistical count. The test command context can be stored in the main control chip 230's internal SRAM, external DRAM, or other volatile memory areas.

[0043] When the host sends a read command, the test firmware determines the data generation method based on the test command context and returns the generated data to the host via the PCIe DMA path or the controller data return path. When the host sends a write command, the test firmware determines the processing method for the written data based on the test command context. The written data can be written to a volatile buffer, its CRC, checksum, or hash value can be calculated, it can be compared for consistency with a preset data pattern, it can enter the DMA loopback path, or it can be included in the statistics area without saving the original data. None of the above processing requires issuing read, write, or erase commands to the non-volatile storage medium 240.

[0044] The test command context enables the test control program to trace back to the specific commit queue, command identifier, logical address range, and data mode of a data error, command timeout, or abnormal completion status. In this way, the test results are not merely general conclusions of "read / write failure" or "link anomaly," but rather have verifiable command and data origins.

[0045] Furthermore, the internal test data path is used to provide a reproducible, comparable, and statistically significant data flow for the server-side PCIe link 130. The internal test data path may include an internal buffer of the main control chip 230, volatile memory connected to the main control chip 230, a fixed test data generation module, an address-dependent test data generation module, a pseudo-random test data generation module, a DMA loopback path, a circular read / write buffer path, a verification statistics area, or an error injection module.

[0046] The fixed test data generation module can generate all-zero, all-one, increasing sequences, alternating bit sequences, or other preset data patterns. The address-related test data generation module can generate data based on logical addresses, command numbers, queue identifiers, and intra-block offsets, enabling the test control program to determine whether the returned data is misaligned, duplicated, lost, or obfuscated across blocks. The pseudo-random test data generation module can generate reproducible pseudo-random data based on preset seeds, allowing the test control program to recalculate and compare returned data under the same test conditions.

[0047] The DMA loopback path is used to verify the data transfer path between the host side, PCIe interface 220, and the main control chip 230. Data written from the host side, after entering the main control chip 230 via PCIe interface 220, is not written to the non-volatile storage medium 240, but instead written to the volatile buffer or directly returned to the host side via the DMA loopback path. The test control program can compare the written data and the returned data to determine whether there are length errors, sequence errors, bit errors, or timeouts in the server-side PCIe link 130, PCIe interface 220, and the internal data transfer path of the main control chip 230.

[0048] A circular read / write buffer path can store the most recently written data or the most recent multiple writes in a volatile buffer, and then transmit it back in subsequent read commands or participate in verification. Since the circular read / write buffer path does not perform power-loss retention, its role is not to provide reliable storage, but rather to provide sufficient data round trips and consistency verification objects during link stress testing.

[0049] The error injection module can inject controllable bit errors, delayed responses, command completion status anomalies, queue depth limits, or data length anomalies into the returned data based on parameters issued by the test control program. The error injection parameters only affect the internal test data path and do not change the state of the non-volatile storage medium 240. Through controllable error injection, the test control program can verify the performance of server drivers, motherboard links, backplane links, or system recovery mechanisms under abnormal conditions.

[0050] Through the aforementioned internal test data path, the target solid-state drive 200 maintains both the enumerability and accessibility of the PCIe / NVMe endpoints, while avoiding the participation of failed or unreliable non-volatile storage media 240 in the test data path.

[0051] Example 2 Combination Figure 2As shown, this embodiment describes the system architecture for connecting a solid-state drive (SSD) test fixture to a server link. The overall system architecture consists of two core parts: a server 100 for performance and reliability testing, and a target SSD 200 reconstructed from a retired SSD. The server 100 is the core component for PCIe link performance and reliability testing, including a server motherboard 110, a PCIe slot or backplane 120, and a server-side PCIe link 130. The server-side PCIe link 130 specifically encompasses various PCIe link components such as motherboard traces, backplane traces, connectors, transmission cables, retimers, and switches. The target SSD 200 is the endpoint of the modified dedicated test fixture. Its hardware structure includes an SSD circuit board 210, and a PCIe interface 220, a controller chip 230, and a non-volatile storage medium 240 integrated on the circuit board 210. The non-volatile storage medium 240 is physically stored on the circuit board 210 and logically shielded by the test firmware; isolation can also be achieved through various methods such as disconnecting power, maintaining reset, disabling chip select, or turning off channel clock. Based on this isolation mechanism, various test commands issued by the host do not need to rely on the non-volatile storage medium 240 to perform storage read and write operations. The main control chip 230 has dedicated test firmware burned inside, providing core logic support for the entire test process. During the device power-on initialization phase, the test firmware can automatically complete the initialization configuration, generate a logical test namespace, and establish a non-volatile storage medium isolation table, completely blocking the data mapping and access path between host-side commands and the non-volatile storage medium 240, and uniformly diverting all PCIe / NVMe test commands from the host side to the internal test data path of the main control, relying only on the communication capability between the main control and the PCIe interface to complete the test interaction.

[0052] This application also includes a dedicated test control program, which can run on the server to be verified 100 or on an external control device that establishes a communication connection with the server to be verified 100. This program can read the endpoint mode information, media isolation status information, and PCIe link status information fed back by the target solid-state drive 200 in real time, automatically complete various verification tests of the PCIe link according to a preset test case table, and finally generate a standardized link verification report.

[0053] Combination Figure 3As shown, after the test control program starts the test, it first automatically scans and identifies the connected target solid-state drive 200, and reads the fixture identification information, endpoint mode information, logical test namespace parameters, isolation table summary, and test firmware version of the target solid-state drive 200. After completing the device information verification and reading, the test control program retrieves the corresponding test case table according to the device matching parameters. The test case table is a standardized preset test case library, covering complete test configuration parameters and judgment criteria, specifically including test name, target link speed, target link width, number of commands, single transmission length, queue depth, timeout time, data mode, allowed error threshold, whether error injection is enabled, whether hot-plugging or link reset is performed, and expected return status.

[0054] This embodiment's test case system includes multi-dimensional test items, comprehensively covering the core performance and reliability indicators of the PCIe link. Among them, the link training test confirms whether the target SSD 200 can successfully complete the link initialization training and device enumeration identification process after being connected to the server-side PCIe link 130. The test control program records the negotiation rate, negotiation width, training time, and whether speed reduction or width degradation occurs. Continuous read tests, continuous write tests, and mixed read / write tests check command completion status, throughput changes, command timeout counts, and data consistency results within preset data lengths, queue depths, and durations. The queue depth stress test verifies the command processing capabilities between the host side and the test endpoint under multiple submission queues or high queue depths.

[0055] Meanwhile, the testing system includes multiple fault tolerance and recovery capability tests, covering recovery performance verification under abnormal link scenarios. The link reset test records the re-enumeration time, renegotiation rate, and error count changes after resetting the server-side PCIe link 130 or the target SSD 200. The hot-swap recovery test records the link recovery time, endpoint re-identification status, and data path recovery status after the target SSD 200 is disconnected and reconnected. The server restart recovery test verifies whether the test endpoint mode can still be recognized after a system restart, whether the logical test namespace is re-established according to preset parameters, and whether the isolation table is reactivated.

[0056] After testing, the test control program automatically integrates all test data and generates a standardized link verification report. The link verification report records not only the link verification conclusions but also endpoint mode information, isolation status information, logical test namespace parameters, test case parameters, and test firmware version. If data consistency fails, but the endpoint logs show an error injection flag in the internal test data path, the test control program can attribute the failure to a preset error injection. If the link negotiation width is lower than a preset value, but the endpoint logs and internal test data path are both in normal condition, the test control program can point the problem to the server-side PCIe link 130, backplane, connector, or cable. If the target SSD 200 cannot enter test endpoint mode or the isolation table is not effective, the test control program can mark the problem as a fixture status anomaly, rather than directly determining that the server-side link is unqualified.

[0057] The link verification report can further associate and save the input conditions, endpoint responses, and judgment results for each test case. Input conditions include the test case number, target link speed, target link width, queue depth, transmission length, data mode, verification seed, and whether error injection is enabled. Endpoint responses include command completion status, returned data verification value, endpoint mode flag, isolation table summary, and command statistics count. Judgment results include pass, suspected link anomaly, suspected endpoint configuration anomaly, suspected fixture status anomaly, or inconsistent test conditions. Through this associated saving, subsequent retesting can use the same test case parameters and verification seed to reproduce the data path without relying on non-volatile storage medium 240 to save historical test data.

[0058] This embodiment's testing scheme is adaptable to multi-slot batch verification scenarios on servers, offering two working modes: single-rig rotation testing and multi-rig synchronous testing. It allows for sequential connection of the same SSD test fixture to different PCIe slots or backplane interfaces on the server for multi-slot rotation testing; alternatively, it allows simultaneous connection of multiple SSD test fixtures for synchronous testing of multiple test endpoints. The test control program distinguishes different test endpoints using the unique identifier of each fixture, binding and independently recording the media isolation status and test results of each endpoint to the 130 slot of the server-side PCIe link it connects to, achieving precise slot-level testing. Based on this binding and recording mechanism, accurate location of anomalies is possible: if a fixed slot repeatedly experiences link degradation or transmission anomalies, while the same test fixture performs normally in other slots, the anomaly is determined to originate from that slot or the corresponding backplane link; if the same test fixture exhibits endpoint mode anomalies or isolation failures in multiple different slots, the anomaly is primarily determined to originate from the test fixture itself, further improving the accuracy and efficiency of troubleshooting server PCIe link faults in multi-slot scenarios.

[0059] In summary, this application has the following technical effects: The still-functioning controller chip and PCIe / NVMe communication endpoint capabilities in retired SSDs are functionally decoupled from the failed or unreliable non-volatile storage media. Since the test firmware enters the test endpoint boot process during the power-on initialization phase and generates a logical test namespace and isolation table before the normal storage boot path, the retired SSD no longer relies on reliable storage media as a prerequisite for being recognized by the host and used by the tested program.

[0060] During command processing, the test firmware severs the data mapping relationship between host-side commands and non-volatile storage media through isolation tables, access prohibition flags, and hierarchical isolation strategies. Even if the non-volatile storage media has bad blocks, uncorrectable errors, read / write timeouts, or abnormal responses, it is not necessary to enter the FTL mapping, NAND read / write, or abnormal recovery process, thereby reducing the interference of failed media on PCIe / NVMe endpoint initialization and command response.

[0061] During the data response process, the main control chip generates or verifies test data based on the internal test data path. Read commands can return fixed data, address-dependent data, or pseudo-random data, while write commands can enter the volatile buffer, verification statistics area, or DMA loopback path. Based on this, the test control program can determine whether data misalignment, duplication, loss, or bit flipping has occurred, enabling retired solid-state drives to still provide the data consistency evidence required for link verification even when they no longer perform reliable storage functions.

[0062] During server link verification, the test control program can write test case parameters, endpoint mode information, NAND isolation status, link negotiation status, and error statistics into the verification report. Therefore, when link verification fails, it not only provides a pass / fail conclusion but also further distinguishes between server-side PCIe link anomalies, test endpoint configuration anomalies, or fixture status anomalies, facilitating production testing, maintenance review, and batch fixture management.

[0063] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A solid-state drive reconstruction method, characterized in that, include: A target solid-state drive (200) is acquired, the target solid-state drive (200) includes a main controller chip (230), a PCIe interface (220) and a non-volatile storage medium (240), the main controller chip (230) and the PCIe interface (220) are in a working state; The main control chip (230) is configured with test firmware, which is configured to: block data access between the host-side conventional storage commands and the non-volatile storage medium (240), and divert host-side PCIe / NVMe test commands to the internal test data path; the internal test data path generates or verifies test data so that the target solid-state drive (200) can be used as a test fixture to verify the host-side PCIe link.

2. The method according to claim 1, characterized in that, The data access between the shielded host-side conventional storage commands and the non-volatile storage medium (240) includes: During the power-on initialization phase of the target solid-state drive (200), the test endpoint startup process is initiated. In the test endpoint startup process, the test firmware generates a logical test namespace that does not correspond to the real physical storage block and establishes an isolation table for the non-volatile storage medium (240). The real physical storage block is the smallest operating unit inside the non-volatile storage medium (240). The test firmware, based on the isolation table, blocks the data mapping relationship between the host-side regular storage commands and the non-volatile storage medium (240).

3. The method according to claim 2, characterized in that, The test firmware, based on the isolation table, blocks the data mapping relationship between the host-side conventional storage commands and the non-volatile storage medium (240), including: The isolation table records the channel number, chip select number, logical cell number, bare die number, plane number and corresponding isolation status of the non-volatile storage medium (240); The test firmware blocks storage access requests at the command scheduling layer according to the isolation table, prohibits the corresponding channel or chip select from entering the valid access state at the channel control layer, and prohibits read retry, bad block remapping or erase recovery processes for the non-volatile storage medium (240) at the anomaly recovery layer.

4. The method according to claim 2, characterized in that, The logical test namespace has a preset capacity, a preset block size, a preset queue depth, or a preset namespace identifier, and the preset capacity is not mapped to the actual physical storage block of the non-volatile storage medium (240); For formatting commands, erase commands, secure erase commands, or commands that change the actual storage state sent from the host side, the test firmware returns a state that it prohibits execution, does not support, or refuses to execute in test endpoint mode.

5. The method according to claim 1, characterized in that, Prior to the step of obtaining the target solid-state drive, the following is also included: Endpoint availability screening is performed on retired solid-state drives. The endpoint availability screening is based on at least one of the following criteria: health information log, media error log, manufacturer log, number of erase / write cycles, number of bad blocks, number of uncorrectable errors, number of read / write timeouts, remaining lifetime information, and data retention test results, to determine whether the non-volatile storage medium (240) is in a failed or unreliable state.

6. The method according to claim 2, characterized in that, The entry conditions for the test endpoint startup process include one or more of the following: endpoint mode flag, fixture identification information, test firmware version flag, non-volatile storage medium status, main control chip working status, PCIe interface working status, or host-side entry command. When the entry conditions are met, the test firmware skips or terminates the normal storage startup process and establishes the test endpoint configuration before the flash conversion layer initialization, mapping table loading, and standard storage namespace mounting.

7. The method according to claim 1, characterized in that, The host-side PCIe / NVMe test commands are offloaded to the internal test data path, including: The test firmware establishes a test command context for PCIe / NVMe test commands issued by the host side, and selects the corresponding internal test data path based on the test command context. The internal test data path includes one or more of the following: the main control chip internal buffer, non-volatile memory, fixed test data generation module, address-related test data generation module, pseudo-random test data generation module, DMA loopback path, circular read / write buffer path, or error injection module.

8. A solid-state drive testing fixture, characterized in that, The system includes a solid-state drive circuit board (210), a main control chip (230) disposed on the solid-state drive circuit board (210), a PCIe interface (220) connected to the main control chip (230), a non-volatile storage medium (240) in a failed or unreliable state, and test firmware configured on the main control chip (230); the test firmware is configured to block data access between the host-side conventional storage commands and the non-volatile storage medium (240), and to divert host-side PCIe / NVMe test commands to an internal test data path.

9. A host link verification system, characterized in that, include: The server to be verified (100) and the solid-state drive test fixture as described in claim 8 are provided, wherein the solid-state drive test fixture is inserted into the communication interface of the server to be verified (100); the server to be verified (100) runs a test control program to verify the link of the server to be verified (100) via the solid-state drive test fixture.

10. The host link verification system according to claim 9, characterized in that, The test control program executes link training, continuous read / write, mixed read / write, queue depth stress, link reset, hot-plug recovery, server restart recovery, or error injection tests according to the test case table, and generates a link verification report. The link verification report records endpoint mode information, isolation status information, logical test namespace parameters, test case parameters, link negotiation results, data consistency results, or link error statistics.

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