Method, device and computer equipment for multi-precision floating point data parallel processing for application specific integrated circuits

Abstract

This disclosure provides a method, apparatus, and computer device for parallel processing of multi-precision floating-point data for application-specific integrated circuits (ASICs), relating to the field of computer technology. The method includes receiving at least one set of operands, each set comprising two operands of the same precision and bit width; when there are multiple sets, the precision of each set may differ. The operands are allocated to multiple segment units based on their precision and bit width. Each segment unit is a fixed-width, smallest-granularity channel determined based on the minimum precision, and its number is determined based on the ratio of the maximum to the minimum precision. The total bit width of each target segment unit is the same as the precision of that set. For each set, based on the exponent difference, a reconstructed shifter is used to perform mantissa alignment on the smaller exponent, with the number of shifter units being the same as the number of target segment units. The mantissas are added to obtain a first result. Based on leading zeros, the shifter is used to normalize the result to obtain a second result and determine the exponent adjustment value. The floating-point addition result is obtained accordingly, which can improve hardware resource utilization and reduce the area overhead and design complexity of ASICs.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of application-specific integrated circuits (ASICs) and floating-point arithmetic, and especially to a method, apparatus, computer device, computer-readable storage medium, and computer program product for multi-precision floating-point data parallel processing of ASICs. Background Technology

[0002] With the widespread application of application-specific integrated circuits (ASICs) in fields such as artificial intelligence, high-performance computing, and data center acceleration, the performance, area, and power consumption of the floating-point arithmetic unit (Floating-Point Unit), as a core computing module, have become key factors affecting the overall efficiency of the chip. Typically, the Floating-Point Unit is designed with independent data paths for different precisions to meet diverse computing needs. However, this approach requires configuring multiple sets of arithmetic units for different precisions, which can lead to severe hardware resource redundancy, large area and power consumption overhead, and is not conducive to the high integration and low power consumption requirements of ASIC design. A more effective method is urgently needed to adapt to the increasingly demanding requirements of various fields for Floating-Point Units. Summary of the Invention

[0003] This disclosure provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for parallel processing of multi-precision floating-point data for application-specific integrated circuits.

[0004] According to one aspect of this disclosure, a method for parallel processing of multi-precision floating-point data for application-specific integrated circuits is provided. The method includes: receiving at least one set of operands, each set of operands including two operands to be processed with the same precision bit width, wherein, when multiple sets of operands are received, the precision bit widths of the operands in different sets are the same or different; allocating the at least one set of operands to a predetermined plurality of segment units based on the precision bit width of each set of operands, wherein the segment unit indicates a minimum-granularity data channel with fixed-bit-width data processing capability, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands, the fixed bit width is determined based on the minimum precision bit width, and the number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width; and executing the operation for each set of operands. The following operations are performed: Based on the exponent difference between two operands, a mantissa alignment shift operation is performed on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portions of each operand, wherein the number of at least one shifter units in the reconstructed shifting device for this set of operands is the same as the number of target segment units to which this set of operands is allocated; the mantissa portions of the two operands are added to obtain a first mantissa result; based on the number of leading zeros in the first mantissa result, a mantissa normalization shift operation is performed on the first mantissa result using the reconstructed shifting device for this set of operands to obtain a second mantissa result and an exponent adjustment value is determined; based on the second mantissa result and the exponent adjustment value, the floating-point addition result of this set of operands is obtained.

[0005] In some embodiments, the shifter unit is configured to: receive a mode selection signal, output data of the previous shifter unit, a fixed zero value, and a shift amount control signal, wherein the mode selection signal is used to determine whether the current shifter unit participates in cascading, and the shift amount control signal is used to control the shift amount; based on the mode selection signal, select one of the output data of the previous shifter unit and the fixed zero value as input data; perform a shift operation on the input data based on the shift amount control signal to output the current shift data, the output data for the next shifter unit, and additional bit information, wherein, in cascading, the output data for the next shifter unit is input as input data to the next shifter unit.

[0006] In some embodiments, when shifter units are cascaded, a multiplexing logic dynamically determines the mapping path from segment units to shifter units, wherein the multiplexing logic is configured to select a target shift mode from multiple preset shift modes based on the shift amount, and the multiple preset shift modes are determined based on the total bit width of all segment units.

[0007] In some embodiments, for each set of operands, after obtaining the mantissa portions of the two operands to be operated on, the following operations are performed: in response to the different signs of the two operands to be operated on, a two's complement conversion is performed on the mantissa portion of the corresponding one of the two operands to be operated on via a reconstructed two's complement conversion device to obtain a first converted mantissa portion, wherein the number of at least one-level two's complement conversion units in the reconstructed two's complement conversion device for the set of operands is the same as the number of target segment units allocated to the set of operands; wherein adding the mantissa portions of the two operands to be operated on includes: adding the mantissa portion of the one of the two operands to be operated on that has not undergone two's complement conversion to the first converted mantissa portion.

[0008] In some embodiments, the two's complement conversion unit is configured to: receive input data, a mode selection signal, the carry output of the previous two's complement conversion unit, and a fixed zero value, wherein the mode selection signal is used to determine whether the current two's complement conversion unit participates in cascading; based on the mode selection signal, select one between the carry output of the previous two's complement conversion unit and the fixed zero value as the carry input of the current stage, wherein, in cascading, the carry output of the previous two's complement conversion unit is selected as the carry input of the current stage; in response to determining to perform two's complement conversion, perform two's complement conversion based on the input data and the carry input of the current stage to obtain the two's complement converted data and the carry output for the next two's complement conversion unit.

[0009] In some embodiments, for each set of operands, after obtaining the first mantissa result, the following operations are performed: performing an inverse complement conversion on the first mantissa result via a reconstructed inverse complement conversion device to obtain the first mantissa result represented in original code form, wherein the number of at least one inverse complement conversion units in the reconstructed inverse complement conversion device for the set of operands is the same as the number of target segment units to which the set of operands is allocated; wherein performing a shift operation for mantissa normalization on the first mantissa result includes: performing a shift operation for mantissa normalization on the first mantissa result represented in original code form.

[0010] In some embodiments, the inverse complement conversion unit is configured to: receive input data, a mode selection signal, the carry output of the previous inverse complement conversion unit, and a fixed zero value, wherein the mode selection signal is used to determine whether the current inverse complement conversion unit participates in cascading; based on the mode selection signal, select one between the carry output of the previous inverse complement conversion unit and the fixed zero value as the carry input of the current stage, wherein, in cascading, the carry output of the previous inverse complement conversion unit is selected as the carry input of the current stage; in response to determining to perform inverse complement conversion, perform inverse complement conversion on the input data to obtain the inverse complement converted data and the carry output for the next inverse complement conversion unit.

[0011] In some embodiments, for each set of operands, the following operation is performed: the number of leading zeros in the first mantissa result is detected via a reconstructed leading zero detection device, wherein the number of at least one leading zero detection units in the reconstructed leading zero detection device for the set of operands is the same as the number of target segment units to which the set of operands is assigned.

[0012] In some embodiments, the leading zero detection unit is configured to: receive a mode selection signal, input data, and a plurality of fixed offsets, wherein the mode selection signal is used to determine whether the current leading zero detection unit participates in cascading; select one of the plurality of fixed offsets as the reference value for the current stage based on the mode selection signal; and in response to determining to perform leading zero detection, perform leading zero detection based on the input data to obtain the leading zero count for the current stage, and perform accumulation based on the leading zero count for the current stage and the reference value for the current stage to obtain the leading zero detection output for the current stage.

[0013] In some embodiments, for each set of operands, the following operation is performed: the second mantissa result obtained by mantissa normalization is rounded based on the nearest even rounding method.

[0014] In some embodiments, the method further includes performing special value detection on non-numbers, infinity, and zero.

[0015] According to another aspect of this disclosure, a multi-precision floating-point data parallel processing apparatus for an application-specific integrated circuit is provided, comprising: a data receiving module configured to receive at least one set of operands, each set of operands including two operands to be processed with the same precision bit width, wherein, when multiple sets of operands are received, the precision bit widths of the operands in different sets are the same or different; a data allocation module configured to allocate at least one set of operands to a predetermined plurality of segment units based on the precision bit widths of the operands, wherein the segment units indicate the smallest granularity data channels with fixed bit width data processing capabilities, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands, the fixed bit width is determined based on the minimum precision bit width, and the number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width; and data processing. The module is configured to perform the following operations for each set of operands: based on the exponent difference between the two operands, perform a mantissa alignment shift operation on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portions of each operand, wherein the number of at least one shifter units in the reconstructed shifting device for the set of operands is the same as the number of target segment units to which the set of operands is allocated; add the mantissa portions of the two operands to obtain a first mantissa result; based on the number of leading zeros in the first mantissa result, perform a mantissa normalization shift operation on the first mantissa result using the reconstructed shifting device for the set of operands, to obtain a second mantissa result and determine an exponent adjustment value; and obtain the floating-point addition result of the set of operands based on the second mantissa result and the exponent adjustment value.

[0016] According to another aspect of this disclosure, a computer device is provided, comprising: a processor; and a memory having a computer program stored thereon, wherein when executed by the processor, the computer program causes the processor to perform the methods provided above in this disclosure.

[0017] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0018] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0019] According to one or more embodiments of this disclosure, it is possible to support single-channel high-bit-width precision operation, multi-channel low-bit-width precision parallel operation, and mixed-precision parallel operation without increasing the number of core computing units, which significantly improves hardware resource utilization and computing flexibility, and reduces the area overhead and design complexity of application-specific integrated circuits.

[0020] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0021] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0022] Figure 1 This is a flowchart illustrating a method for parallel processing of multi-precision floating-point data for application-specific integrated circuits according to an embodiment of the present disclosure.

[0023] Figure 2 This is a circuit diagram illustrating a shifter unit according to an embodiment of the present disclosure.

[0024] Figure 3 This is a circuit diagram illustrating a shifter unit according to an embodiment of the present disclosure in stand-alone mode and cascaded mode.

[0025] Figures 4A to 4E The diagram illustrates different shifting modes when shifter units are cascaded according to embodiments of the present disclosure.

[0026] Figure 5 This is a circuit diagram illustrating a two's complement conversion unit according to an embodiment of the present disclosure.

[0027] Figure 6 This is a circuit diagram illustrating the complement conversion unit according to embodiments of the present disclosure in stand-alone mode and cascaded mode.

[0028] Figure 7 This is a circuit diagram illustrating an inverse complement conversion unit according to an embodiment of the present disclosure.

[0029] Figure 8 This is a circuit diagram illustrating the inverse complement conversion unit according to embodiments of the present disclosure in stand-alone mode and cascaded mode.

[0030] Figure 9 This is a circuit diagram illustrating a leading zero detection unit according to an embodiment of the present disclosure.

[0031] Figure 10 This is a circuit diagram illustrating a leading zero detection unit according to an embodiment of the present disclosure in stand-alone mode and cascaded mode.

[0032] Figure 11This is a block diagram illustrating a multi-precision floating-point data parallel processing apparatus for an application-specific integrated circuit according to an embodiment of the present disclosure.

[0033] Figure 12 An example computer device is shown in which any of the embodiments described herein may be implemented. Detailed Implementation

[0034] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0035] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0036] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0037] In related technologies, to improve resource utilization, traditional methods attempt to adopt multi-precision multiplexing structures, supporting multi-precision computing by sharing a portion of the computational modules. However, such solutions typically rely on complex control logic and multi-level data selection mechanisms during implementation. When supporting multi-precision parallel computing, additional data reorganization and path switching are often required, which not only increases design complexity but also introduces longer critical paths, affecting circuit timing performance and operating frequency.

[0038] Furthermore, in terms of mantissa alignment and shift processing, traditional methods are mostly optimized for single-precision processing. When extended to multi-channel parallel processing, the shift control logic becomes complex, making it difficult to meet the alignment requirements under different precisions, thus affecting overall computational efficiency. In addition and subtraction implementation, traditional methods still use separate addition and subtraction paths, leading to further reduction in hardware utilization. At the same time, unreasonable cross-channel carry control can also introduce additional latency, limiting performance improvement.

[0039] Therefore, embodiments of this disclosure propose a multi-precision floating-point data parallel processing method for application-specific integrated circuits (ASICs). This method can achieve efficient reuse of data paths, reduce hardware overhead, and optimize critical path performance while ensuring computational accuracy and functional integrity, thereby meeting the design requirements of high-performance, low-power ASIC systems.

[0040] Figure 1 This is a flowchart illustrating a method for parallel processing of multi-precision floating-point data for application-specific integrated circuits according to an embodiment of the present disclosure.

[0041] In step S101, at least one set of operands is received, each set of operands comprising two operands to be computed with the same precision bit width. If multiple sets of operands are received, the precision bit widths of the operands in different sets may be the same or different.

[0042] In the example, operands can be double-precision floating-point numbers (FP64), single-precision floating-point numbers (FP32), or double-precision floating-point numbers (BP16), with corresponding precision bit widths of 64 bits, 32 bits, and 16 bits, respectively. One or more sets of operands can be received. Each set of operands contains two operands to be computed, and these two operands have the same precision bit width. When receiving one set of operands, this set of operands can be an FP64 set, an FP32 set, or a BP16 set, etc. When receiving multiple sets of operands, all sets of operands can correspond to the same precision bit width, such as multiple sets of FP64 operands, multiple sets of FP32 operands, or multiple sets of BP16 operands; or the multiple sets of operands can correspond to different precision bit widths, i.e., mixed precision, for example, the multiple sets of operands include one set of FP32 operands and two sets of BP16 operands. In the embodiments of this disclosure, various combination modes can be supported, such as one set of FP64 operands, two sets of FP32 operands, four sets of BP16 operands, one set of FP32 operands and two sets of BP16 operands, etc., which can be achieved by dynamic switching or by pre-setting.

[0043] In the example, the floating-point parsing unit can be configured to parse at least one set of operands received in order to determine the precision bit width of each of the at least one set of operands.

[0044] In step S102, based on the precision bit width of each of the at least one set of operands, the at least one set of operands is allocated to a predetermined plurality of segment units. A segment unit indicates a minimum-granularity data channel with fixed-width data processing capability, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands. The fixed bit width is determined based on the minimum precision bit width. The number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width.

[0045] In the example, assuming a maximum precision bit width of 64 bits and a minimum precision bit width of 16 bits, four segment units can be set, each with a fixed bit width of 16 bits. In this case, for example, if a set of FP64 operands is received, this set of FP64 operands can be assigned to four target segment units; if a set of FP32 operands and two sets of BP16 operands are received, the set of FP32 operands can be assigned to two target segment units, and the two sets of BP16 operands can each be assigned to one target segment unit.

[0046] In the example, a mode selection unit can be configured to perform mode determination and data reorganization, thereby allocating at least one set of operands to multiple predetermined segment units. Furthermore, a floating-point resolution unit can be used to extract the sign bit, exponent, and mantissa from the two operands in each set of operands, thus preparing for floating-point operations.

[0047] In some embodiments, the method according to this disclosure may further include performing special value detection on Not-a-N (NaN), Infinity (Inf), and zero.

[0048] In the example, a special value detection unit can be set up to implement this detection. Correspondingly, a priority control mechanism can be set up to handle special values ​​uniformly. For example, NaN takes priority, Inf takes second priority, and zero and normal values ​​are output according to rules. That is, it can first check for NaN; if there is no NaN, it then checks for Inf; if Inf is found, it is processed according to the Inf rules; only if neither is found, the normal calculation flow is executed. When a special value is detected, relevant flags can be recorded for subsequent priority processing.

[0049] This special value detection uses built-in specific priority judgment logic to ensure that when a special value is encountered, the correct result can be output quickly according to a unified rule without entering the subsequent complex mantissa calculation process, thereby saving clock cycles.

[0050] like Figure 1 As shown, for each set of operands, the operations in steps S103 to S106 are performed.

[0051] In step S103, based on the exponent difference between the two operands, a mantissa alignment shift operation is performed on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portions of each operand. The number of at least one shifter units in the reconstructed shifting device for the set of operands is the same as the number of target segment units to which the set of operands is allocated.

[0052] In the example, a bit resolution and processing unit can be configured to compare the exponents of two operands to determine the larger and smaller numbers, thus obtaining the exponent difference, which provides a basis for mantissa alignment. The exponent difference can also be range-normalized so that saturation truncation occurs when the exponent difference exceeds a preset bit width range to avoid shift overflow. Mantissa alignment ensures that the mantissa portions of the two operands are of the same order of magnitude to facilitate computation. This bit resolution and processing unit can also support parallel processing of multiple segment units.

[0053] In the example, assuming four segment units are set, each segment unit has a fixed bit width of 16 bits, then, for example, if a set of FP64 operands is received and these FP64 operands are assigned to the four target segment units, the reconstructed shifting device may include a four-stage shifter unit; if a set of FP32 operands and two sets of BP16 operands are received, with the set of FP32 operands assigned to two target segment units and the two sets of BP16 operands each assigned to one target segment unit, the reconstructed shifting device may include a two-stage shifter unit for the set of FP32 operands, a one-stage shifter unit for the set of BP16 operands, and a one-stage shifter unit for the other set of BP16 operands.

[0054] In the example, additional bits can be generated during the shift operation. These additional bits can include guard bits, round bits, and sticky bits, where the sticky bits are obtained by a logical OR of all the shifted-out bits.

[0055] In step S104, the mantissa portions of the two operands to be operated on are added together to obtain the first mantissa result.

[0056] In the example, an adder can be configured to add the mantissas. Similar to the reconstructed shifting device mentioned above, this adder can also adopt this segment-based reconstructing approach to support parallel processing of multiple precisions.

[0057] In some embodiments, before executing step S104, i.e. after obtaining the mantissa portions of the two operands in step S103, the following operation may be performed: In response to the different signs of the two operands, a two's complement conversion is performed on the mantissa portion of one of the two operands via a reconstructed two's complement conversion device to obtain a first converted mantissa portion. The number of at least one-level two's complement conversion units in the reconstructed two's complement conversion device for the group of operands is the same as the number of target segment units allocated to the group of operands. Accordingly, adding the mantissa portions of the two operands in step S104 may include adding the mantissa portion of the operand that has not undergone two's complement conversion to the first converted mantissa portion.

[0058] In the example, since the sign bits of the two operands can be extracted, it's possible to determine whether the signs of the two operands are the same or different. If they are different, it means the subtraction operation needs to be converted to an addition operation, which requires performing a two's complement conversion. The two's complement conversion can be performed on the mantissa of the operand with the smaller exponent. This ensures that adding the mantissa of the smaller operand to the mantissa of the larger operand will result in a positive number, avoiding the possibility of a negative result when subtracting the larger number from the smaller one. The two's complement conversion can include bitwise inversion of the mantissa and adding a "1" to the least significant bit.

[0059] By performing a two's complement conversion on the mantissa, addition and subtraction operations can be uniformly implemented as addition operations, thereby simplifying hardware implementation and improving computational reusability.

[0060] In step S105, based on the number of leading zeros in the first mantissa result, the shifting device used for reconstructing the group of operands is reused to perform a shift operation for mantissa normalization on the first mantissa result to obtain the second mantissa result and determine the exponent adjustment value.

[0061] In this step, the reconstructed shifting device based on segment units is reused. Therefore, this reconstructed shifting device can be used for both mantissa alignment and mantissa normalization shifting operations, the only difference being the shift direction. The number of leading zeros in the mantissa result can be counted by detecting leading zeros to determine the shift amount required for normalization. The first mantissa result can be shifted left or right based on the detected number of leading zeros to conform to the normalized floating-point representation. In addition, to compensate for the shift changes that occur during mantissa normalization, the exponent value can be adjusted synchronously to obtain an exponent adjustment value.

[0062] In some embodiments, before executing step S105, i.e. after obtaining the first mantissa result via step S104, the following operation may be performed: The first mantissa result is subjected to inverse complement conversion via a reconstructed inverse complement conversion device to obtain the first mantissa result represented in original code form. The number of at least one-stage inverse complement conversion units in the reconstructed inverse complement conversion device for the group of operands is the same as the number of target segment units to which the group of operands is allocated. Accordingly, performing a shift operation for mantissa normalization on the first mantissa result in step S105 may include performing a shift operation for mantissa normalization on the first mantissa result represented in original code form.

[0063] In the example, if the sign of the first mantissa result is negative, a two's complement conversion is required. This conversion can involve subtracting 1 from the first mantissa result and then inverting all bits. Conversely, if the sign of the first mantissa result is positive, it is output directly without a two's complement conversion.

[0064] By performing inverse complement conversion, the sign of the operation result can be restored, so that the operation result can be restored from the complement form to the sign-amplitude representation. Thus, the pair of operations of complement conversion and inverse complement conversion can simplify hardware implementation and improve computational reusability.

[0065] In some embodiments, the following operation may also be performed: rounding the second mantissa result obtained by mantissa normalization in step S105 based on the nearest even number rounding method.

[0066] In the example, the second mantissa result obtained from mantissa normalization can be precision-corrected based on the nearest even rounding method and the additional bit information generated in the preceding steps to output a floating-point result conforming to the target precision format. The nearest even rounding method rounds to the nearest representable value. If it is exactly in the middle of two representable values, it rounds to the one with an even least significant bit.

[0067] In the example, a rounding unit can be set up to implement rounding. Similar to the reconstructed shifting device, reconstructed two's complement conversion device, and reconstructed inverse two's complement conversion device mentioned above, this rounding unit can also adopt this segment unit-based reconstruction idea to support multi-precision parallel processing.

[0068] By adopting a unified rounding mechanism, we can avoid systematically rounding in a certain direction and reduce long-term cumulative errors.

[0069] In some embodiments, exception handling can be performed again to process special values ​​such as NOT, infinity, and zero according to priority rules, ensuring that the output conforms to the floating-point standard. This processing can be implemented again using a special value detection unit.

[0070] In step S106, based on the second mantissa result and the exponent adjustment value, the floating-point addition result of the operands is obtained.

[0071] In the example, the second mantissa result represents the normalized mantissa portion, the exponent adjustment value represents the final exponent calculated synchronously during the normalization process, and together with the previously determined sign bit, the three can be combined into a complete floating-point number format, which is output as the final floating-point addition result of this group of operands.

[0072] Thus, the operation on this set of operands can be completed. Since the operations in steps S103 to S106 above are performed on each set of operands, when multiple sets of operands are received, the operations in steps S103 to S106 above can be performed on each set of operands.

[0073] The embodiments of this disclosure provide a method for parallel floating-point data processing supporting variable precision. By leveraging segment units, which serve as the smallest granularity standardization module, multiple precision modes can be flexibly adapted based on the same set of hardware resources through dynamic reconfiguration. Since segment units have fixed-width data processing capabilities, the relationship between each segment unit can be dynamically configured through multiplexing logic to form a data channel adapted to the precision of each set of operands. This allows for support of single-channel high-bit-width precision operations, multi-channel low-bit-width precision parallel operations, and mixed-precision parallel operations without increasing the number of core arithmetic units, significantly improving hardware resource utilization and computational flexibility, while reducing the area overhead and design complexity of application-specific integrated circuits (ASICs).

[0074] The various aspects of the shifter unit, the two's complement conversion unit, and the inverse two's complement conversion unit described above are described in detail below.

[0075] In some embodiments, the shifter unit can be configured to: receive a mode selection signal, output data of the previous shifter unit, a fixed zero value, and a shift amount control signal, wherein the mode selection signal is used to determine whether the current shifter unit participates in cascading, and the shift amount control signal is used to control the shift amount; based on the mode selection signal, select one of the output data of the previous shifter unit and the fixed zero value as input data; and perform a shift operation on the input data based on the shift amount control signal to output the current shift data, the output data for the next shifter unit, and additional bit information, wherein, in cascading, the output data for the next shifter unit is input as input data to the next shifter unit.

[0076] Figure 2 This is a circuit diagram illustrating a shifter unit according to an embodiment of the present disclosure.

[0077] like Figure 2As shown, the shifter unit may include a first multiplexer MUX 1, a second multiplexer MUX 2, and a shifter.

[0078] The first multiplexer MUX 1 may have a first input terminal, a second input terminal, and a control terminal. The first input terminal is used to receive the output data shift_out_n of the previous stage shifter unit, the second input terminal is used to receive the fixed zero value 'h0, and the control terminal is used to receive the mode selection signal mode_select. The first multiplexer MUX 1 can select between the output data shift_out_n of the previous stage shifter unit and the fixed zero value 'h0' for output based on the mode selection signal mode_select. When the mode selection signal mode_select indicates cascade mode, the first multiplexer MUX 1 selects the output data shift_out_n of the previous stage shifter unit so that the current shifter unit is connected to the previous stage shifter unit for cascaded operation; when the mode selection signal mode_select indicates independent mode, the first multiplexer MUX 1 selects the fixed zero value 'h0' so that the current shifter unit operates independently.

[0079] The second multiplexer MUX 2 receives signals from external multiplexing logic and the mode selection signal mode_select to output the shift control signal to the shifter.

[0080] The shifter performs a shift operation on the output data of the first multiplexer MUX 1 based on the shift amount control signal to obtain the output data data_out_n-1 of this stage shift, the output data shift_out_n-1 for the next stage shifter unit, and the additional bit information grs.

[0081] This shifter unit design dynamically switches between cascaded and independent operating modes via a mode selection signal. This allows the same standardized hardware to process low-precision floating-point data independently as well as high-precision floating-point data through cascading, significantly improving hardware resource reuse efficiency and architectural flexibility. Simultaneously, the mechanism for generating and reusing additional bit information ensures that aligned shifts and normalized shifts share the same shifter core, further reducing the area overhead and design complexity of the application-specific integrated circuit (ASIC).

[0082] Figure 3 This is a circuit diagram illustrating a shifter unit according to an embodiment of the present disclosure in stand-alone mode and cascaded mode.

[0083] It should be noted that, with Figure 2 The same or similar reference numerals in the accompanying drawings will not be repeated here.

[0084] Figure 3The left side of the diagram illustrates the shift processing of a single segment unit in independent operating mode. The segment unit receives input data `data_in_q`, whose bit width can be equal to the bit width `shifter_width` of a shifter unit, and enters shifter unit N-1 via multiplexing logic. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of shifter unit N-1 is configured in independent mode, causing the first multiplexer to select a fixed zero value `h0` as input data, indicating that this unit does not participate in cascading. Shifter unit N-1 performs the shift operation based on the shift amount control signal, obtaining output data `data_out_N-1`, which is the output result `data_out_q`, along with additional bit information `grs_q`. In independent mode, this segment unit independently completes shift processing of a specified bit width, such as that applicable to floating-point data with smaller precision bit widths.

[0085] Figure 3 The right side of the diagram illustrates the shifting process of multiple segment units in cascaded operation mode. Input data `data_in_p` is provided to multiple segment units, i.e., segment unit i-1 ... segment unit 0. The bit width of this input data `data_in_p` can be equal to `i × shifter_width` (where `i` is a natural number greater than 1). It is mapped to each level of shifter units via multiplexing logic, i.e., shifter units i-1 ... shifter unit 0. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of each level of shifter unit is configured for cascaded mode, causing the first multiplexer to select the output data of the previous level shifter unit as input data, indicating that each level of shifter unit participates in cascading to form an `i`-level cascaded structure. Each level of shifter unit performs a shift operation based on the shift amount control signal, obtaining output data `data_out_i-1 ... data_out_0` respectively. The output data from each level are concatenated into the complete output result `data_out_p`, and simultaneously, each level of shifter unit outputs additional bit information `grs_p`. In cascaded mode, multiple segment units work together to complete the shifting of large-precision bit-width floating-point data.

[0086] In some embodiments, when shifter units are cascaded, a multiplexing logic dynamically determines the mapping path from segment units to shifter units, wherein the multiplexing logic is configured to select a target shift mode from a plurality of preset shift modes based on the shift amount, the plurality of preset shift modes being determined based on the total bit width of all segment units.

[0087] Figures 4A to 4E The diagram illustrates different shifting modes when shifter units are cascaded according to embodiments of the present disclosure.

[0088] It should be noted that, with Figure 2 and Figure 3Similar or identical reference numerals in the accompanying drawings will not be repeated here. Additionally, in Figures 4A to 4E In the illustrated embodiment, the bit width of the shifter unit is represented as shifter_width, and four shifter units are used as an example for explanation. The additional bit information generated during the shift operation is represented as grs.

[0089] like Figure 4A As shown, when the shift amount does not exceed the bit width of one shifter unit (shifter_width), it can be in the first preset shift mode. That is, the multiplexing logic maps the data of each segment unit to the corresponding shifter unit one-to-one. Specifically, segment unit 3 is mapped to shifter unit 3, segment unit 2 to shifter unit 2, segment unit 1 to shifter unit 1, and segment unit 0 to shifter unit 0. In this mode, each segment unit corresponds one-to-one with each level of shifter unit, with no cross-segment mapping.

[0090] like Figure 4B As shown, when the shift amount reaches the bit width of one shifter unit (shifter_width) but does not exceed the bit width of two shifter units (2×shifter_width), it can be in the second preset shift mode. That is, the multiplexing logic maps the data of the higher-order segment units across segments to the lower-order shifter units, while the data of the lower-order segment units is shifted out as additional bit information. Specifically, segment unit 3 is mapped across segments to shifter unit 2, segment unit 2 is mapped across segments to shifter unit 1, segment unit 1 is mapped across segments to shifter unit 0, and the data of segment unit 0 is shifted out as additional bit information (grs). Simultaneously, shifter unit 3 is input with a fixed zero value '0'. In this mode, the lower-order segment unit data is processed first, and the higher-order segment unit data is used to supplement the remaining shift amount, thus implementing a segmented shift strategy.

[0091] like Figure 4C As shown, when the shift amount reaches the bit width of two shifter units (2 × shifter_width) but does not exceed the bit width of three shifter units (3 × shifter_width), it can be in the third preset shift mode. That is, the multiplexing logic further maps the data of the higher-order segment units across segments to lower-order shifter units, while the data of the lower-order segment units is shifted out as additional bit information. Specifically, segment unit 3 is mapped across segments to shifter unit 1, and segment unit 2 is mapped across segments to shifter unit 0. The data of segment units 1 and 0 are shifted out as additional bit information grs, while shifter units 3 and 2 are input with a fixed zero value '0'. In this mode, the data of the lower-order segment units is shifted out first, and the data of the higher-order segment units is used to supplement the remaining shift amount to implement the segmented shift strategy.

[0092] like Figure 4DAs shown, when the shift amount reaches the bit width of three shifter units (3×shifter_width) but does not exceed the bit width of four shifter units (4×shifter_width), it can be in the fourth preset shift mode. That is, the multiplexing logic maps the data of the highest segment unit across segments to the lowest shifter unit, while the data of the remaining low segment units are shifted out as additional bit information. Specifically, segment unit 3 is mapped across segments to shifter unit 0, and the data of segment units 2, 1, and 0 are shifted out as additional bit information grs. At the same time, shifter units 3, 2, and 1 are input with a fixed zero value '0'. In this mode, the low segment unit data is shifted out first, and the high segment unit data is used to supplement the remaining shift amount to implement the segmented shift strategy.

[0093] like Figure 4E As shown, when the shift amount reaches or exceeds the bit width of four shifter units (4 × shifter_width), it can enter the fifth preset shift mode. In this mode, the multiplexing logic shifts out all segment unit data as additional bit information (grs), and all shifter units are input with a fixed zero value (0). In this mode, all segment unit data is saturated and shifted out, and all shifter units output a fixed zero value.

[0094] Therefore, by dynamically determining the mapping path from segment units to shifter units through multiplexing logic, a reconfigurable shifting device composed of cascaded standardized segment units can adaptively adjust the data mapping method according to the actual shift amount. When the shift amount is small, each segment unit processes its corresponding data independently; when the shift amount is large, data from higher-order segment units automatically flows across segments to lower-order shifter units to supplement the processing of the remaining shift amount. This avoids configuring independent shifting hardware for different shift ranges, significantly reducing the area overhead and design complexity of application-specific integrated circuits (ASICs). This segmentation strategy of prioritizing the shifting out of lower-order segments and supplementing the shifting of higher-order segments can effectively shorten the critical path delay and improve timing performance.

[0095] In some embodiments, the two's complement conversion unit can be configured to: receive input data, a mode selection signal, the carry output of the previous two's complement conversion unit, and a fixed zero value, wherein the mode selection signal is used to determine whether the current two's complement conversion unit participates in cascading; based on the mode selection signal, select one between the carry output of the previous two's complement conversion unit and the fixed zero value as the carry input of the current stage, wherein, in cascading, the carry output of the previous two's complement conversion unit is selected as the carry input of the current stage; in response to determining to perform two's complement conversion, perform two's complement conversion based on the input data and the carry input of the current stage to obtain the two's complement converted data and the carry output for the next two's complement conversion unit.

[0096] Figure 5 This is a circuit diagram illustrating a two's complement conversion unit according to an embodiment of the present disclosure.

[0097] like Figure 5 As shown, the two's complement conversion unit may include a third multiplexer MUX 3, a fourth multiplexer MUX 4, and an adder.

[0098] The third multiplexer, MUX 3, has a first input, a second input, and a control input. The first input receives the carry-out_n-1 from the previous two's complement converter. The second input receives the fixed zero value 1'b0 (similar to 'h0' and '0 mentioned above, both of which can represent fixed zero values ​​in this paper). The control input receives the mode selection signal, mode_select. Based on the mode selection signal mode_select, the third multiplexer MUX 3 selects one of the carry-out_n-1 from the previous two's complement converter and the fixed zero value 1'b0 for output. When the mode selection signal mode_select indicates cascade mode, the third multiplexer MUX 3 selects the carry output carry_out_n-1 of the previous two's complement conversion unit, so that the current two's complement conversion unit is connected to the previous two's complement conversion unit for cascade operation; when the mode selection signal mode_select indicates independent mode, the third multiplexer MUX 3 selects a fixed zero value 1'b0, so that the current two's complement conversion unit operates independently.

[0099] The fourth multiplexer, MUX 4, has a first input, a second input, and a control input. The first input receives "0", the second input receives "1", and the control input receives the mode selection signal, mode_select. Based on the mode selection signal mode_select, the fourth multiplexer, MUX 4, selects between "0" and "1" for its output.

[0100] The adder receives input data data_in_n, the output of the fourth multiplexer MUX 4, and the output carry_in of the third multiplexer MUX 3 to perform an addition operation, obtaining the two's complement converted output data data_out_n and the carry output carry_out_n for the next two's complement conversion unit. Specifically, when the fourth multiplexer MUX 4 selects "1", the adder performs an increment operation to achieve the two's complement conversion; when the fourth multiplexer MUX 4 selects "0", the adder does not perform an increment operation.

[0101] This two's complement conversion unit dynamically switches between cascaded and independent operating modes via a mode selection signal. This allows the same set of standardized two's complement conversion units to independently process two's complement conversions of low-bit-width data, or to be cascaded and combined to complete two's complement conversions of high-bit-width data. This unifies addition and subtraction into a single addition operation, avoiding the need to configure separate addition and subtraction paths for different precisions. Simultaneously, by controlling the carry propagation relationship between units, independent operation and carry propagation without crossing channels are achieved in multi-channel low-bit-width precision parallel mode. In single-channel high-bit-width precision mode, carry is propagated from low-bit segments to high-bit segments, significantly improving hardware resource utilization and operational flexibility, while reducing the area overhead and design complexity of the application-specific integrated circuit (ASIC).

[0102] Figure 6 This is a circuit diagram illustrating the complement conversion unit according to embodiments of the present disclosure in stand-alone mode and cascaded mode.

[0103] It should be noted that, with Figures 2 to 5 The same or similar reference numerals in the accompanying drawings will not be repeated here.

[0104] Figure 6 The left side of the diagram illustrates the two's complement conversion process of a single segment unit in independent operating mode. The segment unit receives input data `data_in_q`, whose bit width is equal to the bit width of a single shifter unit (`shifter_width`). This data is then inverted via a bit-inverter and fed into the two's complement conversion unit N-1. The mode selection signal (`mode_select`, not shown in the diagram) of this unit N-1 is configured for independent mode, causing the third multiplexer to select a fixed zero value 1'b0 as the carry input for this stage, indicating that this unit does not participate in cascading. The two's complement conversion unit performs an increment operation based on the input data `data_in_q` and the carry input for this stage, obtaining the converted output data `data_out_N-1`, which is the output result `data_out_q`. In independent mode, this segment unit independently completes the two's complement conversion process for a specified bit width, suitable for floating-point data with smaller precision bit widths.

[0105] Figure 6The right side of the diagram illustrates the two's complement conversion process of multiple segment units in cascaded mode. Input data `data_in_p` is provided to multiple segment units, i.e., segment unit i-1 ... segment unit 0. The total bit width of this input data `data_in_p` is the bit width of i shifter units, i × `shifter_width` (where i is a natural number greater than 1). It is bit-inverted via a bit-inverter and then provided to each stage of the two's complement conversion unit, i.e., two's complement conversion unit i-1 ... two's complement conversion unit 0. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of each stage of the two's complement conversion unit is configured in cascaded mode, causing the third multiplexer to select the carry output of the previous stage's two's complement conversion unit as the carry input of this stage. This indicates that each stage of the two's complement conversion unit participates in cascading to form an i-stage cascaded structure. Each stage of the two's complement conversion unit performs an increment operation based on the input data and the carry input of this stage, obtaining the two's complement converted output data `data_out_i-1 ... data_out_0` respectively. The converted data from each stage are concatenated to form the complete output result `data_out_p`. In cascaded mode, multiple segment units work together to complete the two's complement conversion of large-precision bit-width floating-point data. The carry generated by the lower segment can be passed to the higher segment to realize large-width two's complement arithmetic.

[0106] In some embodiments, the inverse complement conversion unit can be configured to: receive input data, a mode selection signal, the carry output of the previous inverse complement conversion unit, and a fixed zero value, wherein the mode selection signal is used to determine whether the current inverse complement conversion unit participates in cascading; based on the mode selection signal, select one between the carry output of the previous inverse complement conversion unit and the fixed zero value as the carry input of the current stage, wherein, in cascading, the carry output of the previous inverse complement conversion unit is selected as the carry input of the current stage; in response to determining to perform inverse complement conversion, perform inverse complement conversion on the input data to obtain the inverse complement converted data and the carry output for the next inverse complement conversion unit.

[0107] Figure 7 This is a circuit diagram illustrating an inverse complement conversion unit according to an embodiment of the present disclosure.

[0108] like Figure 7 As shown, the inverse complement conversion unit may include a fifth multiplexer MUX 5 and an adder.

[0109] The fifth multiplexer, MUX 5, has a first input, a second input, and a control input. The first input receives the carry-out_n-1 from the previous inverse complement code conversion unit, the second input receives a fixed zero value 1'b0, and the control input receives a mode selection signal, mode_select. Based on the mode selection signal mode_select, the fifth multiplexer, MUX 5, selects either the carry-out_n-1 from the previous inverse complement code conversion unit or the fixed zero value 1'b0 for output. When mode_select indicates cascade mode, the fifth multiplexer, MUX 5, selects the carry-out_n-1 from the previous inverse complement code conversion unit, enabling the current inverse complement code conversion unit to connect and cascade with the previous unit. When mode_select indicates independent mode, the fifth multiplexer, MUX 5, selects the fixed zero value 1'b0, enabling the current inverse complement code conversion unit to operate independently.

[0110] The adder receives input data data_in_n, a fixed all-1 value "1...1", and the output carry_in of the fifth multiplexer MUX 5. Based on the fixed all-1 value and the output of the fifth multiplexer MUX 5, it performs a decrement operation on the input data data_in_n to obtain the output data data_out_n after inverse complement conversion and the carry output carry_out_n for the next stage inverse complement conversion unit.

[0111] This inverse complement conversion unit dynamically switches between cascaded and independent operating modes via a mode selection signal. This allows the same set of standardized inverse complement conversion units to independently process inverse complement conversion of low-bit-width data, and also to be cascaded and combined to complete inverse complement conversion of high-bit-width data, thereby restoring the result in complement form to its original code representation for subsequent normalization processing. Simultaneously, by controlling the carry propagation relationship between units, independent operation and carry propagation without crossing channels are achieved in multi-channel low-bit-width precision parallel mode, while low-bit-width precision mode achieves carry-to-high-bit-width transmission. This significantly improves hardware resource utilization and computational flexibility, while reducing the area overhead and design complexity of the application-specific integrated circuit (ASIC).

[0112] Figure 8 This is a circuit diagram illustrating the inverse complement conversion unit according to embodiments of the present disclosure in stand-alone mode and cascaded mode.

[0113] It should be noted that, with Figures 2 to 7 The same or similar reference numerals in the accompanying drawings will not be repeated here.

[0114] Figure 8The left side of the diagram illustrates the inverse complement conversion process of a single segment unit in independent operating mode. The segment unit receives input data `data_in_q`, whose bit width is equal to the bit width of a single shifter unit `shifter_width`, and enters the inverse complement conversion unit N-1. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of this inverse complement conversion unit N-1 is configured to independent mode, causing the fifth multiplexer to select a fixed zero value 1'b0 as the carry input for this stage, indicating that this unit does not participate in cascading. The inverse complement conversion unit performs a decrement operation based on the input data `data_in_q` and the fixed all-1 value, and then performs a bit-invert operation via a bit-inverter to obtain the output data `data_out_N-1`, which is the output result `data_out_q`. In independent mode, this segment unit independently completes the inverse complement conversion process of a specified bit width, suitable for floating-point data with smaller precision bit widths.

[0115] Figure 8 The right side of the diagram illustrates the inverse complement code conversion process of multiple segment units in cascaded operation mode. The input data_in_p is provided to multiple segment units, i.e., segment unit i-1...segment unit 0. The total bit width of this input data data_in_p is the bit width of i shifter units, i × shifter_width (where i is a natural number greater than 1), and is provided to each level of the inverse complement code conversion unit, i.e., inverse complement code conversion unit i-1...inverse complement code conversion unit 0. The mode selection signal (i.e., mode_select, not shown in the diagram) of each level of the inverse complement code conversion unit is configured in cascaded mode, causing the fifth multiplexer to select the carry output of the previous level's inverse complement code conversion unit as the carry input of this level, indicating that each level of the inverse complement code conversion unit participates in cascading to form an i-level cascaded structure. Each stage of the inverse complement conversion unit performs a decrement operation based on the input data, a fixed all-1 value, and the carry input of the current stage. The data after decrementing at each stage is then inverted bit by bit by a bit-inverter to obtain the output data data_out_i-1 ... data_out_0, which are then concatenated into the complete output result data_out_p. In cascaded mode, multiple segment units work together to complete the inverse complement conversion of large-precision bit-width floating-point data. Carries generated in lower-order segments can be passed to higher-order segments to achieve large-bit-width inverse complement arithmetic.

[0116] Similar to the reconstructed shifting device, the reconstructed two's complement conversion device, and the reconstructed inverse two's complement conversion device described above, embodiments of this disclosure may also use a reconstructed leading zero detection device based on a similar concept, which may also adopt a segment-based reconstruction idea.

[0117] In some embodiments, the above-mentioned combination Figure 1Step S105 is performed based on the number of leading zeros in the first mantissa result. Therefore, the method according to embodiments of this disclosure may further include, for each group of operands, performing the following operation: detecting the number of leading zeros in the first mantissa result via a reconstructed leading zero detection device, wherein the number of at least one-level leading zero detection units in the reconstructed leading zero detection device for the group of operands is the same as the number of target segment units to which the group of operands is assigned.

[0118] This approach allows a detection device consisting of cascaded standardized leading zero detection units to adaptively configure the detection granularity according to the current operation mode. In single-channel high bit-width precision mode, the cascaded leading zero detection units at each level accumulate to obtain the overall number of leading zeros. In multi-channel low bit-width precision parallel mode, each leading zero detection unit independently counts the number of leading zeros in its own channel. This avoids configuring independent leading zero detection circuits for different precisions, significantly reducing the area overhead of application-specific integrated circuits. At the same time, the reuse of a unified detection structure improves the flexibility and scalability of the architecture.

[0119] The various aspects of the aforementioned leading zero detection unit are described in detail below.

[0120] In some embodiments, the leading zero detection unit is configured to: receive a mode selection signal, input data, and a plurality of fixed offsets, wherein the mode selection signal is used to determine whether the current leading zero detection unit participates in cascading; select one of the plurality of fixed offsets as the reference value for the current stage based on the mode selection signal; and in response to determining to perform leading zero detection, perform leading zero detection based on the input data to obtain the leading zero count for the current stage, and perform accumulation based on the leading zero count for the current stage and the reference value for the current stage to obtain the leading zero detection output for the current stage.

[0121] Figure 9 This is a circuit diagram illustrating a leading zero detection unit according to an embodiment of the present disclosure.

[0122] like Figure 9 As shown, the leading zero detection unit may include a leading zero detector LZD, a sixth multiplexer MUX 6, a seventh multiplexer MUX 7, an adder (represented as "+" in the figure), a comparator (represented as "==" in the figure), and an OR gate.

[0123] The leading zero detector (LZD) receives input data data_in_n-1, performs leading zero detection on the input data data_in_n-1, and outputs a leading zero count cnt_n-1.

[0124] The MUX 6 multiplexer has multiple inputs and a control terminal. The inputs receive fixed offsets from 0×shifter_width to (N-1)×shifter_width (where N is a natural number greater than or equal to 1), and the control terminal receives the mode selection signal `mode_select`. Based on the `mode_select` signal, the MUX 6 multiplexer selects one of the multiple fixed offsets for output.

[0125] The adder receives the leading zero count cnt_n-1 output from the leading zero detector LZD and the fixed offset output from the sixth multiplexer MUX6, and performs an accumulation operation on the leading zero count based on the fixed offset.

[0126] The comparator receives the fixed offset output from the sixth multiplexer MUX 6 and the detection output LZD_n from the previous leading zero detection unit, determines whether the two meet the preset conditions, and outputs the comparison result.

[0127] The OR gate receives the comparator's output and the separation enable signal seperate_en, generates a selection control signal based on the comparator's output and the separation enable signal seperate_en, and outputs it to the seventh multiplexer MUX 7.

[0128] The seventh multiplexer, MUX 7, has a first input, a second input, and a control input. The first input receives the detection output LZD_n from the previous leading zero detection unit, the second input receives the accumulation result of the adder, and the control input receives the selection control signal from the OR gate output. Based on this selection control signal, the seventh multiplexer, MUX 7, selects either the detection output LZD_n from the previous leading zero detection unit or the accumulation result of the adder as the output of the current leading zero detection unit, i.e., the detection output LZD_n-1 of the current leading zero detection unit.

[0129] When the OR gate output selection control signal indicates cascading mode, the seventh multiplexer MUX 7 selects the accumulated result output, enabling the current leading zero detection unit to connect with the previous leading zero detection unit for cascading operation, thus achieving cascading accumulation of leading zero counts. When the OR gate output selection control signal indicates independent mode, the seventh multiplexer MUX 7 selects the detection output of the previous leading zero detection unit, enabling the current leading zero detection unit to operate independently, thus achieving independent counting of leading zero counts for each channel.

[0130] This type of leader zero detection unit dynamically switches between cascaded and independent operating modes through a mode selection signal. This allows the same set of standardized leader zero detection units to independently process leader zero detection for low-bit-width data, or to be cascaded and combined to complete leader zero detection for high-bit-width data. This avoids configuring independent leader zero detection circuits for different precisions, significantly reducing the area overhead and design complexity of application-specific integrated circuits. At the same time, the reuse of a unified detection structure improves the flexibility and scalability of the architecture.

[0131] Figure 10 This is a circuit diagram illustrating a leading zero detection unit according to an embodiment of the present disclosure in stand-alone mode and cascaded mode.

[0132] It should be noted that, with Figures 2 to 9 The same or similar reference numerals in the accompanying drawings will not be repeated here.

[0133] Figure 10 The left side of the diagram illustrates the leading zero detection process of a single segment unit in independent operating mode. The segment unit receives input data `data_in_q`, whose bit width is equal to the bit width `shifter_width` of a single shifter unit, and enters the leading zero detection unit N-1. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of the leading zero detection unit N-1 is configured to independent mode, indicating that this unit does not participate in cascading. The leading zero detection unit N-1 performs leading zero detection based on the input data `data_in_q` and outputs the leading zero detection result `LZD_q`. In independent mode, this segment unit independently completes the leading zero detection processing for a specified bit width, suitable for floating-point data with smaller precision bit widths.

[0134] Figure 10 The right side of the diagram illustrates the leading zero detection processing of multiple segment units in cascaded operation mode. Input data `data_in_p` is provided to multiple segment units, i.e., segment unit i-1 ... segment unit 0. The total bit width of this input data `data_in_p` is the bit width of i shifter units, i × `shifter_width` (where i is a natural number greater than 1), and is provided to each level of the leading zero detection unit, i.e., leading zero detection unit i-1 ... leading zero detection unit 0. The mode selection signal (i.e., `mode_select`, not shown in the diagram) of each level of the leading zero detection unit is configured in cascade mode, indicating that each level of the leading zero detection unit participates in cascading to form an i-level cascaded structure. Each level of the leading zero detection unit performs leading zero detection based on the input data, outputs the detection result, and processes it through cascaded multiplexing logic to output the complete leading zero detection result `LZD_p`. In cascaded mode, multiple segment units work together to complete the leading zero detection processing of large-precision bit-width floating-point data. The number of leading zeros in the lower segment can be passed to the higher segment for accumulation to achieve large-bit-width leading zero detection.

[0135] Therefore, in the embodiments of this disclosure, each related operating device, such as the reconstructed shifting device, the reconstructed two's complement conversion device, the reconstructed inverse two's complement conversion device, the reconstructed leading zero detection device, etc., can all be flexibly adapted to multiple precision modes by means of the segment unit, which is the smallest granularity standardization module, based on the same set of hardware resources through dynamic reconstruction.

[0136] According to embodiments of this disclosure, a multi-precision floating-point data parallel processing apparatus for application-specific integrated circuits is also provided.

[0137] Figure 11 This is a block diagram illustrating a multi-precision floating-point data parallel processing apparatus 1100 for an application-specific integrated circuit according to an embodiment of the present disclosure.

[0138] In some embodiments, the apparatus 1100 includes a data receiving module 1101, a data distribution module 1102, and a data processing module 1103.

[0139] The data receiving module 1101 is configured to receive at least one set of operands, each set of operands including two operands to be operated on with the same precision bit width. In the case of receiving multiple sets of operands, the precision bit widths of the operands in different sets may be the same or different.

[0140] The data allocation module 1102 is configured to allocate at least one set of operands to a predetermined plurality of segment units based on the precision bit width of each set of operands, wherein the segment unit indicates the smallest granularity data channel with fixed bit width data processing capability, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands, the fixed bit width is determined based on the minimum precision bit width, and the number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width.

[0141] The data processing module 1103 is configured to perform the following operations for each set of operands: based on the exponent difference between the two operands to be operated on, a shift operation for mantissa alignment is performed on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portions of the two operands respectively, wherein the number of at least one shifter units in the reconstructed shifting device for the set of operands is the same as the number of target segment units to which the set of operands is allocated; the mantissa portions of the two operands to be operated on are added to obtain a first mantissa result; based on the number of leading zeros in the first mantissa result, a shift operation for mantissa normalization is performed on the first mantissa result using the reconstructed shifting device for the set of operands, to obtain a second mantissa result and determine an exponent adjustment value; based on the second mantissa result and the exponent adjustment value, the floating-point addition result of the set of operands is obtained.

[0142] The operation of the aforementioned data receiving module 1101, data distribution module 1102, and data processing module 1103 can be combined with... Figure 1 The corresponding steps described are the same, so the details of each aspect will not be repeated here.

[0143] In some embodiments, the data processing module 1103 is further configured to perform the following operations for each set of operands after obtaining the mantissa portions of the two operands to be operated on: in response to the different signs of the two operands to be operated on, performing a two's complement conversion on the mantissa portion of one of the two operands to be operated on via a reconstructed two's complement conversion device to obtain a first converted mantissa portion, wherein the number of at least one-level two's complement conversion units in the reconstructed two's complement conversion device for the set of operands is the same as the number of target segment units allocated to the set of operands; wherein adding the mantissa portions of the two operands to be operated on includes: adding the mantissa portion of the one of the two operands to be operated on that has not undergone two's complement conversion to the first converted mantissa portion.

[0144] In some embodiments, the data processing module 1103 is further configured to perform the following operations for each set of operands after obtaining the first mantissa result: perform inverse complement conversion on the first mantissa result via a reconstructed inverse complement conversion device to obtain the first mantissa result represented in original code form, wherein the number of at least one inverse complement conversion units in the reconstructed inverse complement conversion device for the set of operands is the same as the number of target segment units to which the set of operands is allocated; wherein performing a shift operation for mantissa normalization on the first mantissa result includes: performing a shift operation for mantissa normalization on the first mantissa result represented in original code form.

[0145] In some embodiments, the data processing module 1103 is further configured to perform the following operation for each set of operands: detect the number of leading zeros in the first mantissa result via a reconstructed leading zero detection device, wherein the number of at least one leading zero detection units in the reconstructed leading zero detection device for the set of operands is the same as the number of target segment units to which the set of operands is assigned.

[0146] In some embodiments, the data processing module 1103 is further configured to perform the following operation for each set of operands: rounding the second mantissa result obtained by mantissa normalization based on the nearest even rounding method.

[0147] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0148] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0149] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0150] Figure 12 An example computer device 1200 is shown in which any of the embodiments described herein may be implemented. Computer device 1200 may be used to implement one or more components of the systems and methods described above. Computer device 1200 may include a bus 1202 or other communication mechanism for communicating information, and a processor 1204 coupled to the bus 1202 for processing information. Processor 1204 may be, for example, one or more general-purpose microprocessors.

[0151] Computer device 1200 may also include main memory 1206, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 1202, for storing information and instructions to be executed by processor 1204. Main memory 1206 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 1204. Such instructions, when stored in a storage medium accessible to processor 1204, enable computer device 1200 to become a special-purpose machine customized to perform the operations specified in the instructions. Main memory 1206 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0152] Computer device 1200 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 1200, enable computer device 1200 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques described herein are executed by computer device 1200 in response to processor 1204 executing one or more sequences of one or more instructions contained in main memory 1206. Such instructions may be read into main memory 1206 from another storage medium, such as storage device 1208. Executing the sequence of instructions contained in main memory 1206 causes processor 1204 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 1206. When these instructions are executed by processor 1204, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0153] Computer device 1200 also includes a network interface 1210 coupled to bus 1202. Network interface 1210 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 1210 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0154] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0155] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0156] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods described in the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0157] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0158] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0159] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0160] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0161] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0162] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0163] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0164] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0165] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A method for parallel processing of multi-precision floating-point data for application-specific integrated circuits, characterized in that, The method includes: Receive at least one set of operands, each set of operands including two operands to be operated on with the same precision bit width, wherein, when multiple sets of operands are received, the precision bit widths of the operands in different sets may be the same or different; Based on the precision bit width of each of the at least one set of operands, the at least one set of operands is allocated to a predetermined plurality of segment units, wherein the segment unit indicates the smallest granularity data channel with fixed bit width data processing capability, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands, the fixed bit width is determined based on the minimum precision bit width, and the number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width; For each set of operands, perform the following operations: Based on the exponent difference between the two operands to be operated on, a shift operation for mantissa alignment is performed on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portion of each of the two operands to be operated on, wherein the number of at least one shifter units in the reconstructed shifting device for the group of operands is the same as the number of target segment units to which the group of operands is allocated; Add the mantissa portions of the two operands to obtain the first mantissa result; Based on the number of leading zeros in the first mantissa result, the shifting device used for the reconstruction of the group of operands is reused to perform a shift operation for mantissa normalization on the first mantissa result to obtain a second mantissa result and determine the exponent adjustment value. Based on the second mantissa result and the exponent adjustment value, the floating-point addition result of this set of operands is obtained.

2. The method according to claim 1, characterized in that, The shifter unit is configured as follows: The receiver receives a mode selection signal, the output data of the previous stage shifter unit, a fixed zero value, and a shift amount control signal, wherein the mode selection signal is used to determine whether the current shifter unit participates in cascading, and the shift amount control signal is used to control the shift amount; Based on the mode selection signal, one of the output data of the previous shifter unit and the fixed zero value is selected as the input data. The input data is shifted based on the shift control signal to output the shifted data of this stage, the output data for the next stage shifter unit, and additional bit information. In cascading, the output data for the next stage shifter unit is input as input data to the next stage shifter unit.

3. The method according to claim 2, characterized in that, When the shifter units are cascaded, the mapping path from the segment unit to the shifter unit is dynamically determined by multiplexing logic, wherein the multiplexing logic is configured to select a target shift mode from multiple preset shift modes based on the shift amount, and the multiple preset shift modes are determined based on the total bit width of all the segment units.

4. The method according to any one of claims 1 to 3, characterized in that, For each set of operands, after obtaining the mantissa portions of the two operands to be operated on, the following operations are performed: In response to the fact that the two operands to be operated on have different signs, a two's complement conversion is performed on the mantissa portion of one of the two operands to be operated on via a reconstructed two's complement conversion device to obtain a first converted mantissa portion, wherein the number of at least one-level two's complement conversion units in the reconstructed two's complement conversion device for the group of operands is the same as the number of target segment units to which the group of operands is allocated; The step of adding the mantissa portions of the two operands to be operated on includes: adding the mantissa portion of the one of the two operands to be operated on that has not undergone the two's complement conversion to the mantissa portion of the first conversion.

5. The method according to claim 4, characterized in that, The two's complement conversion unit is configured as follows: The system receives input data, a mode selection signal, the carry output of the previous two's complement conversion unit, and a fixed zero value. The mode selection signal is used to determine whether the current two's complement conversion unit participates in the cascading. Based on the mode selection signal, one of the carry output of the previous two's complement conversion unit and the fixed zero value is selected as the carry input of this stage. In the case of cascading, the carry output of the previous two's complement conversion unit is selected as the carry input of this stage. In response to determining to perform a two's complement conversion, a two's complement conversion is performed based on the input data and the carry input of the current level to obtain the converted data and the carry output for the next level two's complement conversion unit.

6. The method according to claim 4, characterized in that, For each set of operands, after obtaining the first tail number result, perform the following operation: The first mantissa result is converted to its original code by a reconstructed inverse complement conversion device to obtain the first mantissa result in its original code form. The number of at least one inverse complement conversion units for the set of operands in the reconstructed inverse complement conversion device is the same as the number of target segment units to which the set of operands is allocated. The step of performing a shift operation for mantissa normalization on the first mantissa result includes performing a shift operation for mantissa normalization on the first mantissa result represented in sign-magnitude form.

7. The method according to claim 6, characterized in that, The inverse complement conversion unit is configured as follows: The system receives input data, a mode selection signal, the carry output of the previous inverse complement conversion unit, and a fixed zero value. The mode selection signal is used to determine whether the current inverse complement conversion unit participates in the cascading. Based on the mode selection signal, one of the carry output of the previous inverse complement conversion unit and the fixed zero value is selected as the carry input of this stage. In the case of cascading, the carry output of the previous inverse complement conversion unit is selected as the carry input of this stage. In response to determining to perform inverse complement conversion, the input data is subjected to inverse complement conversion to obtain inverse complement converted data and carry output for the next stage inverse complement conversion unit.

8. The method according to any one of claims 1 to 3, characterized in that, For each set of operands, perform the following operations: The number of leading zeros in the first mantissa result is detected by a reconstructed leading zero detection device, wherein the number of at least one leading zero detection units in the reconstructed leading zero detection device for the group of operands is the same as the number of target segment units to which the group of operands is assigned.

9. The method according to claim 8, characterized in that, The leading zero detection unit is configured as follows: The receiver receives a mode selection signal, input data, and multiple fixed offsets, wherein the mode selection signal is used to determine whether the current leading zero detection unit participates in the cascading. Based on the mode selection signal, one of the plurality of fixed offsets is selected as the reference value for this level; In response to determining to perform leading zero detection, leading zero detection is performed based on the input data to obtain the current level leading zero count, and an accumulation is performed based on the current level leading zero count and the current level reference value to obtain the current level leading zero detection output.

10. The method according to any one of claims 1 to 3, characterized in that, For each set of operands, perform the following operations: The second mantissa result obtained by mantissa normalization is rounded based on the nearest even number rounding method.

11. The method according to any one of claims 1 to 3, characterized in that, The method also includes performing special value detection on non-numbers, infinity, and zero.

12. A multi-precision floating-point data parallel processing device for application-specific integrated circuits, characterized in that, The device includes: The data receiving module is configured to receive at least one set of operands, each set of operands including two operands to be operated on with the same precision bit width. When multiple sets of operands are received, the precision bit widths of the operands in different sets may be the same or different. A data allocation module is configured to allocate at least one set of operands to a predetermined plurality of segment units based on the precision bit width of each set of operands, wherein the segment unit indicates a minimum granularity data channel with fixed bit width data processing capability, such that the total bit width of the target segment units allocated to each set of operands is the same as the precision bit width of that set of operands, the fixed bit width is determined based on the minimum precision bit width, and the number of the plurality of segment units is determined based on the ratio of the maximum precision bit width to the minimum precision bit width; The data processing module is configured to perform the following operations for each set of operands: Based on the exponent difference between the two operands to be operated on, a shift operation for mantissa alignment is performed on the operand with the smaller exponent via a reconstructed shifting device to obtain the mantissa portion of each of the two operands to be operated on, wherein the number of at least one shifter units in the reconstructed shifting device for the group of operands is the same as the number of target segment units to which the group of operands is allocated; Add the mantissa portions of the two operands to obtain the first mantissa result; Based on the number of leading zeros in the first mantissa result, the shifting device used for the reconstruction of the group of operands is reused to perform a shift operation for mantissa normalization on the first mantissa result to obtain a second mantissa result and determine the exponent adjustment value. Based on the second mantissa result and the exponent adjustment value, the floating-point addition result of this set of operands is obtained.

13. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method according to any one of claims 1-11.

15. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-11.

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