A verification method, device and equipment of DDR firmware, a storage medium and a program product

Abstract

The application discloses a verification method, device and equipment of DDR firmware, a storage medium and a program product. The DDR firmware is written through a first programming language, and the DDR firmware comprises DDR initialization logic layer code, a cross-platform interface layer code and platform adaptation implementation layer code; the DDR initialization logic layer code is loaded to a real CPU for execution, and a DPI-C interface is called to perform an initialization operation on a first virtual DDR module to verify a DDR initialization process; wherein the first virtual DDR module is in an IP simulation environment; when the DDR initialization process is verified, the DDR firmware is loaded to a virtual static random access memory (SRAM); a virtual CPU executes the DDR firmware, and a virtual data channel module is used to perform an initialization operation on a second virtual DDR module to verify a data channel in the initialization process; wherein the virtual SRAM, the virtual CPU, the virtual data channel module and the second virtual DDR module are all in an SOC simulation environment. The time cost of firmware code verification and debugging is greatly reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to a method, apparatus, device, storage medium and program product for verifying DDR firmware. Background Technology

[0002] With the development of DDR technology, the DDR initialization process has become increasingly complex. This often requires the DDR firmware to perform numerous complex timing calculations, function enable configurations, and memory training process control during the initialization phase. To ensure rapid DDR startup upon wafer return, thorough verification of the DDR firmware in the pre-silicon stage is crucial. Existing DDR pre-silicon verification methods suffer from the following drawbacks: high code maintenance costs and high verification time costs. Summary of the Invention

[0003] This invention provides a method and program product for verifying DDR firmware, which can not only save the code cost of DDR firmware verification, but also improve the verification efficiency.

[0004] In a first aspect, embodiments of the present invention provide a method for verifying DDR firmware, wherein the DDR firmware is written in a first programming language and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code; the method includes: The DDR initialization logic layer code is loaded into the real CPU for execution, and the DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; wherein, the first virtual DDR module is in an IP emulation environment; When the DDR initialization process is verified, the DDR firmware is loaded into the virtual static random access memory (SRAM); the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process; wherein, the virtual SRAM, virtual CPU, virtual data path module and the second virtual DDR module are all in the SOC simulation environment.

[0005] Secondly, embodiments of the present invention also provide a verification device for DDR firmware, wherein the DDR firmware is written in a first programming language, and the DDR firmware includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code; the device includes: The DDR initialization verification module is used to load the DDR initialization logic layer code into the real CPU for execution, and call the DPI-C interface to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; wherein, the first virtual DDR module is in an IP emulation environment; The data path verification module is used to load the DDR firmware into the virtual static random access memory (SRAM) when the DDR initialization process is verified to be successful; the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process; wherein the virtual SRAM, virtual CPU, virtual data path module and the second virtual DDR module are all in the SOC simulation environment.

[0006] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the DDR firmware verification method described in the embodiments of the present invention.

[0007] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer instructions, which are used to cause a processor to execute and implement the DDR firmware verification method described in the embodiments of the present invention.

[0008] Fifthly, embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the DDR firmware verification method as described in the embodiments of the present invention.

[0009] This invention discloses a method, apparatus, device, storage medium, and program product for verifying DDR firmware. The DDR firmware is written in a first programming language and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code. The method includes: loading the DDR initialization logic layer code into a real CPU for execution, and calling the DPI-C interface to perform initialization operations on a first virtual DDR module to verify the DDR initialization process; wherein the first virtual DDR module is in an IP emulation environment; when the DDR initialization process verification passes, loading the DDR firmware into a virtual static random access memory (SRAM); the virtual CPU executes the DDR firmware and performs initialization operations on a second virtual DDR module through a virtual data path module to verify the data path during the initialization process; wherein the virtual SRAM, virtual CPU, virtual data path module, and second virtual DDR module are all in a SOC emulation environment. The DDR firmware verification method provided in this invention verifies the DDR initialization process using a set of DDR firmware written in a first programming language. This eliminates the need for repeated secondary development during the development phase, reducing development costs. Furthermore, the verification of the DDR initialization process is performed during the IP simulation phase by a real CPU, with only the data paths used during initialization being verified in the SOC simulation phase. Therefore, this significantly reduces the time cost of firmware code verification and debugging. Attached Figure Description

[0010] Figure 1 This is a flowchart of a DDR firmware verification method according to Embodiment 1 of the present invention; Figure 2 This is a software architecture diagram of a DDR firmware according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of an IP emulation environment structure according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a SOC simulation environment structure according to Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of a DDR firmware verification device according to Embodiment 2 of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device according to Embodiment 3 of the present invention. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0014] The current mainstream pre-silicon verification scheme for DDR initialization firmware includes two stages: IP emulation and firmware writing (i.e., SOC emulation). The IP emulation stage involves writing the initialization process using System Verilog and verifying and debugging it in the UVM verification environment of the DDR IP. This stage primarily verifies the correctness of the initialization process. The firmware writing stage involves writing firmware C code that executes in a real SOC environment based on the debugged initialization process. The SOC emulation stage can involve verifying and debugging the DDR initialization firmware in a system-level emulation environment. This stage primarily verifies the firmware's code logic and the data path of the DDR initialization process. The core of this scheme is: first verifying the DDR initialization process in the IP verification environment, then converting the verified process into firmware C code, importing the firmware into SRAM in the system-level emulation environment, and executing it through the MCU or core in the emulation environment.

[0015] The existing technology has the following obvious drawbacks: 1. High code maintenance costs: Because the UVM environment uses System Verilog code, while the firmware needs to be written in C code, the code debugged during the IP simulation phase cannot be directly used in the firmware and needs to be manually converted to C code. This results in duplicated code development, and subsequent updates to the initialization process require modifications to both sets of code, leading to extremely high maintenance costs.

[0016] 2. High time cost for firmware code verification: Because the firmware code needs to be loaded into the virtual SRAM of the simulation environment and executed through the virtual MCU or core, verification can only be performed at the system-level. A single run typically takes tens of hours, resulting in high time costs for verification. Example 1 Figure 1 This is a flowchart of a DDR firmware verification method provided in Embodiment 1 of the present invention. This embodiment is applicable to the verification of DDR firmware. The method can be executed by a DDR firmware verification device, which can be implemented in the form of software and / or hardware, or optionally by an electronic device, such as a mobile terminal, a PC, or a server.

[0017] In this embodiment, Figure 2 This is a software architecture diagram of a DDR firmware according to an embodiment of the present invention. The DDR firmware is written in a first programming language, which can be C language. Figure 2 As shown, the DDR firmware includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code. The DDR initialization logic layer is responsible for implementing all DDR initialization processes, including timing calculation modules, hardware function enable modules, and memory training modules. The cross-platform interface layer abstracts interfaces related to the operating platform for use by the upper layer. These include the SMN interface for register access, as well as SMBUS, GPIO, and interrupt signal interfaces. The platform adaptation implementation layer implements the interfaces abstracted from the cross-platform interface layer according to the specific operating platform. The DPI-C interface is provided by the IP emulation environment. The firmware interface is implemented based on the SOC's data path and serves as the interface called by the firmware during runtime on the silicon chip and in SOC emulation.

[0018] The DDR initialization logic layer code and platform adaptation implementation layer code can be written with reference to the SOC design document. The cross-platform interface layer code is the logical interface implemented by the code framework in this solution. The DPI-C interface of the platform adaptation implementation layer code is provided by the IP emulation environment.

[0019] like Figure 1 As shown, the DDR firmware verification method in this embodiment specifically includes the following steps: S110 loads the DDR initialization logic layer code into the real CPU for execution and calls the DPI-C interface to perform initialization operations on the first virtual DDR module in order to verify the DDR initialization process.

[0020] The first virtual DDR module resides in an IP emulation environment. This first virtual DDR module can be a virtual module that simulates or mimics the functionality of DDR firmware and is deployed within the IP emulation environment.

[0021] For example, Figure 3 This is a schematic diagram of an IP emulation environment structure provided in Embodiment 1 of the present invention, as shown below. Figure 3 As shown, after loading the DDR initialization logic layer code into the real CPU, the real CPU, during the execution of the DDR initialization logic layer code, calls the DPI-C interface to operate the first virtual DDR module in the IP emulation environment, causing the first virtual DDR module to perform initialization operations. This decouples the real CPU from the SOC emulation environment, verifying the logical correctness of the DDR initialization process.

[0022] In this embodiment, the verification of the DDR initialization process mainly includes: the correctness of the initialization timing, the correctness of the register configuration, the initialization state machine logic, and verification of abnormal scenarios.

[0023] Optionally, the process of loading the DDR initialization logic layer code into the real CPU for execution and calling the DPI-C interface to perform initialization operations on the first virtual DDR module to verify the DDR initialization process can be as follows: the DDR initialization logic layer code is loaded into the real CPU and executed at native speed, and the DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; if the verification fails, the adjustment operation of the DDR initialization logic layer code is received, and the adjusted DDR initialization logic layer code is reloaded into the real CPU for execution until the DDR initialization process is verified.

[0024] In this embodiment, when the DDR initialization logic layer code is loaded into the real CPU for execution and fails to call the DPI-C interface to perform the initialization operation on the first virtual DDR module, the user is prompted to adjust the DDR initialization logic layer code. After the DDR initialization logic layer code is adjusted, the adjusted DDR initialization logic layer code is loaded into the real CPU again for execution at native speed to call the DPI-C interface to perform the initialization operation on the first virtual DDR module until the DDR initialization process is verified to be successful.

[0025] In this embodiment, by running the DDR initialization logic layer code on a real CPU, core signals of the DDR IP (such as reset signal, clock signal, configuration bus signal, and calibration completion signal) are captured to confirm that each step of the DDR initialization process meets expectations. Logical errors in the DDR initialization process are located through analysis of the core signals.

[0026] S120: When the DDR initialization process is verified, the DDR firmware is loaded into the virtual static random access memory (SRAM); the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process.

[0027] The virtual SRAM, virtual CPU, virtual data path module, and second virtual DDR module are all located in the SOC simulation environment. The virtual SRAM can be a virtual module that simulates or emulates the hardware and software functions of a real SRAM and is deployed in the SOC simulation environment; the virtual CPU can be a virtual module that simulates or emulates the hardware and software functions of a real CPU and is deployed in the SOC simulation environment; the virtual data path module can be a virtual module that simulates or emulates the hardware and software functions of a real data path and is deployed in the SOC simulation environment; the second virtual DDR module, which simulates or emulates the functions of the DDR firmware and is deployed in the IP simulation environment, is the same as the first virtual DDR module.

[0028] In this embodiment, since the DDR initialization process has been verified through the IP emulation environment in the above steps, in this step, the SOC emulation environment only needs to verify the data path used in the DDR initialization process, which is accomplished by loading the DDR firmware into the SRAM for execution.

[0029] For example, Figure 4 This is a schematic diagram of a SOC simulation environment structure in an embodiment of the present invention, such as... Figure 4 As shown, a virtual SRAM, a virtual CPU, a virtual data path module, and a second virtual DDR module are deployed in the SOC simulation environment, and the virtual SRAM, virtual CPU, and second virtual DDR module are all connected to the data path module.

[0030] In this embodiment, the virtual CPU executes the DDR firmware to perform an initialization operation on the second virtual DDR module through the virtual data path module. The process of initialization can be as follows: the virtual CPU reads the DDR firmware from the virtual SRAM and executes it through the virtual data path module; the virtual CPU performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process.

[0031] Specifically, after loading the DDR firmware into the virtual SRAM in the SOC simulation environment, the virtual CPU reads the DDR firmware from the virtual SRAM through the virtual data path module. During the execution of the DDR firmware, the virtual CPU operates the second virtual DDR module through the virtual data path module, causing the second virtual DDR module to perform initialization operations to verify the data path during the initialization process.

[0032] Optionally, the following steps are also included: if the data path verification fails, the adjustment operation of the virtual data path module and the data path in the initialization process is received, the virtual CPU executes the DDR firmware again, and performs an initialization operation on the second virtual DDR module through the adjusted virtual data path module to re-verify the data path in the initialization process until the verification passes.

[0033] In this embodiment, when the second virtual DDR module fails to perform the initialization operation, the user is prompted to synchronize the real data path and virtual data path module during the initialization process. After the adjustment is completed, the virtual CPU executes the DDR firmware again and performs the initialization operation on the second virtual DDR module through the adjusted virtual data path module to re-verify the data path during the initialization process until the verification is successful.

[0034] In this embodiment, by capturing read and write transactions of the system-level bus, errors in the data path (such as bus timeouts and data parity errors) are analyzed, and the data path is adjusted based on the errors to ensure that the data path verification passes.

[0035] Through the implementation of the above specific solutions, this invention achieves the following significant advantages over existing technologies: 1. Reduced code development and maintenance costs: Since this solution merges the two initialization processes based on System Verilog and C code in the traditional method into a single C code, no secondary development is required during the development phase, reducing development costs. Subsequent updates to the initialization process only require updating the C code, further reducing maintenance costs. 2. Reduced verification time costs: Unlike traditional methods that place the verification of DDR initialization firmware entirely in SOC simulation, this solution verifies the entire firmware logic during the IP simulation phase using a real CPU. In the SOC simulation phase, only the data paths used during initialization are verified. Therefore, the time costs for firmware code verification and debugging are significantly reduced.

[0036] In this embodiment, the DDR firmware is written in a first programming language and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code. The method includes: loading the DDR initialization logic layer code into a real CPU for execution, and calling the DPI-C interface to perform initialization operations on a first virtual DDR module to verify the DDR initialization process; wherein the first virtual DDR module is in an IP emulation environment; when the DDR initialization process verification passes, the DDR firmware is loaded into a virtual static random access memory (SRAM); the virtual CPU executes the DDR firmware and performs initialization operations on a second virtual DDR module through a virtual data path module to verify the data path during initialization; wherein the virtual SRAM, virtual CPU, virtual data path module, and second virtual DDR module are all in a SOC emulation environment. The DDR firmware verification method provided by this embodiment completes the DDR initialization process verification using a set of DDR firmware written in a first programming language, eliminating the need for repeated secondary development during the development phase and reducing development costs; by placing the DDR initialization process verification in the IP emulation stage and having it performed by a real CPU, only the data path used during initialization is verified in the SOC emulation stage. Therefore, the time cost of firmware code verification and debugging can be greatly reduced.

[0037] Example 2 Figure 5 This is a schematic diagram of a DDR firmware verification device provided in Embodiment 2 of the present invention. The DDR firmware is written in a first programming language and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code. The device includes: The DDR initialization verification module 510 is used to load the DDR initialization logic layer code into the real CPU for execution, and call the DPI-C interface to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; wherein, the first virtual DDR module is in an IP emulation environment; The data path verification module 520 is used to load the DDR firmware into the virtual static random access memory (SRAM) when the DDR initialization process verification is successful; the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process; wherein the virtual SRAM, virtual CPU, virtual data path module and the second virtual DDR module are all in the SOC simulation environment.

[0038] Optionally, the DDR initialization verification module 510 is also used for: The DDR initialization logic layer code is loaded into the real CPU and executed at native speed. The DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process. If the verification fails, the adjustment operation of the DDR initialization logic layer code is received, and the adjusted DDR initialization logic layer code is reloaded into the real CPU for execution until the DDR initialization process is verified.

[0039] Optionally, the virtual SRAM, virtual CPU, and the second virtual DDR module are all connected to the virtual data path module.

[0040] Optionally, the data path verification module 520 is also used for: The virtual CPU reads and executes DDR firmware from the virtual SRAM through the virtual data path module; The virtual data path module performs an initialization operation on the second virtual DDR module to verify the data path during the initialization process.

[0041] Optionally, the data path verification module 520 is also used for: If the data path verification fails, the virtual CPU receives an adjustment operation on the virtual data path module and the data path during the initialization process. The virtual CPU then executes the DDR firmware again and performs an initialization operation on the second virtual DDR module through the adjusted virtual data path module to re-verify the data path during the initialization process until the verification passes.

[0042] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in this embodiment can be found in the DDR firmware verification method provided in all the foregoing embodiments of the present invention.

[0043] Example 3 Figure 6 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components, connections and relationships between components, and their functions shown herein are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0044] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0045] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0046] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the verification method for DDR firmware.

[0047] In some embodiments, the DDR firmware verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the DDR firmware verification method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the DDR firmware verification method by any other suitable means (e.g., by means of firmware).

[0048] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0049] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0050] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0051] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0052] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0053] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0054] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the DDR firmware verification method provided in any embodiment of this application.

[0055] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0056] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0057] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for verifying DDR firmware, characterized in that, The DDR firmware is written in a first programming language and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code; the method includes: The DDR initialization logic layer code is loaded into the real CPU for execution, and the DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; wherein, the first virtual DDR module is in an IP emulation environment; When the DDR initialization process is verified, the DDR firmware is loaded into the virtual static random access memory (SRAM); the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process; wherein, the virtual SRAM, virtual CPU, virtual data path module and the second virtual DDR module are all in the SOC simulation environment.

2. The method according to claim 1, characterized in that, The DDR initialization logic layer code is loaded into the real CPU for execution, and the DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process, including: The DDR initialization logic layer code is loaded into the real CPU and executed at native speed. The DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process. If the verification fails, the adjustment operation of the DDR initialization logic layer code is received, and the adjusted DDR initialization logic layer code is reloaded into the real CPU for execution until the DDR initialization process is verified.

3. The method according to claim 1, characterized in that, The virtual SRAM, virtual CPU, and the second virtual DDR module are all connected to the virtual data path module.

4. The method according to claim 3, characterized in that, The virtual CPU executes the DDR firmware to perform initialization operations on the second virtual DDR module through the virtual data path module, and to verify the data path during the initialization process, including: The virtual CPU reads and executes DDR firmware from the virtual SRAM through the virtual data path module; The virtual data path module performs an initialization operation on the second virtual DDR module to verify the data path during the initialization process.

5. The method according to claim 4, characterized in that, Also includes: If the data path verification fails, the virtual CPU receives an adjustment operation on the virtual data path module and the data path during the initialization process. The virtual CPU then executes the DDR firmware again and performs an initialization operation on the second virtual DDR module through the adjusted virtual data path module to re-verify the data path during the initialization process until the verification passes.

6. A verification device for DDR firmware, characterized in that, The DDR firmware is written in a first programming language, and includes DDR initialization logic layer code, cross-platform interface layer code, and platform adaptation implementation layer code; the device includes: The DDR initialization verification module is used to load the DDR initialization logic layer code into the real CPU for execution, and call the DPI-C interface to perform initialization operations on the first virtual DDR module to verify the DDR initialization process; wherein, the first virtual DDR module is in an IP emulation environment; The data path verification module is used to load the DDR firmware into the virtual static random access memory (SRAM) when the DDR initialization process is verified to be successful; the virtual CPU executes the DDR firmware and performs an initialization operation on the second virtual DDR module through the virtual data path module to verify the data path during the initialization process; wherein the virtual SRAM, virtual CPU, virtual data path module and the second virtual DDR module are all in the SOC simulation environment.

7. The apparatus according to claim 6, characterized in that, The DDR initialization verification module is also used for: The DDR initialization logic layer code is loaded into the real CPU and executed at native speed. The DPI-C interface is called to perform initialization operations on the first virtual DDR module to verify the DDR initialization process. If the verification fails, the adjustment operation of the DDR initialization logic layer code is received, and the adjusted DDR initialization logic layer code is reloaded into the real CPU for execution until the DDR initialization process is verified.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the verification method of the DDR firmware according to any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the verification method of the DDR firmware according to any one of claims 1-5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the verification method of the DDR firmware as described in any one of claims 1-5.

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