A BMS batch flashing method, device, equipment and storage medium

Abstract

This invention relates to the field of battery management system (BMS) technology, specifically to a BMS batch flashing method, apparatus, device, and storage medium. The method includes: during batch flashing, real-time monitoring of communication load parameters and calculation of bus occupancy; when the bus occupancy meets the parallelism adjustment rules, initial adjustment of the current parallelism is performed with a step size of 1 to obtain a pending parallelism; subsequently, stability verification is performed on the pending parallelism; if the verification result is stable, the above monitoring and adjustment steps are repeated, and the pending parallelism is adjusted multiple times to obtain the optimal parallelism for batch flashing. This invention ensures that the system has sufficient time to converge to a stable state after each change through a gradual adjustment method with a step size of 1; the stability verification mechanism prevents false, short-term stability from misleading adjustment decisions; and the strategy of iteratively adjusting until the optimal parallelism is found achieves the best balance between efficiency and stability.

Description

Technical Field

[0001] This invention relates to the field of battery management system technology, specifically to a method, apparatus, device, and storage medium for batch flashing and writing a BMS. Background Technology

[0002] A Battery Management System (BMS) is a core component in electric vehicles, energy storage systems, and other fields used to monitor battery status, ensure battery safety, optimize battery performance, and extend battery life. Its operational stability and functional integrity directly determine the reliability and safety of the entire energy storage or power system. During BMS manufacturing, maintenance, and software upgrades, a large number of BMS devices need to be programmed (also known as firmware flashing). This involves writing preset control programs and algorithm logic in binary form into the BMS's storage unit to achieve the BMS's intended functions or upgrade existing functions. Therefore, batch BMS programming is a critical process in BMS production and operation, and its efficiency and success rate directly affect production capacity, maintenance costs, and the subsequent operational stability of the system.

[0003] Currently, in existing BMS batch flashing processes, the parallelism control methods for parallel flashing mainly fall into two categories: one is to use a fixed parallelism for flashing; the other is to significantly adjust the parallelism all at once based on the communication load monitoring results during the flashing process. Both of these control methods are widely used in various BMS batch flashing tools, but in practical applications, they both have significant technical shortcomings, making it difficult to balance flashing efficiency, communication stability, and resource utilization. Specifically: Firstly, using a control method with a fixed degree of parallelism can lead to several problems. If the parallelism is set too high, a large amount of data will accumulate in the communication link when the load increases, causing communication congestion and resulting in data loss and timeouts, which seriously affects the success rate of the write operation. If the parallelism is set too low, even if the communication link is under low load, communication resources and host computer processing resources cannot be fully utilized, resulting in low write efficiency and wasted resources. This defect is particularly prominent in large-scale BMS batch write scenarios, which will significantly increase the time cost of production or maintenance.

[0004] Secondly, the core flaw of the control method that drastically adjusts the parallelism at once is that excessively large adjustments can easily lead to system instability, thereby affecting the flashing success rate. For example, when the communication load is detected to be low, drastically increasing the parallelism from 3 to 10 at once will cause the load on the communication link to surge instantly, exceeding the link's capacity. This can not only cause communication congestion but may also lead to communication handshake failures between the host computer and the BMS device, session interruptions, or even cause the BMS device to enter an abnormal state. Conversely, when the communication load is detected to be high, drastically decreasing the parallelism from 10 to 3 at once will cause the load on the communication link to drop instantly. Previously fully utilized communication resources and host computer processing resources will become idle, resulting in resource waste. At the same time, the sudden drop in parallelism may also cause process disorder in some devices already in the flashing process, further reducing the flashing success rate.

[0005] In summary, the existing parallelism control methods in the batch flashing process of BMS have obvious defects. They cannot achieve dynamic and stable adjustment of parallelism, and it is difficult to balance flashing efficiency, communication stability and resource utilization. They cannot meet the high-efficiency and reliable flashing requirements in large-scale BMS batch flashing scenarios. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention provides a BMS batch writing method, apparatus, device and storage medium, which improves writing efficiency while ensuring stability.

[0007] The technical means adopted by this invention to solve its technical problem is: a BMS batch flashing method, the method comprising: S1. Monitor the real-time parameters of the communication load during the current batch flashing process, and calculate the real-time bus occupancy rate based on the real-time parameters; S2. Based on the real-time bus occupancy rate meeting the preset parallelism adjustment rules, the current parallelism in the current batch writing process is initially adjusted in a step size of 1 to obtain the undetermined parallelism. S3. Perform stability verification on the undetermined parallelism to obtain a stability verification result; the stability verification result is used to indicate the stable state of the adjusted undetermined parallelism. S4. Based on the stability verification result indicating that the undetermined parallelism is stable, repeat S1 and S2 until the optimal parallelism is obtained, and perform batch writing according to the optimal parallelism; the optimal parallelism is the maximum parallelism in a stable state.

[0008] Preferably, S1 includes: Get the number of data packets per unit time and the maximum bus capacity during the current batch flashing process; The real-time bus occupancy rate is obtained by calculating the ratio of the number of data packets per unit time to the maximum bus capacity.

[0009] Preferably, S2 includes: Based on the fact that the real-time bus occupancy rate is within the first threshold range, the current parallelism in the current batch writing process is incremented by 1 to obtain the undetermined parallelism. Based on the fact that the real-time bus occupancy rate is within the second threshold range, the current parallelism in the current batch writing process is kept unchanged to obtain the undetermined parallelism. Based on the fact that the real-time bus occupancy rate is within the third threshold range, the current parallelism in the current batch writing process is reduced by 1 to obtain the undetermined parallelism.

[0010] Preferably, S3 includes: The writing process continues according to the undetermined parallelism, and the bus occupancy rate and writing success rate are continuously monitored after several writing processes according to the undetermined parallelism. During the aforementioned monitoring processes, if the average bus occupancy rate is within a preset threshold range and the write success rate is not less than the preset write threshold, then the stability verification result indicates that the adjusted undetermined parallelism is stable. During the aforementioned monitoring processes, if the average bus occupancy rate is not within the preset threshold range, or the write success rate is less than the preset write threshold, the stability verification result indicates that the adjusted pending parallelism is unstable.

[0011] Preferably, S3 further includes: Record the number of stable iterations after repeated adjustments of the undetermined parallelism. If the number of stable iterations is not less than the preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be truly stable. If the number of stable iterations is less than a preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be falsely stable.

[0012] Preferably, the method includes: Based on the stability verification results indicating that the adjusted undetermined parallelism is unstable or pseudo-stable, the undetermined parallelism is reduced in steps of 1 until the optimal parallelism is obtained.

[0013] Preferably, S2 further includes: Get the minimum parallelism and maximum number of channels in the current batch write process; If the undetermined parallelism is greater than the maximum number of channels, then the maximum number of channels is used as the undetermined parallelism. If the undetermined parallelism is less than the minimum parallelism, then the minimum parallelism is taken as the undetermined parallelism.

[0014] The technical means adopted by this invention to solve its technical problem is: a BMS batch flashing device, the device comprising: The parameter calculation module is used to monitor the real-time parameters of the communication load during the current batch flashing process and calculate the real-time bus occupancy rate based on the real-time parameters. The pending adjustment module is used to make a preliminary adjustment to the current parallelism in the current batch writing process based on the real-time bus occupancy rate meeting the preset parallelism adjustment rules, with a step size of 1, to obtain the pending parallelism. A stability verification module is used to verify the stability of the undetermined parallelism and obtain a stability verification result; the stability verification result is used to indicate the stable state of the adjusted undetermined parallelism. The batch write module is used to trigger the parameter calculation module and the pending adjustment module to repeat execution until the optimal parallelism is obtained based on the stability verification result indicating that the pending parallelism is stable, and to perform batch write according to the optimal parallelism; the optimal parallelism is the maximum parallelism in the stable state.

[0015] The technical means adopted by the present invention to solve its technical problem is: an electronic device, comprising: at least one processor and at least one memory, wherein the memory stores program instructions or code; the program instructions or code are loaded and executed by the processor, thereby enabling the electronic device to implement the BMS batch flashing method as described in any of the preceding claims.

[0016] The technical means adopted by the present invention to solve its technical problem is: a storage medium storing program instructions or code thereon, wherein the program instructions or code are loaded and executed by a processor to realize the BMS batch flashing method as described in any of the above claims.

[0017] The beneficial effects of this invention are: By monitoring communication load parameters, the current parallelism is initially adjusted in steps of 1, and the stability of the adjusted parallelism is continuously monitored. The parallelism is gradually increased or decreased based on the stability results. Under the premise of ensuring stability, the optimal parallelism is gradually found through progressive adjustment. This can avoid resource waste and improve writing efficiency while ensuring stability. It is particularly suitable for batch writing scenarios of BMS of different scales. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a batch flashing method for a BMS according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the S1 method according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the S2 method according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating the S3 method according to an embodiment of the present invention; Figure 5 This is a timing diagram illustrating a gradual adjustment of parallelism according to an embodiment of the present invention; Figure 6 This is a flowchart illustrating another method S3 according to an embodiment of the present invention; Figure 7 This is a flowchart illustrating another method S3 according to an embodiment of the present invention; Figure 8 This is a structural block diagram of a BMS batch writing device according to an embodiment of the present invention; Figure 9 This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0020] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0021] like Figure 1 As shown, this invention provides a BMS batch flashing method, the method comprising: S1. Monitor the real-time parameters of the communication load during the current batch flashing process, and calculate the real-time bus occupancy rate based on the real-time parameters.

[0022] The real-time parameters of the communication load refer to the data traffic characteristics on the communication bus during batch writing, including the number of data packets or data frame density per unit time. Real-time bus occupancy is a quantitative indicator of the current busyness of the communication bus, representing the proportion of the bus occupied by valid data. The purpose of this step is to obtain the current load status of the communication environment, providing a basis for subsequent parallelism adjustments.

[0023] S2. Based on the real-time bus occupancy rate meeting the preset parallelism adjustment rules, the current parallelism in the current batch writing process is initially adjusted in a step of 1 to obtain the undetermined parallelism.

[0024] Parallelism refers to the number of BMSs performing simultaneous write operations. A step size of 1 means that each adjustment only adds or removes one BMS for parallel write operations, disallowing jump adjustments. The preset parallelism adjustment rules divide the bus occupancy rate into different intervals, with each interval corresponding to a specific adjustment action. The core purpose of this step is to probe the system capacity boundaries through small steps, avoiding communication storms or resource idleness caused by large adjustments.

[0025] S3. Perform stability verification on the desired parallelism and obtain the stability verification result; the stability verification result is used to indicate the stable state of the adjusted desired parallelism.

[0026] Stability verification involves performing a write / flush operation for a period of time at the desired parallelism, monitoring whether multiple metrics meet preset stability conditions during this period. This step aims to prevent initial adjustments to the parallelism from meeting instantaneous bus occupancy requirements but causing oscillations or instability during continuous operation. Stability verification requires collecting data from multiple cycles, rather than relying on a single measurement result.

[0027] S4. Based on the stable verification result indicating that the undetermined parallelism is stable, repeat S1 and S2 until the optimal parallelism is obtained, and perform batch writing according to the optimal parallelism; the optimal parallelism is the maximum parallelism in the stable state.

[0028] Once an adjustment achieves stability, this invention does not stop the adjustment process but continues to attempt to further increase the parallelism until an adjustment leads to instability. At this point, the previous stable parallelism is the optimal parallelism. This asymptotic approximation method can find the maximum throughput of the system while ensuring stability.

[0029] In the above embodiments, this invention avoids the dual problems of communication congestion and resource waste through gradual adjustment. The step size of 1 ensures that the system has sufficient time to converge to a stable state after each change. A stability verification mechanism prevents false, transient stability from misleading adjustment decisions. The strategy of iteratively adjusting until the optimal parallelism is found achieves the best balance between efficiency and stability. The entire method does not require manual pre-setting of the parallelism and can automatically adapt to different hardware environments and the number of battery management systems.

[0030] In a preferred embodiment, such as Figure 2 As shown, step S1 may include: S101. Obtain the number of data packets per unit time and the maximum bus capacity of the communication load during the current batch flashing process; S102. Calculate the ratio of the number of data packets per unit time to the maximum bus capacity to obtain the real-time bus occupancy rate.

[0031] Here, "unit time" refers to a pre-defined statistical period length, typically 1 second. "Number of data packets" refers to the total number of complete data frames transmitted on the communication bus within a unit of time; each data frame, from start bit to end bit, is counted as one data packet. "Maximum bus capacity" refers to the theoretically maximum number of data packets that the communication bus can transmit within a unit of time; this value is determined by the physical layer protocol and bit rate of the communication bus, such as 1000 frames / second for the CAN bus. "Real-time bus occupancy" is a dimensionless value between 0% and 100%, characterizing the bus's activity level.

[0032] In one specific embodiment, the host computer communicates with 10 BMS via a CAN bus. The host computer sets a timer with a 1-second cycle. Within this 1-second cycle, the total number of data packets transmitted on the bus is 480, and the real-time bus occupancy rate is 48%.

[0033] This embodiment uses a ratio method to calculate bus occupancy, which has clear physical meaning and engineering interpretability. The introduction of a unit-time statistical window smooths out occupancy changes, avoiding misjudgments caused by instantaneous fluctuations. Calculating the ratio of data packet count to the maximum bus capacity involves only division and multiplication operations, resulting in minimal computational overhead and making it suitable for real-time operation in embedded environments. This method is not dependent on a specific bus protocol; it is applicable as long as the number of data packets can be statistically analyzed.

[0034] In a preferred embodiment, the present invention provides a parallelism adjustment rule, such as... Figure 3 As shown, step S2 may include: S201. Based on the real-time bus occupancy rate being within the first threshold range, increment the current parallelism of the current batch writing process by 1 to obtain the undetermined parallelism. S202. Based on the real-time bus occupancy rate being within the second threshold range, the current parallelism in the current batch writing process remains unchanged to obtain the undetermined parallelism. S203. Based on the real-time bus occupancy rate being within the third threshold range, the current parallelism in the current batch writing process is reduced by 1 to obtain the undetermined parallelism.

[0035] The first threshold range is greater than or equal to 0% and less than 50%, the second threshold range is greater than or equal to 50% and less than 80%, and the third threshold range is greater than or equal to 80% and less than or equal to 100%. In this invention, the second threshold range is set as the ideal range of BMS bus occupancy. Based on this ideal range, the optimal parallelism is sought, which can not lead to communication congestion or resource waste, but also improve the efficiency of BMS batch writing.

[0036] Taking the above real-time bus occupancy rate of 48% as an example, it is within the first threshold range, indicating that the current bus idle resources are sufficient. Therefore, the current parallelism is incremented by 1 to obtain the undetermined parallelism.

[0037] This embodiment simplifies the control logic by discretizing the continuous bus occupancy rate into three explicit adjustment actions. The addition and subtraction operations with a step size of 1 ensure smooth changes in parallelism, preventing system oscillations caused by excessively large single adjustments. The intermediate range maintaining constant parallelism provides a buffer, allowing the parallelism to operate stably within the ideal load range without frequent adjustments.

[0038] In a preferred embodiment, such as Figure 4 As shown, step S3 may include: S301. Continuously write according to the undetermined parallelism, and continuously monitor the bus occupancy rate and writing success rate after writing according to the undetermined parallelism several times. S302. If, during several monitoring processes, the average bus occupancy rate is within the preset threshold range and the write success rate is not less than the preset write threshold, then the stability verification result indicates that the adjusted undetermined parallelism is stable. S303. If, during several monitoring processes, the average bus occupancy rate is not within the preset threshold range, or the write success rate is less than the preset write threshold, the stability verification result indicates that the adjusted pending parallelism is unstable.

[0039] Specifically, taking a BMS batch flashing tool with a preset threshold range of 50%-80%, a preset flashing threshold of 95%, supporting simultaneous flashing of up to 10 BMSs, and a minimum parallelism of 1, connected to the BMS via a CAN bus, with an initial parallelism set to 3 as an example.

[0040] When the real-time bus occupancy rate is detected to be 45%, which is within the first threshold range, the initial parallelism is increased by 1 according to the preset parallelism adjustment rules, and adjusted to 4 as the pending parallelism.

[0041] After initial adjustments, the parallelism was further reduced to 4 for flashing. In five consecutive monitoring runs, the bus utilization rates were 48%, 52%, 49%, 51%, and 50%, with an average of 50%, within the preset threshold range of 50%-80%. Furthermore, the flashing success rate was 100%. Therefore, the adjustment was considered successful, and the stability verification results indicate that the adjusted parallelism is stable. Figure 5 The figure shown is a timing diagram of the gradual adjustment of parallelism in an embodiment of the present invention.

[0042] Second adjustment: Then, continue to repeat steps S1 and S2 with a parallelism of 4. After the initial adjustment, the bus occupancy rate in the host computer is 47%, which is within the first threshold range. According to the preset parallelism adjustment rules, the pending parallelism is increased by 1 and adjusted to 5 as the new pending parallelism.

[0043] Next, continue writing using a parallelism of 5. In five consecutive monitoring sessions, the bus occupancy rates were 53%, 55%, 52%, 54%, and 56%, with an average of 54%, which is within the preset threshold range of 50%-80%. Furthermore, the writing success rate was 100%, indicating that the above adjustment was successful. In other words, the stability verification result indicates that the adjusted parallelism is stable.

[0044] Third adjustment: Then, continue to repeat steps S1 and S2 with a parallelism of 5. After the second adjustment, the bus occupancy rate read directly from the host computer is 46%, which is within the first threshold range. According to the preset parallelism adjustment rules, the pending parallelism is increased by 1 and adjusted to 6 as the new pending parallelism.

[0045] Next, continue writing using a parallelism of 6. In five consecutive monitoring sessions, the bus utilization rates were 58%, 62%, 59%, 61%, and 60%, with an average of 60%, which is within the preset threshold range of 50%-80%. Furthermore, the writing success rate was 98%, indicating that the above adjustment was successful. In other words, the stability verification result indicates that the adjusted parallelism is stable.

[0046] Fourth adjustment: Then, continue to repeat steps S1 and S2 with a parallelism of 6. After the third adjustment, the bus occupancy rate read directly from the host computer is 44%, which is within the first threshold range. According to the preset parallelism adjustment rules, the pending parallelism is increased by 1 and adjusted to 7 as the new pending parallelism.

[0047] Next, continue writing using a parallelism of 7. In five consecutive monitoring sessions, the bus utilization rates were 72%, 75%, 73%, 74%, and 76%, with an average of 74%, which is within the preset threshold range of 50%-80%. Furthermore, the writing success rate was 96%, indicating that the above adjustment was successful. In other words, the stability verification result indicates that the adjusted parallelism is stable.

[0048] Through the above steps, multi-cycle verification avoids misjudgments caused by single, accidental factors. Simultaneous monitoring of both bus utilization and write success rate ensures comprehensive stability assessment. Bus utilization reflects the communication layer load status, while write success rate reflects the application layer execution effect; the two are complementary. Average value calculation smooths out short-term fluctuations, making the judgment results more reliable. While ensuring stability, parallelism is gradually increased, and the bus utilization is pushed as close as possible to the upper limit of the preset range, significantly improving resource utilization and increasing the number of BMSs that can be written simultaneously, thus improving the efficiency of batch BMS writes.

[0049] In a preferred embodiment, such as Figure 6 As shown, S3 also includes: S304. Record the number of stable iterations after repeated adjustments to the undetermined parallelism. S305. If the number of stable iterations is not less than the preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be truly stable. S306. If the number of stable iterations is less than the preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be falsely stable.

[0050] Repeated adjustments refer to situations where the same parallelism value is repeatedly adjusted and verified, and that the parallelism is repeatedly verified as stable. The number of times the same parallelism value is verified as stable is the cumulative number of times. The preset stability threshold is usually set to an integer greater than or equal to 2, with a typical value of 3. True stability indicates that the parallelism has shown stability after multiple independent verifications and has high reliability. False stability indicates that although the parallelism was verified as stable at one time, the number of repeated verifications was insufficient, and there may be randomness involved.

[0051] In the application, this step maintains a lookup table to record the number of times each parallelism value has been verified as stable. When a stability verification result is stable, the lookup table is searched for the existing stable count corresponding to the undetermined parallelism. If it does not exist, it is initialized to 1; if it exists, the count is incremented by 1. Then, the updated stable count is compared with the preset stability threshold.

[0052] Specifically, assume a preset stability threshold of 3. After initially adjusting the parallelism from 5 to 6, the stability verification result is stable, and the stability count for parallelism 6 in the lookup table changes from 0 to 1. Since 1 is less than 3, the verification result is false stability. After the system continues running with parallelism 6 for a period, the verification result is stable again. This time, the stability count for parallelism 6 in the lookup table increases to 2, still less than 3, so the verification result is still false stability. The system continues running with parallelism 6 for a period, and the verification result is still stable, with the stability count reaching 3. At this point, the verification result becomes truly stable. After this, the system can consider parallelism 6 to be truly reliable. Conversely, if an adjustment from 5 to 6 results in instability, the stability count for parallelism 6 in the lookup table is reset to zero. This false stability design avoids premature adoption of an unstable parallelism due to a single accidental success.

[0053] This embodiment eliminates false stability judgments caused by temporary bus idleness or other transient factors through repeated verification. The mechanism of accumulating stable counts ensures that the system remembers each degree of parallelism, preventing the complete rejection of a parallelism due to a single instance of instability, nor over-reliance on a parallelism due to a single instance of stability. This method is particularly suitable for batch write scenarios where communication environments exhibit random fluctuations.

[0054] In a preferred embodiment, the method further includes: Based on the stability verification results indicating that the adjusted undetermined parallelism is unstable or pseudo-stable, the undetermined parallelism is reduced in steps of 1 until the optimal parallelism is obtained.

[0055] In application, this step first determines the type of stability verification result. If the result is unstable or falsely stable, it indicates that the currently attempted undetermined parallelism is unreliable. At this point, the system stops attempting to increase the parallelism and instead begins a rollback operation. The rollback operation involves decrementing the current parallelism by 1, and then re-performing the stability verification with this reduced parallelism. If the re-verification result is still unstable or falsely stable, the parallelism is decremented by 1 again, and this process is repeated. This continues until a parallelism reduced by 1 is determined to be truly stable after stability verification. At this point, the rollback stops, and this parallelism is determined as the optimal parallelism. The rollback process reduces only one parallelism at a time, ensuring a gradual rollback and avoiding the resource waste caused by jumping directly from a high parallelism to a low parallelism.

[0056] Taking the aforementioned parallelism as an example, after writing with a parallelism of 7, the bus occupancy rate monitored by the host computer is 43%, which is within the first threshold range. The pending parallelism is then adjusted to 8.

[0057] However, in three consecutive monitoring tests after adjusting the pending parallelism to 8, the bus utilization rates were 82%, 85%, and 83%, with an average of 83.3%, exceeding the preset threshold. At this point, the stability verification result indicates that the pending parallelism of 8 is unstable. Therefore, the pending parallelism needs to be reduced to 7, and stability verification should be performed again at parallelism of 7. If the verification result for parallelism of 7 is truly stable, the rollback stops, the optimal parallelism is determined to be 7, and batch flashing is performed. If the verification result for parallelism of 7 is still unstable, it is further reduced to 6, and verification is performed again at parallelism of 6. Assuming that parallelism of 6 is truly stable, the optimal parallelism is 6.

[0058] In a pseudo-stable scenario, assuming the mechanism determines that the stability of parallelism 7 occurs only once, less than the threshold of 3, the verification result is considered pseudo-stable. The system then triggers a rollback, reducing the parallelism to 6 and re-verifying. This rollback will not continue indefinitely because the minimum parallelism of 1 is always truly stable.

[0059] It's worth noting that the optimal parallelism can be determined using the first-success principle, where the first parallelism to pass true stability verification during the rollback process is adopted as the optimal parallelism. Alternatively, the least rollback principle can be used, recording all parallelisms that pass true stability verification during the rollback process and selecting the largest one as the optimal parallelism. This principle preserves the maximum possible stable parallelism.

[0060] In one embodiment of the continuously decreasing method, a certain BMS batch writing tool supports simultaneous writing of up to 10 BMSs, connected via a CAN bus, with an initial parallelism set to 8.

[0061] The flashing process is as follows: Initial stage: Parallelism = 8, monitoring bus occupancy rate is 86% (≥80%), according to the gradual adjustment rule, the parallelism is adjusted to 7.

[0062] After the first adjustment: Continue writing using a parallelism of 7. Monitor bus occupancy every 10 seconds for 5 consecutive times, obtaining instantaneous values ​​of 85%, 83%, 81%, 79%, and 78%, respectively. The arithmetic mean of these 5 monitored values ​​is 81.2% (≥80%). The write success rate is 88% (<95%). The stability assessment is unstable, and the parallelism is reduced to 6.

[0063] After the second adjustment: Continue writing using a parallelism of 6. Five consecutive monitoring cycles were performed, with instantaneous values ​​of 68%, 65%, 62%, 60%, and 58%, respectively. The arithmetic mean was 62.6%, falling within the 50%–80% range, and the writing success rate was 97% (≥95%), indicating a successful adjustment.

[0064] Final status: The system confirmed that a parallelism of 6 is a stable parallelism under the current environment. In subsequent monitoring, the average bus occupancy rate remained within the range of 50% to 80% every 5 monitoring sessions, and the flashing success rate remained stable at over 95%.

[0065] This embodiment incorporates both unstable and pseudo-stable scenarios into the rollback trigger condition, reflecting a comprehensive and conservative safety design philosophy. The re-verification mechanism during the rollback process ensures that the final determined optimal parallelism has indeed been confirmed by the current verification standard, rather than based on historical information.

[0066] In a preferred embodiment, such as Figure 7 As shown, S2 also includes: S204. Obtain the minimum parallelism and maximum number of channels in the current batch flashing process; S205. If the undetermined parallelism is greater than the maximum number of channels, then the maximum number of channels shall be used as the undetermined parallelism. S206. If the undetermined parallelism is less than the minimum parallelism, then the minimum parallelism shall be used as the undetermined parallelism.

[0067] In this application, boundary check logic is inserted after obtaining the pending parallelism and before performing stability verification. First, the minimum parallelism and maximum number of channels are read from the system configuration parameters. The minimum parallelism is typically hardcoded to 1. The maximum number of channels needs to be obtained based on the actual hardware configuration. For example, the maximum number of nodes connected to a controller area network bus is limited by the bus electrical characteristics and transceiver drive capability, typically 32, but in actual batch flashing tools, the maximum number of channels may be set to 10 based on the host computer's port configuration. Then, two comparison checks are performed. The first check checks if the pending parallelism is greater than the maximum number of channels; if so, the pending parallelism is forcibly set to the maximum number of channels. The second check checks if the pending parallelism is less than the minimum parallelism; if so, the pending parallelism is forcibly set to the minimum parallelism. After the boundary check is completed, the trimmed pending parallelism is used to continue with subsequent stability verification.

[0068] Specifically, assume the system is configured with a minimum parallelism of 1 and a maximum number of channels of 10. In the first case, the current parallelism is 9, and the real-time bus utilization is 45%. According to the adjustment rules, it should be increased by 1 to obtain a pending parallelism of 10. Since the pending parallelism of 10 equals the maximum number of channels and does not exceed the boundary, it remains unchanged at 10. In the second case, the current parallelism is 10, and the real-time bus utilization is 45%. Increasing by 1 results in a pending parallelism of 11. Because 11 is greater than the maximum number of channels of 10, the pending parallelism is pruned to 10. In the third case, the current parallelism is 1, and the real-time bus utilization is 82%. According to the adjustment rules, it should be decreased by 1 to obtain a pending parallelism of 0. Because 0 is less than the minimum parallelism of 1, the pending parallelism is pruned to 1. Boundary pruning ensures that the parallelism always remains within a closed interval from 1 to the maximum number of channels.

[0069] This embodiment ensures that the adjustment logic will not generate invalid parallelism values ​​under any circumstances through boundary checks, enhancing the system's robustness. The minimum parallelism setting of 1 ensures that at least one battery management system can complete the flashing process even in cases of extreme bus congestion. The limitation on the maximum number of channels respects the actual capabilities of the physical layer and protocol stack, avoiding unpredictable behavior caused by exceeding the hardware-supported parallelism. Boundary pruning and progressive adjustment rules work together to ensure that the adjustment behavior always occurs within an effective range.

[0070] The following are embodiments of the apparatus of the present invention, which can be used to execute the BMS batch flashing method involved in the present invention. For details not disclosed in the embodiments of the apparatus of the present invention, please refer to the method embodiments of the BMS batch flashing method involved in the present invention.

[0071] Please see Figure 8 This invention provides a BMS batch flashing device 50, including but not limited to: a parameter calculation module 510, a pending adjustment module 520, a stability verification module 530, and a batch flashing module 540, wherein: The parameter calculation module 510 is used to monitor the real-time parameters of the communication load during the current batch flashing process and calculate the real-time bus occupancy rate based on the real-time parameters. The pending adjustment module 520 is used to make a preliminary adjustment to the current parallelism in the current batch writing process based on the real-time bus occupancy rate and the preset parallelism adjustment rules, with a step size of 1, to obtain the pending parallelism. The stability verification module 530 is used to verify the stability of the parallelism to be determined and obtain the stability verification result; the stability verification result is used to indicate the stable state of the adjusted parallelism to be determined. The batch writing module 540 is used to trigger the parameter calculation module 510 and the pending adjustment module 520 to repeat execution until the optimal parallelism is obtained based on the stability verification result indicating that the pending parallelism is stable, and to perform batch writing according to the optimal parallelism; the optimal parallelism is the maximum parallelism in the stable state.

[0072] In a preferred embodiment, the BMS batch writing device 50 further includes: The rollback processing module is used to reduce the undetermined parallelism by a step size of 1 until the optimal parallelism is obtained, based on the stability verification result indicating that the adjusted undetermined parallelism is unstable or pseudo-stable.

[0073] It should be noted that the BMS batch writing device provided in the above embodiments is only illustrated by the division of the above functional modules when performing batch writing. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the BMS batch writing device will be divided into different functional modules to complete all or part of the functions described above.

[0074] Furthermore, the BMS batch flashing device and BMS batch flashing method embodiments provided above belong to the same concept, and the specific way each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0075] Please see Figure 9 This invention provides an electronic device 4000, which includes at least one processor 4001 and at least one memory 4003.

[0076] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0077] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0078] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0079] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0080] The memory 4003 stores program instructions or code, and the processor 4001 can read the program instructions or code stored in the memory 4003 through the communication bus 4002.

[0081] When the program instructions or code are executed by the processor 4001, the BMS batch flashing method in the above embodiments is implemented.

[0082] Furthermore, this embodiment of the invention provides a storage medium storing program instructions or code, which is loaded and executed by a processor to implement the BMS batch flashing method described above.

[0083] This invention provides a computer program product, which includes program instructions or code. The program instructions or code are stored in a storage medium. The processor of an electronic device reads the program instructions or code from the storage medium, loads and executes the program instructions or code, so that the electronic device implements the BMS batch flashing method as described above.

[0084] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A method for batch flashing a BMS, characterized in that, include: S1. Monitor the real-time parameters of the communication load during the current batch flashing process, and calculate the real-time bus occupancy rate based on the real-time parameters; S2. Based on the real-time bus occupancy rate meeting the preset parallelism adjustment rules, the current parallelism in the current batch writing process is initially adjusted in a step size of 1 to obtain the undetermined parallelism. S3. Perform stability verification on the undetermined parallelism and obtain the stability verification result; The stability verification result is used to indicate the stable state of the adjusted undetermined parallelism. S4. Based on the stability verification result indicating that the undetermined parallelism is stable, repeat S1 and S2 until the optimal parallelism is obtained, and perform batch writing according to the optimal parallelism; the optimal parallelism is the maximum parallelism in a stable state.

2. The BMS batch flashing method according to claim 1, characterized in that, S1 includes: Get the number of data packets per unit time and the maximum bus capacity during the current batch flashing process; The real-time bus occupancy rate is obtained by calculating the ratio of the number of data packets per unit time to the maximum bus capacity.

3. The BMS batch flashing method according to claim 1, characterized in that, S2 includes: Based on the fact that the real-time bus occupancy rate is within the first threshold range, the current parallelism in the current batch writing process is incremented by 1 to obtain the undetermined parallelism. Based on the fact that the real-time bus occupancy rate is within the second threshold range, the current parallelism in the current batch writing process is kept unchanged to obtain the undetermined parallelism. Based on the fact that the real-time bus occupancy rate is within the third threshold range, the current parallelism in the current batch writing process is reduced by 1 to obtain the undetermined parallelism.

4. The BMS batch flashing method according to claim 1, characterized in that, S3 includes: The writing process continues according to the undetermined parallelism, and the bus occupancy rate and writing success rate are continuously monitored after several writing processes according to the undetermined parallelism. During the aforementioned monitoring processes, if the average bus occupancy rate is within a preset threshold range and the write success rate is not less than the preset write threshold, then the stability verification result indicates that the adjusted undetermined parallelism is stable. During the aforementioned monitoring processes, if the average bus occupancy rate is not within the preset threshold range, or the write success rate is less than the preset write threshold, the stability verification result indicates that the adjusted pending parallelism is unstable.

5. The BMS batch flashing method according to claim 4, characterized in that, S3 further includes: Record the number of stable iterations after repeated adjustments of the undetermined parallelism. If the number of stable iterations is not less than the preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be truly stable. If the number of stable iterations is less than a preset stability threshold, the stability verification result of the undetermined parallelism after repeated adjustments is determined to be falsely stable.

6. A BMS batch flashing method according to claim 4 or 5, characterized in that, Based on the stability verification results indicating that the adjusted undetermined parallelism is unstable or pseudo-stable, the undetermined parallelism is reduced in steps of 1 until the optimal parallelism is obtained.

7. The BMS batch flashing method according to claim 1, characterized in that, S2 further includes: Get the minimum parallelism and maximum number of channels in the current batch write process; If the undetermined parallelism is greater than the maximum number of channels, then the maximum number of channels is used as the undetermined parallelism. If the undetermined parallelism is less than the minimum parallelism, then the minimum parallelism is taken as the undetermined parallelism.

8. A batch writing device for a BMS, characterized in that, The device includes: The parameter calculation module is used to monitor the real-time parameters of the communication load during the current batch flashing process and calculate the real-time bus occupancy rate based on the real-time parameters. The pending adjustment module is used to make a preliminary adjustment to the current parallelism in the current batch writing process based on the real-time bus occupancy rate meeting the preset parallelism adjustment rules, with a step size of 1, to obtain the pending parallelism. A stability verification module is used to verify the stability of the undetermined parallelism and obtain a stability verification result; the stability verification result is used to indicate the stable state of the adjusted undetermined parallelism. The batch write module is used to trigger the parameter calculation module and the pending adjustment module to repeat execution until the optimal parallelism is obtained based on the stability verification result indicating that the pending parallelism is stable, and to perform batch write according to the optimal parallelism; the optimal parallelism is the maximum parallelism in the stable state.

9. An electronic device, characterized in that, include: At least one processor and at least one memory, wherein program instructions or code are stored in the memory; the program instructions or code are loaded and executed by the processor, causing the electronic device to implement the BMS batch flashing method as described in any one of claims 1 to 7.

10. A storage medium storing program instructions or code thereon, characterized in that, The program instructions or code are loaded and executed by the processor to implement the BMS batch flashing method as described in any one of claims 1 to 7.

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