Test control method, device and tester

Abstract

The application relates to a test control method and device and a test machine. When a first logic processing module executes a target micro-instruction in a test vector file, a command block corresponding to the target micro-instruction is determined. The command block is configured in the test vector file, and operation configuration information of at least one measured pin is defined in each row of the command block. In the memory of each board card, the operation configuration information of the corresponding measured pin in the command block is stored. The type of a target board card corresponding to the measured pin in each current row of the command block is determined. Through a target drive corresponding to the target board card type, a target storage address of the operation configuration information of the measured pin in the current row in a target board card of the target board card type is obtained, and the target storage address is sent to a second logic processing module in the target board card, so that the second logic processing module obtains the corresponding operation configuration information from the memory of the target board card, and executes corresponding business operations based on the obtained operation configuration information. The method can improve test efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a test control method, apparatus and test machine. Background Technology

[0002] During the process of running the test vector file (Run Pattern), it is necessary to assign the corresponding business operation to the board corresponding to the pin under test (e.g., business operation such as measuring or modifying the output voltage).

[0003] Traditionally, API calls are used to assign the corresponding board to perform the service operation for a given pin. That is, whenever a service operation needs to be performed on a pin under test, the API corresponding to the board type of that pin needs to be called once to write the data required for the service operation into the corresponding board's memory, and then the written data is read from memory to execute the service operation. This method is inefficient. Summary of the Invention

[0004] Therefore, it is necessary to provide a test control method, device, test machine, computer-readable storage medium, and computer program product to address the above-mentioned technical problems.

[0005] Firstly, this application provides a test control method, which includes:

[0006] When the first logic processing module executes the target microinstruction in the test vector file, it determines the command block to which the target microinstruction is targeted. The command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block. At least one pin under test belongs to at least one board type, and each line of pins under test corresponds to at least one board. The operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board. The target board type corresponding to the pin under test in each current line of the command block is determined. The target storage address of the operation configuration information of the pin under test in the current line in the target board type is obtained through the target driver corresponding to the target board type. The target storage address is sent to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board and to perform the corresponding business operation based on the obtained operation configuration information.

[0007] In one embodiment, the method further includes: generating a current row-level identifier based on a first identifier of the test vector file, a second identifier of the command block, and the row number of the current row. Using the target driver corresponding to the target board type, the method obtains the target storage address of the operation configuration information of the tested pin in the current row within the target board of the target board type, and sends the target storage address to the second logic processing module in the target board. This includes: using the target driver corresponding to the target board type, obtaining the target storage location corresponding to the current row-level identifier based on a pre-recorded correspondence between row-level identifiers and storage locations; the target storage location includes a target board identifier and a target storage address, where the target board identifier is a unique identifier for a target board belonging to the target board type; and sending the target storage address to the second logic processing module in the target board based on the target board identifier.

[0008] In one embodiment, before determining the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file, the method further includes: parsing the loaded test vector file during the data loading phase to obtain the second identifier of the command block, each line number in the command block, the pin identifier of the pin under test defined in each line of the command block, and the operation configuration information corresponding to each pin identifier; obtaining the board type and board information corresponding to each pin identifier from the project configuration file; generating a first-level mapping relationship corresponding to each board type for each board type; wherein, in the first-level mapping relationship, the first-level information includes a line-level identifier composed of the first identifier, the second identifier, and each line number, and the second-level information includes the first line information, which includes the operation configuration information and board information corresponding to the pin identifier belonging to the board type in each line; and storing the operation configuration information corresponding to each pin identifier in each line of the first line information into the memory of the board represented by the corresponding board information through the driver corresponding to the board type, and recording the correspondence between the line-level identifier and the storage location of the operation configuration information.

[0009] In one embodiment, for each board type, a first-level mapping relationship corresponding to the board type is generated, including: generating a second-level mapping relationship; wherein, in the second-level mapping relationship, the first-level information includes a block-level identifier composed of the second identifier and the first identifier of each command block in the test vector file, the second-level information includes each line number in each command block, and the third-level information includes second-line information; the second-line information includes the operation configuration information, board type, and board information corresponding to the pin identifiers in each line of the command block; and a first-level mapping relationship corresponding to each board type is generated based on the second-level mapping relationship.

[0010] In one embodiment, determining the command block targeted by the target microinstruction includes: obtaining a second identifier of the command block returned by the first logic processing module; determining the target board type corresponding to the pin being tested in each current line of the command block includes: generating a target block-level identifier based on the first identifier and the second identifier; searching for the current line number corresponding to the target block-level identifier from a pre-stored second-level mapping relationship, and determining the target board type corresponding to the pin identifier in the current line based on the current line number.

[0011] In one embodiment, the first-level mapping relationship corresponding to each board type is generated by the digital board driver; through the driver corresponding to the board type, the operation configuration information corresponding to each pin identifier in each row of the first row of information is stored in the memory of the board represented by the corresponding board information, including: for the power board type, the digital board driver sends the first-level mapping relationship corresponding to the power board type to the power board driver, so as to instruct the power board driver to store the operation configuration information corresponding to each pin identifier in each row of the sent first-level mapping relationship in the memory of the board represented by the corresponding board information.

[0012] In one embodiment, the current row-level identifier is generated by the digital board driver; when the target board type is a power board type, the target driver is the power board driver; the target driver corresponding to the target board type obtains the target storage location corresponding to the current row-level identifier based on the pre-recorded correspondence between the row-level identifier and the storage location, including: sending the current row-level identifier to the power board driver through the digital board driver, so that the power board driver obtains the target storage location corresponding to the current row-level identifier based on the pre-recorded correspondence.

[0013] In one embodiment, the board information corresponding to each pin identifier in the first row of information includes the board identifier corresponding to the pin identifier and the channel identifier corresponding to the board represented by the board identifier; the method further includes: determining the target channel identifier corresponding to the pin being tested in the current row on the target board based on the first row of information in the first-level mapping relationship corresponding to the target board type through the target driver; sending a target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and performing corresponding business operations based on the obtained operation configuration information, including: sending a target channel identifier and a target storage address to the second logic processing module to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and setting the obtained operation configuration information to each target channel represented by the target channel identifier to perform corresponding business operations.

[0014] Secondly, this application also provides a test control device, which includes:

[0015] The command block determination module is used to determine the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file. The command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block. At least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board. The operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board.

[0016] The board type determination module is used to determine the target board type corresponding to the pin being tested in each current line of the command block;

[0017] The control module is used to obtain the target storage address of the operation configuration information of the pin under test in the current row in the target board of the target board type through the target driver corresponding to the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and execute the corresponding business operation based on the obtained operation configuration information.

[0018] Thirdly, this application also provides a test machine, which includes a driver module and a first resource board; the first resource board includes a first logic processing module;

[0019] The driver module is used to determine the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file. The command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block. At least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board. The operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board.

[0020] The driver module is also used to determine the target board type corresponding to the pin being tested in each current line of the command block; the target board type may be the same as or different from the board type of the first resource board;

[0021] The driver module is also used to obtain the target storage address of the operation configuration information of the pin under test in the current row in the target board of the target board type through the target driver corresponding to the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and perform the corresponding business operation based on the obtained operation configuration information.

[0022] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0023] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0024] In the aforementioned test control method, apparatus, test machine, computer-readable storage medium, and computer program product, the test vector file (i.e., the pattern file) has been optimized and improved. Specifically, a command block is configured in the pattern file, which defines the operation configuration information (i.e., the configuration information of the service operation) of at least one pin under test line by line. Essentially, the command block can instruct which service operations need to be performed on the pin under test, and each line of pins under test corresponds to at least one board. Before running the pattern, the operation configuration information of each pin under test defined in the command block is pre-stored in the memory of the corresponding board. Furthermore, a target microinstruction corresponding to the command block is configured in the pattern file, which is used to trigger the execution of the service operation indicated by the command block. During the execution of the Run Pattern by the first logic processing module (e.g., FPGA) in the first resource board, if the first logic processing module executes the target microinstruction in the Pattern file, it can determine the command block targeted by the target microinstruction, and then determine the target board type corresponding to the pin under test in each current line of the command block. Through the target driver corresponding to the target board type, it obtains the target storage address of the operation configuration information of the pin under test in the current line within the target board of the target board type. Since the operation configuration information of each pin under test has already been pre-stored in the memory of the corresponding board, it is not necessary to call the API to load it into memory. Instead, the target storage address of the operation configuration information of the pin under test in the current line within the corresponding target board is directly obtained on a "line" basis or at a specific granularity. In this case, there can be multiple target boards. Then, the target storage address is sent to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board and execute the corresponding business operation based on the obtained operation configuration information. In this way, without calling the API, business operations can be executed concurrently and synchronously across multiple boards in "rows" or at a specific granularity, greatly improving testing efficiency. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating the test control method in one embodiment;

[0026] Figure 2 This is a simplified flowchart of the data loading stage in one embodiment;

[0027] Figure 3 This is a schematic diagram illustrating the storage principle of operation configuration information in one embodiment;

[0028] Figure 4 This is a simplified diagram of the test vector file in one embodiment;

[0029] Figure 5 This is a simplified flowchart of the test vector execution phase in one embodiment;

[0030] Figure 6 Here is a system architecture diagram of the test machine in one embodiment;

[0031] Figure 7 This is a structural block diagram of the test control device in one embodiment;

[0032] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing specific examples and are not intended to limit the scope of protection of this application.

[0034] like Figure 1 As shown, in some embodiments, a test control method is provided, which is executed by a test machine (e.g., a driver module in the test machine), and specifically includes the following steps:

[0035] S11, when the first logic processing module executes the target microinstruction in the test vector file, the command block targeted by the target microinstruction is determined; the command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block; at least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board; the operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board.

[0036] It should be understood that the test machine includes resource boards and driver modules of at least one board type. For example, digital board types, power board types, etc., belong to different board types. Each board type has at least one board; for example, the test machine may include at least one digital board and / or at least one power board. The driver module includes the driver corresponding to each board type; for example, the driver corresponding to the digital board type is denoted as the digital board driver, and the driver corresponding to the power board type is denoted as the power board driver.

[0037] The first logic processing module is the logic processing module of the first resource board. For example, if the first resource board is a digital board, the first logic processing module is the FPGA within the digital board.

[0038] In this embodiment, the test vector file (pattern file) is a traditional test vector file with at least one command block added. Each command block defines the operation configuration information of at least one pin under test (Pin) line by line. The operation configuration information refers to the configuration information related to the service operation corresponding to the pin under test, which is used to indicate the service operation to be performed for the pin under test, such as measurement operation or voltage modification operation.

[0039] In the Pattern file, command block IDs start from 0 and increment sequentially according to the number of command blocks defined in the Pattern file. For example, if there is only one command block, denoted as block1, then the command block ID corresponding to block1 is 0. If there are multiple command blocks, the command block ID corresponding to the first command block, block1, is 0, and the IDs of each non-first command block are the command block ID of the preceding adjacent command block + 1; for example, the command block ID corresponding to the second command block, block1, is 1, and the command block ID corresponding to the third command block, block3, is 2.

[0040] For example, command blocks can be identified in the pattern file by preset character fields. For instance, the content between BURST BLOCK BEGIN and BURST BLOCK END in the pattern file is the operation configuration information defined for the pin under test within the command block (e.g., defining voltage modification or measurement operations for the pin under test in the command block).

[0041] To facilitate understanding, the command block is illustrated with an example:

[0042] "BURST BLOCK BEGIN (block 1)"

[0043] MEASURE PinHC000;

[0044] MEASURE Pin000;

[0045] CFG Pin000 = {VS = 0.55V};

[0046] CFG PinIO001,PinIO002 = {VIL = 1V, VIH = 3V, VOL = 1V, VOH = 2V};

[0047] BURST BLOCK END

[0048] Here, block1 represents command block 1; “MEASURE PinHC000” and “MEASURE Pin000” represent performing measurement operations on pins PinHC000 and Pin000, respectively; CFG Pin000 = {VS = 0.55V} means configuring (i.e. modifying) the voltage of pin Pin000 to 0.55V; CFG PinIO001,PinIO002 = {VIL = 1V, VIH = 3V, VOL = 1V,VOH = 2V} means configuring (i.e. modifying) the input voltages of PinIO001 and PinIO002 to VIL = 1V and VIH = 3V, and configuring their output voltages to VOL = 1V and VOH = 2V. VIL (Input Low Voltage) refers to a low-level input voltage; VIH (Input High Voltage) refers to a high-level input voltage; VOL (Output Low Voltage) refers to a low-level output voltage; and VOH (Output High Voltage) refers to a high-level output voltage.

[0049] It should be understood that each pin under test can only belong to one type of board (i.e., one board type). Each pin under test defined in the command block belongs to at least one board type; that is, the command block can define corresponding operation configuration information for pins under test under one or more board types. Each line of the command block defines a pin under test corresponding to at least one board. The operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board. In other words, the operation configuration information corresponding to each pin under test in the command block is pre-stored in the memory of the board corresponding to that pin. For example, the operation configuration information corresponding to the pin under test is pre-stored in the memory of the corresponding board during the data loading phase.

[0050] In some embodiments, such as Figure 2As shown, during the data loading phase, the project configuration file and pattern file are loaded into the digital board driver. For example, the host computer can load them into the digital board driver via FTP (File Transfer Protocol). There can be one or more pattern files; the identifier of the pattern file is denoted as the first identifier, which can be PatternName, i.e., the name of the pattern file. For each pattern file, the digital board driver can parse the loaded pattern file. In this way, the second identifier of the command block set in the pattern file, the line numbers in the command block, the pin identifiers (e.g., pin names) of the pins under test defined in each line of the command block, and the operation configuration information corresponding to each pin identifier can be obtained. It should be understood that the line numbers in each command block start from 0, and the line numbers in the same command block are incremented sequentially.

[0051] In addition, please continue to refer to Figure 2 The digital board driver can also obtain the board type corresponding to each pin identifier and the board information under that board type from the project configuration file. For example, the pin mapping module (Pin_map module) in the project configuration file sets the pin identifier (such as Pin_Name) of the pin under test and the board type (Type) of the board to which the pin under test belongs. Another configuration file or configuration module in the project configuration file records the board information under the board type to which the pin under test belongs. Therefore, the board type corresponding to each pin identifier and the board information under that board type can be obtained from the Pin_map module and the configuration module.

[0052] For example, the board information includes the channel identifier of each pin on its corresponding board, that is, the board identifier corresponding to the pin identifier and the channel identifier corresponding to the pin identifier on the board represented by each board identifier. For example, the channel identifier of a digital board can be the PE channel identifier. It should be understood that since a pin under test belongs to only one board type, the various board identifiers corresponding to a single pin identifier belong to the same board type. There is at least one board identifier corresponding to a pin identifier.

[0053] Furthermore, since the command block can define corresponding operation configuration information for the pins under test for one or more board types, the digital board driver can generate a first-level mapping relationship corresponding to each board type. The hierarchical mapping relationship is a multi-level mapping relationship that includes multiple levels of information; therefore, both the first-level mapping relationship and the second-level mapping relationship (described below) include multiple levels of information.

[0054] Specifically, in the first-level mapping relationship, the first-level information includes row-level identifiers; the row-level identifiers consist of a first identifier, a second identifier, and each row number. The second-level information includes the first row information. It should be noted that the first row information does not refer to the information of the first row, but is essentially row information (i.e., each row of information recorded in the first-level mapping relationship). In this application, in order to distinguish the row information in the first-level mapping relationship from that in the second-level mapping relationship described below, the row information in the first-level mapping relationship and the second-level mapping relationship are respectively referred to as the first row information and the second row information.

[0055] That is, the first line of information includes the operation configuration information and board information corresponding to the pin identifiers of this board type in each line. For example, the first-level mapping relationship can be: (PatternName_Block ID_Block ID Row Number (First Level) ---> {All pin identifiers of this board type in each line and their corresponding channel identifiers and operation configuration information on their respective boards} (Second Level)). In this example, PatternName_Block ID_Block ID Row Number is the row-level identifier.

[0056] For example, for a given digital board type, the digital board driver can generate a first-level mapping relationship corresponding to the digital board type. The second-level information of this first-level mapping relationship includes the PE channel identifiers of all pin identifiers (such as PinName) belonging to the digital board type in each row on the corresponding digital board, as well as the operation configuration information corresponding to all pin identifiers belonging to the digital board type in each row.

[0057] For example, for a power board type, the digital board driver can generate a first-level mapping relationship corresponding to the power board type. The second-level information of this first-level mapping relationship includes the channel identifiers on the corresponding power boards for all pin identifiers belonging to the power board type in each row, as well as the operation configuration information corresponding to all pin identifiers belonging to the power board type in each row.

[0058] In some embodiments, during the data loading phase, please refer to... Figure 2 The digital board driver can initially generate and store a second-level mapping relationship without distinguishing between board types. The second-level mapping relationship is a unified hierarchical mapping relationship that includes the operation configuration information corresponding to the tested pins of each board type and the board information.

[0059] Specifically, in the second-level mapping relationship, the first-level information includes a block-level identifier (i.e., PatternName_BlockID) composed of the second identifier (i.e., block ID) of each command block in the Pattern file and the first identifier (such as PatternName). The second-level information includes the line numbers (block ID line numbers) in each command block. The third-level information includes the second line information. The second line information includes the operation configuration information, board type, and board information corresponding to the pin identifiers (such as PinName) in each line of the command block. For example, the board information includes the board identifier corresponding to the pin identifier and the channel identifier corresponding to the board represented by the board identifier. It should be understood that the channel identifiers corresponding to each board can form a set of channel identifiers.

[0060] Please continue reading. Figure 2 The digital board driver can generate a first-level mapping relationship corresponding to each board type based on the second-level mapping relationship. That is, the second-level mapping relationship is split according to the board type to generate a first-level mapping relationship corresponding to each board type.

[0061] For example, the second-level mapping relationship is: (PatternName_Block ID (First Level) ---> Block ID Row Number (Second Level) ---> {PinName, the set of board identifiers of the board where the Pin is located and the specific channel identifiers on the board, the board type to which the Pin belongs, and operation configuration information} (Third Level)). This is then split by board type to generate the first-level mapping relationship: (PatternName_Block ID_Block ID Row Number (First Level) ---> {All pin identifiers belonging to this board type in each row, the channel identifiers on their respective boards, and the corresponding operation configuration information} (Second Level)).

[0062] Furthermore, through the driver corresponding to this board type, the operation configuration information corresponding to each pin identifier in each row of the first row of information (the second-level information contained in the first-level mapping relationship) is stored in the memory of the board represented by the corresponding board information. That is, for each pin identifier in each row of the first row of information, the operation configuration information corresponding to that pin identifier is stored in the memory of the board corresponding to that pin identifier.

[0063] For example, the operation configuration information corresponding to the pin identifier can be the operation configuration information set for the channel corresponding to the pin identifier on the board (i.e., information related to business operations). In other words, each channel corresponding to the pin identifier on the board has corresponding operation configuration information. For each command block of each pattern file, the digital board driver or power board driver can write the operation configuration information corresponding to each channel in each line of the command block to the memory of the corresponding board based on the first-level mapping relationship and based on "block ID_line number_". The memory can be DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) or RAM (Random Access Memory).

[0064] Assume we have Pattern 1 and Pattern 2. For example... Figure 3 As shown, 301 and 302 are used to illustrate the first-level mapping relationship corresponding to Pattern 1 and Pattern2, respectively.

[0065] In the first-level mapping relationship corresponding to Pattern 1, "Block ID0_Row Number 0" and "Block ID0_Row Number 1" belong to different rows within the same command block (e.g., blook1). The content of the channel corresponding to Block ID0_Row Number 0 includes the operation configuration information corresponding to PE channels 0 to N of digital board 1. Since the content corresponding to "Block ID0_Row Number 0" all belongs to the same board—digital board 1—it can be stored contiguously in the DDR of digital board 1, specifically in the contiguous address space from address 1 to address 2 of the DDR. The content of the channel corresponding to Block ID0_Row Number 1 includes the operation configuration information corresponding to the PE channels of different digital boards (i.e., digital board 1 and digital board N) under the same digital board type. Therefore, it can be split and stored separately for its respective digital board 1 or digital board N. That is, the operation configuration information corresponding to the PE channel of digital board 1 is stored starting from address 2 in the DDR of digital board 1 and ending at address M; the operation configuration information corresponding to the PE channel of digital board N is stored starting from address 1 in the DDR of digital board N and ending at address 2 in the same DDR.

[0066] "Block IDn_line number n" can represent the blook in Pattern 1 （n+1）The (n+1)th line of the (i.e., the (n+1)th command block) contains the channel content of block ID n_line number n. This includes the operation configuration information corresponding to the channels of different power boards (i.e., power board 1 and power board N) under the power board type. Therefore, it can be split and stored to the respective power board 1 and power board N. That is, the operation configuration information corresponding to the channels of power board 1 is stored in the RAM of the FPGA of power board 1; the operation configuration information corresponding to the channels of power board N is stored in the RAM of the FPGA of power board N.

[0067] The first-level mapping relationship corresponding to Pattern 2 and the corresponding storage processing principle are the same, so they will not be repeated here.

[0068] Furthermore, the correspondence between row-level identifiers (first-level information contained in the first-level mapping relationship) and the storage location of operation configuration information in memory can be recorded. For example, the storage location includes a board identifier and a storage address. The board identifier is used to characterize the board on which the operation configuration information is stored (i.e., recording which board it is stored on). The storage address in memory includes the starting address and length of the operation configuration information in memory. That is, it records which board the operation configuration information in the second-level information corresponding to PatternName_BlockID_BlockID row number is stored on and its storage address in the board's memory.

[0069] Please continue reading. Figure 2 For each digital board type, after generating the first-level mapping relationship corresponding to the digital board type, the digital board driver stores the first-level mapping relationship corresponding to the digital board type. Then, the digital board driver stores the operation configuration information corresponding to each pin identifier in each row of the first-level mapping relationship into the DDR of the corresponding digital board. The digital board driver can also record the correspondence between the row-level identifier and the corresponding operation configuration information in the DDR (such as the starting address and length in the DDR).

[0070] For each power board type, after generating the first-level mapping relationship corresponding to the power board type, the digital board driver can send the first-level mapping relationship corresponding to the power board type to the power board driver, allowing the power board driver to store the first-level mapping relationship corresponding to the power board type. Then, the power board driver stores the operation configuration information corresponding to each pin identifier in each row of the sent first-level mapping relationship into the RAM of the corresponding power board. The power board driver can also record the correspondence between row-level identifiers and the corresponding operation configuration information storage locations in RAM.

[0071] In addition to command blocks, the Pattern file also includes target microinstructions for each command block. These target microinstructions are used to trigger the execution of the business operation indicated by the corresponding command block. For example... Figure 4 As shown, command block 1 can be set at the beginning of the Pattern file, and the content of the command block is indicated by the dashed line 401. Command block 1 corresponds to the microinstruction TRIG HW_SYNC block 1. When the microinstruction TRIG HW_SYNC block 1 is executed, it is used to trigger the configuration of the input voltages of PinIO001 and PinIO002 to VIL = 0V and VIH = 2V, and the configuration of their output voltages to VOL = 1V and VOH = 4V.

[0072] Specifically, the first logic processing module in the first resource board can run a pattern file. When the first logic processing module executes any target microinstruction in the pattern file, it can determine the command block targeted by the target microinstruction and notify the driver module, thereby enabling the driver module to know the command block targeted by the target microinstruction.

[0073] S12, determine the target board type corresponding to the pin being tested in each current line of the command block.

[0074] As mentioned above, each line in the command block defines the operation configuration information of at least one pin under test. Therefore, after determining the command block to which the target microinstruction is being executed, the digital board driver can traverse each line in the command block. For each current line of the traversal, the board type corresponding to the pin under test in each current line of the command block can be determined and recorded as the target board type.

[0075] S13, by using the target driver corresponding to the target board type, obtain the target storage address of the operation configuration information of the pin under test in the current row in the target board of the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and perform the corresponding business operation based on the obtained operation configuration information.

[0076] In some embodiments, as described above, after the operation configuration information corresponding to the pin under test is pre-stored in the memory of the corresponding board, the correspondence between the row-level identifier (PatternName_Block ID_Block ID Line Number) and the storage location of the operation configuration information can be recorded. Therefore, for each current row traversed in the command block, after determining the target board type corresponding to each pin under test in the current row, the digital board driver generates the current row-level identifier (e.g., PatternName_Block ID_Block ID Line Number) based on the first identifier of the currently running Pattern file, the second identifier of the command block (i.e., the command block targeted by the target microinstruction), and the line number of the current row.

[0077] Furthermore, using the target driver corresponding to the target board type, and based on the pre-recorded correspondence between the storage locations of row-level identifiers and operation configuration information, the target storage location corresponding to the current row-level identifier is obtained. The target storage location includes the target board identifier and the target storage address; the target board identifier is a unique identifier for a target board of this target board type. Then, based on the target board identifier, the target storage address is sent to the second logical processing module in the target board. Consequently, the second logical processing module retrieves the stored operation configuration information from the target board's memory and executes the corresponding business operation based on the retrieved operation configuration information.

[0078] In some embodiments, the board information corresponding to each pin identifier in the first row of information (included in the second-level information of the first-level mapping relationship) includes the board identifier corresponding to the pin identifier and the channel identifier corresponding to the board represented by the board identifier.

[0079] In this embodiment, the target channel identifier corresponding to the pin under test in the current row is determined on the target board based on the first row of information in the first-level mapping relationship corresponding to the target board type, by target driving; the target channel identifier and target storage address are sent to the second logic processing module to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and set the obtained operation configuration information in each target channel represented by the target channel identifier to execute the corresponding business operation.

[0080] It should be noted that the second logic processing module refers to the logic processing module in the target board. The second logic processing module may be the same as or different from the first logic processing module. The first logic processing module is described in more detail below using the FPGA in the digital board as an example.

[0081] In some examples, if the target board type is a digital board type, the target driver is a digital board driver, the target board is a target digital board, and the second logic processing module is the FPGA in the target digital board (the second logic processing module is the same as the first logic processing module).

[0082] In this scenario, after generating the current row-level identifier, the digital board driver can obtain the target storage location corresponding to the current row-level identifier based on the pre-stored correspondence between the row-level identifiers and the storage locations of the operation configuration information. This target storage location includes the identifier of the target digital board and the target storage address of the operation configuration information. Furthermore, the digital board driver can send the target storage address to the FPGA in the target digital board based on the identifier of the target digital board. Further, the FPGA in the target digital board can obtain the stored operation configuration information from the DDR of the target digital board and execute corresponding service operations based on the obtained operation configuration information.

[0083] For example, the digital board driver can determine the target PE channel identifier corresponding to the tested pin in the current row on the target digital board based on the first row of information in the first-level mapping relationship corresponding to the digital board type; and send the target PE channel identifier and target memory address (including the start address and length in DDR) to the FPGA in the target digital board to instruct the FPGA in the target digital board to obtain the corresponding stored operation configuration information from the DDR of the target digital board. That is, the FPGA in the target digital board can obtain the operation configuration information written in DDR according to the start address and length in DDR. Further, the obtained operation configuration information is set in each target PE channel represented by the target PE channel identifier to execute the corresponding service operation, thereby realizing the parallel execution of service operations on multiple channels on the board.

[0084] It should be understood that since there can be multiple target boards (such as target digital boards or target power boards), it is possible to achieve parallel execution of business operations by multiple boards and multiple channels.

[0085] In some examples, if the target board type is a power board type, the target driver is a power board driver, the target board is a target power board, and the second logic processing module is the FPGA in the target power board (i.e., the second logic processing module is different from the first logic processing module).

[0086] In this scenario, after the digital board driver generates the current row-level identifier "PatternName_Block ID_Block ID Row Number", it can send this identifier to the power board driver corresponding to the power board type. The power board driver, based on the pre-stored correspondence between row-level identifiers and the storage locations of operation configuration information, obtains the target storage location corresponding to the current row-level identifier. This target storage location includes the identifier of the target power board and the target storage address of the operation configuration information. The power board driver can then send the target storage address to the FPGA in the target power board based on the identifier of the target power board. Furthermore, the FPGA in the target power board can retrieve the stored operation configuration information from RAM and execute corresponding business operations based on the retrieved operation configuration information, thereby enabling multi-channel parallel execution of business operations on the board.

[0087] For example, the power board driver can determine the target channel identifier corresponding to the pin under test in the current row on the target power board based on the first row of information in the first-level mapping relationship corresponding to the power board type; send the target channel identifier and target storage address to the FPGA in the target power board to instruct the FPGA in the target power board to obtain the corresponding operation configuration information from the memory of the target power board, and set the obtained operation configuration information to each target channel represented by the target channel identifier to perform the corresponding service operation.

[0088] The above method optimizes the test vector file (i.e., the pattern file). Command blocks are configured within the pattern file, instructing which business operations need to be performed on the pin under test. Each line defines a pin under test corresponding to at least one board. Before running the pattern, the operation configuration information for each pin under test defined in the command block is pre-stored in the memory of the corresponding board. Furthermore, target microinstructions corresponding to the command blocks are configured in the pattern file. During the execution of the Run Pattern by the first logic processing module (e.g., FPGA) on the first resource board, if the target microinstruction in the pattern file is executed, it is not necessary to call the API to load the operation configuration information of the pin under test defined in the command block into memory. Instead, it directly obtains the target storage address of the operation configuration information of the pin under test in the corresponding target board, line by line. In this case, there can be multiple target boards. Then, the target storage address is sent to the second logic processing module on the target board, instructing it to retrieve the corresponding operation configuration information from the target board's memory and perform the corresponding business operations based on the retrieved operation configuration information. In this way, without calling the API, business operations can be executed concurrently and synchronously across multiple boards in "rows" or at a specific granularity, greatly improving testing efficiency.

[0089] In some embodiments, determining the command block targeted by the target microinstruction in step S11 includes obtaining a second identifier of the command block returned by the first logic processing module. Specifically, when any target microinstruction in the Pattern file is executed, the first logic processing module can obtain the second identifier of the command block targeted by the target microinstruction and return the second identifier of the command block to the driver module.

[0090] In this embodiment, step S12 determines the target board type corresponding to the pin being tested in each current row of the command block, including: generating a target block-level identifier based on a first identifier and a second identifier; searching for the current row number corresponding to the target block-level identifier from the pre-stored second-level mapping relationship, and determining the target board type corresponding to the pin identifier in the current row based on the current row number.

[0091] Taking an FPGA whose first logic processing module is a digital board as an example, the user selects the PatternName (i.e., the first identifier) ​​of the Pattern file to be run. The test machine can call the Run Pattern interface to make the FPGA run the user-specified Pattern file. When executing the target microinstruction TRIG HW_SYNC block1, the FPGA of the digital board will return the command block ID (i.e., the second identifier of command block1) corresponding to command block1 to the digital board driver. This command block ID is 0. The digital board driver can then obtain the command block ID corresponding to command block1 returned by the FPGA.

[0092] After receiving the command block ID corresponding to the target microinstruction returned by the FPGA, the digital board driver combines the PatternName (i.e., the first identifier) ​​of the currently running Pattern file and the command block ID (i.e., the second identifier) ​​into an identifier, which is recorded as the target block-level identifier (i.e., PatternName_blockID). The digital board driver can search for the existence of this target block-level identifier from the pre-stored second-level mapping relationship "(PatternName_blockID(first level) ---> block ID line number(second level) ---> {PinName, the set of board identifier of the board where the Pin is located and the specific channel identifier on the board, the board type to which the Pin belongs, operation configuration information}(third level))".

[0093] If it exists, traverse the internal hierarchy information of the second-level mapping relationship to obtain the current line number (block ID line number) corresponding to the target block-level identifier, and determine the target board type corresponding to the pin identifier in the current line (i.e., the board type to which the pin in the current line belongs) based on the current line number. In addition, the digital board driver generates a unique current line-level identifier (i.e., PatternName_Block ID_Block ID line number) based on the PatternName, command block ID, and block ID line number in the Pattern file.

[0094] For ease of understanding, combined with Figure 5 The processing of the test vector execution phase (i.e., the Run Pattern phase) is illustrated below. For example... Figure 5 As shown, during the test vector execution phase, the host computer of the test machine can send a start command to the digital board driver. The digital board driver then sends the start command to the FPGA of the digital board, causing the FPGA to run the specified Pattern file. When the FPGA executes the target microinstruction in the Pattern file, the digital board driver obtains the command block ID returned by the FPGA (i.e., the ID of the command block targeted by the target microinstruction), and constructs PatternName_Block ID (i.e., the target block-level identifier) ​​based on PatternName and the command block ID. Then, it traverses the second-level mapping relationship to obtain the block ID line number (i.e., the current line number) corresponding to PatternName_Block ID. Furthermore, the digital board driver generates PatternName_Block ID_Block ID line number (i.e., the current line-level identifier) ​​based on PatternName, command block ID, and the block ID line number. In addition, the digital board driver determines the target board type corresponding to the pin identifier in the current line based on the block ID line number.

[0095] When the target board type is a digital board (referred to as Case 1), the digital board driver, based on a pre-stored mapping, looks up the DDR start address and length on the storage board corresponding to the PatternName_BlockID_BlockID row number. It should be understood that a storage board refers to the board that stores operation configuration information; the DDR start address and length indicate the target storage address of the operation configuration information in the storage board's DDR. Furthermore, the digital board driver can also determine the target PE channel identifier on the target digital board corresponding to the pin under test corresponding to PatternName_BlockID_BlockID row number (i.e., the current row number) based on the first-level mapping relationship.

[0096] Furthermore, the digital board driver sends the found DDR start address and length (i.e., target memory address) and target PE channel identifier to the FPGA, enabling the FPGA to obtain the corresponding memory operation configuration information from the DDR and set the obtained operation configuration information to the hardware. That is, the FPGA can set the obtained operation configuration information to each target PE channel represented by the target PE channel identifier to execute the corresponding service operation.

[0097] When the target board type is a power board (referred to as Case 2), the digital board driver sends the PatternName_BlockID_BlockID row number (i.e., the current row-level identifier) ​​to the power board driver. Based on a pre-stored mapping, the power board driver looks up the RAM start address and length on the storage board corresponding to the PatternName_BlockID_BlockID row number. The RAM start address and length indicate the target storage address of the operation configuration information in the storage board's RAM. Furthermore, the power board driver can also determine the target channel identifier on the target power board corresponding to the tested pin on the PatternName_BlockID_BlockID row number (i.e., the current row number) based on the first-level mapping.

[0098] Furthermore, the power board driver sends the found RAM start address and length (i.e. target storage address) and target channel identifier to the FPGA, enabling the FPGA to obtain the corresponding stored operation configuration information from the RAM and set the obtained operation configuration information to the hardware.

[0099] Now combined Figure 6 The system architecture diagram of the test machine shown below explains the test control method in the embodiments of this application. Figure 6 There should be no limitation on the modules included in the test machine.

[0100] like Figure 6 As shown, the test machine in this embodiment includes a host computer, a driver module, a communication board (HTI), a DIO digital board, and a DSP power board. The driver module includes a test engine, a driver service process, a digital board driver (DIO driver), and a power board driver (DPS driver). The test engine and the driver service process interact and communicate to transmit / forward information or data. The driver service process can communicate directly with the digital board driver and the power board driver.

[0101] It should be noted that in traditional methods, the digital board driver and the power board driver do not interact; both communicate with upper-level modules such as driver service processes, for example, by receiving instructions or information from these upper-level modules. In this application, an optimization is proposed that enables the digital board driver to send information to the power board driver to implement the methods in the various embodiments of this application. For example, the first-level mapping relationship corresponding to the power board type is generated by the digital board driver and sent to the power board driver; the digital board driver can also send the current row-level identifier to the power board driver, etc.

[0102] Figure 6 The DIO digital board and DPS power board are equivalent to upper-level boards, each representing a type of board, both including a BE communication module and at least one FE (Electronic Equipment). Figure 6 (Only one FE is shown for simplified illustration). In the DIO digital board, the FE is a specific digital board, including the FPGA, DDR, and peripherals. In the DPS power board, the FE is a specific power board, including the FPGA and peripherals; the FPGA includes RAM. It should be noted that... Figure 6 The illustration uses only the FPGA in the FE of the DIO digital board or the FPGA in the FE of the DPS power board as examples, but this should not be construed as limiting. In practice, other FPGAs in the DIO digital board or the DPS power board can also perform the relevant processing in the embodiments of this application, as long as the relevant processing involving each resource board is performed by its internal FPGA (i.e., the relevant processing of the DIO digital board is performed by the FPGA in the DIO digital board, and the relevant processing involving the DPS power board is performed by the FPGA in the DPS power board).

[0103] During the data loading phase, for each board type, the operation configuration information of the pins under test belonging to that board type in the command block of the Pattern file is stored line by line in the memory of the board under that board type. The correspondence between the row-level identifier and the storage location is recorded, as well as the first-level mapping relationship corresponding to that board type is recorded.

[0104] For example, the digital board driver pre-stores the operation configuration information of the tested pins belonging to the digital board type into the corresponding digital board's DDR, and records the correspondence between row-level identifiers and storage locations, as well as the first-level mapping relationship corresponding to the digital board type. In addition, the digital board driver also records the overall second-level mapping relationship.

[0105] The power board driver pre-stores the operation configuration information of the tested pins belonging to the power board type into the RAM of the corresponding power board's FGPA, and records the correspondence between row-level identifiers and storage locations, as well as the first-level mapping relationship corresponding to the power board type.

[0106] During the Run Pattern phase, the host computer sends a start / run command for the specified Pattern file to the test engine. The test engine then forwards the start / run command to the digital board driver via the driver service process. The digital board driver can then distribute this start / run command to the FPGA of the FE through the communication board and the BE communication module of the DIO digital board. The FPGA can run the Pattern file, and upon executing the target microinstruction, it returns the command block ID of the command block targeted by the target microinstruction to the digital board driver.

[0107] The digital board driver combines the above information, which is stored or recorded in advance, to determine the target board type corresponding to the pin being tested in each current row of the command block represented by the returned command block ID, and generates a current row-level identifier.

[0108] When the target board type is a digital board, the digital board driver, in conjunction with the pre-stored correspondence, locates the corresponding target storage location based on the current row-level identifier. Then, based on the FPGA in the target digital board (i.e., the target FE) indicated by this target storage location, it retrieves the corresponding operation configuration information from the target digital board's DDR. Finally, it executes the corresponding service operation based on the retrieved operation configuration information. Detailed processing is described above and will not be repeated here.

[0109] When the target board type is a power board, the digital board driver sends the current row-level identifier to the power board driver. The power board driver then looks up the corresponding target storage location based on the pre-stored correspondence, and retrieves the corresponding operation configuration information from the RAM of the FPGA in the target power board (i.e., the target FE) indicated by the target storage location. Based on the retrieved operation configuration information, the driver executes the corresponding service operation. See the previous description for detailed processing.

[0110] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. At least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the steps or stages of other steps.

[0111] Based on the same inventive concept, this application also provides a test control device for implementing the above-mentioned test control method. The solution provided by this device is similar to the solution described in the above-described method; therefore, for specific limitations in one or more test control device embodiments provided below, please refer to the limitations of the test control method described above.

[0112] like Figure 7 As shown, in one embodiment, a test control device is provided, the device comprising:

[0113] The command block determination module 702 is used to determine the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file. The command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block. At least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board. The operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board.

[0114] The board type determination module 704 is used to determine the target board type corresponding to the pin being tested in each current line of the command block;

[0115] The control module 706 is used to obtain the target storage address of the operation configuration information of the tested pin of the current row in the target board of the target board type through the target driver corresponding to the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and perform the corresponding business operation based on the obtained operation configuration information.

[0116] Each module in the aforementioned test control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0117] In one embodiment, a computer device is provided, which may be a test machine. The internal structure diagram of the computer device may be as follows: Figure 8As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external devices via a network connection. When the computer program is executed by the processor, it implements a test control method.

[0118] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0119] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the embodiments of this application.

[0120] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the embodiments of this application.

[0121] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.

[0122] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A test control method, characterized in that, The method includes: When the first logic processing module executes the target microinstruction in the test vector file, it determines the command block to which the target microinstruction is directed; the command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block; the at least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board; the operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board. Determine the target board type corresponding to the pin being tested in each current line of the command block; By using the target driver corresponding to the target board type, the target storage address of the operation configuration information of the tested pin in the current row in the target board of the target board type is obtained, and the target storage address is sent to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and to perform the corresponding business operation based on the obtained operation configuration information.

2. The method according to claim 1, characterized in that, The method further includes: A current line-level identifier is generated based on the first identifier of the test vector file, the second identifier of the command block, and the line number of the current line; The step of obtaining the target storage address of the operation configuration information of the tested pin in the current row in the target storage address of the target board of the target board type through the target driver corresponding to the target board type, and sending the target storage address to the second logic processing module in the target board includes: Using the target driver corresponding to the target board type, and based on the pre-recorded correspondence between row-level identifiers and storage locations, the target storage location corresponding to the current row-level identifier is obtained; the target storage location includes the target board identifier and the target storage address, and the target board identifier is a unique identifier of the target board belonging to the target board type; Based on the target board identifier, the target storage address is sent to the second logic processing module in the target board.

3. The method according to claim 2, characterized in that, Before determining the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file, the method further includes: During the data loading phase, the loaded test vector file is parsed to obtain the second identifier of the command block, the line numbers in the command block, the pin identifiers of the tested pins defined in each line of the command block, and the operation configuration information corresponding to each pin identifier; Obtain the board type and board information corresponding to each pin identifier from the project configuration file; For each board type, a first-level mapping relationship corresponding to the board type is generated; wherein, in the first-level mapping relationship, the first-level information includes a row-level identifier composed of the first identifier, the second identifier, and each row number, and the second-level information includes first row information, which includes the operation configuration information and the board information corresponding to the pin identifiers belonging to the board type in each row; The operation configuration information corresponding to each pin identifier in each row of the first row of information is stored in the memory of the board represented by the corresponding board information through the driver corresponding to the board type, and the correspondence between the row identifier and the storage location of the operation configuration information is recorded.

4. The method according to claim 3, characterized in that, The step of generating a first-level mapping relationship corresponding to each of the board types includes: A second-level mapping relationship is generated; wherein, in the second-level mapping relationship, the first-level information includes a block-level identifier composed of the second identifier of each command block in the test vector file and the first identifier, the second-level information includes each line number in each command block, and the third-level information includes second-line information; the second-line information includes the operation configuration information, the board type, and the board information corresponding to the pin identifiers in each line of the command block; Based on the second-level mapping relationship, a first-level mapping relationship corresponding to each of the board types is generated.

5. The method according to claim 4, characterized in that, Determining the command block targeted by the target microinstruction includes: Obtain the second identifier of the command block returned by the first logic processing module; Determining the target board type corresponding to the pin being tested in each current line of the command block includes: Based on the first identifier and the second identifier, generate a target block-level identifier; From the pre-stored second-level mapping relationship, find the current row number corresponding to the target block-level identifier, and determine the target board type corresponding to the pin identifier in the current row based on the current row number.

6. The method according to claim 3, characterized in that, The first-level mapping relationship corresponding to each of the aforementioned board types is generated by the digital board driver; The step of storing the operation configuration information corresponding to each pin identifier in each row of the first row of information into the memory of the board represented by the corresponding board information, through the driver corresponding to the board type, includes: For each power board type, the digital board driver sends the first-level mapping relationship corresponding to the power board type to the power board driver, instructing the power board driver to store the operation configuration information corresponding to each pin identifier in each row of the first-level mapping relationship into the memory of the board represented by the corresponding board information.

7. The method according to claim 3, characterized in that, The current row-level identifier is generated by the digital board driver; when the target board type is a power board type, the target driver is a power board driver. The step of obtaining the target storage location corresponding to the current row-level identifier through the target driver corresponding to the target board type, based on the pre-recorded correspondence between row-level identifiers and storage locations, includes: The digital board driver sends the current row-level identifier to the power board driver, so that the power board driver can obtain the target storage location corresponding to the current row-level identifier based on the pre-stored correspondence.

8. The method according to claim 3, characterized in that, The board information corresponding to each pin identifier in the first row of information includes the board identifier corresponding to the pin identifier and the channel identifier corresponding to the board represented by the board identifier; The method further includes: Based on the first row of information in the first-level mapping relationship corresponding to the target board type, the target channel identifier corresponding to the tested pin in the current row on the target board is determined by the target driver. The step of sending the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and to perform corresponding business operations based on the obtained operation configuration information, includes: The target channel identifier and the target storage address are sent to the second logic processing module to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and to set the obtained operation configuration information in each target channel represented by the target channel identifier to execute the corresponding business operation.

9. A test control device, characterized in that, The method includes: The command block determination module is used to determine the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file; the command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block; the at least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board; the operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board. The board type determination module is used to determine the target board type corresponding to the pin being tested in each current line of the command block; The control module is used to obtain the target storage address of the operation configuration information of the tested pin of the current row in the target board of the target board type through the target driver corresponding to the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and perform corresponding business operations based on the obtained operation configuration information.

10. A testing machine, characterized in that, The test machine includes a driver module and a first resource board; the first resource board includes a first logic processing module. The driving module is used to determine the command block targeted by the target microinstruction when the first logic processing module executes the target microinstruction in the test vector file; the command block is configured in the test vector file, and the operation configuration information of at least one pin under test is defined line by line in the command block; the at least one pin under test belongs to at least one board type, and each line of pin under test corresponds to at least one board; the operation configuration information of the corresponding pin under test in the command block is stored in the memory of each board. The driver module is further configured to determine the target board type corresponding to the pin being tested in each current line of the command block; the target board type may be the same as or different from the board type corresponding to the first resource board. The driver module is further configured to obtain the target storage address of the operation configuration information of the tested pin of the current row in the target board of the target board type through the target driver corresponding to the target board type, and send the target storage address to the second logic processing module in the target board to instruct the second logic processing module to obtain the corresponding operation configuration information from the memory of the target board, and perform corresponding business operations based on the obtained operation configuration information.

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