Corelet interrupt management circuit and multi-corelet system

Abstract

The application provides a kind of core particle interrupt management circuit and multi-core particle system, comprising: register and master module, the register is used to store the management rule of interrupt signal;The master module includes: multiple source receiving unit, for receiving the standard MSI information of multiple source core particles;Mailbox exclusive control unit, for when the target mailbox is idle state, the standard MSI information is output to the target mailbox;MSI information management unit, for decoding and checking the standard MSI information, if accurate, then based on the management rule and the standard MSI information after decoding, the gateway latch signal corresponding to the interrupt signal is output to local receiving target core particle by the interrupt gateway unit;And interrupt gateway unit;For the standard MSI information after decoding is latched to form the gateway latch signal.The core particle interrupt management circuit and multi-core particle system of the application can realize multiple sending source receiving, mailbox exclusive, automatic decoding response, error detection.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip interrupt management circuit and a multi-chip system. Background Technology

[0002] There is currently no standard, universally applicable technology in the industry for chiplet reception and cross-chiplet interrupt transmission. Traditional interrupt transmission circuits cannot solve problems such as multi-source concurrency, mailbox conflicts, and error management when receiving cross-chiplet interrupts from a local target chiplet.

[0003] Therefore, it is necessary to provide a chip interrupt management circuit and a multi-chip system to effectively solve the above problems. Summary of the Invention

[0004] This invention provides a chip interrupt management circuit and a multi-chip system.

[0005] This invention provides a chip interrupt management circuit, including: a register and a main control module, wherein the register and the main control module are connected, and the register is used to store management rules for interrupt signals; the main control module includes: A multi-source receiving unit is used to receive standard MSI information from multiple source chips, and each of the standard MSI information corresponds to one of the interrupt signals. The mailbox exclusive control unit is connected to the multi-source receiving unit and is used to obtain the status of the target mailbox and output the standard MSI information to the target mailbox when the target mailbox is in an idle state. The MSI information management unit, connected to the mailbox exclusive control unit and the interrupt gateway unit, is used to decode and verify the standard MSI information. If accurate, based on the management rules and the decoded standard MSI information, the interrupt gateway unit outputs the gateway latch signal corresponding to the interrupt signal to the local receiving target chip. The interrupt gateway unit is used to latch the decoded standard MSI information to form the gateway latch signal.

[0006] Preferably, the register further includes a read-clear type register configured for the mailbox exclusive control unit, and the mailbox exclusive control unit controls the target mailbox to receive only one standard MSI message at a time based on the information stored in the read-clear type register.

[0007] Preferably, the management rules for the interrupt signal include the interrupt number, priority, ID of the source chip, and ID and address of the local receiving target chip.

[0008] Preferably, the register includes a three-dimensional register, which is used to obtain and store the address of the local receiving target chip corresponding to the standard MSI information based on the management rules and the standard MSI information. The MSI information management unit obtains the address of the local receiving target chip from the three-dimensional register and transmits the gateway latch signal to the address of the local receiving target chip.

[0009] Preferably, the verification of the standard MSI information includes verifying whether the ECC error correction code is correct and whether the ID and address of the local receiving target chip are correct.

[0010] Preferably, the main control module further includes an automatic feedback unit, which is connected to the MSI information management unit. The automatic feedback unit is used to return a correct reception signal to the feedback reception register of the source chip at the transmitting end when the standard MSI information verification is accurate, and otherwise return an incorrect reception signal to the feedback reception register of the source chip at the transmitting end when the MSI information verification is incorrect. At the same time, the multi-source receiving unit waits to re-receive the standard MSI information.

[0011] Preferably, the local receiving target chip includes a PLIC or a CPU core.

[0012] Preferably, the number of local receiving target chips can be configured to be 1 or greater than or equal to 2 and less than or equal to 8, and each standard MSI information corresponds to at least one local receiving target chip.

[0013] Preferably, the interrupt gateway unit is further configured to receive a reset signal fed back by the local CPU core, and to perform a reset upon receiving the reset signal.

[0014] The present invention also provides a multi-core system, including a plurality of source cores, a plurality of local receiving target cores, and a core interrupt management circuit as described in any of the preceding claims, wherein each of the source cores and each of the local receiving target cores is connected to the core interrupt management circuit.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: The chip interrupt management circuit and multi-chip system provided in this invention support concurrent access of multiple source chips and reliably distribute interrupts to local receiving target chips through exclusive access via mailbox and automatic hardware decoding and verification. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the chip interrupt management circuit provided in one embodiment of the present invention; Figure 2 A schematic diagram of the chip interrupt management circuit provided in another embodiment of the present invention; Figure 3 A control timing diagram of a mailbox exclusive control unit provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of three-dimensional register coordinate transformation provided for an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0020] To address the problems existing in the prior art, this invention provides a chip interrupt management circuit and a multi-chip system.

[0021] Figure 1 This is a schematic diagram of a chip interrupt management circuit provided according to an embodiment of the present invention. Figure 1As shown, a chip interrupt management circuit includes: a register 10 and a main control module 20. Register 10 and the main control module are connected. Register 10 is used to store management rules for interrupt signals. The main control module includes: a multi-source receiving unit 21, a mailbox exclusive control unit 22, a Message Signaled Interrupts (MSI) information management unit, and an interrupt gateway unit 24. Specifically: the multi-source receiving unit 21 receives standard MSI information from multiple source chips, each standard MSI corresponding to an interrupt signal. The mailbox exclusive control unit 22 is connected to the multi-source receiving unit 21 and is used to obtain the status of the target mailbox, and output standard MSI information to the target mailbox when the target mailbox is idle. The MSI information management unit 23 is connected to the mailbox exclusive control unit 22 and the interrupt gateway unit 24, and is used to decode and verify the standard MSI information. If accurate, based on the management rules and the decoded standard MSI information, the gateway latch signal corresponding to the interrupt signal is output to the local receiving target chip via the distribution unit through the interrupt gateway unit 24. Interrupt gateway unit 24 is used to latch the decoded standard MSI information to form a gateway latch signal.

[0022] Specifically, the interrupt signal can be an external interrupt signal received by the source chip. Each source chip can have a built-in interrupt collection and packetized controller transmission unit (ICPC_Tx). The interrupt collection module collects its internal interrupts, supporting the collection of up to 1024 internal interrupt signals. These interrupt signals are then preprocessed to obtain standard MSI information. For example, when there is only one interrupt signal, it is directly packaged into an MSI transmission message, i.e., standard MSI information. The standard MSI information can be formed based on various formats well-known in the art and includes various information related to the interrupt signal, such as source chip ID, local receiving target chip ID, priority, interrupt number, etc. When the source chip collects multiple internal interrupts, the preprocessing can first use a priority comparison circuit to determine the highest priority interrupt signal, then perform a threshold comparison. If the priority exceeds a certain threshold, it can be output, and the highest priority interrupt signal is packaged into an MSI transmission message, i.e., standard MSI information. The standard MSI information can be formed based on various formats well-known in the art and includes various information related to the interrupt signal, such as source chip ID, local receiving target chip ID, interrupt number, interrupt priority, etc. In this embodiment, the number of source chips can be one or more than or equal to two and less than or equal to eight. After each source chip collects its internal interrupt, the interrupt signal is preprocessed to obtain standard MSI information. When the above conditions are met to generate standard MSI information, an interrupt request can be sent simultaneously to the chip interrupt management circuit of the local receiving target chip, and the interrupt management circuit receives the standard MSI information.

[0023] For example, the multi-source receiving unit 21 and the mailbox exclusive control unit 22 can be integrated. The multi-source receiving unit 21 described in this invention for receiving standard MSI information of multiple source chips does not mean receiving standard MSI information of multiple source chips at the same time. Rather, it means that after receiving the interrupt request of a source chip, the mailbox exclusive control unit 22 obtains the status of the target mailbox. When the target mailbox is in an idle state, the multi-source receiving unit 21 receives the interrupt request and standard MSI information sent by one source chip. However, at different times when the target mailbox is in an idle state, it can receive and process standard MSI information of different source chips respectively, that is, it can receive standard MSI information of multiple source chips.

[0024] For example, the target mailbox can be a storage space in register 10. In addition to storing the management rules for interrupt signals, this storage space can also have a storage unit used as the target mailbox storage space. In addition to storing the received MSI information, the storage space corresponding to the target mailbox can also have a space for a memory status flag.

[0025] For example, register 10 also includes a read-clear type register configured for mailbox exclusive control unit 22, which controls the target mailbox to receive only one standard MSI message at a time based on the information stored in the read-clear type register.

[0026] Specifically, such as Figure 3 As shown, the working process of the mailbox exclusive control circuit is as follows: ICPC_Tx0 and ICPC_Tx1 independently send query requests to the MSI status bit (MSI_AVAIL, MSI Available) address of the target mailbox (Target Mbx). ICPC_Tx0 and ICPC_Tx1 here are only for illustration. In actual operation, up to 8 ICPC_Tx can be supported, that is, ICPC_Tx0 to ICPC_Tx7 independently send query requests to the MSI_AVAIL address of the target mailbox.

[0027] When the MSI_AVAIL bit of the target mailbox is high, as soon as any read request is received, the MSI_AVAIL bit will toggle to low in the next clock cycle, and the value returned by the read request (APB_RD) will be high.

[0028] When the MSI_AVAIL value read by ICPC_Tx is high (ICPC_Tx0 in the diagram), it means that exclusive access to the target mailbox has been obtained, and MSI data (MSI_DATA, referring to the standard MSI information mentioned above) is written (APB_WR).

[0029] Then, ICPC_Tx sends 128 bits ([127:0]) of MSI_DATA to the target mailbox. After sending MSI_DATA, it writes 1 to the MSI data valid flag (MSI_VALID, MSI Valid) address to indicate that the MSI data transmission is complete. After the data transmission is complete, ICPC_Tx writes bit 1 to MSI_AVAIL, indicating that the current ICPC_Tx relinquishes exclusive access rights and the target mailbox can be accessed again.

[0030] When the MSI_AVAIL value read by ICPC_Tx is low (ICPC_Tx1 in the diagram), it will wait for a period of time before resending a query request to the MSI_AVAIL address. The interval can be configured via register 10. The query continues until the MSI_AVAIL value of the target mailbox is found to be high, indicating that exclusive access to the target mailbox has been obtained, and MSI data writing begins. After writing is complete, the MSI_AVAIL value will be reset to high, indicating that the target mailbox can be accessed again.

[0031] Specifically, after the target mailbox receives the standard MSI information, the MSI information management unit 23 decodes and verifies the standard MSI information. If accurate, the interrupt gateway unit 24 latches the decoded standard MSI information based on management rules and the decoded standard MSI information to form a gateway latch signal. The MSI information management unit 23 then outputs the gateway latch signal corresponding to the interrupt signal to the local receiving target chip through the interrupt gateway unit 24. For example, an error correction code (ECC) can be used for verification.

[0032] For example, the management rules for interrupt signals include the interrupt number, priority, source chip ID, and the ID and address of the local receiving target chip.

[0033] For example, verifying standard MSI information includes: verifying whether the ECC error correction code is correct, and verifying whether the ID and address of the local receiving target chip are correct. Only when both of these are correct is the verification considered correct.

[0034] For example, register 10 includes a three-dimensional register, which is used to obtain and store the address of the local receiving target chip corresponding to the standard MSI information based on management rules and standard MSI information. The MSI information management unit 23 obtains the address of the local receiving target chip from the three-dimensional register and transmits the gateway latch signal to the address of the local receiving target chip.

[0035] Specifically, such as Figure 4 As shown, the three-dimensional register coordinate transformation process is as follows: For input interrupts, corresponding register control and status reading are required. Represented by a register file, there are MSI_TX_VALID_NUM chiplets (maximum 8), each with MSI_TX_PLIC_IRQ_NUM interrupts (maximum 1024). Each interrupt bit is connected to local LOCAL_PLIC_VALID_NUM PLIC cores (maximum 8). Therefore, the interrupt coordinates received by each local PLIC can be represented as (j, k, t), where J is LOCAL_PLIC_VALID_NUM, K is MSI_TX_PLIC_IRQ_NUM, and T is MSI_TX_VALID_NUM. Thus, the position of point P in the register file is represented as: , If the control bit corresponding to the control output to the local receiving target chip (PLIC CORE) is replaced with another representation, then: , In this context, expressions (1) and (2) represent the same control bit.

[0036] Based on the above transformation of the interrupt coordinates, the address of the corresponding local receiving target chip that the gateway latch signal corresponding to the final interrupt signal needs to be transmitted can be obtained. Then, the MSI information management unit 23 transmits the gateway latch signal to the corresponding local receiving target chip based on the address of the corresponding local receiving target chip.

[0037] For example, the local receiving target chip includes a local platform-level interrupt controller (PLIC) or a central processing unit (CPU) core.

[0038] For example, the number of local receiving target chips is 1 or more than or equal to 2 and less than or equal to 8, and each standard MSI information corresponds to at least one local receiving target chip.

[0039] Specifically, such as Figure 2 As shown, the interrupt gateway unit 24 can be multiple processing units, each used to perform gateway latching on the interrupt signal after decoding the corresponding standard MSI information to obtain a gateway latch signal. The working principle of a simple interrupt latch circuit is as follows: The input interrupt (MSI decoded IRQ) is triggered to level 1 by a 2-to-1 multiplexer, then passed through a second 2-to-1 multiplexer and latched in the gateway register (MSI Gateway, which can be a storage unit in register 10). After passing through a comparator, it is ANDed with the current input interrupt, triggering a latch level that is sent to subsequent circuits. The current gateway register state can be read from register 10. The current gateway register state can also be cleared using register 10. The inputs to the interrupt latch circuit include the MSI decoded interrupt signal and the register write signal.

[0040] For example, the interrupt gateway unit 24 is also used to receive a clear signal fed back by the local target CPU core, and to reset after receiving the clear signal. Specifically, the reset process can be to configure the status storage area of ​​the interrupt gateway unit 24 in register 10. Resetting involves setting its working status flag in the status storage area to indicate whether the interrupt gateway unit 24 can receive and process the currently decoded standard MSI information.

[0041] For example, the main control module 20 also includes an automatic feedback unit 25. The automatic feedback unit 25 is connected to the MSI information management unit 23 and is used to return a correct reception signal to the feedback reception register of the transmitting source chip when the standard MSI information verification is accurate, and to return an error reception signal to the feedback reception register of the transmitting source chip when the standard MSI information verification is incorrect. At the same time, the multi-source receiving unit 21 waits to re-receive the standard MSI information.

[0042] Specifically, a storage area for the verification result can be configured in register 10, and after verification, the verification result bit can be set in this storage area to indicate whether the verification result is accurate.

[0043] This invention also provides a multi-chip system, including multiple source chips, multiple local receiving target chips, and a chip interrupt management circuit as described in any of the above embodiments. Each source chip and each local receiving target chip is connected to the chip interrupt management circuit. The specific working process will not be described in detail.

[0044] The chiplet interrupt management circuit and multi-chiplet system provided in this application support concurrent access from up to 8 chiplets. Through exclusive mailbox access, automatic hardware decoding and verification, and three-dimensional register routing, interrupts are reliably distributed to multiple CPU cores, making it suitable for high-performance computing, autonomous driving, and other multi-core, multi-chiplet high-reliability systems. Specifically, it supports 8 senders and 1 receiver, meeting the needs of large-scale multi-chiplet heterogeneous systems; the exclusive mailbox mechanism completely resolves concurrency conflicts; three-dimensional coordinate routing accurately distributes interrupts to any CPU core; fully automated hardware processing ensures zero CPU involvement; and multi-dimensional error detection significantly improves system stability.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip interrupt management circuit, characterized in that, include: A register and a main control module, wherein the register and the main control module are connected, and the register is used to store the management rules for interrupt signals; the main control module includes: A multi-source receiving unit is used to receive standard MSI information from multiple source chips, and each of the standard MSI information corresponds to one of the interrupt signals. The mailbox exclusive control unit is connected to the multi-source receiving unit and is used to obtain the status of the target mailbox and output the standard MSI information to the target mailbox when the target mailbox is in an idle state. The MSI information management unit, connected to the mailbox exclusive control unit and the interrupt gateway unit, is used to decode and verify the standard MSI information. If accurate, based on the management rules and the decoded standard MSI information, the interrupt gateway unit outputs the gateway latch signal corresponding to the interrupt signal to the local receiving target chip. The interrupt gateway unit is used to latch the decoded standard MSI information to form the gateway latch signal.

2. The chip interrupt management circuit according to claim 1, characterized in that, The register also includes a read-clear type register configured for the mailbox exclusive control unit, and the mailbox exclusive control unit controls the target mailbox to receive only one standard MSI message at a time based on the information stored in the read-clear type register.

3. The chip interrupt management circuit according to claim 1, characterized in that, The management rules for the interrupt signal include the interrupt number, priority, ID of the source chip, and ID and address of the local receiving target chip.

4. The chip interrupt management circuit according to claim 3, characterized in that, The register includes a three-dimensional register, which is used to obtain and store the address of the local receiving target chip corresponding to the standard MSI information based on the management rules and the standard MSI information. The MSI information management unit obtains the address of the local receiving target chip from the three-dimensional register and transmits the gateway latch signal to the address of the local receiving target chip.

5. The chip interrupt management circuit according to claim 4, characterized in that, The verification of the standard MSI information includes verifying whether the ECC error correction code is correct and whether the ID and address of the local receiving target chip are correct.

6. The chip interrupt management circuit according to claim 1, characterized in that, The main control module also includes an automatic feedback unit, which is connected to the MSI information management unit. The automatic feedback unit is used to return a correct reception signal to the feedback reception register of the source chip at the transmitting end when the standard MSI information verification is accurate, and otherwise return an error reception signal to the feedback reception register of the source chip at the transmitting end when the standard MSI information verification is incorrect. At the same time, the multi-source receiving unit waits to re-receive the standard MSI information.

7. The chip interrupt management circuit according to claim 1, characterized in that, The local receiving target chip includes a PLIC or a CPU core.

8. The chip interrupt management circuit according to claim 1, characterized in that, The number of local receiving target chips is 1 or greater than or equal to 2 and less than or equal to 8, and each standard MSI information corresponds to at least one local receiving target chip.

9. The chip interrupt management circuit according to claim 1, characterized in that, The interrupt gateway unit is also used to receive the reset signal fed back by the local receiving target CPU core, and to reset after receiving the reset signal.

10. A multi-core particle system, characterized in that, It includes a plurality of source chips, a plurality of local receiving target chips, and a chip interrupt management circuit as described in any one of claims 1 to 9, wherein each source chip and each local receiving target chip is connected to the chip interrupt management circuit.

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