Layout processing task distribution method, device and program product

Abstract

The application discloses a layout processing task distribution method, device and program product, and relates to the technical field of semiconductor integrated circuits. The method comprises the following steps: according to the unit hierarchical structure information of a layout, decomposing layout processing tasks according to units to obtain subtasks corresponding to each unit; determining the task series parallel execution order between the subtasks based on the layer dependency relationship in the layer logical operation to be executed by each subtask; identifying target subtasks that meet a preset parallel degree improvement strategy according to the input characteristics and / or output characteristics of each subtask; adjusting the execution order of the target subtasks in the task series parallel execution order according to the preset parallel degree improvement strategy to obtain an adjusted task series parallel execution order; and performing task distribution based on the adjusted task series parallel execution order. The application can improve the parallel degree of layout processing and thus improve the layout processing efficiency.

Description

Technical Field

[0001] This application belongs to the field of semiconductor integrated circuit technology, and in particular relates to a layout processing task distribution method, device and program product. Background Technology

[0002] In integrated circuit yield management, layout processing is the foundation of core processes such as electron beam inspection and computational lithography. Due to the large amount of data and the complexity of the processing flow, layout processing has extremely high requirements for processing efficiency.

[0003] To improve layout processing speed, most systems currently adopt a distributed task processing architecture, which decomposes the complete layout processing task into multiple subtasks, analyzes the dependencies between subtasks, determines the parallel execution order of the task strings between subtasks, and distributes the parallel subtasks to different processing nodes for synchronous processing.

[0004] However, existing technologies still suffer from insufficient parallelism in terms of processing efficiency. Summary of the Invention

[0005] This application provides a layout processing task distribution method, device, and program product, which can improve the parallelism of layout processing and thus improve layout processing efficiency.

[0006] A first aspect of this application provides a layout processing task distribution method, including: Based on the unit hierarchical structure information of the layout, the layout processing task is decomposed into units to obtain the sub-tasks corresponding to each unit; Based on the layer dependencies in the layer logical operations to be executed in each of the subtasks, the parallel execution order of the task strings among the subtasks is determined. Based on the input and / or output characteristics of each subtask, identify the target subtask that conforms to the preset parallelism enhancement strategy; In the parallel execution order of the task string, the execution order of the target subtasks is adjusted according to the preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task string; Tasks are distributed based on the adjusted parallel execution order of the task strings.

[0007] A second aspect of this application provides a layout processing task distribution apparatus, comprising: The decomposition device is used to decompose the layout processing task into units according to the unit hierarchical structure information of the layout, so as to obtain the sub-task corresponding to each unit. A determining device is used to determine the parallel execution order of task strings among the subtasks based on the layer dependency relationship in the layer logical operation to be executed by each subtask; The identification device is used to identify target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask. An adjustment device is used to adjust the execution order of the target subtasks in the parallel execution order of the task string according to the preset parallelism enhancement strategy, so as to obtain the adjusted parallel execution order of the task string. A distribution device is used to distribute tasks based on the adjusted parallel execution order of the task strings.

[0008] A third aspect of this application provides an electronic device, including: a processor and a memory storing computer program instructions, wherein the processor executes the computer program instructions stored in the memory to implement the layout processing task distribution method provided in the first aspect of this application as described above.

[0009] A fourth aspect of the embodiments of this application provides a computer-readable storage medium on which a program or instructions are stored. When the program or instructions are executed by a processor, they implement the layout processing task distribution method provided in the first aspect of the embodiments of this application described above.

[0010] A fifth aspect of the embodiments of this application provides a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform the layout processing task distribution method provided in the first aspect of the embodiments of this application described above.

[0011] The layout processing task distribution method, device, and program product provided in this application decompose the layout processing task into units according to the unit hierarchical structure information of the layout, obtaining subtasks corresponding to each unit, so that subtasks correspond one-to-one with units; based on the layer dependency relationship in the layer logical operation to be executed by each subtask, the parallel execution order of the task strings between each subtask is determined, which can accurately determine the execution order between each subtask; based on the input and output characteristics of each subtask, target subtasks that meet the preset parallelism enhancement strategy are identified, and the execution order of the target subtasks in the parallel execution order of the task strings is adjusted according to the preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task strings. Based on the adjusted parallel execution order of the task strings, the parallelism of tasks can be improved, the idle waiting between tasks can be reduced, thereby reducing the processing time of layout processing tasks and improving processing efficiency and resource utilization. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic flowchart of a layout processing task distribution method provided in one embodiment of this application; Figure 2 This is a schematic diagram of a unit hierarchy structure provided in one embodiment of this application; Figure 3 This is a schematic diagram illustrating the parallel execution order of a task string provided in one embodiment of this application; Figure 4 This is a schematic diagram of the adjusted parallel execution order of task strings provided in one embodiment of this application; Figure 5 This is a schematic diagram illustrating the parallel execution order of task strings provided in another embodiment of this application; Figure 6 This is a schematic diagram of the adjusted parallel execution order of task strings provided in another embodiment of this application; Figure 7 This is a schematic diagram illustrating the parallel execution order of a task string provided in another embodiment of this application; Figure 8 This is a schematic diagram of the adjusted parallel execution order of task strings provided in another embodiment of this application; Figure 9 This is a schematic diagram of the adjusted parallel execution order of task strings provided in another embodiment of this application; Figure 10 This is a schematic diagram of the structure of a layout processing task distribution device provided in one embodiment of this application; Figure 11 This is a schematic diagram of an electronic device provided in one embodiment of this application. Detailed Implementation

[0014] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0016] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0017] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0018] A layout is a collection of geometric shapes on a physical mask used in the field of semiconductor integrated circuit design to manufacture chips. The layout defines the shape, size, spatial location, and electrical connections of each device and its interconnects.

[0019] The chip layout is composed of multiple stacked layers, each corresponding to a specific process step in chip manufacturing, such as active areas, polysilicon gates, and metal interconnects. The layers record the position and shape of geometric shapes, and the layers are combined according to strict alignment relationships to form the three-dimensional structure of the chip.

[0020] In integrated circuit yield management, layout processing is the foundation of core processes such as electron beam inspection and computational lithography. Due to the large amount of data and the complexity of the processing flow, layout processing has extremely high requirements for processing efficiency.

[0021] To improve layout processing speed, most systems currently adopt a distributed task processing architecture, which decomposes the complete layout processing task into multiple subtasks, analyzes the dependencies between subtasks, determines the parallel execution order of the subtask strings, and distributes the parallel subtasks to different processing nodes for synchronous processing.

[0022] However, as the scale of map data continues to expand, the number of tasks far exceeds the resources required for computation, and the processing efficiency of existing technologies still suffers from insufficient parallelism.

[0023] In view of this, this application provides a method, apparatus and program product for distributing map processing tasks.

[0024] The layout processing task distribution method provided in the embodiments of this application is described below. In practical applications, the execution entity of the layout processing task distribution method in the embodiments of this application can be an electronic device.

[0025] The following describes specific embodiments of the layout processing task distribution method, device, and program product provided in this application. First, the layout processing task distribution method will be introduced.

[0026] Figure 1 This is a flowchart illustrating a layout processing task distribution method provided in one embodiment of this application. Figure 1 As shown, the method includes: Step 101: Based on the unit hierarchical structure information of the layout, decompose the layout processing task into units to obtain the sub-tasks corresponding to each unit. Step 102: Based on the layer dependencies in the layer logical operations to be executed in each subtask, determine the parallel execution order of the task strings between each subtask; Step 103: Identify the target subtasks that conform to the preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask. Step 104: Adjust the execution order of the target subtasks in the parallel execution order of the task string according to the preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task string. Step 105: Distribute tasks based on the adjusted parallel execution order of the task strings.

[0027] The layout typically employs a hierarchical design, with top-level cells containing multiple bottom-level cells, and bottom-level cells containing even lower-level cells or basic graphics. A cell is a reusable functional module, such as a standard logic gate, a memory block, an analog macrocell, or any submodule with well-defined boundaries and internal graphics. Each cell can contain multiple layers of graphics. Cells are connected via pins and interconnects drawn on metal layers or other interconnect layers.

[0028] Cell hierarchy information refers to the containment relationships between cells in a layout and the position of each cell in the layout's hierarchy tree. Cell hierarchy information can be obtained from the layout's hierarchy description.

[0029] Figure 2 This is a schematic diagram of a unit hierarchy structure provided in one embodiment of this application, as shown below. Figure 2As shown, the layout includes a top-level TOP cell 20. TOP cell 20 includes CELL A cell 21, CELL B cell 22, and CELL C cell 23. CELL A cell 21 includes CELL D cell 24. CELL D cell 24 includes CELL F cell 27. CELL B cell 22 includes CELL E cell 25 and another CELL A cell 26. CELL A cell 21 and CELL A cell 26 can be the same functional module. Figure 2 It clearly reflects the hierarchical structure between units in the integrated circuit layout and the reuse of the same unit.

[0030] In step 101, the entire layout processing task can be divided into multiple subtasks, with each subtask responsible for performing the operations specified by the layout processing task on a single cell. For example, a subtask could be calculating the area of ​​a layer within a cell, checking design rules within a cell, or determining the connection relationship between two layers within a cell.

[0031] For example, the layout processing task is to calculate the total area of ​​a certain metal layer in the layout. The layout includes a top-level cell A and a top-level cell B. The top-level cell A contains two bottom-level cells A1 and A2. Then, step 101, based on the hierarchical relationship between the top-level cell A, bottom-level cell A1, bottom-level cell A2, and top-level cell B, breaks down the task of calculating the total area S of the metal layer into: calculating the area S of the metal layer in A. A Calculate the area S of the metal layer in B. B Based on the area S of the metal layer in A A and the area S in B B Calculate the total area S of the metal layer. Specifically, calculate the area S of the metal layer within region A. A Separated: Calculate the area S of the metal layer in A1 A1 Calculate the area S of the metal layer in A2. A2 Based on the area S of the metal layer in A1 A1 and the area S in A2 A2 Calculate the area S of the metal layer in A. A .

[0032] In step 102, layer logic operations refer to specific operations performed on one or more graphic layers in the layout. Layer logic operations may include: calculating the total area or perimeter of graphics in a layer, checking the minimum spacing between graphics within the same layer, determining whether graphics in two different layers overlap or touch, performing Boolean operations on two layers to generate a new layer, and verifying whether a graphic in one layer falls within the graphic area of ​​another layer, etc. Each subtask performs one or more layer logic operations on the graphics within its corresponding unit.

[0033] Layer dependencies can be categorized into two types. The first type is the physical geometric relationship between layers determined by the semiconductor manufacturing process. The second type is the data transfer relationship between the results of subtask operations, where the output data of one subtask is used as input data by another subtask.

[0034] The first type of relationship can include sequential relationships, where a layer must be created after another layer. For example, the second metal layer must be created after the first metal layer.

[0035] The second type of relationship can be determined based on the hierarchical relationship between the units corresponding to the subtasks, or it can be determined when decomposing the layout processing task according to the unit hierarchy. For example, for parent and child units with an inclusion relationship, when calculating attributes that require summary results, the subtasks corresponding to the child units usually need to be executed before the subtasks corresponding to the parent units, because the calculation of the parent unit depends on the results of the child units.

[0036] The parallel execution order of a task string can be represented by the priority of task execution. Tasks with different priorities need to be processed sequentially from highest to lowest priority, while tasks with the same priority can be processed in parallel. The parallel execution order of a task string can reflect the order in which each subtask is executed and which subtasks can run simultaneously. Sequential execution means that one subtask can only begin after another subtask has been completed; parallel execution means that two or more subtasks can be executed simultaneously without waiting for each other.

[0037] When a layout processing task is broken down into multiple subtasks, each subtask performs specific layer logic operations on the graphics within its corresponding unit. These operations might include checking if a layer conforms to the expected hierarchical order, verifying alignment requirements between two layers, or determining if two layers violate mutual exclusion. These layer logic operations operate on different layers within the same physical unit. Because layer dependencies dictate the order of these layers in the manufacturing process or spatial constraints, these operations must be performed in the order determined by these dependencies; otherwise, invalid checks or incorrect judgments may occur. Based on this principle, the parallel execution order of the task strings between subtasks can be determined according to the layer dependencies involved in the layer logic operations to be performed by each subtask.

[0038] In one implementation of step 102, for any two subtasks, the layer dependency relationship between the layers involved in the subtasks is determined, and the parallel execution order of the task strings between the subtasks is determined according to the type of the layer dependency relationship.

[0039] If the output data of one subtask is the input data of another subtask, that is, there is a second type of relationship between the two subtasks, then the two subtasks are also in a serial relationship, with the subtask that outputs the data coming first and the subtask that uses the data coming later.

[0040] For example, the first subtask calculates the local area of ​​the metal layer in cell A and outputs the area value S. A The second subtask is based on S. A And another area value S B Calculate the total area S of the metal layer in cells A and B. The input of the second subtask depends on the output of the first subtask; there is a data transfer relationship between them, therefore the first subtask must be executed before the second subtask.

[0041] If there is a sequential relationship between the layers processed by one subtask and the layers processed by another subtask, that is, the layer operated on by the previous subtask must be created before the layer operated on by the next subtask, then the two subtasks are in a serial relationship, with the previous subtask coming first and the next subtask coming last.

[0042] For example, if the first subtask is to define a metal layer, that is, to generate the graphic of the metal layer within this unit and determine its geometric position and shape, the second subtask is to check the alignment relationship between the metal layer and the via layer, that is, to verify whether the vias fall completely within the graphic area of ​​the metal layer. Since the metal layer is manufactured before the via layer, and the alignment check depends on the exact position of the metal graphic, the second subtask can only obtain the accurate position of the metal graphic after the first subtask is completed, thus enabling effective alignment checking. Therefore, the first subtask must be executed before the second subtask.

[0043] If the layers processed by one subtask and the layers processed by another subtask do not have a first-type relationship or a second-type relationship, then the two subtasks can be executed in parallel.

[0044] Figure 3 This is a schematic diagram illustrating the parallel execution order of a task string provided in one embodiment of this application. For example... Figure 3 As shown, the layout processing task is divided into subtasks A, B, C, D, E, F, and G. Subtasks A, B, D, G, and H are sequential; subtasks A, C, E, G, and H are sequential; and subtasks A, C, F, and H are sequential. Subtasks that are not sequential can be parallel. For example, subtasks B and C can be parallel, subtasks B and E can be parallel, and subtasks E and F can be parallel.

[0045] In step 103, input characteristics may include the data sources required for subtask execution, such as which layout data needs to be read and which subtask outputs need to be awaited. Output characteristics may include the nature of the outputs produced after the subtask is completed, such as whether the outputs will be used as inputs by other subtasks. Input and output data characteristics can be determined at the time of creation for each subtask.

[0046] In such Figure 3 In the parallel execution order of the task string shown, the input characteristics of subtask A may include the input data being the initial data in the layout, which is unrelated to the output data of other subtasks, and the output characteristics may include the output data being used as input data by subtasks B and C; the input characteristics of subtask H may include the input data being the output data of subtasks G and F, and the output characteristics may include the output data not being used as input data by other subtasks.

[0047] In one implementation, the pre-defined parallelism enhancement strategy may include at least one of the following: merging multiple subtasks with the same input data into one subtask, executing subtasks whose output results are used as input by other subtasks in advance, delaying the execution of subtasks whose output results are not used as input by other subtasks, and executing subtasks that need to summarize the results of multiple subtasks in advance.

[0048] In step 104, without violating the serial constraint, the execution order of the target subtasks in the parallel execution order of the task string can be adjusted according to a preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task string.

[0049] Preset parallelism enhancement strategies may include at least one of the following: moving the target subtask forward in the parallel execution order of the task string, moving the target subtask backward in the parallel execution order of the task string, or merging multiple target subtasks into a new subtask.

[0050] In step 105, subtasks can be dispatched to idle computing nodes for execution according to the adjusted parallel execution order of the task string.

[0051] The layout processing task distribution method provided in this application decomposes the layout processing task into subtasks corresponding to each unit according to the unit hierarchical structure information of the layout, so that the subtasks correspond one-to-one with the units. Based on the layer dependency relationship in the layer logical operation to be executed by each subtask, the parallel execution order of the task strings between each subtask is determined, which can accurately determine the execution order between each subtask. According to the input and output characteristics of each subtask, the target subtask that meets the preset parallelism enhancement strategy is identified. The execution order of the target subtask in the parallel execution order of the task strings is adjusted according to the preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task strings. Based on the adjusted parallel execution order of the task strings, the parallelism of the tasks can be improved, the idle waiting between tasks can be reduced, and thus the processing time of the layout processing tasks can be reduced, improving the processing efficiency and resource utilization.

[0052] In some embodiments, the preset parallelism enhancement strategy includes: merging multiple subtasks that are executed in parallel and have the same input data; the processing procedure of step 103 includes: Step 201: Based on the input characteristics of each subtask, identify multiple first target subtasks that are executed in parallel and have the same input data; Step 104 includes the following processing steps: Step 202: In the parallel execution sequence of the task string, multiple first target subtasks are merged into one subtask.

[0053] In this embodiment, after determining the parallel execution order of the task strings between each subtask, the subtasks to be executed in parallel can be determined from the parallel execution order of the task strings between each subtask. Then, based on the input characteristics of the subtasks to be executed in parallel, multiple subtasks with the same input data can be determined as the first target subtask.

[0054] For example, in such Figure 3 In the parallel execution order of the task string shown, subtasks E and F are subtasks that are executed in parallel and have the same input data, which is the output data of subtask C. Therefore, subtasks E and F can be identified as two first target subtasks that are executed in parallel and have the same input data.

[0055] After identifying multiple primary target subtasks, they can be merged into a new subtask during the parallel execution of the task string. For example, the input data of multiple primary target subtasks can be merged into one input data, and the output data of multiple primary target subtasks can be merged into one output data set.

[0056] Figure 4 This is a schematic diagram illustrating the adjusted parallel execution order of task strings provided in one embodiment of this application. Continuing from the previous example, in... Figure 3 In the parallel execution order of the task string shown, after identifying subtasks E and F as two first target subtasks with the same input data and to be executed in parallel, subtasks E and F can be combined into a single subtask M, resulting in the following... Figure 4 The diagram shows the adjusted parallel execution order of the task strings.

[0057] In one example, the layout processing task was split into subtasks, resulting in a total of 253,680 subtasks. After merging multiple subtasks that were executed in parallel and had the same input data, the total number of subtasks was reduced to 211,750. When using a 200-core processor to process this layout processing task, the total time could be reduced by about 15%.

[0058] In one example, the map processing task was split into 208 subtasks. After merging the tasks, the number of subtasks can be reduced to 169, which is a 19% reduction in the number of tasks. The total time can be reduced from 2339 seconds to 1637 seconds, which is a 30% reduction in the total time.

[0059] The layout processing task distribution method provided in this application identifies multiple first target subtasks that are executed in parallel and have the same input data, and merges multiple first target subtasks into one subtask in the parallel execution order of the task string. This reduces the number of subtasks in the parallel execution order of the task string, reduces I / O time, and thus improves the efficiency of layout processing.

[0060] In some embodiments, when the operation instructions of multiple first target subtasks are different, the operation instructions of the merged subtask include a set of operation instructions of multiple first target subtasks; when the operation instructions of multiple first target subtasks are the same but the operation parameters are different, the operation instructions of the merged subtask are the operation instructions of one of the multiple first target subtasks, and the operation parameters include a set of operation parameters of multiple first target subtasks.

[0061] In such Figure 3 and Figure 4 In the case shown where subtasks E and F are merged into subtask M, the input data of subtasks E and F are the same. If the operation instructions of subtasks E and F are different, then the operation instructions of the merged subtask M are a set of the operation instructions of subtasks E and F.

[0062] For example, subtask E's operation instruction is to calculate the area of ​​layer 1 in unit a, and subtask F's operation instruction is to check whether the minimum spacing of the graphics in layer 1 of unit a is less than 0.1 micrometers. The input data for subtasks E and F are both graphic data of layer 1 in unit a. Therefore, the input data for the merged subtask M is still the graphic data of layer 1 in unit a, and its operation instruction set includes area calculation and spacing check. When subtask M is executed, the instructions for area calculation and spacing check can be executed sequentially or in parallel, and the area value and spacing check result can be output respectively.

[0063] If subtasks E and F have the same operation instructions but different operation parameters, then the operation instructions of the merged subtask M are either the operation instructions of subtasks E or F, and the operation parameters are the set of operation parameters of subtasks E and F.

[0064] For example, the operation instructions for subtasks E and F are both to perform an addition operation on layer1 in unit a, with the operation parameter for subtask E being +10 and the operation parameter for subtask F being +20. Therefore, the input data for subtasks E and F is the graphic data of layer1 in unit a. After merging, the input data for subtask M is still layer1 in unit a, and the operation instruction is an addition operation, with the operation parameter set including +10 and +20. During execution, subtask M only needs to read the graphic data of layer1 in unit a once, and then perform the +10 and +20 operations on the read data respectively, outputting two different results. Compared to the previous subtasks E and F requiring two independent reads and two independent addition operations, the merged subtask M only needs one read and one addition operation to simultaneously complete the calculation of both offsets, reducing input / output operations and saving computational resources.

[0065] The layout processing task distribution method provided in this embodiment can merge different instructions into a set of operation instructions when multiple first target subtasks have different operation instructions. This can merge multiple independent input data reads into a single read, thereby reducing input / output I / O time. When multiple first target subtasks have the same operation instructions but different operation parameters, the merged subtask can merge the operation parameters into a set of parameters. This can merge multiple instruction operations into a single instruction operation, reducing I / O time and computation time, thereby improving the efficiency of layout processing.

[0066] In some embodiments, the preset parallelism enhancement strategy includes: adjusting the execution order of subtasks whose output is a non-independent graphics processing result in the direction of earlier execution; the processing procedure of step 103 includes: Step 401: Based on the output characteristics of each subtask, identify at least one second target subtask whose output is a non-independent graphics processing result. Step 104 includes the following processing steps: Step 402: Adjust the execution order of the second target subtask in the parallel execution order of the task string to the direction of earlier execution.

[0067] In integrated circuit layout, the patterns on the layout are ultimately translated into actual physical structures on the chip. A complete, continuous pattern is physically an independent entity, such as a metal line, a contact hole, or an active region. When the layout is decomposed according to a cell-level structure, the originally complete physical entity may be cut into multiple fragments, and each fragment does not exist independently in physical terms.

[0068] Non-independent graphics processing results are a consequence of the decomposition of layout processing tasks into cells. In undecomposed global processing, physically meaningful conclusions, such as the total area of ​​continuous graphics and the overall connectivity across cells, could be obtained directly. However, after decomposition into cell-level subtasks, each subtask can only see data within its own cell, limiting its local perspective. Consequently, the calculation results of a single subtask may not be independent graphics processing results and must be integrated with the results of at least one other subtask in a specific form to obtain the complete processing result.

[0069] For example, for multiple cells with graphical connections, each cell outputs a local area of ​​a segment of a continuous graphic after it has been cut. This local area is not the complete result; the local areas of all cells along the same connection line must be added together to obtain the complete area of ​​the continuous graphic. Similarly, in interaction relationship checks, the local Boolean value output by a single cell is not a complete result because the metal line segment may only lack vias locally, but the whole may be connected to vias. Only the final result after logical OR integration is the complete and accurate result.

[0070] Therefore, in this embodiment, non-independent graphics processing results refer to incomplete or inaccurate processing results that cannot directly reflect the true state of physical entities.

[0071] Accordingly, an independent pattern processing result refers to a processing result that, without requiring any integration with the results of other subtasks, can directly and completely or accurately reflect the true state of the physical entities in an integrated circuit. For example, an independent pattern processing result can be a locally valid result on an intermediate processing path, such as the area of ​​a complete pattern within a single cell, or the area of ​​a complete metal pattern integrated from multiple interconnected cells.

[0072] Execution direction adjustment refers to moving a subtask forward in the parallel execution order of a task string, so that it is executed earlier than other subtasks.

[0073] In one implementation, when the output of a subtask can correctly and completely reflect the physical entities or local rule conclusions involved in its corresponding unit without depending on the results of other subtasks, and can be directly used for the final output or downstream processing without needing to be integrated with the results of other subtasks in any form, such as arithmetic summation, logical OR, logical AND, cross-unit comparison, or graphic splicing, then the output of the subtask is an independent graphics processing result; otherwise, the output of the subtask is a non-independent graphics processing result.

[0074] For each second target subtask, its upstream subtasks can be determined first; these are the subtasks whose output data is used as input data by the second target subtask. Since the execution of a second target subtask must wait for all its upstream subtasks to complete, when moving the second target subtask forward in the parallel execution order of the task string, its new position cannot be earlier than any of its upstream subtasks. For example, the second target subtask can be moved to the first position after all its upstream subtasks have completed, that is, immediately after its last completed upstream subtask.

[0075] If the second target subtask does not have any upstream subtasks, that is, its input data comes entirely from the layout data and does not depend on the output of any other subtask, then the second target subtask is moved directly to the front of the parallel execution order of the task string.

[0076] The layout processing task distribution method provided in this embodiment adjusts the execution order of the second target subtask, which outputs non-independent graphics processing results, in the direction of earlier execution. This enables the non-independent graphics processing results to be ready earlier, reduces the waiting time of subtasks that use non-independent graphics processing results as input data, and improves the execution efficiency of layout processing tasks.

[0077] In one embodiment, the process of determining whether the output of a subtask is an independent graphics processing result or a non-independent graphics processing result may include: By analyzing the hierarchical structure information of the layout, the graphic data of each unit and the geometrical positional relationships between units are obtained. Based on the graphic data of each unit and the geometrical positional relationships between units, it is determined whether the graphic of the unit corresponding to the subtask has geometric interactions such as overlap, contact, or cross-boundary extension with the graphics of other units. If the graphic of a unit has no geometric interaction with the graphic of any other unit, then the unit is an independent unit. If the graphic of a unit has geometric interaction with the graphic of at least one other unit, then the unit is a unit with a graphic connection relationship. Depending on the type of layout processing task, it is determined whether the output of the subtask is an independent graphic processing result or a non-independent graphic processing result.

[0078] Specifically, for summable tasks such as area calculation, perimeter calculation, and graphic counting, the final result of a summable task is the sum of the results of each unit. The graphics within an independent unit are complete physical entities; the area, perimeter, or graphic count calculated by that unit is itself the actual value of the corresponding physical entity, possessing independent physical meaning, and can be directly summed. Therefore, the subtask output of an independent unit is an independent graphic processing result. For units with graphic connections, since the complete graphic is cut into multiple segments within these units, the area or perimeter calculated for each segment alone does not have complete physical meaning. The local results of all segments belonging to the same continuous graphic must be integrated, for example, by adding the areas of each segment, to restore the complete physical meaning. Therefore, the subtask output of a unit with graphic connections is a non-independent graphic processing result.

[0079] For logically aggregated tasks such as layer connectivity checks and signal connectivity checks, these tasks require determining the overall conclusion across cells, such as whether a metal line is connected to a via. The final conclusion is often not a simple summation, but rather an aggregation operation like logical OR or logical AND. Independent cells, because their graphics do not interact with other cells, can directly determine the presence or absence of connections internally. This determination result reflects the true physical connection status of that local area and can be used independently. Therefore, the subtask output of an independent cell is an independent graphics processing result. For cells with graphical connections, because the graphics extend across cells, a single cell can only see a local portion of the graphics, and its local determination result cannot reflect the true connection status of the entire line. For example, a cell might determine no interaction internally, but the entire line may be connected at another cell. The local result must be logically ORed with the local results of other cells on the same line to obtain a physically meaningful overall conclusion. Therefore, the subtask output of a cell with graphical connections is a non-independent graphics processing result.

[0080] For global constraint tasks such as minimum spacing checks, linewidth checks, and inclusion relationship checks, since these tasks check whether the layout meets certain design rules, the conclusion is usually a judgment of the entire layout, such as whether there are spacing violations, or it is necessary to mark all violation locations. For spacing checks, if the check is for the spacing between two patterns within the same cell, the check result can be used directly as an independent pattern processing result. If the check is for the spacing between two patterns across cells, such as the distance between the ends of the metal lines in cell A and cell B, the position information of both cells needs to be obtained simultaneously. A single cell cannot independently draw the correct conclusion. In this case, the local spacing information or local violation mark of each cell's subtask output is a non-independent pattern processing result. For inclusion relationship checks, such as the requirement that an N-well must completely surround a PMOS, if the surrounded pattern and the surrounding pattern are both within the same cell, the subtask result can be independent as an independent pattern processing result. If the surrounded pattern and the surrounding pattern belong to different cells, the local information output by each cell is a non-independent pattern processing result, requiring cross-cell comprehensive judgment.

[0081] For Boolean generation tasks, such as performing AND, OR, XOR, etc., operations on two layers to generate a new layer, these tasks are typically executed independently per unit. The Boolean operation results within a unit can be directly output as a new layer for that unit, without needing cross-unit integration. Therefore, regardless of whether the unit is an independent unit or a unit with graphical connections, the output of each subtask can be directly used as an independent graphics processing result.

[0082] In some embodiments, the preset parallelism enhancement strategy includes: adjusting the subtasks whose input data originates from the output data of multiple other subtasks to be executed earlier; the processing of step 103 includes: Step 501: Based on the input characteristics of each subtask, identify at least one third target subtask whose input data originates from the output data of multiple other subtasks. Step 104 includes the following processing steps: Step 502: Adjust the execution order of the third target subtask in the parallel execution order of the task string to the direction of earlier execution.

[0083] Input data originating from the output data of multiple other subtasks means that a subtask needs to read the results of multiple different upstream subtasks before execution. The outputs of these multiple different upstream subtasks together constitute the complete input of the subtask. For example, a summarization subtask needs to read the outputs of multiple local area calculation subtasks, add them together to obtain the total area, and the input data of this summarization subtask originates from the output data of multiple other subtasks.

[0084] In one implementation, the input characteristics of each subtask can be examined to determine whether the input data of a subtask originates from the output data of multiple different other subtasks. If a subtask requires the results of at least two other subtasks as its input, then that subtask is identified as a third target subtask.

[0085] For example, if the layout processing task is to calculate the total area of ​​a certain metal layer on the entire chip, after decomposing the layout processing task into cells, multiple local area calculation subtasks are obtained, each subtask outputting the local area of ​​its corresponding cell. In addition, there is a summarizing subtask used to add all the local areas to obtain the total area. The input data for the summarizing subtask comes from the output of each local area calculation subtask. Therefore, this summarizing subtask is identified as the third target subtask.

[0086] For each third target subtask, its upstream subtasks can be determined first; these are the subtasks whose output data is used as input data by the third target subtask. Since the execution of the third target subtask must wait for all its upstream subtasks to complete before it can begin, when moving the third target subtask forward in the parallel execution order of the task string, its new position cannot be earlier than any of its upstream subtasks. For example, the third target subtask can be moved to the first position after all its upstream subtasks have completed, that is, immediately after its last completed upstream subtask.

[0087] The layout processing task distribution method provided in this embodiment identifies a third subtask whose input data originates from the output data of multiple other subtasks, and adjusts its execution order in the direction of earlier execution. This allows the third subtask to be executed faster after all its upstream subtasks are completed, reducing the waiting time of the third subtask and thus improving the overall execution efficiency of the layout processing task.

[0088] In some embodiments, the preset parallelism enhancement strategy further includes: adjusting the execution direction of subtasks whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result; the processing of step 103 further includes: Step 601: Based on the input and output characteristics of each subtask, identify at least one fourth target subtask whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result. The processing in step 104 also includes: Step 602: Adjust the execution order of the fourth target subtask in the parallel execution order of the task string to the backward direction.

[0089] The input data does not originate from multiple other subtasks. The output data can be that the input data of a subtask comes entirely from the layout data and does not depend on any other subtask, or the input data of a subtask comes only from the output data of one other subtask.

[0090] Execution direction adjustment refers to moving a subtask to the back of the parallel execution order in a task string, so that it is executed later than other subtasks.

[0091] In one implementation, for each subtask, if its input data does not originate from the output data of multiple other subtasks, and its output is an independent graphics processing result, then the subtask is identified as the fourth target subtask.

[0092] In this embodiment, since the output of the fourth target subtask is an independent graphics processing result, adjusting the execution order of the fourth target subtask to the backward direction can prioritize the allocation of the early stages of the layout processing task to other subtasks whose output is not an independent graphics processing result, reduce the waiting time of other subtasks, and thus improve the overall processing efficiency of the layout processing task.

[0093] In some embodiments, the layout processing task method includes a task of calculating the graphic area of ​​a specified layer; prior to step 103, the method further includes: Step 701: Classify the subtasks after the decomposition of the layout processing task to distinguish the subtasks corresponding to units containing independent graphics, the subtasks corresponding to multiple units with graphic connection relationships, and the subtasks used for area summation. Step 702: For the subtask corresponding to the unit containing independent graphics, determine that the input feature representation of the subtask does not originate from the output data of multiple other subtasks, and that the output feature representation of the subtask is the processing result of the independent graphics. Step 703: For subtasks corresponding to multiple units with graphical connection relationships, determine the output feature representation of the subtask as a non-independent graphical processing result. Step 704: For the subtask used for area summation, determine the input feature representation of the subtask, the input data of which originates from the output data of multiple other subtasks, and the output feature representation of the subtask, the output data of which is an independent graphics processing result.

[0094] A specified layer can refer to a specific metal layer, polysilicon layer, or other conductive or dielectric layer in the layout that requires area calculation. The graphic area refers to the size of the planar region occupied by all graphics within the layer.

[0095] In step 701, a cell containing independent graphics refers to a cell whose graphics are completely located within the cell boundary and do not have any geometric connection, contact or cross-boundary extension with the graphics of adjacent cells.

[0096] Multiple units with graphical connections refer to two or more units whose graphics are connected at the boundary. For example, a metal line extends from unit A into unit B, or the graphics of two units happen to meet at the boundary.

[0097] The subtask for area summation does not directly read the layout data, but relies on the area values ​​output by other subtasks. Furthermore, the output of the subtask for area summation is the final result of the task that calculates the graphic area of ​​the specified layer.

[0098] In step 702, for subtasks corresponding to units containing independent graphics, since the input data of such subtasks originates from a specified layer of graphics in the layout data and does not depend on the output of other subtasks, the input feature of such subtasks is determined to be that the input data does not originate from the output data of multiple other subtasks. Simultaneously, since the local area output by such subtasks is the actual area of ​​the complete graphic and has independent physical meaning, it can be directly used for subsequent area summation without needing to be integrated with the results of other subtasks; therefore, its output feature is determined to be that the output data is the result of independent graphic processing.

[0099] In step 703, for subtasks corresponding to multiple units with graphical connections, since the local area output by such subtasks is the area of ​​the cut graphical fragments and does not have complete physical meaning, it must be added to the area of ​​other fragments belonging to the same continuous graphic to restore the physical meaning. Therefore, the output feature characterization output data of such subtasks is determined to be a non-independent graphical processing result.

[0100] In step 704, for the subtask of area summation, since the input data for this type of subtask comes from the outputs of all local area subtasks (i.e., it requires reading multiple area values ​​for addition), it is determined that the input feature representation of this type of subtask originates from the output data of multiple other subtasks. Simultaneously, the total area output by this type of subtask has complete physical meaning; therefore, the output feature representation of this type of subtask is determined to be an independent graphics processing result.

[0101] In one implementation, the subtasks corresponding to multiple units with graphical connections and the subtasks corresponding to units containing independent graphics can be executed in parallel. However, since the input characteristics of the subtasks corresponding to units containing independent graphics indicate that the input data does not originate from the output data of multiple other subtasks, and the output is the result of independent graphics processing, the backward execution direction of the subtasks corresponding to units containing independent graphics can be adjusted.

[0102] Figure 5 This is a schematic diagram illustrating the parallel execution order of task strings provided in another embodiment of this application. Figure 6 This is a schematic diagram of the adjusted parallel execution order of task strings provided in another embodiment of this application.

[0103] In one embodiment, if the layout processing task is to calculate the area of ​​a specified layer, the layout processing task is decomposed into: subtask task1 corresponding to a unit containing independent graphics, subtasks task21 and task22 corresponding to multiple units with graphic connections, and subtask task3 for area summation. Based on the layer dependencies in the layer logical operations to be executed in tasks1, task21, task22, and task3, the parallel execution order of the task strings between the subtasks is determined as follows: Figure 5 As shown, Figure 5 In the process, tasks 1, 21, and 22 are executed in parallel first, and then task 3 is executed based on the output of tasks 1, 21, and 22 to obtain the graphic area of ​​the specified layer.

[0104] However, since the input data for task1 does not originate from the output data of multiple other subtasks, and the output is an independent graphics processing result, the execution order of task1 can be adjusted backwards. The adjusted parallel execution order of the task string is as follows: Figure 6 As shown, tasks21 and22 can be executed in parallel first, so that the outputs of tasks21 and22 are ready. Then, task1 can be executed first to obtain all the input data required by task3, and finally task3 can be executed.

[0105] Since the input data for subtask 3 originates from the output data of multiple other subtasks, the execution order of task 3 can be adjusted to prioritize tasks. That is, after tasks 21 and 22 are executed, tasks 3 and 1 can be executed in parallel. Task 3 can first calculate the sum of tasks 21 and 22, and then continue calculation after the output of task 1 is ready. This reduces the waiting time of task 3 and improves overall processing efficiency. When resources are sufficient, tasks 21, 22, and 3 can be executed simultaneously. Task 1 can be executed after tasks 21 and 22 are completed. Task 3 can obtain a portion of the input data immediately after tasks 21 and 22 are completed, and obtain the remaining input data after task 1 is completed, further reducing the execution waiting time of task 3.

[0106] Figure 7 This is a schematic diagram illustrating the parallel execution order of task strings provided in another embodiment of this application. Figure 8 This is a schematic diagram of the adjusted parallel execution order of task strings provided in another embodiment of this application.

[0107] In one embodiment, if the layout processing task is to calculate the area of ​​a graphic in a specified layer, the layout processing task is decomposed into: a subtask task1 corresponding to a unit containing independent graphics, subtasks task21 and task22 corresponding to multiple units with graphic connection relationships, a subtask task31 for summarizing the area of ​​multiple units with graphic connection relationships, and a subtask task32 for summing the areas.

[0108] Based on the layer dependencies in the layer logical operations to be executed in tasks 1, 21, 22, 31, and 32, the parallel execution order of the task strings among the subtasks is determined as follows: Figure 7 As shown, Figure 7 In the process, task1, task21, and task22 are executed in parallel first, then task31 is executed, and finally task32 is executed to obtain the graphic area of ​​the specified layer.

[0109] Since the input data of subtask 1 does not originate from the output data of multiple other subtasks and the output is an independent graphics processing result, the outputs of task 21 and task 22 are not independent graphics processing results. The input data of task 31 and task 32 originate from the output data of multiple other subtasks. Therefore, at least one of the following preset parallelism enhancement strategies can be executed: adjust the execution order of subtask 1 to be executed backward, adjust the execution order of task 21 and task 22 to be executed earlier, and adjust the execution order of task 31 and task 32 to be executed earlier.

[0110] The adjusted parallel execution order of the task strings is as follows: Figure 8 As shown, tasks 21 and 22 are executed in parallel first to obtain the input data for task 31. Then, tasks 31 and 1 are executed in parallel to obtain the input data for task 32. Finally, task 32 is executed to obtain the graphic area of ​​the specified layer. By prioritizing the parallel execution of tasks 21 and 22, task 31 can meet the startup conditions, thus allowing task 1 and task 31 to be executed in parallel, improving task parallelism. Task 31 no longer needs to wait for task 1 to complete, and task 32 can start faster because the results of tasks 31 and 1 are ready earlier. This effectively reduces the idle waiting time between subtasks, improves the utilization of computing resources, and increases the efficiency of layout processing tasks.

[0111] The layout processing task method provided in this application defines the output data of subtasks corresponding to units containing independent graphics as independent graphics processing results, and the output data of subtasks corresponding to multiple units with graphic connection relationships as non-independent graphics processing results. The area summation subtask is defined as having input from the outputs of multiple other subtasks. This allows for the priority execution of subtasks corresponding to non-independent graphics processing results, ensuring their output is ready as early as possible, while delaying the execution of subtasks corresponding to independent graphics processing results to avoid consuming critical resources. Furthermore, it advances the preprocessing of the area summation subtask, reducing waiting time and reducing the overall execution time of the area calculation task, thereby improving resource utilization.

[0112] In some embodiments, the layout processing task method includes a task of calculating the connectivity between the master layer and the reference layer; prior to step 103, the method further includes: Step 801: Classify the subtasks after the decomposition of the map processing task to distinguish between subtasks that can independently calculate layer connection relationships, subtasks that cannot independently calculate layer connection relationships, and subtasks used for comprehensive relationship judgment. Step 802: For subtasks that can independently calculate layer connection relationships, determine that the input feature representation of the subtask does not originate from the output data of multiple other subtasks, and that the output feature representation of the subtask is the final result. Step 803: For subtasks that cannot independently calculate layer connection relationships, determine the output feature representation of the subtask as an intermediate result. Step 804: For the subtask used for relational comprehensive judgment, determine the input feature representation of the subtask, indicating that the input data originates from the output data of multiple other subtasks.

[0113] The primary layer refers to a graphic layer whose connectivity needs to be checked, such as a metal layer. The reference layer refers to another graphic layer whose connectivity is determined in relation to the primary layer, such as a via layer or contact hole layer. Connectivity refers to whether there are geometric interactions such as overlap, contact, or containment between the graphics of the primary layer and the graphics of the reference layer. Physically, this interaction indicates an electrical connection between the two layers at corresponding locations.

[0114] In integrated circuit manufacturing processes, the graphics of certain layers must be precisely aligned with those of other layers to form effective electrical connections. For example, vias must fall above metal lines; otherwise, an open circuit will occur. The purpose of calculating the connectivity between the master layer and the reference layer is to check whether the master layer and the reference layer in the entire layout meet the expected connectivity requirements. Typically, this requires outputting the locations where connections exist or the overall assessment results.

[0115] A subtask that can independently calculate layer connectivity refers to a subtask within its corresponding cell where the connectivity between the graphics of the main layer and the graphics of the reference layer can be determined directly within that cell without needing to refer to information from other cells. When the main layer graphics within a cell are complete, do not extend across cells, and the graphics of the reference layer do not depend on other cells, the subtask corresponding to that cell can typically calculate layer connectivity independently.

[0116] A subtask that cannot independently calculate layer connectivity refers to a subtask where, within the corresponding cell, the graphics of the main layer may extend across cells, or the graphics of the reference layer may be related to adjacent cells. This makes it impossible to complete a full connectivity determination within that cell, and only a partial conclusion can be drawn. This partial conclusion may be true or false, but it cannot represent the true connectivity of the entire continuous graphic.

[0117] The subtask used for relational synthesis and judgment refers to the task of logically aggregating the partial results of multiple subtasks that cannot be calculated independently, such as through a logical OR operation, to obtain the final overall connection relationship. The input of this subtask comes from the outputs of multiple subtasks.

[0118] In step 801, for subtasks that can independently calculate layer connectivity, the input data for these subtasks comes from the main and reference layer graphics in the layout data and does not depend on the output of any other subtasks. Therefore, their input characteristic is determined to be that the input data does not originate from the output data of multiple other subtasks. The connectivity judgment results output by these subtasks are already complete and correct within this unit and can be directly used as part of the final result or directly without needing to be integrated with the results of other subtasks. Therefore, their output characteristic is determined to be that the output data is an independent graphics processing result.

[0119] In step 802, for subtasks that cannot independently calculate layer connectivity, the local connectivity judgment results output by such subtasks may be false negatives or false positives. This is because the main layer graphic may extend to adjacent units, where connectivity exists, causing a local false negative result for this unit to not represent the true situation of the entire line. Conversely, a local true positive result may be correct, but a comprehensive analysis is still needed to obtain an overall conclusion. Therefore, the output results of such subtasks do not have independent physical meaning and must be logically ORed with the local results of other units on the same continuous graphic to obtain the final conclusion. Thus, their output characteristics are determined as output data that is not an independent graphic processing result.

[0120] In step 803, for the subtask used for relational comprehensive judgment, the input data of this type of subtask comes from the output of multiple subtasks that cannot independently calculate the connection relationship. That is, it requires reading multiple local Boolean values ​​for logical OR and other aggregation operations. Therefore, its input feature is determined to be that the input data comes from the output data of multiple other subtasks. The final connection relationship output by this type of subtask has complete physical meaning. Therefore, the output feature of this type of subtask is determined to represent the output data as an independent graph processing result.

[0121] This implementation defines the output data of subtasks that can independently calculate layer connectivity as independent graphics processing results, and the output data of subtasks that cannot independently calculate layer connectivity as non-independent graphics processing results. Subtasks used for comprehensive relation judgment are defined as having input sources from multiple other subtask outputs. This allows for the priority execution of subtasks corresponding to non-independent graphics processing results, ensuring their output is ready as early as possible. Subtasks corresponding to independent graphics processing results are executed later to avoid consuming critical resources. Preprocessing of the comprehensive relation judgment subtask is advanced to reduce waiting time, thereby reducing the overall execution time of the layer connectivity check task and improving resource utilization.

[0122] Figure 9 This is a schematic diagram of the adjusted parallel execution order of a task string provided in another embodiment of this application. In one embodiment, based on the input characteristics and / or output characteristics of each subtask, a second target subtask whose output is a non-independent graphics processing result is identified; a third target subtask whose input data originates from the output data of multiple other subtasks is identified; and at least one fourth target subtask whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result is identified. Then, in the parallel execution order of the task string, the execution order of the second target subtask is adjusted to the earlier execution direction, the execution order of the third target subtask is adjusted to the earlier execution direction, and the execution order of the fourth target subtask is adjusted to the later execution direction, resulting in the following... Figure 9 The diagram shown illustrates the parallel execution order of the adjusted task sequence. During task distribution, the second and third target subtasks are executed first, followed by the fourth target subtask.

[0123] In one implementation, to address the issue of delays caused by unstable subtask execution in scenarios such as complex defect detection, the layout processing task distribution method provided in this application embodiment can evaluate and reconstruct dependencies in real time to improve task distribution efficiency. Specifically, during subtask execution, execution data of subtasks (such as intermediate output data, computation progress, resource usage, etc.) are collected in real time to dynamically evaluate the dependency strength between subtasks. For subtasks waiting to be executed, the execution of subtasks with strong dependencies is monitored. If a delay occurs during execution, and the intermediate output data of the strongly dependent subtask has met the basic execution requirements of the subtask to be executed (such as the error being within the allowable range and not affecting the core processing accuracy), the strongly dependent subtask is automatically and temporarily downgraded to a weak dependency, the dependency is reconstructed, and the subtask to be executed is allowed to start execution ahead of schedule. After the strongly dependent subtask is completed, it is asynchronously corrected back to a strong dependency so that it can continue to execute reliably according to the original dependency.

[0124] In this implementation, the problem of insufficient parallelism and idle computing power caused by determining the dependencies of all subtasks at once during the task decomposition stage in traditional task distribution, even if the execution of strongly dependent subtasks is delayed, still requires waiting for completion before subsequent subtasks can be started, is addressed by evaluating the dependency strength in real time. Without affecting the processing accuracy, some constraints of strong dependencies are temporarily released, effectively releasing potential parallel space and improving task distribution efficiency.

[0125] In other implementations, to distribute tasks more efficiently, the decision-making data required for task distribution, such as subtask decomposition granularity, dependency changes, node computing power matching, parallel execution efficiency, blocking scenarios and resolution effects, can be categorized and stored according to layout type (e.g., logic chip, memory chip), process node (e.g., 7nm, 5nm), and task type (e.g., graphics area calculation task, connection relationship calculation task) for quick retrieval according to category.

[0126] As can be seen from the above one or more embodiments, the layout processing task distribution method provided in this application can improve the task parallelism of layout task processing, thereby improving processing speed and efficiency.

[0127] Based on the layout processing task distribution method, this application also provides specific embodiments of a layout processing task distribution apparatus.

[0128] Figure 10 This is a schematic diagram of the structure of a layout processing task distribution apparatus provided in one embodiment of this application. Figure 9 As shown, the layout processing task distribution device 90 provided in this application embodiment includes: The decomposition device 91 is used to decompose the layout processing task into units according to the unit hierarchical structure information of the layout, and obtain the sub-tasks corresponding to each unit. Determining device 92 is used to determine the parallel execution order of task strings among subtasks based on the layer dependency relationship in the layer logical operation to be executed by each subtask. The identification device 93 is used to identify target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask. The adjustment device 94 is used to adjust the execution order of the target subtasks in the parallel execution order of the task string according to a preset parallelism enhancement strategy, so as to obtain the adjusted parallel execution order of the task string. The distribution device 95 is used to distribute tasks based on the adjusted parallel execution order of the task strings.

[0129] As an optional embodiment, the preset parallelism enhancement strategy includes: merging multiple subtasks that are executed in parallel and have the same input data; the identification device 93 is specifically used to: identify multiple first target subtasks that are executed in parallel and have the same input data based on the input characteristics of each subtask; the adjustment device 94 is specifically used to: merge multiple first target subtasks into one subtask in the parallel execution order of the task string.

[0130] As an optional embodiment, when the operation instructions of multiple first target subtasks are different, the operation instructions of the merged subtask include a set of operation instructions of multiple first target subtasks; when the operation instructions of multiple first target subtasks are the same but the operation parameters are different, the operation instructions of the merged subtask are the operation instructions of one of the multiple first target subtasks, and the operation parameters include a set of operation parameters of multiple first target subtasks.

[0131] As an optional embodiment, the preset parallelism enhancement strategy includes: adjusting the execution order of subtasks whose output is a non-independent graphics processing result to the direction of earlier execution; the identification device 93 is specifically used to: identify at least one second target subtask whose output is a non-independent graphics processing result according to the output characteristics of each subtask; the adjustment device 94 is specifically used to: adjust the execution order of the second target subtask in the parallel execution order of the task string to the direction of earlier execution.

[0132] As an optional embodiment, the preset parallelism enhancement strategy includes: adjusting the subtask whose input data originates from the output data of multiple other subtasks to be executed first; the identification device 93 is specifically used to: identify at least one third target subtask whose input data originates from the output data of multiple other subtasks based on the input characteristics of each subtask; the adjustment device 94 is specifically used to: adjust the execution order of the third target subtask in the parallel execution order of the task string to be executed first.

[0133] As an optional embodiment, the preset parallelism enhancement strategy further includes: adjusting the execution direction of subtasks whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result; the identification device 93 is specifically used to: identify at least one fourth target subtask whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result based on the input and output characteristics of each subtask; the adjustment device 94 is specifically used to: adjust the execution order of the fourth target subtask in the parallel execution order of the task string to the backward execution direction.

[0134] As an optional embodiment, the layout processing task method includes the task of calculating the graphic area of ​​a specified layer; the apparatus further includes: Before identifying the target subtask that conforms to the preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask, the device further includes: The first classification module is used to classify the subtasks after the decomposition of the layout processing task, in order to distinguish the subtasks corresponding to the unit containing independent graphics, the subtasks corresponding to multiple units with graphic connection relationships, and the subtasks used for area summation. The second determining module is used to determine, for the subtask corresponding to the unit containing independent graphics, that the input feature characterization of the subtask is not derived from the output data of multiple other subtasks, and that the output feature characterization of the subtask is the result of independent graphics processing. For subtasks corresponding to multiple units with graphical connections, the output features of the subtasks are determined to represent the output data as non-independent graphical processing results; For the subtask used for area summation, the input feature representation of the subtask is determined to be derived from the output data of multiple other subtasks, and the output feature representation of the subtask is that the output data is an independent graph processing result.

[0135] As an optional embodiment, the layout processing task method includes the task of calculating the connectivity between a master layer and a reference layer, and the apparatus further includes: The second classification module is used to classify the subtasks after the decomposition of the map processing task, in order to distinguish subtasks that can independently calculate the layer connection relationship, subtasks that cannot independently calculate the layer connection relationship, and subtasks used for comprehensive relationship judgment. The third determination module is used to: for subtasks that can independently calculate layer connection relationships, determine that the input feature representation of the subtask is not derived from the output data of multiple other subtasks, and that the output feature representation of the subtask is an independent graphics processing result. For subtasks that cannot independently calculate layer connectivity, the output features of the subtasks are determined to represent the output data as non-independent graphics processing results. For the subtask used for comprehensive relation judgment, the input features of the subtask are determined to represent that the input data comes from the output data of multiple other subtasks.

[0136] The layout processing task distribution apparatus provided in this application embodiment can be used to execute the layout processing task distribution method provided in any of the above embodiments and achieve the same effect, which will not be elaborated here.

[0137] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 10 As shown, the electronic device provided in this application embodiment may include: a processor 1001 and a memory 1002 storing computer program instructions.

[0138] Specifically, the processor 1001 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0139] Memory 1002 may include mass storage for data or instructions. For example, and not limitingly, memory 1002 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 1002 may include removable or non-removable (or fixed) media. Where appropriate, memory 1002 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 1002 is non-volatile solid-state memory.

[0140] The processor 1001 reads and executes computer program instructions stored in the memory 1002 to implement any of the layout processing task distribution methods in the above embodiments.

[0141] In one example, the electronic device may also include a communication interface 1003 and a bus 1010. Wherein, as... Figure 10 As shown, the processor 1001, memory 1002, and communication interface 1003 are connected through bus 1010 and complete communication with each other.

[0142] The communication interface 1003 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0143] Bus 1010 includes hardware, software, or both, that couples the components of the electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 1010 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0144] Furthermore, in conjunction with the layout processing task distribution method in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the layout processing task distribution methods in the above embodiments.

[0145] In addition, in conjunction with the layout processing task distribution method in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device executes the layout processing task distribution method provided by any aspect of the above embodiments of this application.

[0146] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0147] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0148] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0149] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0150] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for distributing layout processing tasks, characterized in that, include: Based on the unit hierarchical structure information of the layout, the layout processing task is decomposed into units to obtain the sub-tasks corresponding to each unit; Based on the layer dependencies in the layer logical operations to be executed in each of the subtasks, the parallel execution order of the task strings among the subtasks is determined. Based on the input and / or output characteristics of each subtask, identify the target subtask that conforms to the preset parallelism enhancement strategy; In the parallel execution order of the task string, the execution order of the target subtasks is adjusted according to the preset parallelism enhancement strategy to obtain the adjusted parallel execution order of the task string; Tasks are distributed based on the adjusted parallel execution order of the task strings.

2. The map processing task distribution method according to claim 1, characterized in that, The preset parallelism enhancement strategy includes: merging multiple subtasks that are executed in parallel and have the same input data; The step of identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask includes: Based on the input characteristics of each subtask, identify multiple first target subtasks that are executed in parallel and have the same input data; In the parallel execution order of the task string, the execution order of the target subtasks is adjusted according to the preset parallelism enhancement strategy, including: In the parallel execution sequence of the task string, the multiple first target subtasks are merged into one subtask.

3. The map processing task distribution method according to claim 2, characterized in that, When the operation instructions of the multiple first target subtasks are different, the operation instructions of the merged subtask include the set of operation instructions of the multiple first target subtasks; When the operation instructions of the multiple first target subtasks are the same but the operation parameters are different, the operation instruction of the merged subtask is the operation instruction of one of the multiple first target subtasks, and the operation parameters include the set of operation parameters of the multiple first target subtasks.

4. The map processing task distribution method according to claim 1, characterized in that, The preset parallelism enhancement strategy includes: adjusting the execution order of subtasks whose output is a non-independent graphics processing result to be executed earlier; The step of identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask includes: Based on the output characteristics of each subtask, identify at least one second target subtask whose output is a non-independent graphics processing result; In the parallel execution order of the task string, the execution order of the target subtasks is adjusted according to the preset parallelism enhancement strategy, including: In the parallel execution order of the task string, the execution order of the second target subtask is adjusted to the direction of earlier execution.

5. The layout processing task distribution method according to claim 1 or 4, characterized in that, The preset parallelism enhancement strategy includes: adjusting the subtasks whose input data originates from the output data of multiple other subtasks to be executed first; The step of identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask includes: Based on the input characteristics of each subtask, identify at least one third target subtask whose input data originates from the output data of multiple other subtasks; In the parallel execution order of the task string, the execution order of the target subtasks is adjusted according to the preset parallelism enhancement strategy, including: In the parallel execution order of the task string, the execution order of the third target subtask is adjusted to the direction of earlier execution.

6. The map processing task distribution method according to claim 5, characterized in that, The preset parallelism enhancement strategy also includes: adjusting the execution direction of subtasks whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result; The step of identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output features of each subtask further includes: Based on the input and output characteristics of each subtask, identify at least one fourth target subtask whose input data does not originate from the output data of multiple other subtasks and whose output is an independent graphics processing result. The step of adjusting the execution order of the target subtasks according to the preset parallelism enhancement strategy in the parallel execution order of the task string further includes: In the parallel execution order of the task string, the execution order of the fourth target subtask is adjusted to the backward execution direction.

7. The map processing task distribution method according to claim 6, characterized in that, The layout processing task includes calculating the graphic area of ​​a specified layer; Before identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask, the method further includes: The subtasks after the decomposition of the map processing task are classified to distinguish the subtasks corresponding to units containing independent graphics, the subtasks corresponding to multiple units with graphic connection relationships, and the subtasks used for area summation. For the subtask corresponding to the unit containing independent graphics, it is determined that the input feature characterization of the subtask indicates that the input data does not originate from the output data of multiple other subtasks, and the output feature characterization of the subtask indicates that the output data is the result of independent graphics processing. For the subtasks corresponding to the multiple units with graphical connections, the output feature representation of the subtasks is determined to be a non-independent graphical processing result; For the subtask of area summation, the input feature representation of the subtask is determined to be derived from the output data of multiple other subtasks, and the output feature representation of the subtask is determined to be the result of independent graphics processing.

8. The map processing task distribution method according to claim 6, characterized in that, The layout processing task includes calculating the connection relationship between the main layer and the reference layer; Before identifying target subtasks that conform to a preset parallelism enhancement strategy based on the input and / or output characteristics of each subtask, the method further includes: The subtasks after the decomposition of the map processing task are classified to distinguish between subtasks that can independently calculate layer connection relationships, subtasks that cannot independently calculate layer connection relationships, and subtasks used for comprehensive relationship judgment. For subtasks that can independently calculate layer connection relationships, it is determined that the input feature representation of the subtask is not derived from the output data of multiple other subtasks, and the output feature representation of the subtask is an independent graphics processing result. For subtasks that cannot independently calculate layer connectivity, the output feature representation of the subtask is determined to be a non-independent graphics processing result; For a subtask used for comprehensive relation judgment, the input features of the subtask are determined to represent that the input data originates from the output data of multiple other subtasks.

9. An electronic device, characterized in that, include: Processor and memory storing computer program instructions; When the processor executes the computer program instructions stored in the memory, it implements the layout processing task distribution method as described in any one of claims 1-8.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the layout processing task distribution method as described in any one of claims 1-8.

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