A dynamic scheduling system of rail transit AI algorithm warehouse and edge node

Abstract

The application provides a dynamic scheduling system of a rail transit AI algorithm warehouse and an edge node, relates to the technical field of rail transit edge computing and resource scheduling, and comprises an algorithm warehouse, an edge cluster, a dynamic scheduler and a review center. The dynamic scheduler predicts the remaining span of a target train arriving at a monitoring defense zone according to a train occupancy signal, instructs a target heterogeneous edge device to pre-load model weights to establish a silent shadow container when the remaining span is lower than a threshold value, and activates the target heterogeneous edge device as an inference container when the train enters. When the burst same type alarm reaches the concurrent congestion limit value, the target heterogeneous edge device aggregates all same type alarm events into a homologous disturbance cluster according to the space intersection ratio and the time span to implement interception, extracts the target image features with the highest confidence to submit to the review center, and performs batch state overwrite according to the verification conclusion. The application realizes the on-demand dynamic allocation of computing power resources and reduces the communication and cloud review load.

Description

Technical Field

[0001] This invention relates to the field of edge computing and resource scheduling technology for rail transit, and in particular to a dynamic scheduling system for rail transit AI algorithm warehouses and edge nodes. Background Technology

[0002] Numerous video surveillance devices are deployed along rail transit lines to ensure train safety. To reduce the communication pressure of transmitting massive amounts of video data to the central data center, the industry often adopts a cloud-edge collaborative architecture, distributing visual analysis algorithms to edge computing nodes along the line for inference tasks to be performed locally. This model improves the processing efficiency of video data and offloads the computing load from the cloud.

[0003] In actual operation, rail transit exhibits significant spatiotemporal tidal characteristics. Trains physically shuttle through different block sections along predetermined routes, and the computing resource requirements of each station's monitoring zone dynamically change with the train's movement. If the visual algorithm container is continuously hosted in the physical memory of all edge nodes, long periods without trains will result in prolonged idleness of underlying computing resources, hindering the coordinated allocation of computing power. If the inference program is only temporarily launched when the train enters the monitoring zone, the underlying system will incur significant time consumption in processes such as reading files and allocating physical page tables, leading to a cold start delay in the model and making it difficult to meet the business requirements of real-time analysis.

[0004] Furthermore, when a train travels at high speed through a monitored area, the alternating sweep of the rapidly moving train body and the headlights causes frequent changes in the ambient light and shadow. When dealing with such drastically fluctuating image sequences, the edge-side inference model is prone to continuously outputting a large number of similar and overlapping inference results within a short period. In the absence of an effective local filtering mechanism, the edge device pushes all these concurrent alarms caused by sudden environmental changes to the central review node. This processing method consumes limited network bandwidth and also puts instantaneous high-frequency access pressure on the visual large-scale model interface of the review center. Summary of the Invention

[0005] The purpose of this invention is to provide a dynamic scheduling system for rail transit AI algorithm warehouses and edge nodes, in order to solve the technical problems in the prior art, such as idle resources caused by static deployment of edge computing power, cold start delay due to temporary loading, and transmission network congestion and excessive cloud review load caused by a large number of redundant alarms induced by train passing through.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: A dynamic scheduling system for rail transit AI algorithm warehouses and edge nodes, comprising: Algorithm repository, a standard container image used for centralized storage of visual algorithms; An edge cluster consists of multiple heterogeneous edge devices to build a schedulable pool of computing resources; A dynamic scheduler is used to distribute the standard container image to target heterogeneous edge devices among the plurality of heterogeneous edge devices to perform inference; The verification center is used to call the large model interface to perform verification on the alarm events generated by inference; The dynamic scheduler is configured to predict the remaining span of the target train to reach the monitoring zone of the target heterogeneous edge device based on the received train physical occupancy signal, and when the remaining span is equal to or less than a set threshold, instruct the target heterogeneous edge device to load model weights into video memory to establish a silent shadow container, and activate the silent shadow container as an inference container when the target train enters the monitoring zone. The target heterogeneous edge device is configured to perform interception filtering based on the concurrent state of sudden similar alarm events triggered by the inferred container activation. When the sudden similar alarm events are detected to reach the concurrent congestion limit, all similar alarm events are aggregated into a homogeneous disturbance cluster according to the spatial intersection-union ratio and time span to intercept redundant requests. Only the target image features with the highest confidence are extracted and sent to the verification center. The device is also configured to perform batch state overwrite on all alarm events in the homogeneous disturbance cluster based on the verification conclusion returned by the verification center.

[0007] Optionally, the algorithm repository has built-in multi-vendor isolation engines; The multi-vendor isolation engine is configured to intercept the ingestion of standard container images with specific vendor identifiers and call the built-in scanning program to perform security vulnerability scans. It uses a namespace isolation mechanism to control the deployment of standard container images from different vendors in a completely isolated virtual runtime environment. At the underlying level, it allocates physically isolated input data mount volumes and inferred log volumes and configures directory access control permissions to prohibit cross-vendor resource access.

[0008] Optionally, the dynamic scheduler is configured with a dual verification logic component for computing power; The computing power dual verification logic component is configured to extract the real-time remaining available graphics processor memory capacity of the target heterogeneous edge device before distributing the standard container image, and compare it with the minimum memory requirement parameter declared by the standard container image. When it is determined that the real-time remaining available graphics processor memory capacity is greater than or equal to the sum of the minimum memory requirement parameter and the preset fluctuation buffer capacity, the underlying distribution instruction is permitted to be issued.

[0009] Optionally, the dynamic scheduler is configured with a multi-algorithm logic orchestration wizard component; The multi-algorithm logic orchestration wizard component is configured to receive a parallel inference task submitted by the front end, which contains multiple independent algorithm containers, perform frame-level timestamp synchronization alignment on the alarm events output by each independent algorithm container in the multiple independent algorithm containers at different frame rates, and generate fused alarm events according to the pre-configured combined operation rules of logical AND, logical OR, or logical NOT to be collaboratively uploaded to the review center.

[0010] Optionally, a hardware abstraction agent is deployed within each of the plurality of heterogeneous edge devices; The hardware abstraction proxy is configured to encapsulate the underlying calling interfaces of physical graphics processors, virtualized graphics processors, and tensor processors, integrating the computing units of various processors into a computing resource pool that supports dynamic allocation. The dynamic scheduler is configured to perform adaptive load balancing allocation to all computing units in the computing resource pool based on the weighted minimum connection number state and the memory fragmentation rate.

[0011] Optionally, the dynamic scheduler is configured to acquire the status of the train's physical occupancy section and the real-time train speed issued by the external rail transit signaling system in real time, and calculate the remaining span by combining the pre-recorded physical track topology information. When the remaining span is equal to or less than the pre-calculated extreme value of the total cold start time of the container, a preheating wake-up command is sent to the target heterogeneous edge device, so that the target heterogeneous edge device extracts the model weight file into the graphics processor's memory block, and completes the memory preemption construction of the silent shadow container.

[0012] Optionally, the dynamic scheduler is configured to retrieve the physical train schedule timetable after the target train has completely left the monitoring zone to obtain the estimated physical train intervals for adjacent subsequent trains to arrive at the monitoring zone; When the estimated physical driving interval is determined to be less than the set degradation cooling threshold, the target heterogeneous edge device is controlled to destroy the application layer memory buffer queue, and at the same time, a video memory latch instruction is sent to the target operating system, so that the model weight parameters are forced to reside in the corresponding video memory block.

[0013] Optionally, the dynamic scheduler is further configured to issue a deep destruction command to the target heterogeneous edge device when it is determined that the estimated physical driving interval is greater than or equal to the set degradation cooling threshold; The target heterogeneous edge device is configured to terminate the corresponding underlying inference daemon process according to the deep destruction instruction, trigger the operating system's garbage collection mechanism to completely clear the occupied video memory block, and immediately return the corresponding computing resources to the computing resource pool.

[0014] Optionally, the target heterogeneous edge device records a pixel optical flow rate of change benchmark value that characterizes the severity of image changes, and is configured to automatically intercept the inference data sent to the cloud to start clustering logic when the actual optical flow rate of change in a continuous image sequence exceeds the pixel optical flow rate of change benchmark value, and the number of sudden similar alarm events generated within a specific time window reaches the concurrency congestion limit used to protect the request frequency of the large model interface. The target heterogeneous edge device calculates the spatial intersection-union ratio of each inferred detection bounding box in adjacent time periods. When the spatial intersection-union ratio is greater than the overlap determination threshold, it determines that the same source interference condition is met, and then extracts features to generate the same source perturbation cluster.

[0015] Optionally, the target heterogeneous edge device is configured to establish a pointer mapping tracking table for the homogeneous perturbation cluster in a local memory database, and to establish a binding mapping between the unique identification code of all inferred data in the homogeneous perturbation cluster and the extracted target image features; The target heterogeneous edge device is configured to look up the pointer mapping tracking table when it receives a valid verification result or false alarm judgment result issued by the verification center, use the underlying pointer call mechanism to write the corresponding verification conclusion in batches to the status field of all inferred data with binding mapping, and perform a centralized archiving operation after completing the status transition.

[0016] The present invention has achieved the following beneficial effects: The dynamic scheduling system for the rail transit AI algorithm warehouse and edge nodes of this invention predicts the remaining span by combining the train's physical occupancy signal with a dynamic scheduler. Before the train arrives at the defense zone, the system controls the target heterogeneous edge devices to preload model weights and construct silent shadow containers. These shadow containers are then activated as inference containers for target detection as the train enters the zone. This mechanism enables edge computing power to be scheduled on demand, closely following the train's spatial displacement, improving resource idleness in static deployment mode and reducing model startup time loss caused by temporary loading. For situations involving drastic changes in light and shadow and concurrent alarms caused by high-speed train passage, the target heterogeneous edge devices initiate local interception when they detect a sudden surge of similar alarms reaching the concurrent congestion limit. Based on the spatial intersection-union ratio and time span, similar alarm events are aggregated into clusters of shared disturbances. The system extracts only the target image features with the highest confidence from these clusters for review and performs batch status overwriting of locally associated alarms based on the verification conclusions issued by the review center. This local filtering and aggregation mechanism based on physical conditions reduces the transmission consumption of redundant inference data to external networks, alleviates the concurrent request load of the cloud-based large model interface, and optimizes the stable operation and data flow efficiency of the rail transit monitoring network in complex operating scenarios.

[0017] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0018] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a structural block diagram of the dynamic scheduling system for the rail transit AI algorithm warehouse and edge nodes in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the method for securely storing and isolating standard container images using a multi-vendor isolation engine, as described in this invention. Figure 3 This is a flowchart illustrating the method for the dynamic scheduler to perform adaptive load balancing allocation and dual memory verification in an embodiment of the present invention. Figure 4 This is a flowchart of the inference container preheating construction and dynamic activation method based on train displacement prediction in an embodiment of the present invention; Figure 5 This is a flowchart of the local interception and filtering and homogeneous disturbance cluster aggregation method for sudden redundant alarms in an embodiment of the present invention; Figure 6 This is a flowchart of the edge computing power lifetime degradation cooling and resource recycling method based on physical driving intervals in an embodiment of the present invention. Detailed Implementation

[0020] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0021] This embodiment provides a dynamic scheduling system for rail transit AI algorithm warehouses and edge nodes. For example... Figure 1 As shown, this system is deployed between the central data environment of rail transit and stations along the line, and is configured to dynamically allocate heterogeneous computing resources and perform inference task flow. Specifically, the dynamic scheduling system for the rail transit AI algorithm warehouse and edge nodes includes an algorithm warehouse, an edge cluster, a dynamic scheduler, and a review center.

[0022] The algorithm repository is used to centrally store standard container images of visual algorithms. It is understood that these standard container images encapsulate the operating system runtime environment, deep learning framework, network topology parameters, and model weight files required to perform visual inference tasks. Through hierarchical file system packaging, the standard container images ensure consistent runtime dependencies for visual algorithms across different deployment nodes.

[0023] The edge cluster consists of multiple heterogeneous edge devices to construct a schedulable computing resource pool. Each of these heterogeneous edge devices is distributed across physical stations along the rail transit line and includes various computing units such as central processing units, physical graphics processing units, and tensor processors provided by different manufacturers. The computing resource pool logically abstracts and integrates the physically dispersed computing units, providing a unified resource allocation and addressing interface.

[0024] The dynamic scheduler is used to distribute the standard container image to target heterogeneous edge devices among the multiple heterogeneous edge devices for inference. The dynamic scheduler connects to the edge cluster via a network communication protocol, obtains the hardware resource status of the edge devices, and issues container creation, startup, and resource reclamation control commands for the standard container image.

[0025] The verification center is used to call the large model interface to verify the inferred alarm events. After the edge side completes visual inference and generates inferred alarms, the verification center receives the feature data sequence uploaded by the target heterogeneous edge device, and calls the large visual model deployed on the central node to perform secondary recognition and analysis calculations on the image feature matrix in the alarm event.

[0026] Furthermore, integrated monitoring systems for rail transit typically integrate visual network models from multiple independent algorithm vendors. To control the boundary constraints of low-level calls and file read / write operations between algorithms from different vendors, such as... Figure 2 As shown, the algorithm repository incorporates a multi-vendor isolation engine. This engine is configured to intercept standard container image import operations containing specific vendor identifiers and invoke a built-in scanner to perform security vulnerability scans. Specifically, when an external platform pushes a standard container image to the algorithm repository, the multi-vendor isolation engine intercepts the data packet at the application layer and extracts the specific vendor identifier from the packet.

[0027] The multi-vendor isolation engine blocks direct write system calls to the storage array, redirecting the mirrored data stream to an isolated memory sandbox. Within this sandbox, the multi-vendor isolation engine initiates its built-in scanning program.

[0028] The built-in scanner parses the layered structure of the standard container image, extracts the code instruction sequences of executable files and linked libraries, and matches them with the execution patterns in the local security risk signature database. Once the built-in scanner confirms that the target image does not contain any unauthorized calls to read kernel registers or unauthorized network port configurations, and outputs a compliance status code, the multi-vendor isolation engine removes the blocking status and transfers the standard container image to the main storage pool of the algorithm repository.

[0029] The multi-vendor isolation engine utilizes a namespace isolation mechanism to control the deployment of standard container images from different vendors in a completely isolated virtual runtime environment. Before the dynamic scheduler instructs the instantiation process of the target heterogeneous edge device, the multi-vendor isolation engine allocates a dedicated process identifier namespace and network namespace for image instances with specific vendor identifiers. Under this process identifier namespace, when the algorithm process calls the interface to enumerate the system process list, it can only obtain the status parameters of its own derived child processes and cannot obtain the process status of the host machine or other vendors' containers. At the same time, the system configures a dedicated virtual Ethernet card and an independent routing table for this instance to restrict cross-namespace data packet transmission routes.

[0030] At the data persistence isolation level, the multi-vendor isolation engine allocates physically isolated input data mount volumes and inferred log volumes at the underlying layer. The multi-vendor isolation engine invokes the logical volume management module of the edge device's operating system to divide the storage medium into independent data partitions with non-overlapping physical address spaces, defining them as the input data mount volume and inferred log volume, respectively. During the image boot phase, the multi-vendor isolation engine uses the operating system's file system mount instructions to precisely map these partitions to specific file directories of the corresponding virtual runtime environment. Furthermore, the multi-vendor isolation engine configures directory access control permissions to prohibit cross-vendor resource access. In its access control architecture, the multi-vendor isolation engine registers a specific vendor identifier as a unique system user identification code. The system reads the node attribute table and uses access control list commands to establish configuration bindings between the read, write, and execute permission masks of the directories associated with the input data mount volume and inferred log volume and this user identification code. When the operating system's file access audit module detects an access call initiated by a mismatched user identification code, it directly blocks the addressing operation that crosses the file mount point boundary in kernel mode.

[0031] To address the heterogeneity of physical hardware architecture within the edge cluster, a hardware abstraction agent is deployed within each of the multiple heterogeneous edge devices. This hardware abstraction agent is configured to encapsulate the low-level calling interfaces of physical graphics processors, virtualized graphics processors, and tensor processors, integrating the computing units of various processors into a dynamically allocated pool of computing resources. As a resident system service process, the hardware abstraction agent loads the low-level driver mapping libraries corresponding to various computing architectures. The hardware abstraction agent intercepts memory allocation requests and computation queue submission instructions issued by the dynamic scheduling system and converts them into a communication protocol format natively compatible with the corresponding hardware, according to the instruction operation specifications of the target processor. The hardware abstraction agent periodically extracts parameters such as the number of active processing cores, logical clock frequency, and data throughput bandwidth from the computing chip. The hardware abstraction agent calls a parameter conversion algorithm component to normalize and convert the above multi-dimensional physical characteristic parameters, generating a comprehensive evaluation scalar for heuristically evaluating scheduling. The specific parameter conversion mathematical equation is as follows: ; in, For a dimensionless heuristic evaluation scalar used in weighted ranking, For the local minima normalization function, and These are the preset computing power feature weights and bandwidth feature weights, respectively, and satisfy the following conditions: , This represents the number of processing cores in the underlying active state. The core logic clock frequency (in GHz). Data throughput bus bandwidth (in GB / s). The built-in dictionary of the hardware abstraction agent contains empirical constants for instruction throughput (IPC) per cycle, pre-calibrated for different chip instruction set architectures (such as ARM, x86, or GPU architecture).

[0032] Specifically, the empirical constant of instruction throughput per cycle The calibration values ​​are obtained offline from the standard SPEC CPU test suite and the Generalized Matrix Multiplication (GEMM) benchmark. In the system's default built-in hardware abstraction map dictionary, when the underlying architecture is an ARM architecture processor based on the RISC instruction set, due to its simplified pipeline characteristics... The value range is defined as 2.5 to 3.5; when it is a multi-core processor based on the CISC instruction set x86 architecture, The value range is defined as 4.0 to 5.5; when it is a graphics processing unit (GPU) based on a streaming multiprocessor concurrent architecture, because its single-core instruction execution pipeline is shallow, its corresponding single CUDA core The value is fixed and defined as 0.8 to 1.2. By looking up a table to match the α constant corresponding to the hardware architecture, the system achieves standardized quantification of the basic computing power of heterogeneous chips. Through this multiplication derivation, the characteristics of heterogeneous hardware are uniformly converged and mapped into a scalar value representing the computing power per second. The hardware abstraction agent registers the encapsulated computing unit objects and their computing power indicators to the global resource directory table of the edge cluster, constructing a unified computing power resource pool at the logical level.

[0033] like Figure 3 As shown, during the distribution scheduling, the dynamic scheduler is configured to perform adaptive load balancing allocation to all computing units within the computing resource pool based on the weighted minimum connection count status and the memory fragmentation rate. Specifically, the load analysis component of the dynamic scheduler sends a status request message to each computing unit node through the status synchronization interface to query the total number of concurrent inferred daemons currently allocated and running. The dynamic scheduler extracts the static load weight value based on the floating-point instruction complexity of the network model corresponding to each inferred daemon. The load analysis component performs a multiplication-addition operation on the total number of concurrent connections and the static load weight value, outputting the weighted minimum connection count status parameter to characterize the pipeline load pressure of the computing node. In addition, the dynamic scheduler obtains the underlying memory address mapping status map through the hardware abstraction proxy. The dynamic scheduler counts the total number of bytes of discrete memory fragments in the free memory blocks whose continuous capacity is lower than the model's preset memory loading benchmark due to physical address dispersion, divides the total number of bytes of fragments by the current total capacity of the free memory of the device, and calculates the memory fragmentation rate parameter. The dynamic scheduler substitutes the calculated weighted minimum connection number state parameter and memory fragmentation rate parameter into the load evaluation cost function of the adaptive scheduling module for numerical solution, and binds the distributed task route to the available computing unit node with the lowest solution value of the evaluation cost function.

[0034] The load assessment cost function is constructed as a nonlinear constraint equation in the continuous-time domain within the adaptive scheduling module: ; In the formula, Cost of load assessment; The weighted minimum connection number state parameter collected from the front end; The maximum concurrent thread context limit allowed by the target heterogeneous hardware under the current computing bandwidth; This represents the calculated memory fragmentation rate scalar. For the natural constant An exponential function with base 0; and For normalized business configuration coefficients; This is the physical fragmentation penalty factor for video memory.

[0035] The and The range of values ​​is And strictly meet Under normal monitoring conditions in rail transit, to balance the response time of concurrent tasks and the stability of video memory, the default values ​​for both are respectively... When the dynamic scheduler detects that the overall memory utilization rate of the entire computing resource pool exceeds the warning threshold (e.g., 80%), the control plane built into the dynamic scheduler will adaptively adjust the weights. The value is dynamically adjusted to the range of 0.7 to 0.8 to prioritize suppressing the dispatch of new tasks to nodes with high fragmentation rates by increasing the weight of memory fragmentation penalty.

[0036] For 4K ultra-high-definition surveillance video streams accessed by rail transit station defense zones, the multi-scale feature maps in deep convolutional inference cause an exponential increase in the demand for physical memory contiguous page tables. The system will incorporate a physical fragmentation penalty factor. The value is forcibly defined within the range of 3.5 to 4.5. When the memory fragmentation rate of the target computing node crosses the preset 30% critical threshold, the exponential term... The output value of the driving cost function jumps sharply, and the operation instructions of the inference container are directly rejected at the resource addressing layer through the mathematical extremum property.

[0037] Because the operation of the visual reasoning model has a hard dependency threshold on the underlying physical memory capacity, the dynamic scheduler is configured with a dual-check logic component. This dual-check logic component is configured to extract the real-time remaining available GPU memory capacity of the target heterogeneous edge device before distributing the standard container image, and compare it with the minimum memory requirement parameter declared by the standard container image. Specifically, the dual-check logic component constructs a system memory probe message and sends it to the target heterogeneous edge device. The device's hardware monitoring process calls the underlying driver interface to read the storage hardware status and obtain the total physical memory page frame capacity parameter. The hardware monitoring process reads the used memory bytes that have been locked and page-mapped in the system memory allocation table. Through difference calculation, the hardware monitoring process obtains the unoccupied real-time remaining available GPU memory capacity parameter and reports it to the dual-check logic component. Simultaneously, the dual-check logic component parses the metadata configuration file of the standard container image to be distributed, extracts the minimum memory requirement parameter marked during the model compilation and optimization stage, which limits the basic physical storage required for instantiating the network topology and computing tensors.

[0038] The dual-verification logic component allows the issuance of a low-level distribution instruction when it determines that the real-time remaining available GPU memory capacity is greater than or equal to the sum of the minimum memory requirement parameter and the preset fluctuation buffer capacity. The dynamic anchor frames and intermediate tensor variables generated by the visual algorithm during the multi-scale feature extraction stage of the image will cause additional memory page frames to be requested during network operation. The preset fluctuation buffer capacity is configured as a fixed constant to compensate for and absorb this dynamic memory usage. Specifically, the preset fluctuation buffer capacity is set as a fixed percentage conversion value between 15% and 20% of the minimum memory requirement parameter based on the test results of the deployed visual algorithm generating feature pyramids at standard definition to 4K resolutions. Alternatively, it can directly use a system-level hard constant, with a value range between 256MB and 512MB, thereby accurately covering the additional memory overhead of the object detection network generating dynamic anchor frames and temporary tensor variables during the inference stage. The dual-verification logic component performs arithmetic addition to add the minimum memory requirement parameter to the preset fluctuation buffer capacity to generate the total threshold parameter for the admitted memory. The dual-verification logic component uses a comparator module to compare the real-time remaining available GPU memory capacity parameter with the total threshold parameter for admission memory. When the real-time remaining available GPU memory capacity is determined to be greater than or equal to the total threshold parameter, the dual-verification logic component outputs a resource approval ready flag to the scheduling state machine. The dynamic scheduler then issues a low-level distribution instruction containing mirroring startup parameters to the target heterogeneous edge device in the network control plane. If the determination is not valid, the resource distribution request is rejected, and a node meeting the available memory conditions is re-searched in the computing resource pool to perform the resource allocation process.

[0039] To address the scheduling requirements of multiple types of visual detection networks operating in parallel within a single monitoring zone, the dynamic scheduler is equipped with a multi-algorithm logic orchestration wizard component. This component is configured to receive parallel inference tasks submitted by the front-end, each containing multiple independent algorithm containers. The front-end task orchestration system compiles the detection business rules into a structured orchestration list and distributes it to the multi-algorithm logic orchestration wizard component. Based on this list, the wizard component extracts model identifiers and controls the target heterogeneous edge devices to launch the corresponding multiple independent algorithm containers in parallel. The devices allocate a shared image buffer queue in main memory, introduce the raw digital image sequences output from the decoding hardware pipeline into this queue, and distribute read pointers to the input ingestion nodes of each independent algorithm container.

[0040] Because deep neural network models at different levels differ in the size of hidden layer nodes and computational complexity, there is temporal asynchrony in the process of generating output inference results for the same video frame. The multi-algorithm logic orchestration wizard component performs frame-level timestamp synchronization alignment on the alarm events output by each independent algorithm container at different frame rates. Specifically, when the video data preprocessing component acquires image frames and stores them in the database, it calls the system monotonic clock module to append a global absolute timestamp parameter to each frame of digital image. After each independent algorithm container completes the network forward propagation calculation, it copies and encapsulates the read global absolute timestamp parameter into the alarm event structure generated by its output. The multi-algorithm logic orchestration wizard component establishes and manages a message buffer storage queue in memory for receiving associated results. The multi-algorithm logic orchestration wizard component extracts the global absolute timestamp of the first alarm event as a hash key and polls other independent buffer storage queues within the configured time tolerance sliding window. The span of the time tolerance sliding window is dynamically and adaptively set based on the physical input frame rate parameter of 25 frames per second for the standard video source of rail transit, with its specific absolute time value constantly limited to a closed interval of 40 milliseconds to 120 milliseconds. This window span can accurately encompass and absorb the asynchronous network inference offset of up to three video frames caused by differences in computing power between the heterogeneous front-end containers on the physical timeline. The multi-algorithm logic orchestration wizard component extracts alarm event structures with the same global absolute timestamp and uses memory reference mounting operations to merge and combine them into a pre-allocated frame-level alignment context, thereby achieving alignment of heterogeneous parallel network detection data frame results.

[0041] The multi-algorithm logic orchestration wizard component generates fused alarm events based on pre-configured combined operation rules of logical AND, logical OR, or logical NOT, and uploads them collaboratively to the review center. After timing synchronization alignment is achieved, the logic evaluation engine of the multi-algorithm logic orchestration wizard component retrieves the combined operation rule structure tree generated by the corresponding parallel inference task. When a node in the structure tree is parsed as a logical AND operation, the logic evaluation engine checks whether all alarm status words of specified classification attributes within the frame-level alignment context jointly present a true value; when parsed as a logical OR operation, it checks whether it contains a true value for the judgment output of any classification dimension; when parsed as a logical NOT operation, it checks whether the trigger state of the limiting condition data is simultaneously excluded when a specific main classification judgment output exists. If the Boolean algebra solution result performed based on the above structure tree is valid, the multi-algorithm logic orchestration wizard component extracts target boundary coordinate data and classification feature tensor matrix data containing each independently calculated associated alarm event from the frame-level alignment context. The system performs field content assembly and serialized packet compression processing to generate a fused alarm event message with a single structure, and calls the transmission control network layer protocol to send it to the review center.

[0042] The physical computing resource requirements of a rail transit system exhibit a spatiotemporal distribution characteristic derived from the displacement of the train entity. The dynamic scheduler is configured to acquire in real-time the train entity occupancy status and real-time speed from the external rail transit signaling system, and calculate the remaining span by combining this with pre-recorded physical track topology information. Specifically, axle counters deployed along the line by the external rail transit signaling system continuously detect the train entity's wheelset positions, generating data messages reflecting physical section occupancy and clearance, and sending them via the industrial communication bus network. The dynamic scheduler's message receiving daemon listens to a specific port in real-time, intercepts and parses the data message to extract the train's unique identification sequence number, block section code segment, and instantaneous displacement speed scalar. The block section code segment represents the train entity occupancy status, and the instantaneous displacement speed scalar represents the real-time speed. The dynamic scheduler persistently maintains a physical track topology graph in its database. This graph maps the coordinates of the boundary nodes of the entire block section and the starting physical coordinates of the monitoring zones covered by cameras of each edge device into directed graph vertex objects, mapping the physical running distance length of the corresponding section into edge weight parameters. The dynamic scheduler's calculation module invokes the graph structure addressing algorithm component, using the vertices corresponding to the obtained block section coding segments as the starting point of spatial calculation and the vertices corresponding to the starting physical coordinates of the target monitoring zone as the ending point. It accumulates edge weight data along the shortest connected path to obtain the physical trajectory length variable of the train's leading part from the entrance section of the target monitoring zone. The dynamic scheduler divides this physical trajectory length variable by the real-time train speed parameter, performs numerical calculations to obtain the remaining span parameter in the time dimension, and records it in the memory state control block.

[0043] For the non-uniform speed controlled operation of rail transit trains in block sections, simply using scalar division will introduce prediction drift in arrival time. The dispatcher system extracts the automatic train protection speed limit step curve broadcast in real time from the rail transit signaling network. When the detected real-time train speed is equal to or less than the speed limit jump boundary ahead of the monitored zone, it indicates that the locomotive will enter the deceleration braking phase. The computing engine retrieves the commonly used braking deceleration physical calibration constant for the corresponding train formation model. This constant is constrained by the rail adhesion coefficient and is limited to 0.8 to 1.1 meters per square second. The microprocessor divides the physical running trajectory length along the speed limit step into two spatial slices: uniform speed cruise and braking deceleration. The braking deceleration slice is substituted into the locomotive dynamics calculus equation derived from classical kinematics to solve for the absolute transition time of the speed decay process. The specific expression of this equation is: ; To adapt to the rapid discretization of industrial control systems, it is transformed into a linear deceleration model equation: ; in, For absolute transition time, This refers to the instantaneous braking deceleration of a train during the braking and deceleration process. This refers to the instantaneous train speed variable during braking and deceleration. This refers to the initial real-time train speed when the train enters the deceleration phase. Set the speed limit jump boundary speed for the target in the preceding section. This involves retrieving the commonly used physical calibration constants for braking deceleration, which are defined as being between 0.8 and 1.1 meters per square second. The time consumption data for each slice is then summed to generate the corrected final remaining span parameters. This mechanism eliminates the estimation error of cold start warm-up time caused by train braking at the station and prevents premature invalid locking of the computing node's memory page table.

[0044] like Figure 4 As shown, the dynamic scheduler is configured to predict the remaining span of the target train's arrival at the target heterogeneous edge device's monitoring zone based on the received train physical occupancy signal, and instruct the target heterogeneous edge device to load model weights into video memory to establish a silent shadow container when the remaining span is equal to or less than a set threshold. Further, when the remaining span is equal to or less than the pre-calculated maximum total cold start time of the container, a preheating wake-up command is sent to the target heterogeneous edge device, causing the target heterogeneous edge device to extract the model weight file into the graphics processor's video memory block, completing the memory preemption construction of the silent shadow container. The maximum total cold start time of the container is a time cost constant fixed by the control system based on the underlying hardware benchmark test of the deployment node, which covers the total cumulative latency required for the device system to call the underlying bus to read the image data file, decompress the hierarchical structure file, and allocate a continuous video memory page table to the graphics processor. When the dynamic scheduler's timed task state machine compares and confirms that the remaining span parameter is equal to or less than the sum of the extreme value of the total cold start time of the container and the instruction transmission delay parameter, it sends a warm-up wake-up command carrying resource target location configuration parameters to the target heterogeneous edge device. The instruction transmission delay parameter is dynamically assigned by the liveness detection daemon thread built into the dynamic scheduler's network layer by periodically sending ICMP protocol echo request messages to the target heterogeneous edge device and extracting half of the average round-trip time (RTT) of the most recent 5 time periods. For the physical environment of the local fiber optic private network along the rail transit line, the safety upper limit of this instruction transmission delay parameter is forcibly truncated and converged to the range of 15 milliseconds to 25 milliseconds.

[0045] After receiving the warm-up wake-up command, the resource process scheduling module of the target heterogeneous edge device sends a request to the underlying video memory resource allocation component to allocate a contiguous physical page frame address in the available space of the graphics processor's physical video memory for storing parameter tensors. The operating system of the target heterogeneous edge device initiates the file peripheral read operation process, using the system bus data block transfer mechanism to map and load the model weight file data stream from the non-volatile storage medium and write it to the allocated physical video memory block, completing the locking and modification settings of the corresponding page table occupancy status bits. At this time, the listening input port of the visual analysis container application is not bound to the front-end video stream distribution queue channel of the associated system. The task scheduler response component of the target operating system sets the system execution thread of the inference daemon process to a blocked and suspended state configuration, stopping the allocation of machine instruction time slice sequences for the execution cycle of the central computing processor. This configuration object node, which implements resource page loading and solidification at the physical storage level but is in a logical waiting and dormant working environment at the instruction control computing level, is defined as a silent shadow container.

[0046] The dynamic scheduler is configured to activate the silent shadow container as an inference container when the target train enters the monitoring zone. The dynamic scheduler's position coordinate tracker performs cyclic calculations to track changes in the train's physical occupancy status. When the comparison logic compares and confirms that the acquired physical coordinate position of the train's leading edge crosses the calibrated starting physical boundary record point of the target monitoring zone, the dynamic scheduler triggers an interrupt to push a control state change network packet to the target heterogeneous edge device. After obtaining the packet payload content through protocol parsing, the system process control unit of the target heterogeneous edge device calls the system operation mechanism interface component to modify the application thread state flag corresponding to the frozen phase of the silent shadow container to the ready-to-run queue layer. During this synchronization process, the device data ingestion and distribution service binds the first address of the buffered data output by the video decoding unit to the data ingress port node of the inference container environment, thereby importing a continuously input digital array matrix stream. Since the weight matrix of the correlation model required for computation in the underlying hardware structure has been put in place through physical residency operations, the main computation thread of the program directly obtains the extracted data resource stream, starts and calls the corresponding operation logic pipeline to carry out forward propagation mathematical model calculation instructions such as tensor convolution and feature pooling mapping operations, and then continuously outputs inference monitoring data events.

[0047] When a train intrudes at high speed into the physical field of view of the camera equipment along the line, the high-gloss sweep of its front end and the rapid displacement of the physical vehicle structure will cause the environmental background light and shadow signals to exhibit nonlinear high-frequency conversion disturbance waveforms. This will cause the image feature acquisition hidden layer to make incorrect response calculations and judgments, resulting in dense similarity result parameters and generating a large number of redundant alarm events.

[0048] The target heterogeneous edge device records a baseline value for the pixel optical flow rate of change, characterizing the severity of image changes. The system is configured with a visual analysis and calibration control module to measure, acquire, and define this value. During a background reference time period with stable physical lighting and no train obstruction, the system retrieves a dense pixel optical flow tracking basic model. Considering the strict power consumption limitations and real-time requirements of edge computing nodes, this basic model adopts the Gunnar Farneback traditional classical visual optical flow algorithm model based on polynomial expansion. Its internal operation logic is as follows: by extracting approximate values ​​of local spatial polynomial coefficients from the pyramid of adjacent video frames, and using the pixel displacement polynomial constraint equation, the dense displacement vector field of each pixel in the two-dimensional coordinate system is directly iteratively solved, thereby completing the average summarization of the optical flow offset vector with extremely low computational overhead. The mean value of the optical flow coordinate motion offset vector of all corresponding grid points in the continuous static image group array of the historical view is read and captured and summarized; mean smoothing processing is performed to obtain the noise floor parameter setting constant of the static deviation environment parameter; then, the record is solidified through the file input module and set as this pixel optical flow rate of change baseline value for environmental situation reference comparison.

[0049] Within the parallel operation of the inference engine pipeline service startup phase, the independent optical flow calculation and detection module receives and parses the grayscale parameter channel tensor corresponding to the captured video frame, performs two-dimensional spatiotemporal gradient displacement calculation and differential calculation process, obtains the mean value structure of the global distribution, and thus calculates in real time the actual optical flow change rate representing the actual light and shadow parameter changes of the current physical environment image sequence.

[0050] like Figure 5 As shown, the target heterogeneous edge device is configured to perform interception filtering based on the concurrent state of sudden similar alarm events triggered by the activation of the inference container. The local network communication component of the target heterogeneous edge device opens a ring-shaped area for allocating statistical variables as a sliding statistical calculation window of fixed time length. This component generates a cumulative total number of sudden similar alarm events that have entered the buffer from the inference queue and carry the same identification and classification label configuration parameters by accumulating function counts. The target heterogeneous edge device is configured to automatically intercept inference data sent to the cloud to initiate clustering logic when the actual optical flow change rate in a continuous image sequence exceeds the pixel optical flow change rate benchmark value, and the number of sudden similar alarm events generated within a specific time window reaches the concurrent congestion limit used to protect the request frequency of the large model interface. The large model interface analyzes the maximum calculated throughput load index of the received requests, converts it into the corresponding set concurrent congestion limit parameter threshold, and uses it as a stable protection boundary value. The conversion steps and related logical equations are as follows: ; in, For concurrent congestion limits, The maximum allowed network receive bandwidth per unit time configured for the verification center gateway. This refers to the average byte size of a single uploaded "target image feature package" in historical statistics. The preset network jitter buffer coefficient (constantly set to 0.8) is used, and the calculation result is rounded down. This derivation ensures that the amount of alarm feature data sent out instantaneously will never exceed the carrying capacity limit of the cloud physical channel.

[0051] The device operating system deploys a discriminant analysis execution component monitoring and comparison system that collects two monitoring parameter streams. When it is confirmed that the actual optical flow change rate measurement value returned by the inferred calculation is higher than the fixed pixel optical flow change rate benchmark value, and the total number of sudden similar alarm events generated within a specific time period is also greater than or equal to the protection limit for concurrent congestion, the system status control center decides to confirm that the current device node monitoring viewpoint is being interfered with by high-frequency disturbances. At this time, the core execution module immediately sends a port locking intervention signal to the network protocol processing driver to block the service call logic of the transport layer outgoing socket. This operation causes the already generated and packaged network packet outgoing step to fail, and the data is temporarily suspended in the internal storage segment of the buffer queue preset by the memory application interface, thereby preventing the upward transmission from blocking the trunk path. Then, the system call code processing branch switches the processing flow, activating the pipeline module process of data reorganization, aggregation, merging and other analysis and processing.

[0052] When the target heterogeneous edge device detects that the sudden similar alarm events have reached the concurrent congestion limit, it aggregates all similar alarm events into a homogeneous disturbance cluster based on the spatial intersection-union ratio (CIU) and time span to intercept redundant requests. Specifically, the target heterogeneous edge device calculates the CIU of each inferred detection bounding box within adjacent time periods, and determines that the homogeneous interference condition is met when the CIU is greater than the overlap determination threshold. The arithmetic unit sorts the time records extracted from the sequence combination. Within the nearest adjacent time interval, two alarm records with the same type of target inference label are randomly selected for judgment. The system executes geometric calculation rules, compares the projected overlapping area of ​​the intersection region of the two coordinate mapping bounding boxes, and calculates the quotient of this overlapping area and the total area of ​​the union of the two bounding boxes, thereby obtaining the spatial CIU used to measure the degree of overlap. The comparison control register performs a comparison judgment on this value. When the spatial intersection-union ratio is found to be greater than the set overlap judgment threshold, and the time span difference between the two extracted processing timestamps falls within the time-series distance period requirement of the constrained constraint, the output content of the relevant object is determined to meet the characteristics caused by a single disturbance, that is, it is confirmed to meet the preset same-source interference condition.

[0053] The conditions for interference from the same source are subject to the dual rigid constraints of spatial geometric overlap and temporal span. Considering the nonlinear affine deformation induced by the high-brightness sweep of the train headlights and the reflection of the vehicle body within the monitoring lens, the overlap judgment threshold is dynamically mapped based on the calibration installation pitch angle parameters of the track-side camera: when the installation pitch angle is below 30 degrees, it is set to a reference constant of 0.85; when the pitch angle is between 30 and 60 degrees, to compensate for the natural attenuation of the target bounding box intersection area caused by the longitudinal trapezoidal perspective distortion of the image, the system forcibly lowers the judgment threshold to a closed interval of 0.65 to 0.75. The temporal dimension constraint period is anchored to the maximum buffer queuing depth of the target heterogeneous edge device video decoding pipeline, and is rigidly truncated into a sliding tolerance time window of 120 milliseconds under the 25 frames per second rail transit standard input format. The above-mentioned mechanism for disclosing the judgment parameters of the fusion camera's three-dimensional pose and the video physical frame rate accurately removes the redundant feature accumulation caused by high-frequency in-situ spot jitter. The clustering control execution module extracts event data that conforms to the judgment rules, obtains the starting address value of its physical pointer and performs binding mapping; it loads and places it in a specific tree-like aggregation feature data container dynamically allocated in the system's main memory, thereby constructing a cluster of related objects containing underlying attribution details and connection path mapping logic, namely, a homogeneous perturbation cluster structure.

[0054] The target heterogeneous edge device extracts only the target image features with the highest confidence and sends them to the verification center. The analysis and processing module retrieves and traverses the independent inference events bound to the nodes within the aggregated data object set tree of the same source perturbation cluster, extracting the stored floating-point values ​​containing the inference confidence scores reflecting the credibility of the network operation. The system sorts these values ​​in descending order, filters and retrieves the alarm event objects with the highest scores, and designates them as the core data for sampling reference benchmarks. The system generates extraction and acquisition instructions based on the physical mapping relationship of the boundary coordinates set by the reference, calls the hardware operation register to address the video frame buffer block space; specifies the start and end offset row and column numbers for this region, submits matrix block memory direct copy read operations and cropping instructions, separates and obtains matrix segments related to the results reflected in the local image; at the same time, it merges the high-dimensional classification corresponding feature tensor data output by the hidden layer of the neural network in this processing logic, performs sequence packaging integration and final compilation and encapsulation, and generates the target image feature package to be published and uploaded to the transmission channel.

[0055] To establish a feedback coverage control synchronization mechanism from the review center's judgment to the local intercepted inferred data group, the target heterogeneous edge device is configured to create a pointer mapping tracking table for the same-source disturbance cluster in its local memory database. This table binds the unique identification code of all inferred data within the same-source disturbance cluster to the extracted target image features. Specifically, the target heterogeneous edge device uses a hash information processing procedure to extract the physical identifier address of the access media hardware of the computing terminal device and concatenates it with the physical acquisition absolute timestamp. A one-way encrypted solution is then performed using an information hash function to generate a string variable of a specific length with guaranteed uniqueness, serving as a unique identification code for associated records. This unique identification code is recorded in system memory as the identification credential for the target data. The system calls and mounts the memory working environment to maintain a table-based database component; a new management application data registration table record is created, with the unique identification code as the primary key, configured in the pointer mapping tracking table. Simultaneously, the addressing and tracing process traverses and reads the storage structure of all collected events within the same source disturbance cluster, extracts their task code, and queries the absolute starting address of the record in the physical memory space; it calls the addressing operation pointer to perform displacement matching calculations, synthesizes the associated string arrangement content; and loads it into a pointer mapping tracing array sequence of a specific size, configures and stores it in the data field block, so that the external network flow judgment packet can establish a tight binding mapping with the local memory data entity based on the identity recognition code.

[0056] The target heterogeneous edge device is configured to perform batch state overwrite on all alarm events within the same source disturbance cluster based on the verification conclusion returned by the verification center. The verification center obtains the target feature processing calculation service, calls the loaded computing power to process the large model to perform calculation and discrimination on the multi-dimensional vector graph structure. The bottom layer of the large model adopts a topology structure based on the fusion of the Visual Transformer (ViT) backbone network and the Feature Pyramid Network (FPN). Its internal composition and specific data flow are as follows: After the data access layer of the large model receives the extracted target image features, it first cuts and maps the image feature matrix into a fixed-length one-dimensional sequence through the image patch embedding subunit, and superimposes the spatiotemporal position encoding; then the data flows into the Transformer encoder, which is composed of a multi-layer masked self-attention mechanism and a feedforward neural network (FFN) stacked alternately, to extract global long-distance dependent features.

[0057] To address the dimensionality difference between the single-scale one-dimensional sequence output by the standard ViT and the two-dimensional multi-scale feature maps required by the Feature Pyramid Network (FPN), a feature reorganization and dimensionality reduction pipeline is deployed within the large model. This pipeline sets feature truncation probes at the outputs of the attention blocks in layers 4, 8, 12, and 16 of the Transformer encoder. The truncated fixed-length one-dimensional sequences (with end-classification tokens separated and discarded) are inversely reshaped into two-dimensional spatial feature matrices based on the original spatial row and column segmentation indices of the image patches. Subsequently, corresponding to these four two-dimensional feature matrices of different depths, the system performs two-dimensional transposed convolutional upsampling with stride parameters of 4x, 8x, 16x, and 32x, respectively, along with channel mapping dimensionality reduction operations, thereby converting them into four-layer two-dimensional feature maps with progressively decreasing spatial resolution.

[0058] After the above reorganization process, the multi-scale hidden features output from each stage of the encoder are then fed into the Feature Pyramid Network (FPN) to perform top-down deep and shallow feature cascade fusion. Finally, the fused feature tensor is fed into the classifier head composed of a multilayer perceptron (MLP), where it is normalized using the Softmax activation function, and the output is an array of confidence probability distributions used to characterize valid verification or false alarm determination.

[0059] The verification center confirms the verification result as a valid verification result configuration identifier reflecting a physically valid record, or identifies it as a false alarm result identifier caused by noise interference; it also queries the received exclusive identification code, combines and encapsulates it to generate a verification data operation response confirmation message, and transmits the distribution operation message to the sending end through the outer wide area communication link.

[0060] The target heterogeneous edge device is configured to look up the pointer mapping tracking table when it receives a valid verification result or a false alarm judgment result issued by the verification center, and use the underlying pointer call mechanism to write the corresponding verification conclusion in batches to the status fields of all inferred data with binding mapping. The communication application of the target heterogeneous edge device listens to the protocol messages of the background component unblocking the network port, and extracts information data containing configuration update flags, verification conclusions, and the unique identification code used for traceability comparison. The device system control bus logic calls the database lookup interface component, uses the unique identification code as the primary key for address retrieval, and extracts the pointer mapping tracking array content containing the absolute starting address. The system kernel uses this array sequence to bypass the read restrictions of the front-end object model through the underlying memory management component; it performs addressing according to register instructions and address offset displacement to obtain the target memory segment used to store the discrimination identifier; then it issues a physical storage overwrite instruction to perform batch loop overwrite of the judgment status flag code, thereby completing the update association of all associated inferred data status fields.

[0061] The target heterogeneous edge devices are configured to centrally perform archiving operations after completing state transitions. The operating system's task monitoring interface awaits a full confirmation response from the probe control memory bus write operation controller regarding the hardware processing response flag information submitted to the aforementioned register segments. The system reads and collects all alarm result record block structures that are currently stored in the temporary memory buffer pool and whose judgment fields have been modified. Through a parsing interface, these records are converted, combined, and merged to generate a fixed-length binary sequence log for communication, which is then uniformly output and stored in character stream file mode. Subsequently, a non-volatile physical storage device is invoked to append the logs to the corresponding storage medium segment area. After the disk appending operation of the fixed-allocation content is completed, the reserved memory-related control record table configuration field resources are released, the physical resources occupied by the corresponding structure data in the system memory paging unit are released, and the registration marker items in the control table are cleared.

[0062] After the physical train leaves the designated protected viewpoint area, computing resources need to undergo dynamic hierarchical configuration, lifecycle adjustment, control, recycling, and transfer command operations. For example... Figure 6 As shown, the dynamic scheduler is configured to retrieve the physical train schedule timetable to obtain the estimated physical train intervals for subsequent adjacent trains arriving at the monitored area after the target train has completely left the monitored area. Sensors are deployed along the external track edge to acquire detection information from the block section boundary control detection hardware. After confirming that the axle entity has crossed the boundary and exited, a section clearing status message containing control information is sent to the shared configuration information interaction port. The dynamic scheduler message listening unit, through parsing operations, determines that the position of the train's tail marker has indeed exceeded the boundary of the set target area end detection coordinate range. Upon this determination, it issues a system-level blocking control signal to the target computing power carrying node to stop the relevant inference pipeline calculations and freeze the system operation control actions.

[0063] Subsequently, the system performs dynamic network communication retrieval, reads the train command and dispatch system's business control database module through the connection data acquisition gateway, loads the configuration, and outputs a list of data related to the entire line's operation and scheduling for the day, thereby constructing the physical train dispatch timetable, and extracts snapshot file data. The system extracts the operational sequence according to the current route travel direction, reads and sorts the next-order follow-up train plans, obtains the estimated time taken for each train to cross the target defense zone boundary node, and generates the system's estimated absolute timestamp data. The system then performs a difference and subtraction operation between the planned absolute timestamp data and the currently acquired environmental baseline absolute timestamp variable to obtain the estimated physical train interval time variable parameter.

[0064] The dynamic scheduler is configured to, when determining that the estimated physical travel interval is less than a set degradation cooling threshold, control the target heterogeneous edge device to destroy the application layer's memory buffer queue and simultaneously send a memory latch instruction to the target operating system, forcing the model weight parameters to reside in the corresponding memory block. The degradation cooling threshold is a threshold value established by measuring the energy consumption of the underlying hardware system maintaining static current reserves and the time cost of the system transferring large data block requests from the hard drive to the operating computing area, and then evaluating the control. The physical derivation of this threshold is based on a break-even constraint model of underlying hardware power consumption indicators and visual network response lag. The hardware monitoring component collects the steady-state standby power consumption per second of the edge node's graphics processor maintaining chip capacitor power supply refresh in a memory page-locked state. Simultaneously, the total energy consumption of a single cold start when the storage bus is operating at full load, completely mounting the model weight file from non-volatile media to physical video memory, was calculated. And the corresponding amount of physical time consumed. The scheduler introduces a time delay penalty coefficient that characterizes the track safety tolerance. The latency penalty coefficient is forcibly converted into an equivalent energy cost for each millisecond of delay in the inference process due to cold start. The value range is calibrated between 0.05 joules / millisecond and 0.15 joules / millisecond. Its specific value is mapped to the physical line speed limit level of the monitoring zone where the target heterogeneous edge device is located: when the train speed limit in the zone is below 80 km / h, the safe tracking distance is longer. The value is 0.05; when the speed limit is between 80km / h and 120km / h, The value is set to 0.10; when the speed limit is above 120km / h, the tolerance for system cold start lag is reduced to the minimum. We directly take the extreme value of 0.15. The system performs equilibrium constraint solving based on the following equation: ; In the formula, The cooling threshold is set to be lowered. This represents the steady-state standby power consumption constant per second of the graphics processor when the video memory page is locked. This represents the total energy consumption for a single cold start. This is the delay penalty coefficient; This represents the amount of physical time required for a single cold start.

[0065] Then, the equipment baseline data is input, and the degradation cooling threshold is extracted and output. This decision equation perfectly fits the timing of resource latching and clearing actions to the actual energy consumption physical characteristics of the underlying silicon-based components and the spatiotemporal frequency of train safety tracking, completely eliminating the high-frequency abnormal overload of the system bus caused by blindly applying static keep-alive sleep time.

[0066] During the state comparison process, if the calculated physical travel interval based on the aforementioned solution parameters is found to be less than the degradation cooling threshold read from the pre-stored configuration, it is determined that the physical operation tracking object is about to arrive quickly, and there is no need to transfer the working configuration computing power. Under this condition, a control requirement command is issued to execute the node hardware-level local configuration simplification instruction package to reduce the load on the target heterogeneous edge device environment. The target computing physical hardware device performs a recycling, cleanup, and release task according to the instruction operation, releasing the memory heap segment occupied by the circular buffer pool storage area allocated by the application for video format restoration, preprocessing conversion, and creation of receiving, decoding, and saving data. At the same time, the device's underlying system registers the allocation mapping with the graphics management component responsible for the allocation configuration management of the video memory page according to the driver request, and attaches a special memory lock resident request attribute to the fixed physical display page table registration project block occupied by the corresponding storage network neural layer inference model data. This configuration changes the storage control item flag status to an internal operating system-disabled replacement flag, controlling the page scan management replacement operation component to bypass access and not execute the addressing data replacement overwrite exchange policy, thus protecting the underlying data. This avoids repeated data transmission processing requests due to interval-triggered cleanup, reducing the communication operation data stream transfer overhead that consumes time in reactivating network inference wake-up model process calls.

[0067] In scenarios involving long-term operational scheduling and shift work gaps, and when optimizing the overall resource control of the computing cluster during processing, the dynamic scheduler is further configured to issue a deep destruction command to the target heterogeneous edge device when the estimated physical travel interval is greater than or equal to the set degradation cooling threshold. During performance evaluation, if the estimated physical travel interval obtained from the above calculation is found to be equal to or far exceeds the set degradation cooling threshold constant, the system will assess the application carrying capacity loss caused by the long-term allocation of fixed hardware address reserves; subsequently, it will send the deep destruction command, containing computing power preemption and execution termination control codes, to the corresponding target node gateway via the link sender. The target heterogeneous edge device is configured to terminate the corresponding underlying inference daemon process according to the deep destruction command, triggering the operating system's garbage collection mechanism to completely clear the occupied video memory block and immediately return the corresponding computing resources to the computing resource pool. After obtaining the communication message and unpacking and reading the control field, the physical device sends a low-level operation termination command. This instruction interrupts the core clock calculation instruction sequence of the associated processing device node, terminates the deployment and occupation of the target inference daemon process, and cuts off the socket data link port. The device's underlying garbage page recycling service then gains control, releases the task record data area related to the target process management, withdraws the device physical mapping addressing operation, and unbinds the mapping pointer of the memory addressing page space. The operation processing controller directly sends management commands via the peripheral bus, notifying the physical hardware array write controller to apply a memory write reset initialization operation to the corresponding responsible area; that is, to overwrite the corresponding storage matrix block with a fixed blank value of all-zero pulse voltage, thereby completing the physical release of the occupied storage block resources. Finally, the heterogeneous device operation monitoring driver subroutine uses a scanning mechanism to update the status report of the total number of remaining idle computing cores of the physical components; the computing module summarizes and assembles the data, uploads and sends a synchronization communication packet to the resource allocation directory node statistics center of the dynamic scheduling system to update the globally shared available and idle computing scheduling database, thereby completing the closed-loop control release management operation for this batch.

[0068] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dynamic scheduling system for rail transit AI algorithm warehouses and edge nodes, characterized in that, include: Algorithm repository, a standard container image used for centralized storage of visual algorithms; An edge cluster consists of multiple heterogeneous edge devices to build a schedulable pool of computing resources; A dynamic scheduler is used to distribute the standard container image to target heterogeneous edge devices among the plurality of heterogeneous edge devices to perform inference; The verification center is used to call the large model interface to perform verification on the alarm events generated by inference; The dynamic scheduler is configured to predict the remaining span of the target train to reach the monitoring zone of the target heterogeneous edge device based on the received train physical occupancy signal, and when the remaining span is equal to or less than a set threshold, instruct the target heterogeneous edge device to load model weights into video memory to establish a silent shadow container, and activate the silent shadow container as an inference container when the target train enters the monitoring zone. The target heterogeneous edge device is configured to perform interception filtering based on the concurrent state of sudden similar alarm events triggered by the inferred container activation. When the sudden similar alarm events are detected to reach the concurrent congestion limit, all similar alarm events are aggregated into a homogeneous disturbance cluster according to the spatial intersection-union ratio and time span to intercept redundant requests. Only the target image features with the highest confidence are extracted and sent to the verification center. The device is also configured to perform batch state overwrite on all alarm events in the homogeneous disturbance cluster based on the verification conclusion returned by the verification center.

2. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The algorithm repository has built-in multi-vendor isolation engines; The multi-vendor isolation engine is configured to intercept the ingestion of standard container images with specific vendor identifiers and call the built-in scanning program to perform security vulnerability scans. It uses a namespace isolation mechanism to control the deployment of standard container images from different vendors in a completely isolated virtual runtime environment. At the underlying level, it allocates physically isolated input data mount volumes and inferred log volumes and configures directory access control permissions to prohibit cross-vendor resource access.

3. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The dynamic scheduler is equipped with a dual verification logic component for computing power. The computing power dual verification logic component is configured to extract the real-time remaining available graphics processor memory capacity of the target heterogeneous edge device before distributing the standard container image, and compare it with the minimum memory requirement parameter declared by the standard container image. When it is determined that the real-time remaining available graphics processor memory capacity is greater than or equal to the sum of the minimum memory requirement parameter and the preset fluctuation buffer capacity, the underlying distribution instruction is permitted to be issued.

4. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The dynamic scheduler is configured with a multi-algorithm logic orchestration wizard component; The multi-algorithm logic orchestration wizard component is configured to receive a parallel inference task submitted by the front end, which contains multiple independent algorithm containers, perform frame-level timestamp synchronization alignment on the alarm events output by each independent algorithm container in the multiple independent algorithm containers at different frame rates, and generate fused alarm events according to the pre-configured combined operation rules of logical AND, logical OR, or logical NOT to be collaboratively uploaded to the review center.

5. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, Each of the plurality of heterogeneous edge devices has a hardware abstraction agent deployed within it. The hardware abstraction proxy is configured to encapsulate the underlying calling interfaces of physical graphics processors, virtualized graphics processors, and tensor processors, integrating the computing units of various processors into a computing resource pool that supports dynamic allocation. The dynamic scheduler is configured to perform adaptive load balancing allocation to all computing units in the computing resource pool based on the weighted minimum connection number state and the memory fragmentation rate.

6. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The dynamic scheduler is configured to acquire the status of the train's physical occupancy section and the real-time train speed issued by the external rail transit signaling system in real time, and calculate the remaining span by combining the pre-recorded physical track topology information. When the remaining span is equal to or less than the pre-calculated extreme value of the total cold start time of the container, a preheating wake-up command is sent to the target heterogeneous edge device, so that the target heterogeneous edge device extracts the model weight file into the graphics processor's memory block, and completes the memory preemption construction of the silent shadow container.

7. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The dynamic scheduler is configured to retrieve the physical train schedule timetable to obtain the estimated physical train intervals for adjacent subsequent trains arriving at the monitoring zone after the target train has completely left the monitoring zone. When the estimated physical driving interval is determined to be less than the set degradation cooling threshold, the target heterogeneous edge device is controlled to destroy the application layer memory buffer queue, and at the same time, a video memory latch instruction is sent to the target operating system, so that the model weight parameters are forced to reside in the corresponding video memory block.

8. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 7, characterized in that, The dynamic scheduler is also configured to issue a deep destruction command to the target heterogeneous edge device when it determines that the estimated physical driving interval is greater than or equal to the set degradation cooling threshold. The target heterogeneous edge device is configured to terminate the corresponding underlying inference daemon process according to the deep destruction instruction, trigger the operating system's garbage collection mechanism to completely clear the occupied video memory block, and immediately return the corresponding computing resources to the computing resource pool.

9. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 1, characterized in that, The target heterogeneous edge device records a pixel optical flow rate of change benchmark value that characterizes the severity of image changes, and is configured to automatically intercept inference data sent to the cloud to start clustering logic when the actual optical flow rate of change in a continuous image sequence exceeds the pixel optical flow rate of change benchmark value, and the number of sudden similar alarm events generated within a specific time window reaches the concurrency congestion limit used to protect the request frequency of the large model interface. The target heterogeneous edge device calculates the spatial intersection-union ratio of each inferred detection bounding box in adjacent time periods. When the spatial intersection-union ratio is greater than the overlap determination threshold, it determines that the same source interference condition is met, and then extracts features to generate the same source perturbation cluster.

10. The dynamic scheduling system for rail transit AI algorithm warehouse and edge nodes according to claim 9, characterized in that, The target heterogeneous edge device is configured to establish a pointer mapping tracking table for the homogeneous perturbation cluster in a local memory database, and to establish a binding mapping between the unique identification code of all inferred data in the homogeneous perturbation cluster and the extracted target image features; The target heterogeneous edge device is configured to look up the pointer mapping tracking table when it receives a valid verification result or false alarm judgment result issued by the verification center, use the underlying pointer call mechanism to write the corresponding verification conclusion in batches to the status field of all inferred data with binding mapping, and perform a centralized archiving operation after completing the status transition.

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