A method for testing single power-on time of SATA hard disk

Abstract

The application discloses a kind of test methods of single power-on time of SATA hard disk, it is related to storage device performance test technical field.The method is by constructing the unified synchronous time benchmark of covering test whole process, synchronously collects the ready state signal of five levels of SATA protocol stack physical layer, link layer, transport layer, application layer and host operating system layer and corresponding effective trigger time, sets preset timing determination window with physical layer ready time as starting point, after timing window compliance and the double check of inherent power-on progressive timing of SATA protocol, mark effective ready time stamp, finally the single power-on time of measured SATA hard disk is obtained.The method eliminates the inherent synchronization deviation of multiple node acquisition from the root, restores the whole link timing of hard disk power-on completely, realizes single test, can obtain high precision, high reliability result, effectively considers test efficiency and result reliability, adapts hard disk research and development, production screening and other application scenarios, provides technical support for storage device start performance standardization test.

Description

Technical Field

[0001] This invention relates to the field of storage device performance testing technology, and in particular to a method for testing the single power-on time of a SATA hard drive. Background Technology

[0002] As one of the most widely used mainstream interfaces in the storage field, the SATA interface is widely adapted to various application scenarios such as consumer electronics, enterprise-level storage, industrial control, and cold data archiving, thanks to its good compatibility, mature deployment solutions, and controllable costs. Hard drive power-on time, which is the entire process from the issuance of the power-on enable command to the host operating system's ability to access the hard drive normally, is a universally used core performance indicator in the industry for evaluating hard drive boot performance, conducting mass production yield screening, and locating cold start failures. Its accurate and reproducible testing methods are a crucial foundational technology for the entire process of storage device R&D, production, and maintenance. Currently, most conventional power-on time testing solutions in the industry are based on SATA protocol layer status acquisition. To reduce random errors in a single test, multiple cyclic tests are typically used to take the average value to meet basic testing requirements.

[0003] In practical engineering applications, existing conventional testing solutions still have several objective limitations. In existing solutions, multi-node timing signal acquisition often uses distributed time bases, with different acquisition nodes having clocks from different sources, easily introducing inherent synchronization deviations and making it difficult to guarantee test accuracy. In batch testing, the comparability of data from different samples and rounds is insufficient. Simultaneously, existing solutions do not fully cover the signal acquisition hierarchy, failing to completely cover the entire link from physical layer initialization to the host operating system completing device mounting. Test results cannot accurately reflect the true readiness performance of the hard drive in real-world application scenarios. Furthermore, existing solutions lack a rigorous end-to-end timing compliance verification mechanism, making it difficult to effectively eliminate invalid data such as timing violations and exceeding time limits. They require numerous iterative tests to reduce the impact of outliers, resulting in low testing efficiency and making it impossible to obtain stable and effective compliance results through a single test.

[0004] To address the limitations of existing testing methods, this invention provides a method for testing the single power-on time of a SATA hard drive. By constructing a unified synchronous time benchmark throughout the entire process, it reduces the inherent synchronization deviation of multi-node data acquisition at the source, ensuring the consistency of timing data and testing accuracy throughout the process. By collecting full-link ready state data covering all four layers of the SATA protocol stack and the host operating system layer, it completely recreates the entire hard drive power-on process, ensuring that the test results closely match the actual boot performance of the hard drive. Through a dual verification mechanism of preset timing judgment window constraints and inherent power-on progressive timing verification of the SATA protocol, invalid test data is eliminated at the source, enabling compliant and reliable results to be obtained in a single test, effectively improving testing efficiency. It can be adapted to various application scenarios such as hard drive R&D performance verification, mass production batch screening, and cold start fault location. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for testing the single power-on time of a SATA hard drive, comprising the following steps: S1: Construct a unified synchronization time base for the entire process and obtain the base timestamp T1 of the power-on start time of the SATA hard drive under test; S2: Based on the aforementioned synchronization time reference, during the power-on process of the SATA hard drive under test, collect the ready status signals of the five layers of the SATA protocol stack, namely the physical layer, link layer, transport layer, application layer, and host operating system layer, as well as the effective trigger time corresponding to each layer's ready status signal. S3: Set a preset timing judgment window starting from the effective trigger time of the physical layer ready state signal; S4: When the effective trigger times of the ready status signals of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window, and the effective trigger times of the five layers strictly follow the inherent power-on progressive timing defined by the SATA protocol specification, the effective trigger time of the host operating system layer ready status signal is marked as an effective ready timestamp T2. S5: Calculate the single power-on time of the tested SATA hard drive based on the base timestamp T1 and the effective ready timestamp T2.

[0006] Preferably, the specific process of step S1 is as follows: S11: Select the master clock source and the auxiliary clock source to construct a dual-clock source synchronization verification system; S12: Perform continuous synchronous sampling on the master clock source and the auxiliary clock source, and filter out the valid sampled data that meets the preset deviation requirements; S13: Based on the effective sampled data, a unified synchronization time base is obtained for the entire process. Based on the completed synchronization time base, the power-on enable command of the SATA hard drive under test and the sampling action of the reference timestamp T1 are synchronously triggered to obtain the reference timestamp T1 at the start time of power-on of the SATA hard drive under test.

[0007] Preferably, step S2 specifically includes the following steps: S21: Based on the synchronization time reference, collect the physical layer ready state signal and the corresponding valid trigger time, and determine the validity of the physical layer ready state. S22: If the physical layer is determined to be in a valid state, the ready state signals and corresponding valid trigger times of the link layer, transport layer, and application layer are collected in sequence. Each layer must be determined to be in a valid state before the collection and determination of the next layer are performed. S23: If the application layer ready state is determined to be valid, then collect the ready state signal of the host operating system layer and the corresponding valid trigger time to complete the collection of ready state signals and valid trigger times at all levels.

[0008] Preferably, step S3 specifically includes the following steps: S31: Retrieve the predetermined timing window parameters, which are fixed duration parameters that conform to the SATA protocol specifications and are obtained based on the statistical analysis of power-on test data of a preset number of SATA hard drives of the same type. S32: Taking the effective trigger time of the physical layer ready state signal as the starting point, set a preset timing judgment window of fixed duration according to the retrieved timing window parameters. The window parameters are not dynamically adjusted during the test.

[0009] Preferably, step S4 specifically includes the following steps: S41: Verify whether the valid trigger times of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window; S42: Verify whether the effective trigger times of the five layers strictly follow the inherent power-on sequence defined by the SATA protocol specification for the physical layer, link layer, transport layer, application layer, and host operating system layer; S43: If both checks in steps S41 and S42 pass, mark the valid trigger time of the host operating system layer ready state signal as the valid ready timestamp T2; if either check fails, the test is deemed invalid and the test process is terminated.

[0010] Preferably, step S5 specifically includes the following steps: S51: Obtain the pre-calibrated system inherent delay Δt of the current test platform, wherein the system inherent delay Δt is calibrated on the current test platform using a standard SATA hard drive with a known standard power-on time; S52: Based on the baseline timestamp T1 and the effective ready timestamp T2, and combined with the inherent system delay Δt, the single power-on time of the tested SATA hard drive is calculated.

[0011] Preferably, step S5 is followed by an endogenous data closed-loop validity verification step, including: S61: Calculate the intrinsic time span ΔT between the effective triggering time of the physical layer ready state and the effective triggering time of the host operating system layer ready state in this test; S62: Retrieve the preset effective threshold range of ΔT and verify the validity of the single power-on time obtained in this test; S63: The test result is deemed valid and output only if ΔT falls within the effective threshold range; otherwise, the test result is deemed abnormal and a retest process is triggered.

[0012] Preferably, in step S22, the effective determination rule for the ready state of each level is as follows: The link layer needs to confirm that there are no SATA protocol link communication errors and complete rate negotiation and flow control initialization. The transport layer needs to confirm that there are no FIS frame transmission errors and that frame transmission, reception, and verification can be completed normally; The application layer needs to confirm that it can receive complete and valid standard ATA device identification response frames reported by the hard drive without frame transmission errors.

[0013] Preferably, the calibration step for the system's inherent delay Δt in step S5 is as follows: S501: Using a standard SATA hard drive with a known standard power-on time, repeat steps S1-S4 on the current test platform to obtain a valid reference timestamp T1 and a valid ready timestamp T2, and calculate the original power-on time test value without introducing inherent system latency compensation. No latency compensation correction is performed throughout a single test. S502: Calculate the difference between each group of valid test raw values ​​and the standard power-on time, and take the average of all differences as the system inherent delay Δt of the current test platform.

[0014] Preferably, after step S5, a multi-round test optimization step is further included, the specific process of which is as follows: S71: Repeat steps S1 to S5 to obtain multiple sets of valid test results of single power-on time of the same SATA hard drive under test, which have passed the verification in step S4. S72: Use outlier detection algorithms to remove outlier data from multiple sets of valid test results; S73: Based on the timing jitter parameters corresponding to each group of valid test results, the valid data after removing outliers are weighted and fused to obtain the final optimized test result of the single power-on time of the tested SATA hard drive.

[0015] The beneficial effects of this invention are: 1. By constructing a unified synchronous time reference covering the entire process of a single test, the power-on start time and the ready trigger time of each level of the entire link share the same source time scale, eliminating the inherent synchronization deviation caused by the decentralized time reference from the root, stably achieving microsecond-level timestamp acquisition accuracy, and ensuring that the test data of the same batch have a consistent comparison benchmark.

[0016] 2. By synchronously collecting the ready status and corresponding trigger times of five complete link layers, including the four layers of the SATA protocol stack and the host operating system layer, the actual usable power-on time of the hard drive can be accurately characterized, so that the test results are completely matched with the performance of the actual application scenario of the terminal, and fully meet the core requirements of hard drive power-on performance testing for full-link timing restoration and test results that fit the actual application.

[0017] 3. By setting a timing judgment window starting from the physical layer readiness time, and combining the dual verification mechanism of the SATA protocol's inherent power-on progressive timing, invalid data with timing out-of-range or timing violations can be directly filtered out from the data source. There is no need to rely on the processing method of taking the average of multiple loop tests. Stable and compliant valid results can be obtained in a single test, while ensuring test reliability and mass production test efficiency. This fully meets the core requirements of hard drive power-on time test for pre-control of data validity and synergistic improvement of test accuracy and efficiency. Attached Figure Description

[0018] Figure 1 A flowchart illustrating the steps of a method for testing the single power-on time of a SATA hard drive; Figure 2 This is a flowchart of the dual-clock source synchronization verification and full-process time base construction of the present invention; Figure 3 This is a flowchart of the five-level ready state acquisition steps of the present invention; Figure 4 A flowchart illustrating the steps for setting the timing determination window in this invention; Figure 5 This is a flowchart illustrating the steps of dual verification and valid ready timestamp marking in this invention. Figure 6 This is a flowchart illustrating the steps for calculating the single power-on time of the present invention. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described content is only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] The features and effects of the present invention will be further described in detail below with reference to embodiments.

[0021] In one embodiment, such as Figure 1As shown, a test method for the single power-on time of a SATA hard drive is provided. This method is based on a conventional SATA hard drive power-on test system in this field. To ensure a unified test benchmark and comparable test data across all batches, all test actions must be completed under the same test system with fixed hardware configuration, software environment, and acquisition parameters. Within a single test batch, the physical hardware connections, driver versions, operating system configurations, and signal acquisition parameters must not be changed. Specifically, the test method includes the following steps: Step S1: Construct a unified synchronization time base for the entire process and obtain the base timestamp T1 of the power-on start time of the SATA hard drive under test; Step S2: Based on the synchronization time reference, collect the ready status signals of the five layers of the SATA protocol stack during the power-on process of the tested SATA hard drive, namely the physical layer, link layer, transport layer, application layer, and host operating system layer, as well as the effective trigger time corresponding to each layer's ready status signal. Step S3: Set a preset timing determination window starting from the effective trigger time of the physical layer ready state signal; Step S4: When the effective trigger times of the ready status signals of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window, and the effective trigger times of the five layers strictly follow the inherent power-on progressive timing defined by the SATA protocol specification, the effective trigger time of the host operating system layer ready status signal is marked as an effective ready timestamp T2. Step S5: Calculate the single power-on time of the tested SATA hard drive based on the reference timestamp T1 and the valid ready timestamp T2.

[0022] In this embodiment, the unified synchronization time reference throughout the entire process refers to the unique global same source time scale that covers the entire process of this single power-on test and is shared by all timestamp acquisition nodes, ensuring that the time reference marked at all moments throughout the entire process is completely consistent. The five-level ready status signals refer to the status signals of the five core nodes covering the entire power-on startup chain of the SATA hard drive, including the four standard protocol layers of the SATA protocol stack: physical layer, link layer, transport layer, and application layer, as well as the ready nodes of the host operating system storage subsystem, which fully cover the entire process from power-on to normal access by the host. The effective trigger moment refers to the transition moment when the ready state signal of the corresponding level first stably meets the effective conditions of the protocol. All time markers are completed based on the unified synchronization time base of the whole process constructed in this embodiment. The inherent power-on sequence defined by the SATA protocol specification refers to the fixed power-on initialization sequence of the physical layer, link layer, transport layer, application layer, and host operating system layer. The preset timing judgment window refers to a timing compliance verification interval with a fixed duration, which is set in advance with the effective trigger time of the physical layer ready state signal as the starting point. It is used to constrain the reasonable range of the ready time of each layer in the upper layer.

[0023] The sampling action of the reference timestamp T1 must be triggered synchronously with the issuance of the power-on enable command of the SATA hard drive under test to ensure that there is no trigger delay deviation in the marking of the power-on start time. The acquisition of all levels of ready status signals and the marking of the corresponding valid trigger times in step S2 must be performed based on the same synchronous time reference constructed in step S1 throughout the entire process. Step S4 requires the synchronous execution of two verification logics. If both verifications pass, the valid ready timestamp T2 is marked. If any verification fails, the test is directly determined to be invalid, the test process is terminated, and the subsequent calculation stage is not entered. The calculation logic of the single power-on time in step S5 is: single power-on time of the SATA hard drive under test = valid ready timestamp T2 - reference timestamp T1.

[0024] This embodiment eliminates the inherent synchronization deviation caused by inconsistent time bases across multiple nodes by constructing a unified synchronization time base throughout the entire process, thereby improving the timestamp accuracy of a single test. By covering the full-link readiness status acquisition of all four layers of the SATA protocol stack and the host operating system layer, it completely restores the entire process from power-on triggering of the hard drive to normal accessibility by the host, solving the problems of incomplete acquisition layers and test results that cannot reflect the true readiness performance of the hard drive. Through a dual verification mechanism of preset timing judgment window constraints and inherent power-on progressive timing verification defined by the SATA protocol specification, invalid test data with timing out-of-specification or timing violations are eliminated, and the host operating system layer readiness time that conforms to the specification is marked as a valid readiness timestamp T2, solving the defects of poor reliability and many outliers in a single test. It achieves high-precision, high-reliability, and fully compliant accurate testing of the single power-on time of SATA hard drives, without relying on averaging multiple loop tests to obtain valid results, and can be directly adapted to core application scenarios such as mass production screening of hard drives, cold start fault location, and boot performance testing.

[0025] In all the following embodiments and preferred embodiments, the execution rules of steps S1 to S5, the rules for constructing and using the unified synchronization time base throughout the entire process, and the benchmark uniformity constraint requirements of the test system have been fully described in this embodiment and will not be repeated here. The test actions, time acquisition, calculation, verification, and calibration operations in all embodiments fully reuse the unified synchronization time base constructed in this embodiment, keeping the hardware configuration, software environment, and parameter settings of the test system completely consistent with this embodiment, ensuring that all test data are from the same source and comparable, and that the judgment criteria are unified.

[0026] In one embodiment, such as Figure 2 As shown, the specific process of step S1 is as follows: Step S11: Select the master clock source and the auxiliary clock source to construct a dual-clock source synchronization verification system; Step S12: Perform continuous synchronous sampling on the master clock source and the auxiliary clock source, and filter out the valid sampled data that meets the preset deviation requirements; Step S13: Based on the valid sampled data, a unified synchronization time base is obtained for the entire process. Based on the completed synchronization time base, the sampling action of the power-on enable command of the SATA hard drive under test and the reference timestamp T1 is triggered synchronously to obtain the reference timestamp T1 at the power-on start time of the SATA hard drive under test.

[0027] In this embodiment, the dual-clock source synchronous verification system refers to a dual-source clock verification architecture consisting of a master clock source and an auxiliary clock source. This architecture enables mutual verification and deviation calibration of clock references, preventing time reference inaccuracies caused by single clock source drift, failure, or system interference. The master clock source is the core reference source for the entire time stamp acquisition process, while the auxiliary clock source is an independent verification and calibration traceability reference source. The system's construction includes: the master clock source preferentially uses a hardware-level high-precision clock from the test platform host, including but not limited to a CPU-built-in high-precision clock module or a motherboard-controlled temperature-controlled crystal oscillator clock, with a timing accuracy of at least 1μs; the auxiliary clock source uses an external high-precision clock device independent of the host operating system and hardware system, including but not limited to a dedicated time stamp acquisition card or a high-bandwidth oscilloscope-built-in reference clock, with a timing accuracy of at least 100ns; the nominal frequency deviation between the master and auxiliary clock sources is controlled within ±5ppm to avoid calibration failure due to performance mismatch of the clock sources themselves.

[0028] Continuous synchronous sampling refers to the continuous, same-frequency, and same-start-point synchronous sampling of the clock output signals of the master clock source and the auxiliary clock source under the control of the same hardware trigger signal, ensuring the time comparability of the sampled data from the master and auxiliary clock sources. The execution of this sampling action includes: powering on and warming up the master clock source and auxiliary clock source before sampling, with a warm-up time of no less than 30 seconds to eliminate frequency drift during the cold start phase of the clock sources; prioritizing the use of hardware-level same-source trigger signals for synchronous sampling, avoiding pure software triggers to prevent sampling asynchrony caused by operating system scheduling delays; and conducting at least 1000 consecutive synchronous samples at a sampling frequency consistent with the nominal operating frequency of the master clock source to ensure the statistical validity of the sampled data.

[0029] The preset deviation requirement refers to the maximum allowable time deviation threshold between the synchronous sampling results of the master clock source and the auxiliary clock source, which is a core criterion for selecting valid sampled data. This requirement is set such that the maximum allowable deviation threshold is no greater than 1 μs. This threshold is set based on the microsecond-level precision requirements of SATA hard drive power-on time testing, ensuring that deviations in the clock reference do not have a perceptible impact on the final test results.

[0030] Valid sampled data refers to a qualified sampled dataset that, after continuous synchronous sampling, shows a sampling deviation between the primary and secondary clock sources that meets preset deviation requirements and can be used for subsequent time base calibration. The selection rules for this dataset are as follows: After completing continuous synchronous sampling, calculate the time deviation of the sampling results from the primary and secondary clock sources group by group, and select sampled data whose deviation values ​​do not exceed a preset threshold as valid sampled data; if the proportion of valid sampled data is lower than the preset target proportion of valid data, re-execute the clock source warm-up and continuous synchronous sampling process, and do not directly use unqualified data for time base calibration; if the proportion of valid sampled data still fails to reach the target proportion after continuously executing the resampling process to the preset upper limit of retest times, immediately terminate the current test process, and re-execute the calibration and testing process after the anomaly is resolved; for example, the preset target proportion of valid data can be set to 99.9%, and the preset upper limit of retest times can be set to 3 times.

[0031] The sampling of the reference timestamp T1 and the issuance of the power-on enable command are implemented using the hardware-level synchronous triggering method specified in the aforementioned embodiments. The host's power-on enable command output port and timestamp sampling port share the same trigger signal. The hardware delay of the trigger path does not exceed 100ns, effectively reducing the scheduling delay and time deviation caused by software triggering, ensuring accurate marking of the power-on start time, and avoiding trigger delay deviation.

[0032] The execution logic of time base calibration is as follows: Based on the filtered valid sampled data, the average time deviation of the master clock source relative to the auxiliary clock source is calculated. Using the auxiliary clock source as the traceability benchmark, deviation compensation is performed on the timing output of the master clock source. The unified synchronous time base obtained after calibration remains fixed throughout the entire power-on test process and must not be dynamically adjusted to ensure the consistency of the benchmark for all timestamps collected throughout the entire process. Clock source verification, continuous synchronous sampling and valid data filtering, and time base calibration must all be completed before the single power-on test of the SATA hard drive under test. Clock sampling and calibration operations must not be performed during the hard drive's power-on test to avoid interfering with the time base during the test process.

[0033] This embodiment solves the problems of insufficient time reference accuracy and poor stability caused by single clock source being susceptible to system interference, frequency drift, and fault inaccuracy. By constructing a dual-clock source synchronous verification system, it solves the problems of single clock source being susceptible to system interference, frequency drift, and fault inaccuracy. Through continuous synchronous sampling and effective data screening, it ensures the reliability of the sampling data used for calibration, providing a qualified data foundation for the construction of a high-precision time reference. Through hardware-level homogeneous synchronous triggering, it effectively reduces the trigger delay and reference deviation at the power-on start time, providing a stable, high-precision, and traceable global time reference for single power-on time testing, further improving the accuracy and reliability of single power-on time testing, and ensuring the homogeneity and comparability of all timestamp data throughout the process.

[0034] In a preferred embodiment, for the unified synchronization time base of the entire process after the aforementioned dual-clock source synchronization verification system is constructed, a dynamic phase drift compensation step is added to eliminate the accumulated timestamp error caused by dual-clock source phase drift and frequency offset in real time throughout the test process, further improving the acquisition accuracy of the effective trigger time at all levels. This dynamic phase drift compensation step is executed synchronously and in parallel with the aforementioned step S2 level ready state signal acquisition action. The specific steps are as follows: Step S101: During the entire power-on test of the SATA hard drive under test, continuous synchronous phase-locked sampling is performed on the main clock source and the auxiliary clock source at preset fixed time intervals. Step S102: Based on each phase-locked sampling result, calculate the phase difference and frequency deviation coefficient of the dual clock sources in real time; Step S103: Based on the phase difference and frequency deviation coefficient calculated in real time, perform dynamic phase compensation on the effective trigger times of each level collected in step S2 to eliminate the timestamp error caused by clock drift.

[0035] In this embodiment, the entire power-on test process of the SATA hard drive under test refers to the complete test cycle from the completion of the unified synchronous time base construction and the initiation of the power-on enable command of the hard drive under test in step S1, to the completion of the single power-on time calculation in step S5. This ensures that the phase-locked sampling fully covers the acquisition window of all effective trigger times at all levels, with no sampling blind spots. The preset fixed time interval refers to the pre-set time interval between two adjacent synchronous phase-locked samples. Its setting needs to match the power-on timing characteristics of the SATA hard drive under test. The interval length needs to be less than the minimum interval for power-on initialization of adjacent levels defined by the SATA protocol specification. For example, the preset fixed time interval can be set to 10μs, which ensures that the sampling density is sufficient to capture small clock drifts without bringing excessive computational load to the test system. Continuous synchronous phase-locked sampling adopts the same hardware-level same-source triggering method as the aforementioned dual-clock source refined embodiment. The sampling resolution is not lower than the timing accuracy of the auxiliary clock source, ensuring that the accuracy of the sampled data matches the performance of the clock source.

[0036] The phase difference between the two clock sources refers to the rise time difference between the clock signals of the master clock source and the auxiliary clock source at the same frequency during the same phase-locked sampling. It is a core parameter characterizing the real-time synchronization deviation of the two clock sources. The frequency deviation coefficient refers to the ratio of the actual frequency of the master clock source calculated in this phase-locked sampling to the nominal frequency, and is used to characterize the degree of real-time frequency drift of the clock source. The calculation of the phase difference and the frequency deviation coefficient must be performed immediately after each phase-locked sampling to ensure the real-time performance of the calculation results. During the calculation process, abnormal sampling data exceeding the preset deviation threshold must be removed. The preset deviation threshold is consistent with the preset deviation requirement in the aforementioned detailed embodiment of the two clock sources to ensure a unified judgment benchmark throughout the process. If the frequency deviation coefficient calculated in three consecutive phase-locked samplings exceeds the preset allowable range, the clock benchmark is directly determined to be unstable, the current test process is terminated, and a retest mechanism is triggered to prevent inaccurate data from entering the subsequent verification stage.

[0037] Dynamic phase compensation is performed point-by-point for each effective trigger moment acquired in step S2. The compensation formula is: Compensated effective trigger moment = Original effective trigger moment - Real-time phase difference - Accumulated frequency deviation error, where the accumulated frequency deviation error is calculated based on the frequency deviation coefficient and the time interval between the effective trigger moment and the completion of the synchronization time base construction. The compensation action must be completed after the effective trigger moment of the corresponding level is acquired and before entering the timing judgment window verification in step S3. The compensated effective trigger moment serves as the sole valid value for subsequent verification in steps S3 and S4 and calculation in step S5. The compensation process reuses the unified synchronization time base throughout the entire process, and the compensated value remains fixed throughout this test.

[0038] This embodiment addresses the problem that performing only one clock calibration before testing cannot eliminate real-time phase and frequency drift caused by clock source temperature drift and system electromagnetic interference during testing, leading to accumulated errors in timestamps. By adding a parallel process of dual-clock source synchronous phase-locked sampling, real-time deviation calculation, and dynamic phase compensation throughout the entire testing process, this embodiment solves the problem of accumulated errors in timestamps caused by real-time phase and frequency drift due to clock source temperature drift and system electromagnetic interference during testing, which cannot be eliminated by performing clock calibration only once before testing. Through a dynamic compensation mechanism that is synchronized and parallel with hierarchical signal acquisition, the acquisition accuracy of effective trigger times at all levels is further improved without interfering with the timing of the main testing process. This reduces testing errors in complex testing environments and enhances the adaptability and stability of this solution in harsh scenarios such as high and low temperature environment testing and long-cycle batch testing.

[0039] In one embodiment, such as Figure 3 As shown, step S2 specifically includes the following steps: Step S21: Based on the synchronization time reference, collect the physical layer ready state signal and the corresponding valid trigger time, and determine the validity of the physical layer ready state. Step S22: If the physical layer is determined to be in a valid state, the ready state signals and corresponding valid trigger times of the link layer, transport layer, and application layer are collected in sequence. Each layer must be determined to be in a valid state before the collection and determination of the next layer are performed. Step S23: If the application layer ready state is determined to be valid, then the ready state signal of the host operating system layer and the corresponding valid trigger time are collected to complete the collection of ready state signals and valid trigger times at all levels.

[0040] In this embodiment, the acquisition of all level ready status signals and the marking of effective trigger times are strictly aligned with the reference to ensure that the marking error of effective trigger times does not exceed 1μs.

[0041] The monitoring and acquisition of all levels of ready status signals are synchronized with the issuance of the power-on enable command of the SATA hard drive under test, ensuring that no transition moment of each level of ready status is missed.

[0042] The implementation rules for determining the validity of the physical layer ready state are as follows: the physical layer ready state signal is preferentially acquired by direct hardware acquisition to ensure the real-time performance of the signal acquisition; it must simultaneously meet the physical layer initialization completion standard defined by the SATA protocol specification, and there must be no abnormalities such as physical layer communication failure, clock lockout, or out-of-band signal negotiation failure, in order to be deemed valid; if it is deemed invalid, the current full-level acquisition process is terminated directly, and no further steps are required.

[0043] The specific requirements for data acquisition and judgment at the link layer, transport layer, and application layer are as follows: Data acquisition must be performed in a fixed, progressive order as defined by the SATA protocol specification. Link layer ready status signals should be acquired primarily using direct hardware acquisition to ensure real-time signal acquisition. Transport layer and application layer ready status signals can be acquired using a combination of protocol parsing methods to match the signal characteristics of the corresponding layer. After acquiring signals at each layer, the validity of the ready status at that layer must be determined first. Only when the determination is valid can the acquisition of the next layer begin. If any layer's determination is invalid, the current acquisition process must be terminated immediately.

[0044] Complete the acquisition of readiness status signals and valid trigger times across all layers. The acquisition criteria are as follows: all valid readiness status signals from the physical layer, link layer, transport layer, application layer, and host operating system layer have been acquired, along with the valid trigger time corresponding to each signal, marked with the same synchronization time base. The readiness status signals of the host operating system layer can be acquired in conjunction with the system status callback method to match the signal characteristics of the corresponding layer. If there are no missing layers or inconsistent timestamp bases, the acquisition is considered complete.

[0045] This embodiment solves the problems of invalid data redundancy and low testing efficiency caused by disordered full data collection by executing a data collection process of sequential collection at each level and determining the readiness and validity of each level. While ensuring the integrity of the full-link data collection at five levels, it can terminate invalid operations of abnormal power-on processes in advance, improve the execution efficiency of batch testing scenarios, and provide compliant and reliable basic data for subsequent timing verification and power-on time calculation.

[0046] In a preferred embodiment, the effective determination rule for the ready state at each level in step S22 is as follows: The link layer needs to confirm that there are no SATA protocol link communication errors and complete rate negotiation and flow control initialization. The transport layer needs to confirm that there are no FIS frame transmission errors and that frame transmission, reception, and verification can be completed normally; The application layer needs to confirm that it can receive complete and valid standard ATA device identification response frames reported by the hard drive without frame transmission errors.

[0047] In this preferred embodiment, the validity determination of each level must strictly follow the above rules. Only when the corresponding level meets the rule requirements at the same time is it determined to be ready and valid, and the collection process of the next level is started.

[0048] In a preferred embodiment, the acquisition of readiness status signals at each level in the aforementioned embodiments is achieved using a full-process non-intrusive passive monitoring method, specifically as follows: The physical layer ready status signal is obtained by passively polling the link negotiation of the SATA controller PHY status register, without modifying the register configuration or sending link control commands throughout the process; Readiness status signals of the link layer, transport layer, and application layer are obtained by passively listening to the hard drive actively reporting device identification FIS frames received by the SATA controller. The system does not actively send ATA identification commands to the hard drive or interfere with the hard drive initialization process. The host operating system layer acquires ready status signals by passively listening to the disk device enumeration of the system kernel, without calling active operations such as disk partition lookup or volume mounting.

[0049] In this preferred embodiment, the passive monitoring action is initiated synchronously with the issuance of the power-on enable command for the SATA hard drive under test, and the monitoring continues until the full-level signal acquisition is completed or the acquisition process termination condition is triggered, without interruption throughout the entire process.

[0050] This preferred embodiment achieves the acquisition of readiness status signals at each level through a non-intrusive passive monitoring method throughout the entire process. This solves the problem that active acquisition and active command issuance would interfere with the normal power-on initialization process of the hard drive and cause distortion of power-on time test results. The entire process does not interfere with the original power-on process of the hard drive, does not modify the hardware configuration, and does not send active control commands, completely restoring the true power-on sequence of the hard drive, further ensuring the authenticity and accuracy of the test results, and providing more reliable basic data for power-on time calculation.

[0051] In one embodiment, such as Figure 4 As shown, step S3 specifically includes the following steps: Step S31: Retrieve the predetermined timing window parameters, which are fixed duration parameters that conform to the SATA protocol specification and are obtained based on the statistical analysis of power-on test data of a preset number of SATA hard drives of the same type. Step S32: Taking the effective triggering time of the physical layer ready state signal as the starting point, set a preset timing judgment window of fixed duration according to the retrieved timing window parameters. The window parameters are not dynamically adjusted during the test.

[0052] In this embodiment, a pre-determined timing window parameter is retrieved. This timing window parameter is a fixed-duration parameter conforming to the SATA protocol specification. It needs to be determined based on the maximum allowable interval of power-on timing at each level as defined by the SATA protocol specification. The fixed duration of the parameter must completely cover the maximum allowable interval of power-on timing at all levels required by the protocol. This parameter is also a fixed-duration parameter obtained based on the statistical analysis of a preset number of power-on test data of the same type of SATA hard drives. The same type of SATA hard drives refers to SATA hard drives with the same interface version, capacity specification, and main controller scheme. The preset number can be set to no less than 100 sets of valid power-on test data. The timing window parameter must be pre-determined before the power-on test of the SATA hard drive under test. Parameter statistics, calculations, and adjustments must not be performed during the power-on test of the hard drive. For the same type of SATA hard drives in a single test batch, the same set of pre-determined timing window parameters is retrieved.

[0053] The specific rules for setting a fixed-duration preset timing determination window are as follows: the effective trigger time of the physical layer ready state signal must be the sole time starting point, and the time base cannot be changed or the starting time adjusted; the fixed-duration preset timing determination window must be set strictly according to the retrieved timing window parameters, and the window duration must be completely consistent with the fixed duration of the timing window parameters. Throughout the entire process of a single hard drive power-on test, the duration and start and end times of the preset timing determination window remain fixed, and the parameters cannot be modified midway.

[0054] This embodiment solves the problems of inconsistent timing verification standards and poor comparability of test results caused by dynamically adjusting windows and lacking a unified judgment benchmark by retrieving timing window parameters and setting a fixed-duration preset timing judgment window. By strictly following the requirements of fixed parameters and fixed time start, it ensures that the judgment benchmark for power-on time testing of hard drives in the same batch is consistent, providing a unified and compliant judgment benchmark for subsequent timing compliance verification.

[0055] In one embodiment, such as Figure 5 As shown, step S4 specifically includes the following steps: Step S41: Verify whether the valid trigger times of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window; Step S42: Verify whether the effective trigger times of the five layers strictly follow the inherent power-on progression sequence defined by the SATA protocol specification for the physical layer, link layer, transport layer, application layer, and host operating system layer. Step S43: If both checks in steps S41 and S42 pass, mark the valid trigger time of the host operating system layer ready state signal as the valid ready timestamp T2; if either check fails, the test is deemed invalid and the test process is terminated.

[0056] In this embodiment, all verification actions must follow general execution rules: verification must be initiated after the preset timing judgment window is completely closed and all valid trigger times of the five levels have been collected. It must not be executed prematurely within the window's valid period to avoid distortion of verification results due to incomplete collection of valid trigger times at each level; verification must be based on the corresponding level's valid trigger times collected in real time during this hard drive power-on test, and data collected from other hard drives or other test batches must not be mixed; throughout the entire verification process, the collected valid trigger time values ​​must not be modified to ensure a unified verification benchmark and accurate and objective results.

[0057] Timing window compliance verification refers to the compliance verification action performed on whether the valid trigger times of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing judgment window. It is the first layer of screening rules for the validity of the test data, and its core function is to eliminate abnormal layer trigger data that exceeds the protocol's allowed timing range. The execution of this verification action includes: verifying the valid trigger times of the four layers (link layer, transport layer, application layer, and host operating system layer) one by one, without omitting any layer; the valid trigger time of each layer must simultaneously meet the condition of being later than the start time of the preset timing judgment window and earlier than the end time of the preset timing judgment window in order to be judged as passing the verification for that layer; the start and end times and duration parameters of the preset timing judgment window cannot be adjusted throughout the verification process; if the valid trigger time of any layer does not fall within the preset timing judgment window, the entire verification is judged as failing.

[0058] The power-on progressive timing compliance check refers to the compliance check action performed on whether the effective trigger times of the five layers strictly follow the inherent power-on progressive timing of the physical layer, link layer, transport layer, application layer, and host operating system layer defined by the SATA protocol specification. It is the second layer of filtering rules for the validity of the test data. Its core function is to remove abnormal data with reversed timing or that does not conform to the hard drive power-on initialization logic. The execution of this verification action includes: strictly following the fixed order of the physical layer, link layer, transport layer, application layer, and host operating system layer defined by the SATA protocol specification, performing timing comparisons on the effective trigger times of adjacent layers one by one, without skipping any set of adjacent layer comparisons; the judgment criteria for timing comparison are: the effective trigger time of the later layer must be strictly later than the effective trigger time of the earlier layer, and there must be no reversal or overlap of timings in order to determine that the comparison is passed; only when all adjacent layer timing comparisons are passed can this verification be determined to be passed as a whole; if any set of adjacent layer timing comparisons fails, this verification is determined to be failed as a whole; the inherent power-on progressive timing defined by the SATA protocol specification is completely consistent with the layer order from the physical layer to the host operating system layer specified in this embodiment, which meets the layer progressive requirements for hard disk power-on initialization in the SATA protocol specification.

[0059] The marking rules for the valid ready timestamp T2 are as follows: the marking action can only be performed when both checks in steps S41 and S42 are deemed to have passed; the value of T2 must be completely consistent with the valid trigger time of the host operating system layer ready state signal collected in this test, and the time value must not be modified or adjusted; the marked T2 remains fixed throughout the entire test process.

[0060] If any check fails, the test is deemed invalid and a valid ready timestamp T2 must not be generated. After being deemed invalid, the entire test process must be terminated immediately, and no subsequent actions related to the calculation of the power-on time must be performed. A single invalid test only invalidates the power-on result of this test and does not affect the execution of subsequent new hard drive power-on test processes.

[0061] This embodiment addresses the issues of distorted power-on time test results and invalid data mixed into the final statistical results caused by single-level timing anomalies and reversed power-on timing, through a dual verification mechanism of timing window compliance and power-on progressive timing compliance. Strict dual verification pass rules and an invalid test termination mechanism ensure the compliance and accuracy of valid ready timestamps, eliminating distorted and invalid test results from the data source. This improves the reliability of single power-on time test results for SATA hard drives and the effectiveness of batch testing, providing a qualified and compliant data foundation for accurate calculation of subsequent power-on times.

[0062] In a preferred embodiment, a three-level dynamic linkage calibration step for timing thresholds—physical layer, protocol layer, and operating system layer—is added between steps S3 and S4. This step is used to adapt to differences in physical layer link negotiation among different hard drives, reduce the false judgment rate of timing verification in batch testing scenarios, and improve the batch adaptability of the solution. The three-level dynamic linkage calibration step for timing thresholds specifically includes: Step S301: Based on the effective triggering time of the physical layer ready state signal, calculate the timing deviation between the actual physical layer link negotiation time and the reference negotiation time. Step S302: Based on the timing deviation value, synchronously and dynamically calibrate the protocol layer effective trigger condition response time threshold and the operating system layer effective trigger condition timing judgment boundary within the preset timing judgment window; Step S303: Based on the calibrated threshold and boundary, execute the valid trigger time verification logic of step S4.

[0063] In this preferred embodiment, the physical layer link negotiation timing deviation value refers to the difference between the actual negotiation time of the tested hard drive and the preset benchmark negotiation time, calculated based on the actual collected data of the physical layer ready state. It is the core calculation basis for subsequent threshold dynamic calibration. The calculation rules for this deviation value include: the benchmark negotiation time is a predetermined standard time for physical layer link negotiation of the same type of SATA hard drives, determined based on the average value of the batch power-on measured data of the same type of hard drives; the actual physical layer link negotiation time is the time interval from the time the power-on enable command of the tested hard drive is issued to the time when the physical layer ready state signal is effectively triggered, calculated based on the aforementioned unified synchronization time benchmark; the timing deviation value = actual physical layer link negotiation time - benchmark negotiation time, and the calculation result retains the positive and negative signs, divided into positive deviation (actual time is greater than benchmark time, and the calculation result is positive) and negative deviation (actual time is less than benchmark time, and the calculation result is negative).

[0064] In this preferred embodiment, synchronous dynamic calibration refers to performing simultaneous and proportional adjustments on the response time threshold of the effective triggering condition of the protocol layer and the timing judgment boundary of the effective triggering condition of the operating system layer, based on the timing deviation value. The adjustment range is equal to the timing deviation value multiplied by a preset calibration coefficient. The preset calibration coefficient is determined in advance based on batch test data of the same type of hard drives, with a value range of 0.8-1.2. This avoids over-calibration that could lead to inaccurate verification standards, while fully covering the individual timing differences of the same type of hard drives. This ensures that the adjusted thresholds and boundaries accurately adapt to the timing offset of individual hard drives, guaranteeing the consistency and rigor of the verification logic. The implementation rules for this calibration action include: dynamic calibration can only be performed if the timing deviation value is within the preset allowable deviation range. The preset allowable deviation range is determined in advance based on the maximum allowable time for physical layer link negotiation as defined by the SATA protocol specification. For example, the maximum allowable deviation does not exceed ±20% of the maximum physical layer negotiation time specified by the protocol. If the timing deviation value exceeds the preset allowable deviation range, the test is directly deemed invalid, the process is terminated, and no subsequent calibration and verification actions are performed. The adjustment ratio of dynamic calibration is positively correlated with the timing deviation value. The threshold and boundary after calibration must not exceed the start and end range of the preset timing judgment window set in step S3 above, nor break through the power-on timing boundary defined by the SATA protocol specification. If the calibration exceeds any of the above constraints, the test is directly deemed invalid, the process is terminated, and no subsequent verification actions are performed. The calibration action must be completed before the verification logic in step S4 above is executed, and the threshold and boundary after calibration remain fixed throughout the entire verification process.

[0065] In this preferred embodiment, the effective trigger condition response time limit of the protocol layer refers to the latest allowed time limit for the effective triggering time of each layer of the link layer, transport layer, and application layer within the preset timing judgment window; the effective trigger condition timing judgment boundary of the operating system layer refers to the latest allowed time limit for the effective triggering time of the host operating system layer within the preset timing judgment window; both are layer check sub-thresholds within the preset timing judgment window, and after calibration, they must not exceed the start and end boundaries of the window.

[0066] In this preferred embodiment, the timing window compliance verification and power-on progressive timing compliance verification in step S4 are both performed based on the thresholds and boundaries after this calibration, and the original verification rules, judgment logic, and invalid termination mechanism remain unchanged.

[0067] This preferred embodiment adds a process of calculating the physical layer negotiation time deviation and calibrating the threshold linkage between the protocol layer and the operating system layer. Without disrupting the core logic of the original solution's fixed timing benchmark and unified verification rules, it achieves dynamic adaptation to the power-on timing differences of different hard drives. This effectively reduces the timing verification misjudgment rate of normal individual hard drives in batch testing scenarios, further improving the batch adaptability and testing stability of the solution. At the same time, through the rigid boundary constraints of the calibration range, it avoids the problems of inconsistent verification standards and incomparable test results caused by dynamic adjustments, and is fully compatible with the core invention purpose of the original solution.

[0068] In one embodiment, such as Figure 6 As shown, step S5 specifically includes the following steps: Step S51: Obtain the pre-calibrated system inherent delay Δt of the current test platform. The system inherent delay Δt is obtained by calibrating the current test platform using a standard SATA hard drive with a known standard power-on time. Step S52: Based on the reference timestamp T1 and the effective ready timestamp T2, and combined with the inherent system delay Δt, the single power-on time of the tested SATA hard drive is calculated.

[0069] In this embodiment, the inherent system latency Δt refers to the sum of fixed delays introduced by the current test platform's hardware links, software drivers, and operating system environment, which are unrelated to the power-on performance of the SATA hard drive under test itself. It is the core compensation parameter for eliminating test system errors and restoring the true power-on time of the hard drive. The core implementation rules for obtaining and calibrating this parameter include: the calibration must be completed before the batch testing of the hard drives under test; recalibration is required after changes to the hardware and software configuration of the test platform; the standard SATA hard drive used for calibration must have the same interface version and main control scheme as the hard drive under test, and the standard power-on time must have a traceable calibration value; the same set of calibrated Δt parameters must be reused for hard drives of the same type within a single test batch, and must not be modified midway.

[0070] The single power-on time of the tested SATA hard drive refers to the actual time taken from power-on to the host operating system's recognition and mounting of the hard drive after system inherent latency compensation correction. This is the core output of this test. The calculation rules for this parameter include: the formula for calculating the single power-on time T is: T = T2 - T1 - Δt; the calculation is only performed if T1 and T2 are valid flag values ​​that have passed the aforementioned steps and Δt has been pre-calibrated; any invalid parameter will render the test invalid and no calculation result should be generated; the calculated value is fixed throughout the entire test process and cannot be modified.

[0071] This embodiment solves the problem of distorted test results and inability to restore the true performance of the hard drive caused by inherent errors in the test platform by using standard hard drive pre-calibration system latency and dual timestamps combined with latency compensation calculation logic, thus ensuring the authenticity and reliability of power-on time test results.

[0072] In a preferred embodiment, the calibration step of the system's inherent delay Δt in step S5 specifically includes: Step S501: Using a standard SATA hard drive with a known standard power-on time, repeat steps S1-S4 on the current test platform to obtain a valid reference timestamp T1 and a valid ready timestamp T2, and calculate the original power-on time test value without introducing inherent system delay compensation. No delay compensation correction is performed throughout the entire test. Step S502: Calculate the difference between each group of valid test raw values ​​and the standard power-on time, and take the average of all differences as the system inherent delay Δt of the current test platform.

[0073] In this preferred embodiment, the original power-on time test value refers to the actual total time calculated directly from T2 and T1 without delay compensation. The acquisition implementation rules include: the calibration test process, parameters, ambient temperature, and platform preheating status, which are completely consistent with the subsequent hard drive test. For example, the calibration test is repeated no less than 50 times, and the hard drive power-on and power-off and time reference calibration are re-executed for each test to eliminate heat accumulation and interference from continuous testing.

[0074] In this preferred embodiment, the rules for determining the inherent system latency Δt include: after completing the full calibration test, removing abnormal difference data that exceed the average test value of a single standard hard disk ±3σ (3 times the standard deviation), and taking the arithmetic mean of the remaining valid data as the final Δt; the Δt parameter after calibration is strictly executed in accordance with the general calibration rules in the aforementioned main embodiment.

[0075] This preferred embodiment further reduces the random error of a single calibration by using a calibration method that involves full-process closed-loop reproduction and statistical filtering of multiple sets of data, thereby improving the calibration accuracy of the system's inherent delay and optimizing the accuracy of power-on time testing from the source.

[0076] In a preferred embodiment, after step S5 completes the calculation of the single power-on time, the following SATA protocol compliance linkage verification step is added, specifically: Step S511: Extract timing parameters of physical layer link negotiation time, protocol layer initialization time, and total power-on time obtained from the test. Step S512: Compare the extracted timing parameters with the power-on timing compliance threshold range specified by the SATA protocol item by item; Step S513: Automatically identify non-compliant timing items that exceed the protocol specifications and generate a SATA protocol compliance test report containing compliance judgment results, non-compliant item locations, and timing deviation data.

[0077] In this preferred embodiment, the physical layer link negotiation time refers to the interval between the power-on enable issuance time and the effective triggering time of the physical layer readiness; the protocol layer initialization time refers to the time interval between the link layer readiness and the application layer readiness; and the total power-on time refers to the single power-on time of the tested hard disk calculated in this instance. The parameter extraction implementation rules include: the extraction action is performed after the single power-on time calculation is completed and before the next test starts, and must not interfere with the main test process.

[0078] In this preferred embodiment, the power-on timing compliance threshold range specified by the SATA international protocol refers to the maximum allowable power-on time at each level as specified in the SATA specification corresponding to the interface version of the hard drive under test. The compliance comparison rules include: timing parameters that do not exceed the threshold are considered compliant, and those that exceed the threshold are considered non-compliant. A unified threshold standard is used throughout the comparison.

[0079] In this preferred embodiment, the generation rules for the SATA protocol compliance test report include: the report must clearly state the information of the hard drive under test, the test platform information, and the overall compliance judgment result; for non-compliant items, the measured value, compliance threshold, and deviation amount should be marked; and the T1, T2, and power-on time calculation results of this test should be synchronously associated to achieve linkage and traceability between test data and compliance results.

[0080] This preferred embodiment simultaneously achieves automatic detection and anomaly location of protocol compliance for power-on timing without interfering with the main testing process, expands the batch testing functionality of the solution, eliminates the need to build an additional compliance testing platform, and improves the execution efficiency of mass production testing scenarios.

[0081] In one embodiment, step S5 is followed by an endogenous data loop closure validity verification step, including: Step S61: Calculate the intrinsic time span ΔT between the effective triggering time of the physical layer ready state and the effective triggering time of the host operating system layer ready state in this test. Step S62: Retrieve the preset effective threshold range of ΔT and verify the validity of the single power-on time obtained in this test; Step S63: If ΔT falls within the effective threshold range, the test result is determined to be valid and output; otherwise, the test result is determined to be abnormal and a retest process is triggered.

[0082] In this test, the intrinsic time span ΔT between the effective trigger time of the physical layer ready state and the effective trigger time of the host operating system layer ready state refers to the end-to-end intrinsic time from the completion of the hard disk physical layer initialization to the completion of the host operating system's recognition and mounting, calculated based on the original data collected in this test. It is the core calculation parameter for verifying the validity of this test, and its calculation formula is ΔT = effective trigger time of the host operating system layer ready state in this test - effective trigger time of the physical layer ready state in this test. Both times used in the calculation are original valid values ​​collected during this test and verified by the aforementioned steps. The calculation action is executed immediately after the single power-on time calculation is completed in step S5, without interfering with the storage of the original test results.

[0083] The preset effective threshold range of ΔT refers to the upper and lower limits of the pre-set thresholds used to verify the validity of the single power-on time obtained in this test. It is the core judgment benchmark of this closed-loop verification. Its upper limit shall not exceed the fixed duration of the timing window parameter retrieved in the aforementioned step S3. The lower limit is determined based on the minimum reasonable time consumption of the entire link in the actual power-on test of the same type of SATA hard drives. The threshold range is matched with the interface version and main control scheme of the SATA hard drive under test. The same set of threshold ranges is retrieved for the same type of hard drives in a single test batch. After the setting is completed, no dynamic adjustment is made during the test.

[0084] The validity of the single power-on time obtained in this test is verified. The sole criterion is whether ΔT falls within the preset effective threshold range of ΔT. Only when the intrinsic time span ΔT simultaneously meets the conditions of being greater than or equal to the lower limit of the effective threshold range and less than or equal to the upper limit of the effective threshold range, is the test result deemed valid and the single power-on time calculated in step S5 is output. If ΔT does not fall within the effective threshold range, the test result is directly deemed abnormal and the original calculation result should not be output.

[0085] Triggering the retest process means that when the test result is abnormal, the complete power-on test process of steps S1 to S5 mentioned above will be re-executed. For example, the number of retests for a single test is preset to no more than 3 times. If the test fails for 3 consecutive times, the test will be terminated and a hardware fault warning will be output to avoid invalid loop testing.

[0086] This embodiment uses the end-to-end time span verification of the endogenous data in this test to form a triple closed-loop verification system with the dual timing verification in step S4 above. This solves the problem that relying solely on independent hierarchical verification cannot identify end-to-end timing anomalies and invalid result outputs caused by incorrect timestamp marking. It can complete the self-closed-loop validity verification of the test results without introducing external parameters, further improving the reliability of the single power-on time test results.

[0087] In one embodiment, step S5 is followed by a multi-round test optimization step, the specific process of which is as follows: Step S71: Repeat steps S1 to S5 to obtain multiple sets of valid test results of single power-on time of the same SATA hard drive that have passed the verification in step S4. Step S72: Use an outlier detection algorithm to remove outlier data from multiple sets of valid test results; Step S73: Based on the timing jitter parameters corresponding to each group of valid test results, the valid data after removing outliers is weighted and fused to obtain the final optimized test result of the single power-on time of the tested SATA hard drive.

[0088] In this embodiment, steps S1 to S5 are repeated to obtain multiple sets of valid single power-on time test results of the same SATA hard drive under test, which have passed the verification in step S4. This means that multiple independent and complete power-on tests are performed on the same hard drive under test. The number of complete test rounds is no less than 10. Each round of testing independently completes the hard drive power-on and power-off operations, synchronous time base calibration, full-level signal acquisition, timing verification, and power-on time calculation. Data collected in previous rounds cannot be reused. Only test results from previous rounds that have passed the double verification in step S4 and have not been determined to be invalid can be included in the valid test result dataset. The interval between each round of testing is no less than 30 seconds to eliminate the interference of hard drive heat accumulation effect on the test results during continuous testing.

[0089] Outlier detection algorithms are used to remove outlier data from multiple sets of valid test results. This involves filtering the data from the multiple sets of valid test results. For example, the 3-standard-deviation criterion or Grubbs' test algorithm, which are suitable for small-sample, multi-round testing scenarios, can be used to calculate the arithmetic mean and standard deviation of the multiple sets of valid test results. Test results that exceed the range of the mean ± 3 standard deviations are identified as outlier data and removed. After removing outlier data, the amount of remaining valid data should not be less than 80% of the original test rounds. Otherwise, the multi-round testing process must be repeated. Unqualified datasets should not be used directly for subsequent calculations.

[0090] Based on the timing jitter parameters corresponding to each group of valid test results, the valid data after removing outliers are weighted and fused to obtain the final optimized test result of the single power-on time of the tested SATA hard drive. The weighted calculation is based on the timing jitter parameters, which are the actual interval values ​​of the effective trigger times of adjacent layers in each test group, and the relative deviation from the standard layer interval values ​​of the same type of SATA hard drive. The smaller the relative deviation, the smaller the timing jitter, and the higher the weight value of the test result of that group. The sum of the weight values ​​of all valid data is 1. The final optimized test result is the sum of the products of each group of valid test results and their corresponding weight values. The calculated final optimized test result is the final output data of this test, which remains fixed throughout the entire test process and cannot be modified twice.

[0091] This embodiment addresses the problem of large random errors in single tests and the inability to accurately characterize the steady-state power-on performance of hard drives by optimizing the entire process through multiple rounds of independent repeated testing, outlier removal, and timing jitter weighted fusion. By replacing the traditional arithmetic mean calculation method with weighted fusion based on endogenous timing jitter parameters, it further improves the accuracy and anti-interference ability of test results, providing reliable data support for high-precision quantitative evaluation of hard drive power-on performance and batch performance grading.

[0092] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for testing the single power-on time of a SATA hard drive, characterized in that, Includes the following steps: S1: Construct a unified synchronization time base for the entire process and obtain the base timestamp T1 of the power-on start time of the SATA hard drive under test; S2: Based on the aforementioned synchronization time reference, during the power-on process of the SATA hard drive under test, collect the ready status signals of the five layers of the SATA protocol stack, namely the physical layer, link layer, transport layer, application layer, and host operating system layer, as well as the effective trigger time corresponding to each layer's ready status signal. S3: Set a preset timing judgment window starting from the effective trigger time of the physical layer ready state signal; S4: When the effective trigger times of the ready status signals of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window, and the effective trigger times of the five layers strictly follow the inherent power-on progressive timing defined by the SATA protocol specification, the effective trigger time of the host operating system layer ready status signal is marked as an effective ready timestamp T2. S5: Calculate the single power-on time of the tested SATA hard drive based on the base timestamp T1 and the effective ready timestamp T2.

2. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, The specific process of step S1 is as follows: S11: Select the master clock source and the auxiliary clock source to construct a dual-clock source synchronization verification system; S12: Perform continuous synchronous sampling on the master clock source and the auxiliary clock source, and filter out the valid sampled data that meets the preset deviation requirements; S13: Based on the effective sampled data, a unified synchronization time base is obtained for the entire process. Based on the completed synchronization time base, the power-on enable command of the SATA hard drive under test and the sampling action of the reference timestamp T1 are synchronously triggered to obtain the reference timestamp T1 at the start time of power-on of the SATA hard drive under test.

3. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, Step S2 specifically includes the following steps: S21: Based on the synchronization time reference, collect the physical layer ready state signal and the corresponding valid trigger time, and determine the validity of the physical layer ready state. S22: If the physical layer is determined to be in a valid state, the ready state signals and corresponding valid trigger times of the link layer, transport layer, and application layer are collected in sequence. Each layer must be determined to be in a valid state before the collection and determination of the next layer are performed. S23: If the application layer ready state is determined to be valid, then collect the ready state signal of the host operating system layer and the corresponding valid trigger time to complete the collection of ready state signals and valid trigger times at all levels.

4. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, Step S3 specifically includes the following steps: S31: Retrieve the predetermined timing window parameters, which are fixed duration parameters that conform to the SATA protocol specifications and are obtained based on the statistical analysis of power-on test data of a preset number of SATA hard drives of the same type. S32: Taking the effective trigger time of the physical layer ready state signal as the starting point, set a preset timing judgment window of fixed duration according to the retrieved timing window parameters. The window parameters are not dynamically adjusted during the test.

5. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, Step S4 specifically includes the following steps: S41: Verify whether the valid trigger times of the link layer, transport layer, application layer, and host operating system layer all fall within the preset timing determination window; S42: Verify whether the effective trigger times of the five layers strictly follow the inherent power-on sequence defined by the SATA protocol specification for the physical layer, link layer, transport layer, application layer, and host operating system layer; S43: If both checks in steps S41 and S42 pass, mark the valid trigger time of the host operating system layer ready state signal as the valid ready timestamp T2; if either check fails, the test is deemed invalid and the test process is terminated.

6. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, Step S5 specifically includes the following steps: S51: Obtain the pre-calibrated system inherent delay Δt of the current test platform, wherein the system inherent delay Δt is calibrated on the current test platform using a standard SATA hard drive with a known standard power-on time; S52: Based on the baseline timestamp T1 and the effective ready timestamp T2, and combined with the inherent system delay Δt, the single power-on time of the tested SATA hard drive is calculated.

7. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, The step S5 is followed by an endogenous data closed-loop validity verification step, including: S61: Calculate the intrinsic time span ΔT between the effective triggering time of the physical layer ready state and the effective triggering time of the host operating system layer ready state in this test; S62: Retrieve the preset effective threshold range of ΔT and verify the validity of the single power-on time obtained in this test; S63: The test result is deemed valid and output only if ΔT falls within the effective threshold range; otherwise, the test result is deemed abnormal and a retest process is triggered.

8. The method for testing the single power-on time of a SATA hard drive according to claim 3, characterized in that, In step S22, the valid determination rule for the ready state at each level is as follows: The link layer needs to confirm that there are no SATA protocol link communication errors and complete rate negotiation and flow control initialization. The transport layer needs to confirm that there are no FIS frame transmission errors and that frame transmission, reception, and verification can be completed normally; The application layer needs to confirm that it can receive complete and valid standard ATA device identification response frames reported by the hard drive without frame transmission errors.

9. The method for testing the single power-on time of a SATA hard drive according to claim 6, characterized in that, The calibration steps for the system's inherent delay Δt in step S5 are as follows: S501: Using a standard SATA hard drive with a known standard power-on time, repeat steps S1-S4 on the current test platform to obtain a valid reference timestamp T1 and a valid ready timestamp T2, and calculate the original power-on time test value without introducing inherent system latency compensation. No latency compensation correction is performed throughout a single test. S502: Calculate the difference between each group of valid test raw values ​​and the standard power-on time, and take the average of all differences as the system inherent delay Δt of the current test platform.

10. The method for testing the single power-on time of a SATA hard drive according to claim 1, characterized in that, Following step S5, multiple rounds of testing and optimization steps are included, the specific process of which is as follows: S71: Repeat steps S1 to S5 to obtain multiple sets of valid test results of single power-on time of the same SATA hard drive under test, which have passed the verification in step S4. S72: Use outlier detection algorithms to remove outlier data from multiple sets of valid test results; S73: Based on the timing jitter parameters corresponding to each group of valid test results, the valid data after removing outliers are weighted and fused to obtain the final optimized test result of the single power-on time of the tested SATA hard drive.

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