Processor testing system and processor testing apparatus

Abstract

The application discloses a processor test system and a processor test device, and relates to the technical field of processor testing.The system comprises a plurality of test bearing modules, a resource expansion module and at least one PCIe test module;each test bearing module is connected with the resource expansion module, the resource expansion module is connected with the PCIe test module;the test bearing module is used for bearing a processor under test, receiving a PCIe test signal generated by the processor under test, and transmitting the PCIe test signal to the resource expansion module;the resource expansion module is used for receiving the PCIe test signal and routing the PCIe test signal to the PCIe test module;and the PCIe test module is used for performing a test operation on the processor under test according to the PCIe test signal.Compared with the prior art, the application connects a plurality of test bearing modules with at least one PCIe test module by introducing a resource expansion module, so that the plurality of processors under test share the PCIe test module, and the hardware cost of the test system is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor testing, and particularly relates to a processor testing system and a processor testing device. BACKGROUND

[0002] System-level testing (SLT) of a server CPU is a key link in a mass production stage, and PCIe interface performance testing is particularly important. A current mainstream testing scheme adopts a "one-to-one" direct connection architecture, that is, each CPU to be tested on each testing single board needs to be independently configured with a complete PCIe testing device (such as an NVMe SSD). Under this architecture, the number of PCIe devices purchased is linearly proportional to the testing scale.

[0003] However, this high-cost hardware investment brings significant problems in mass production testing: the high-performance PCIe device is high in unit price, which causes the hardware cost of the testing environment to sharply rise with the capacity demand. Meanwhile, a large number of devices have a high failure rate in high-load testing, which further increases the maintenance overhead and testing interruption risk.

[0004] Therefore, how to reduce the PCIe device hardware cost in SLT testing is a problem to be solved. SUMMARY

[0005] The main purpose of the present application is to provide a processor testing system and a processor testing device, aiming to solve the technical problem of how to reduce the PCIe device hardware cost in SLT testing.

[0006] To achieve the above-mentioned purpose, the present application provides a processor testing system, which comprises: a plurality of testing bearing modules, a resource expansion module and at least one PCIe testing module; Each of the testing bearing modules is connected with the resource expansion module, and the resource expansion module is connected with the PCIe testing module; The testing bearing module is configured to bear a processor to be tested, receive a PCIe testing signal generated by the processor to be tested, and transmit the PCIe testing signal to the resource expansion module; The resource expansion module is configured to receive the PCIe testing signal and route the PCIe testing signal to the PCIe testing module; The PCIe testing module is configured to perform a testing operation on the processor to be tested according to the PCIe testing signal.

[0007] In an embodiment, the testing bearing module comprises a testing bearing board and a connecting cable. The testing bearing board is connected with the resource expansion module through the connecting cable; The test support board is used to support the processor under test; The connection cable is used to connect the PCIe port of the processor under test to the resource expansion module.

[0008] In one embodiment, the resource expansion module includes: a PCIe expansion board and a PCIe switching unit disposed on the PCIe expansion board; The PCIe switching unit is disposed on the PCIe expansion board, and the PCIe expansion board is connected to the test bearer module and the PCIe test module respectively through the PCIe switching unit; The PCIe expansion board is used to carry the PCIe switching unit; The PCIe switching unit is used to receive PCIe test signals and route the PCIe test signals to the PCIe test module.

[0009] In one embodiment, the resource expansion module further includes: a firmware configuration unit and a resource partition storage unit; The firmware configuration unit is connected to the PCIe switching unit and the resource partition storage unit, respectively. The firmware configuration unit is used to configure the resource partitioning of the PCIe switching unit; The resource partition storage unit is used to store the configuration information of the resource partition. The configuration information is used to divide the downlink port of the PCIe switching unit into multiple logical resource areas corresponding to each of the processors under test.

[0010] In one embodiment, the PCIe switching unit includes: a plurality of uplink ports, a plurality of downlink ports, a signal routing subunit, and a hardware isolation subunit; The signal routing subunit is connected to each of the uplink ports, the hardware isolation subunit, and the resource partition storage unit, respectively; the hardware isolation subunit is connected to each of the downlink ports. The uplink port is used to receive the PCIe test signal; The signal routing subunit is used to obtain the configuration information from the resource partition storage unit and send the PCIe test signal to the corresponding hardware isolation subunit according to the configuration information. The hardware isolation subunit is used to isolate PCIe test signals belonging to different logical resource regions and send the isolated PCIe test signals to the corresponding downlink ports. The downlink port is used to output the PCIe test signal to the PCIe test module.

[0011] In one embodiment, the PCIe test module includes: a storage device provided with a PCIe interface; The storage device is connected to the resource expansion module; The storage device is used to perform data write operations or data read operations based on the PCIe test signal.

[0012] In one embodiment, the PCIe testing module includes: a network device equipped with a PCIe interface; The network device is connected to the resource expansion module; The network device is used to perform data transmission or data reception operations based on the PCIe test signal.

[0013] In one embodiment, the system further includes: a test control module; The test control module is connected to the resource expansion module and each of the test carrier modules respectively; The test control module is used to control the power-on timing of the processor under test on each of the test carrier modules; The test control module is also used to initialize and configure the resource expansion module.

[0014] In one embodiment, the test bearer module further includes: a fault reporting unit; The fault reporting unit is connected to the processor under test; The fault reporting unit is used to collect PCIe error information of the processor under test and report the PCIe error information to an external terminal.

[0015] In addition, to achieve the above objectives, this application also proposes a processor testing device, which includes the processor testing system described above.

[0016] This application proposes a processor testing system, comprising: a plurality of test carrier modules, a resource expansion module, and at least one PCIe test module; each of the test carrier modules is connected to the resource expansion module, and the resource expansion module is connected to the PCIe test module; the test carrier module is used to carry the processor under test, receive the PCIe test signal generated by the processor under test, and then transmit the PCIe test signal to the resource expansion module; the resource expansion module is used to receive the PCIe test signal and route the PCIe test signal to the PCIe test module; the PCIe test module is used to perform test operations on the processor under test according to the PCIe test signal.

[0017] This application includes a processor testing system within a processor testing device. This system comprises: several test carrier modules, a resource expansion module, and at least one PCIe test module. Each test carrier module is connected to a resource expansion module, which in turn is connected to the PCIe test module. The test carrier modules carry the processor under test (DUT), receive PCIe test signals generated by the DUT, and then transmit the PCIe test signals to the resource expansion modules. The resource expansion modules receive the PCIe test signals and route them to the PCIe test module. The PCIe test module performs test operations on the DUT based on the PCIe test signals. Compared to existing methods, this application introduces a resource expansion module to connect multiple test carrier modules to at least one PCIe test module, thereby enabling multiple DUTs to share the PCIe test module and reducing the hardware cost of the testing system. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the first embodiment of the processor testing system proposed in this application; Figure 2 This is a schematic diagram of the test support module in the first embodiment of the processor test system proposed in this application. Figure 3 This is a schematic diagram of the resource expansion module in the second embodiment of the processor testing system proposed in this application. Figure 4 This is a schematic diagram of the PCIe switching unit in the second embodiment of the processor testing system proposed in this application. Figure 5 This is a schematic diagram of the PCIe test module in the third embodiment of the processor test system proposed in this application. Figure 6 This is a schematic diagram of the first structure of the third embodiment of the processor testing system proposed in this application; Figure 7 This is a second structural schematic diagram of the third embodiment of the processor testing system proposed in this application.

[0021] Explanation of icon numbers: 1. Test Bearer Module; 11. Test Bearer Board; 12. Connecting Cable; 13. Fault Reporting Unit; 2. Resource Expansion Module; 21. PCIe Expansion Board; 22. PCIe Switching Unit; 221. Uplink Port; 222. Signal Routing Subunit; 223. Hardware Isolation Subunit; 224. Downlink Port; 23. Firmware Configuration Unit; 24. Resource Partition Storage Unit; 3. PCIe Test Module; 31. Storage Device; 32. Network Device; 4. Processor Under Test; 5. Test Control Module.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0026] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0027] It's important to note that System-Level Testing (SLT) for server CPUs is a critical step in the mass production phase, with PCIe interface performance testing being particularly important. Current mainstream testing solutions employ a "one-to-one" direct-connect architecture, meaning each CPU under test on each test board requires an independent set of complete PCIe testing equipment (such as an NVMe SSD). Under this architecture, the number of PCIe devices procured is linearly proportional to the scale of the test.

[0028] However, this high-cost hardware investment has brought significant problems to mass production testing: the high unit price of high-performance PCIe equipment causes the hardware cost of the testing environment to rise sharply with production capacity requirements. At the same time, the high failure rate of a large number of devices under high load testing further increases maintenance costs and the risk of test interruption.

[0029] To address the aforementioned technical problems, this embodiment provides a processor testing system. This embodiment includes a processor testing system within a processor testing device. The system comprises: several test carrier modules 1, resource expansion modules 2, and at least one PCIe test module 3. Each test carrier module 1 is connected to a resource expansion module 2, and the resource expansion module 2 is connected to the PCIe test module 3. The test carrier modules 1 carry the processor under test (DUT) 4, receive the PCIe test signal generated by the DUT 4, and then transmit the PCIe test signal to the resource expansion modules 2. The resource expansion modules 2 receive the PCIe test signal and route it to the PCIe test module 3. The PCIe test module 3 performs test operations on the DUT 4 based on the PCIe test signal. Compared to existing systems, this embodiment introduces a resource expansion module 2 to connect multiple test carrier modules 1 to at least one PCIe test module 3, thereby enabling multiple DUT processors 4 to share the PCIe test module 3 and reducing the hardware cost of the testing system.

[0030] For ease of understanding, the following is combined with Figures 1 to 7 The processor testing system provided in the embodiments of this application will be described in detail.

[0031] Reference Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the processor testing system proposed in this application.

[0032] like Figure 1 As shown, in this embodiment, the system includes: several test bearer modules 1, resource expansion modules 2, and at least one PCIe test module 3; Each of the test bearer modules 1 is connected to the resource expansion module 2, and the resource expansion module 2 is connected to the PCIe test module 3; The test bearer module 1 is used to carry the processor under test 4, receive the PCIe test signal generated by the processor under test 4, and then transmit the PCIe test signal to the resource expansion module 2. The resource expansion module 2 is used to receive the PCIe test signal and route the PCIe test signal to the PCIe test module 3. The PCIe test module 3 is used to perform test operations on the processor under test 4 according to the PCIe test signal.

[0033] It should be explained that the aforementioned test carrier module 1 can refer to a physical carrier used to carry the processor under test 4 and provide electrical connection, such as a test board used for system level test (SLT), which is equipped with a processor socket, power management circuit and signal output interface.

[0034] The aforementioned resource expansion module 2 can refer to an intermediate device with signal exchange and resource allocation functions. Its core component is a PCIe switching unit 22 that supports multi-host functionality, used to aggregate PCIe signals from multiple upstream processors and forward them to downstream test equipment according to preset rules. The aforementioned PCIe test module 3 can refer to a test device with a PCIe interface, used to simulate the processor's PCIe communication behavior in real-world application scenarios, such as NVMe solid-state drives and high-speed Ethernet cards, and to verify the functional correctness of the processor's PCIe interface by performing data read / write or network transmission / reception operations.

[0035] The aforementioned PCIe test signals can refer to data communication commands issued by the processor under test 4 through its PCIe interface, such as memory read / write requests, configuration space access requests, or interrupt requests.

[0036] The processor under test 4 mentioned above can refer to the Central Processing Unit (CPU) or other processor chip with a PCIe interface.

[0037] In its implementation, the processor testing system includes multiple test carrier modules 1, a resource expansion module 2, and at least one PCIe test module 3. Each test carrier module 1 in the processor testing system is physically connected to the resource expansion module 2 via a connecting cable 12, and the resource expansion module 2 is physically connected to at least one PCIe test module 3 via its downstream port 224. This connection architecture allows the processors under test 4 on multiple test carrier modules 1 to share the same set of PCIe test modules 3. The test carrier module 1 first carries the processor under test 4, providing it with power supply, clock signal, and signal output interface. When the processor under test 4 is powered on, it generates a PCIe test signal through its PCIe interface according to a preset test program. The test carrier module 1 receives the PCIe test signal and transmits it to the resource expansion module 2 via the connecting cable 12. Next, the resource expansion module 2 receives PCIe test signals from multiple test bearer modules 1, and selectively routes the received PCIe test signals to the designated PCIe test module 3 according to the preset resource partition configuration information through its internal PCIe switching unit 22, which supports multi-host functionality. Subsequently, the PCIe test module 3 receives the PCIe test signals from the resource expansion module 2, and performs corresponding test operations on the processor under test 4 according to the instruction type carried in the PCIe test signal, such as returning data in response to a read instruction or storing data according to a write instruction, thereby verifying whether the communication function of the PCIe interface of the processor under test 4 is normal.

[0038] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, suppose that in a server CPU mass production testing scenario, the processor testing system includes eight test support modules 1, each with one server CPU to be tested installed. The resource expansion module 2 includes a PCIe switch chip supporting eight uplink ports 221 and four downlink ports 224. The PCIe test module 3 consists of four NVMe solid-state drives. In this example, the eight test support modules 1 are connected to the eight uplink ports 221 of the resource expansion module 2 via MCIO cables, and the four downlink ports 224 of the resource expansion module 2 are connected to the four NVMe solid-state drives. When eight CPUs under test execute the PCIe test program simultaneously, each CPU under test generates a PCIe read / write request signal. The test bearer module 1 receives the signal and transmits it to the resource expansion module 2. The resource expansion module 2 routes the PCIe signals of every two CPUs to the same NVMe solid-state drive according to the pre-configured resource partitioning rules. The NVMe solid-state drive performs the corresponding data read / write operation according to the received read / write request and returns the operation result to the corresponding CPU under test, thereby achieving the effect of multiple CPUs sharing the PCIe test device.

[0039] Furthermore, in order to connect the processor under test 4 to the resource expansion module, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the test support module 1 in the first embodiment of the processor testing system proposed in this application. In this embodiment, the test support module 1 includes: a test support board 11 and connecting cables 12; The test carrier board 11 is connected to the resource expansion module 2 via the connecting cable 12; The test support plate 11 is used to support the processor under test 4; The connecting cable 12 is used to connect the PCIe port of the processor under test 4 to the resource expansion module 2.

[0040] It should be explained that the aforementioned test carrier board 11 can refer to a circuit board assembly used to carry the processor under test 4 and provide electrical connection and physical support, such as the SLT test board used in system-level testing, which is equipped with a processor socket, power management circuit, clock circuit and signal output interface.

[0041] The aforementioned connecting cable 12 may refer to a cable assembly for high-speed signal transmission, such as an MCIO (Mini CoolEdge Input / Output) connector cable, used to reliably lead out the PCIe signal on the test carrier board 11 and connect it to the resource expansion module 2.

[0042] In its implementation, the test carrier board 11 establishes a physical connection with the resource expansion module 2 via a connecting cable 12. Specifically, the test carrier board 11 is provided with a signal output interface, which connects to one end of the connecting cable 12, and the other end of the connecting cable 12 connects to a corresponding interface on the resource expansion module 2, thereby forming a high-speed signal transmission channel from the test carrier board 11 to the resource expansion module 2. The test carrier board 11 is used to carry the processor under test 4. Specifically, the test carrier board 11 is provided with a processor socket that matches the package form of the processor under test 4. The processor under test 4 is installed in the socket. The test carrier board 11 provides the power supply voltage, clock signal, and reset signal required for the operation of the processor under test 4, and leads the PCIe interface pins of the processor under test 4 to the signal output interface. The connecting cable 12 is used to connect the PCIe port of the processor under test 4 to the resource expansion module 2. Specifically, one end of the connecting cable 12 is connected to the signal output interface on the test carrier board 11, and the other end is connected to the uplink port 221 on the resource expansion module 2, thereby transmitting the PCIe test signal emitted by the processor under test 4 through its PCIe port to the resource expansion module 2. The connecting cable 12 uses high-speed signal transmission cable, which can ensure the signal integrity and anti-interference capability of the PCIe signal during transmission.

[0043] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, the test support board 11 is specifically an SLT test board. This test board is equipped with an LGA socket for mounting an Intel Xeon series server CPU. The test board leads the CPU's PCIe signal pins to two MCIO connectors on the edge of the board. The connecting cables 12 are specifically two MCIO-to-MCIO high-speed cables. One end of each cable is inserted into the MCIO connector on the test board, and the other end is inserted into the corresponding MCIO connector on the resource expansion module 2, thereby establishing a physical connection between the CPU's PCIe port on the test board and the resource expansion module 2. When the CPU executes the PCIe test program, the test signal emitted by the CPU through its PCIe port passes sequentially through the PCB traces on the test board, the MCIO connectors, and the MCIO cables, and is finally transmitted to the resource expansion module 2 for processing.

[0044] This embodiment provides a processor testing system. The system includes several test carrier modules 1, resource expansion modules 2, and at least one PCIe test module 3. Each test carrier module 1 is connected to a resource expansion module 2, and the resource expansion module 2 is connected to the PCIe test module 3. The test carrier modules 1 carry the processor under test (DUT) 4, receive the PCIe test signal generated by the DUT 4, and then transmit the PCIe test signal to the resource expansion modules 2. The resource expansion modules 2 receive the PCIe test signal and route it to the PCIe test module 3. The PCIe test module 3 performs test operations on the DUT 4 based on the PCIe test signal. Compared to existing systems, this embodiment introduces a resource expansion module 2 to connect multiple test carrier modules 1 to at least one PCIe test module 3, thereby enabling multiple DUTs 4 to share the PCIe test module 3 and reducing the hardware cost of the testing system.

[0045] Reference Figure 3 , Figure 3 This is a schematic diagram of the resource expansion module 2 in the second embodiment of the processor testing system proposed in this application.

[0046] Based on the above embodiments, a second embodiment of this application is proposed. In order to receive PCIe test signals, such as... Figure 3 As shown, in this embodiment, the resource expansion module 2 includes: a PCIe expansion board 21 and a PCIe switching unit 22 disposed on the PCIe expansion board 21; The PCIe switching unit 22 is disposed on the PCIe expansion board 21, and the PCIe expansion board 21 is connected to the test bearer module 1 and the PCIe test module 3 respectively through the PCIe switching unit 22; The PCIe expansion board 21 is used to carry the PCIe switching unit 22; The PCIe switching unit 22 is used to receive PCIe test signals and route the PCIe test signals to the PCIe test module 3.

[0047] It should be explained that the aforementioned PCIe expansion board 21 can refer to a circuit board assembly used to carry the PCIe switching unit 22 and provide signal interconnection. It has multiple signal connection interfaces for connecting multiple test bearer modules 1 and multiple PCIe test modules 3 to realize signal aggregation and distribution functions. The aforementioned PCIe switching unit 22 can refer to a PCIe switching chip that supports multi-host functionality. This chip has multiple uplink ports 221 and multiple downlink ports 224, and can simultaneously receive PCIe signals from multiple upstream host devices, and forward these signals to downstream PCIe devices according to preset routing rules, realizing shared access of multiple hosts to the same PCIe device.

[0048] In its implementation, the PCIe switching unit 22 is surface-mount soldered to the circuit surface of the PCIe expansion board 21, and its signal pins are electrically connected to the PCB traces on the PCIe expansion board 21. The PCIe expansion board 21 is connected to the test carrier module 1 and the PCIe test module 3 via the PCIe switching unit 22. Specifically, the PCIe expansion board 21 has multiple signal connection interfaces, which are connected to the uplink port 221 and downlink port 224 of the PCIe switching unit 22 via PCB traces. The test carrier module 1 is connected to the uplink interface on the PCIe expansion board 21 via a connecting cable 12, and the PCIe test module 3 is connected to the downlink interface on the PCIe expansion board 21 via a connecting cable 12 or by direct plug-in connection, thus forming a complete signal path. The PCIe expansion board 21 is used to carry the PCIe switching unit 22. Specifically, the PCIe expansion board 21 provides the PCIe switching unit 22 with an installation location, power supply, clock signal, and peripheral circuit support, ensuring the stable operation of the PCIe switching unit 22. The PCIe expansion board 21 also brings out the signal ports of the PCIe switching unit 22 to the connectors on the board for easy connection to external devices. The PCIe switching unit 22 is used to receive PCIe test signals and route the received PCIe test signals to the PCIe test module 3. Specifically, when the PCIe switching unit 22 receives a PCIe test signal from the test bearer module 1 through its uplink port 221, the switching logic inside the PCIe switching unit 22 determines the target downlink port 224 of the PCIe test signal according to preset configuration information (such as resource partition configuration), and then sends the PCIe test signal out from the corresponding downlink port 224, thereby routing the signal to the PCIe test module 3 connected to the downlink port 224.

[0049] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For instance, assuming a server CPU mass production testing scenario, the PCIe expansion board 21 is specifically a custom-designed PCIe switching backplane. This backplane has a PCIe switching chip soldered on it, supporting 8 uplink ports 221 and 8 downlink ports 224. This switching chip is a Broadcom PEX88000 series chip. The PCIe expansion board 21 has 8 MCIO uplink connectors, which are connected to the 8 uplink ports 221 of the PCIe switching chip via PCB traces. It also has 4 MCIO downlink connectors, which are connected to the 4 downlink ports 224 of the PCIe switching chip via PCB traces. Eight test carrier modules 1 are connected to the 8 uplink connectors via MCIO cables, and four NVMe solid-state drives are connected to the 4 downlink connectors via MCIO cables. When the CPU on a certain test bearer module 1 sends a PCIe test signal, the signal enters the uplink connector of the PCIe expansion board 21 through the MCIO cable, and is transmitted to the uplink port 221 of the PCIe switching chip through the PCB traces. The PCIe switching chip outputs the signal from the corresponding downlink port 224 according to the pre-configured resource partitioning rules, and transmits it to the target NVMe solid-state drive through the PCB traces and downlink connector, thereby completing the signal aggregation and routing.

[0050] Furthermore, in order to make reasonable use of the resource partitioning of resource expansion module 2, we will continue as follows: Figure 3 As shown, in this embodiment, the resource expansion module 2 further includes: a firmware configuration unit 23 and a resource partition storage unit 24; The firmware configuration unit 23 is connected to the PCIe switching unit 22 and the resource partition storage unit 24 respectively; The firmware configuration unit 23 is used to configure the resource partitioning of the PCIe switching unit 22; The resource partition storage unit 24 is used to store the configuration information of the resource partition. The configuration information is used to divide the downlink port 224 of the PCIe switching unit 22 into multiple logical resource areas corresponding to each of the processors under test 4.

[0051] It should be explained that the aforementioned firmware configuration unit 23 may refer to a non-volatile storage device and supporting processing circuitry used to store and execute configuration programs, such as a combination of flash memory chips and microcontrollers, which stores firmware programs for configuring PCIe switching unit 22. These firmware programs are automatically executed when the system is powered on to initialize PCIe switching unit 22.

[0052] The aforementioned resource partition storage unit 24 may refer to a storage device used for persistently storing resource configuration information, such as an electrically erasable programmable read-only memory (EEPROM) or a flash memory chip, which stores the resource partitioning rules of the PCIe switching unit 22.

[0053] The aforementioned resource partitioning can refer to dividing the downlink port 224 resources of the PCIe switching unit 22 into multiple mutually isolated logical regions according to predetermined rules. Each logical region corresponds to one or more processors under test 4, so that PCIe test traffic from different processors under test 4 is transmitted within their respective independent partitions without interference. The aforementioned logical resource region can refer to the logical representation of resource partitioning. Each logical resource region is associated with one or more downlink ports 224 and bound to one or more processors under test 4, forming a mapping relationship from the processor under test 4 to the PCIe test device.

[0054] In its implementation, the firmware configuration unit 23 connects to the resource partition storage unit 24 via a communication interface such as the Serial Peripheral Interface (SPI) or Integrated Circuit Bus (I2C) to read configuration information stored in the resource partition storage unit 24. The firmware configuration unit 23 also connects to the PCIe switching unit 22 via its configuration interface (e.g., SMBus or JTAG interface) to write configuration information into the registers inside the PCIe switching unit 22, thus completing the resource partition configuration of the PCIe switching unit 22. When the processor test system powers on, the firmware configuration unit 23 automatically executes its internally stored firmware program, reads the pre-stored resource partition configuration information from the resource partition storage unit 24, and then writes this configuration information into the registers inside the PCIe switching unit 22 via the configuration interface, enabling the PCIe switching unit 22 to operate according to preset resource partitioning rules. The resource partition storage unit 24 stores the resource partition configuration information, which is used to divide the downlink port 224 of the PCIe switching unit 22 into multiple logical resource regions corresponding to each processor under test 4. The configuration information stored in resource partition storage unit 24 includes a mapping table between uplink port 221 and downlink port 224. This mapping table defines which downlink ports 224 each processor under test 4 (corresponding to a specific uplink port 221) can access, the access permission rules, and the traffic isolation policy. Based on this configuration information, PCIe switching unit 22 can route PCIe test signals from different processors under test 4 to their corresponding downlink ports 224 during operation, while ensuring that the PCIe test traffic of different processors under test 4 is transmitted within their respective logical resource areas without mutual interference.

[0055] For ease of understanding, the following explanation uses examples, but does not limit the scope of this embodiment. For example, in a server CPU mass production testing scenario, assume that the PCIe switching unit 22 has 8 uplink ports 221 (connected to 8 CPUs under test respectively) and 4 downlink ports 224 (connected to 4 NVMe solid-state drives respectively), and it is desired to implement a resource configuration scheme where every 2 CPUs share 1 solid-state drive. The operator pre-writes the configuration information into the resource partition storage unit 24. Specifically, the configuration information is as follows: uplink ports A and B are mapped to downlink port A, uplink ports C and D are mapped to downlink port B, uplink ports E and F are mapped to downlink port C, and uplink ports G and H are mapped to downlink port D. When the processor test system is powered on, the firmware configuration unit 23 (e.g., an SPI flash memory storing the configuration program) runs automatically, reads the above mapping configuration information from the resource partition storage unit 24 (e.g., an EEPROM) through the SPI interface, and then writes the configuration information into the registers inside the PCIe switching chip through the SMBus interface. After configuration, the PCIe switch chip operates according to the mapping rules: when a PCIe test signal arrives from uplink port A or uplink port B, the switch chip routes the signal to downlink port A, and the NVMe solid-state drive connected to downlink port A receives and responds to the signal; at the same time, the test traffic of uplink port A and the test traffic of uplink port B are transmitted in their respective independent logical resource areas without interfering with each other, thereby realizing the functions of resource partitioning and resource sharing.

[0056] Further, refer to Figure 4 , Figure 4 This is a schematic diagram of the PCIe switching unit 22 in the second embodiment of the processor testing system proposed in this application. In this embodiment, the PCIe switching unit 22 includes: a plurality of uplink ports 221, a plurality of downlink ports 224, a signal routing subunit 222, and a hardware isolation subunit 223; The signal routing subunit 222 is connected to each of the uplink ports 221, the hardware isolation subunit 223 and the resource partition storage unit 24 respectively, and the hardware isolation subunit 223 is connected to each of the downlink ports 224. The uplink port 221 is used to receive the PCIe test signal; The signal routing subunit 222 is used to obtain the configuration information from the resource partition storage unit 24 and send the PCIe test signal to the corresponding hardware isolation subunit 223 according to the configuration information. The hardware isolation subunit 223 is used to isolate PCIe test signals belonging to different logical resource regions and send the isolated PCIe test signals to the corresponding downlink port 224. The downlink port 224 is used to output the PCIe test signal to the PCIe test module 3.

[0057] It should be explained that the aforementioned uplink port 221 may refer to the signal interface of the PCIe switching unit 22 facing the host side, which is used to connect to the upstream test bearer module 1 and receive PCIe test signals from the processor under test 4.

[0058] The aforementioned downstream port 224 may refer to the signal interface of the PCIe switching unit 22 facing the device side, which is used to connect to the downstream PCIe test module 3 and output PCIe test signals to the test device.

[0059] The aforementioned signal routing subunit 222 may refer to the logic circuit inside the PCIe switching unit 22 that is responsible for signal forwarding. According to the preset configuration information, it forwards the PCIe test signal received from one port to another designated port.

[0060] The aforementioned hardware isolation subunit 223 may refer to the hardware circuitry inside the PCIe switching unit 22 used to implement traffic isolation, such as isolation logic based on virtual channels or port groups, which ensures that PCIe test signals belonging to different logical resource areas are physically or logically isolated from each other, and that data confusion or conflict will not occur.

[0061] In the specific implementation, the input terminal of the signal routing subunit 222 is connected to each uplink port 221 to receive PCIe test signals from the uplink ports 221; the control terminal of the signal routing subunit 222 is connected to the resource partition storage unit 24 to obtain resource configuration information; the output terminal of the signal routing subunit 222 is connected to the hardware isolation subunit 223 to send the processed PCIe test signals to the hardware isolation subunit 223. The hardware isolation subunit 223 is further connected to each downlink port 224 to send the isolated PCIe test signals to the corresponding downlink port 224. The uplink port 221 is used to receive PCIe test signals. When the processor under test 4 sends a PCIe test signal through the test bearer module 1, the signal is transmitted to the PCIe switching unit 22 via the connection cable 12, received by the uplink port 221 connected to the cable, and then transmitted to the signal routing subunit 222. The signal routing subunit 222 is used to obtain configuration information from the resource partition storage unit 24 and send the received PCIe test signal to the corresponding hardware isolation subunit 223 according to the configuration information. During the processor test system initialization phase or operation, the signal routing subunit 222 reads resource configuration information through its communication interface with the resource partition storage unit 24. This resource configuration information contains signal forwarding rules, such as which hardware isolation subunit 223 should forward a signal received by a specific uplink port 221. When the signal routing subunit 222 receives a PCIe test signal through a certain uplink port 221, it parses the source identifier carried in the signal or, based on the receiving port information, looks up the corresponding forwarding rule in the resource configuration information to determine the target hardware isolation subunit 223, and then sends the PCIe test signal to the corresponding hardware isolation subunit 223. The hardware isolation subunit 223 is used to isolate PCIe test signals belonging to different logical resource regions and sends the isolated PCIe test signal to the corresponding downlink port 224. Each hardware isolation subunit 223 is configured to handle PCIe test traffic from one or more logical resource areas. When a hardware isolation subunit 223 receives a PCIe test signal from a signal routing subunit 222, it ensures, according to the isolation policy defined in the resource configuration information, that the signal is transmitted only within its own logical resource area and does not intersect or interfere with signals from other logical resource areas. Subsequently, the hardware isolation subunit 223 sends the isolated PCIe test signal to the downlink port 224 associated with that logical resource area. The downlink port 224 is used to output the PCIe test signal to the PCIe test module 3.Downlink port 224 and PCIe test module 3 establish a physical connection through connection cable 12. When downlink port 224 receives a PCIe test signal from hardware isolation subunit 223, it sends the signal to the corresponding PCIe test module 3 through connection cable 12 so that PCIe test module 3 can perform the corresponding test operation.

[0062] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, assume that the PCIe switching unit 22 is configured with 8 uplink ports 221 and 4 downlink ports 224, and the configuration information stored in the resource partition storage unit 24 defines the following mapping rules: uplink ports A and B correspond to logical resource region A, associated with hardware isolation subunit 223 and downlink port A; uplink ports C and D correspond to logical resource region B, associated with hardware isolation subunit 223 and downlink port B; uplink ports E and F correspond to logical resource region C, associated with hardware isolation subunit 223 and downlink port C; uplink ports G and H correspond to logical resource region D, associated with hardware isolation subunit 223 and downlink port D. When uplink port A receives a PCIe read request signal from the first CPU under test, the signal is transmitted to the signal routing subunit 222. Signal routing subunit 222 obtains the configuration information from resource partition storage unit 24. Based on the information that the receiving port is uplink port A, it determines that the signal should be forwarded to hardware isolation subunit 223. Signal routing subunit 222 sends the PCIe read request signal to hardware isolation subunit 223. Hardware isolation subunit 223 confirms that the signal belongs to logical resource area A and performs isolation processing within this area to ensure that the signal will not be confused with signals from other logical resource areas. Subsequently, hardware isolation subunit 223 sends the isolated PCIe read request signal to downlink port A. Downlink port A outputs the signal to the NVMe solid-state drive connected to downlink port A via the MCIO cable. After receiving the signal, the solid-state drive performs a read operation and returns the read data to the first CPU under test through the same path. During this process, assuming that uplink port C simultaneously receives a PCIe write request signal from the second CPU under test, this signal is routed to hardware isolation subunit 223 and downlink port B, and is transmitted independently in physically isolated channels from the test traffic of uplink port A, without interfering with each other.

[0063] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of the PCIe test module 3 in the third embodiment of the processor test system proposed in this application.

[0064] Based on the above embodiments, a third embodiment of this application is proposed. For example... Figure 5As shown, in this embodiment, the PCIe test module 3 includes: a storage device 31 with a PCIe interface; The storage device 31 is connected to the resource expansion module 2; The storage device 31 is used to perform data write operations or data read operations according to the PCIe test signal.

[0065] It should be explained that the aforementioned storage device 31 equipped with a PCIe interface can refer to a non-volatile storage device 31 that communicates with the host via the PCIe bus, such as an NVMe (Non-Volatile Memory Express) solid-state drive. This type of storage device 31 utilizes the high-speed serial transmission characteristics of the PCIe bus to achieve high-throughput data read and write operations, and is used during processor testing to verify the data transmission function and stability of the PCIe interface of the processor under test. The aforementioned data write operation can refer to the process by which the storage device 31 receives data from the processor and writes it to its internal storage medium, and the aforementioned data read operation can refer to the process by which the storage device 31 retrieves data from its internal storage medium according to the processor's read instructions and returns it to the processor.

[0066] In the specific implementation, storage device 31 is connected to the downstream port 224 on resource expansion module 2 via a PCIe connector or MCIO cable, making storage device 31 a downstream device of PCIe switching unit 22, receiving PCIe test signals forwarded from resource expansion module 2. When the processor under test 4 issues a write command to storage device 31 through the PCIe test program, the write command, as a PCIe test signal, is transmitted and routed through test bearer module 1 and resource expansion module 2, finally reaching storage device 31. After receiving the write command, storage device 31 parses the target address and data to be written contained in the command, and then writes the data to the corresponding storage cell, completing the data write operation. When the processor under test 4 issues a read command to storage device 31 through the PCIe test program, the read command, as a PCIe test signal, reaches storage device 31 through the same transmission path. After receiving the read command, storage device 31 parses the source address contained in the command, reads data from the corresponding storage cell, and returns the read data to processor under test 4 through the same path. By performing data write and data read operations, storage device 31 can simulate data access behavior in real application scenarios, thereby verifying whether the data transmission function of the 4PCIe interface of the processor under test is normal.

[0067] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, assume that PCIe test module 3 is specifically an NVMe solid-state drive (SSD), which is connected to one of the downstream ports 224 of resource expansion module 2 via an MCIO cable. When the CPU under test executes the PCIe test program, the test program first sends a data write command to the SSD, which includes the data to be written (e.g., a randomly generated test data) and the target logical block address. This write command, as a PCIe test signal, is transmitted to resource expansion module 2 via test bearer module 1. The PCIe switching unit 22 in resource expansion module 2 routes the command to the downstream port 224 connected to the SSD. After receiving the command, the SSD writes the test data to the specified logical block address and returns a confirmation message indicating successful write. Subsequently, the test program sends a data read command to the SSD, which includes the same logical block address as before. After receiving the read command, the SSD reads the data from the specified logical block address and returns the read data to the CPU under test via the original path. The CPU under test compares the data it reads with the original data it wrote. If they match, it indicates that the PCIe interface of the CPU under test is functioning normally in terms of data transmission. If they do not match or a timeout error occurs, it indicates that there is a potential PCIe interface problem.

[0068] Furthermore, continue as Figure 5 As shown, in this embodiment, the PCIe test module 3 includes: a network device 32 equipped with a PCIe interface; The network device 32 is connected to the resource expansion module 2; The network device 32 is used to perform data transmission or data reception operations based on the PCIe test signal.

[0069] It should be explained that the network device 32 equipped with a PCIe interface can refer to a communication device that communicates with the host via the PCIe bus and has network data transmission and reception capabilities, such as a high-speed Ethernet card with a PCIe interface (e.g., a 10GbE, 25GbE, or 100GbE network card). This type of network device 32 utilizes the high bandwidth of the PCIe bus to realize data exchange between the processor and the external network. During processor testing, it is used to verify the data transmission function, interrupt handling capability, and packet processing stability of the PCIe interface of the processor under test in a network communication scenario. The aforementioned data transmission operation can refer to the process by which the network device 32 receives network data packets from the processor and sends them to the external network; the aforementioned data reception operation can refer to the process by which the network device 32 receives data packets from the external network and passes them to the processor for processing.

[0070] In the specific implementation, network device 32 is connected to the downlink port 224 on resource expansion module 2 via a PCIe connector or MCIO cable, making network device 32 a downstream device of PCIe switching unit 22, receiving PCIe test signals forwarded from resource expansion module 2. Simultaneously, network device 32's own network port is connected to an external network test environment or loopback test equipment via an Ethernet cable. When the processor under test 4 sends a data transmission command to network device 32 through the PCIe test program, this transmission command, as a PCIe test signal, is transmitted and routed through test bearer module 1 and resource expansion module 2, ultimately reaching network device 32. After receiving the transmission command, network device 32 parses the network data packet content contained in the command, encapsulates the data packet into a data frame conforming to the Ethernet protocol, and sends it to the external network through its network port, completing the data transmission operation. When network device 32 receives a data packet from the external network through its network port, network device 32 converts the received data packet into PCIe data format, generates a data reception signal, and returns it to processor under test 4 through resource expansion module 2 and test bearer module 1. By reading the content of the received data packets, the processor under test 4 can verify whether the PCIe interface functions normally in the data reception scenario.

[0071] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, assume that the PCIe test module 3 is specifically a 25GbE high-speed Ethernet card. This network card is connected to one of the downlink ports 224 of the resource expansion module 2 via an MCIO cable. The Ethernet port of the network card is connected to a dedicated network tester via a fiber optic cable. When the CPU under test executes the PCIe test program, the test program first sends a data transmission command to the network card, which contains a pre-generated network test data packet. This transmission command, as a PCIe test signal, is transmitted to the resource expansion module 2 via the test bearer module 1. The PCIe switching unit 22 in the resource expansion module 2 routes the command to the downlink port 224 connected to the network card. After receiving the command, the network card sends the network test data packet to the network tester via the fiber optic cable. After receiving the data packet, the network tester records the content of the received data packet and returns a response data packet to the network card. After receiving the response data packet, the network card returns the response data packet to the CPU under test through the PCIe switching unit 22 and the test bearer module 1. The CPU under test compares the data packets it sends with the response data packets it receives. If they match as expected, it indicates that the CPU's PCIe interface is functioning normally in network data transmission and reception scenarios. If data packet loss, content errors, or transmission timeouts occur, it indicates a potential PCIe interface problem. By configuring different data packet sizes, transmission rates, and transmission modes, the performance of the processor under test's 4 PCIe interfaces under different network load conditions can be comprehensively verified.

[0072] Further, refer to Figure 6 , Figure 6 This is a first structural schematic diagram of a third embodiment of the processor testing system proposed in this application. In this embodiment, the system further includes: a test control module 5; The test control module 5 is connected to the resource expansion module 2 and each of the test carrier modules 1 respectively; The test control module 5 is used to control the power-on timing of the processor under test 4 on each of the test carrier modules 1; The test control module 5 is also used to initialize and configure the resource expansion module 2.

[0073] It should be explained that the aforementioned test control module 5 may refer to a controller unit used to coordinate and manage the working status of each component in the processor test system, such as a microcontroller, embedded processor, or programmable logic device. It performs unified scheduling and management of the test carrier module 1 and the resource expansion module 2 by executing a preset control program.

[0074] The aforementioned power-on sequence refers to the order and time interval of powering on multiple processors under test 4 during system startup. A reasonable power-on sequence can avoid power surge impacts, ensure stable operation of the power system, and provide the correct initialization order for PCIe link training. The aforementioned initialization configuration refers to the process of configuring initial parameters such as register settings, resource partitioning, and routing table establishment for the PCIe switching unit 22 in the resource expansion module 2, so that the resource expansion module 2 is in the correct preparatory working state before the test begins.

[0075] In its implementation, the test control module 5 connects to each test carrier module 1 via a general-purpose input / output interface or a dedicated control bus. It sends power-on control signals to the test carrier modules 1 and monitors their operational status. The test control module 5 also connects to the resource expansion module 2 via a management bus (e.g., SMBus, I2C bus, or JTAG interface) to send configuration commands and read status information. During the processor test system startup, the test control module 5 sends power-on enable signals to each test carrier module 1 sequentially according to a preset power-on timing strategy. Upon receiving the power-on enable signal, each test carrier module 1 activates its onboard power management circuitry to provide the processor under test (DUT) 4 with core voltage, input / output voltage, and auxiliary voltage, enabling the DUT 4 to power on sequentially according to a preset order and time interval. For example, the test control module 5 can be configured to power on the first group of test carrier modules 1 first, wait for a preset stabilization time (e.g., 100 milliseconds), then power on the second group of test carrier modules 1, and so on, until all test carrier modules 1 are powered on. By precisely controlling the power-on sequence, the test control module 5 ensures a smooth transition of the power load of the entire test system, avoiding instantaneous high-current surges caused by simultaneous power-on, and providing a correct initialization sequence guarantee for PCIe link training. After the test bearer module 1 is powered on, the test control module 5 sends an initialization configuration command to the resource expansion module 2 via the management bus. This initialization configuration command includes setting the resource configuration, resource partitioning, routing table establishment, and hardware isolation policy for the PCIe switching unit 22. After receiving the configuration command, the firmware configuration unit 23 writes to the registers inside the PCIe switching unit 22 according to the command content, enabling the PCIe switching unit 22 to operate according to the preset configuration rules. For example, the test control module 5 can send a pre-stored resource configuration table to the resource expansion module 2 via the management bus. The resource expansion module 2 saves the configuration table to the resource partition storage unit 24 and instructs the firmware configuration unit 23 to complete the initialization settings of the PCIe switching unit 22 according to the configuration table. After completing the initialization configuration, the resource expansion module 2 enters the working state, ready to receive PCIe test signals from the test bearer module 1.

[0076] For ease of understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, assume that the processor testing system includes 8 test support modules 1, each test support module 1 has a CPU to be tested installed on it, and the test control module 5 is specifically an ARM architecture microcontroller. This microcontroller is connected to the power management chip of each test support module 1 through an independent I2C bus, and is connected to the firmware configuration unit 23 of the resource expansion module 2 through another SMBus bus.

[0077] When the test system starts, the test control module 5 executes a preset power-on sequence program. This program first sends a power-on command to the power management chip of the first group of test carrier modules 1 (including test carrier modules A and B), enabling these two CPUs to power on and start. After waiting 200 milliseconds, the test control module 5 sends a power-on command to the second group of test carrier modules 1 (including test carrier modules C and D). After waiting another 200 milliseconds, the same power-on operation is performed sequentially on the third group (test carrier modules E and F) and the fourth group (test carrier modules G and H), until all eight CPUs have been powered on.

[0078] After all test bearer modules 1 have powered on, the test control module 5 sends an initialization configuration command to the firmware configuration unit 23 of the resource expansion module 2 via the SMBus bus. This command contains a pre-configured resource partition mapping table, specifically mapping uplink port A to uplink port B to downlink port A, uplink port C to uplink port D to downlink port B, uplink port E to uplink port F to downlink port C, and uplink port G to uplink port H to downlink port D. Upon receiving this configuration command, the firmware configuration unit 23 writes the mapping table to the resource partition storage unit 24 and configures the registers inside the PCIe switching unit 22, enabling the PCIe switching unit 22 to route signals according to this mapping rule. After completing the initialization configuration, the resource expansion module 2 enters normal operation, and the eight CPUs begin executing the PCIe test program. The four NVMe solid-state drives are shared through the resource expansion module 2 to achieve PCIe interface function testing.

[0079] Further, refer to Figure 7 , Figure 7 This is a second structural schematic diagram of a third embodiment of the processor testing system proposed in this application. In this embodiment, the test support module 1 further includes: a fault reporting unit 13; The fault reporting unit 13 is connected to the processor under test 4; The fault reporting unit 13 is used to collect PCIe error information of the processor under test 4 and report the PCIe error information to an external terminal.

[0080] It should be explained that the aforementioned fault reporting unit 13 can refer to a hardware circuit or logic module used to monitor, collect, and report abnormal operating states of the processor under test 4, such as a Baseboard Management Controller (BMC), a Complex Programmable Logic Device (CPLD), or a dedicated monitoring chip. It connects to the error reporting interface of the processor under test 4 to acquire error information generated internally by the processor in real time. The aforementioned PCIe error information can refer to various abnormal state records detected by the processor under test 4 during its PCIe interface operation, such as PCIe link training failure, data link layer error, transaction layer error, timeout error, correctable error, and uncorrectable error. The aforementioned external terminal can refer to a device that receives and displays the information reported by the fault reporting unit 13, such as a test management server, a host computer, a human-machine interface of the test machine, or a centralized monitoring system.

[0081] In its implementation, the fault reporting unit 13 connects to the processor under test (DUT) 4 via a dedicated error reporting interface, such as through the processor's System Management Bus (SMBus), JTAG interface, General Purpose Input / Output (GPIO), or the error reporting mechanism of the PCIe interface itself. The fault reporting unit 13 can monitor the error status register of the DUT 4 in real time, acquiring various abnormal information generated within the processor. During the operation of the processor test system, the DUT 4 continuously performs high-speed data transmission through its PCIe interface while executing the PCIe test program. If the DUT 4's PCIe interface detects any abnormal conditions, such as link training failure with the PCIe switching unit 22, packet verification errors during data transmission, the transaction layer receiving unexpected completion messages, or timeouts, the DUT 4 will record these abnormal information in its internal error status register. The fault reporting unit 13 continuously monitors the DUT 4's error status register using either polling or interrupt-triggered methods. When the fault reporting unit 13 detects that a new PCIe error message has been recorded in the error status register, the fault reporting unit 13 immediately reads the PCIe error message from the error status register of the processor under test 4. The read PCIe error message may contain detailed data such as error type identifier, timestamp of error occurrence, PCIe port number involved in the error, link status information, and error count.

[0082] Subsequently, the fault reporting unit 13 formats the collected PCIe error information, converting it into a data format suitable for transmission, and reports the PCIe error information to the external terminal through its communication interface (such as an Ethernet interface, serial interface, or USB interface). Upon receiving the PCIe error information, the external terminal can record, store, and display the error information, allowing testers to promptly understand PCIe anomalies occurring during testing and to locate and analyze these anomalies. Through the real-time monitoring and reporting function of the fault reporting unit 13, when multiple processors under test 4 report similar PCIe errors during testing, testers can quickly determine that the root cause of the fault lies with the PCIe testing equipment rather than the processor under test 4, thereby shortening troubleshooting time and reducing losses caused by test interruptions.

[0083] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, in a server CPU mass production testing scenario, assume that the fault reporting unit 13 on the test support module 1 is specifically a CPLD device. This CPLD is connected to the CPU under test via the SMBus interface and establishes a network connection with the test management server via the Ethernet interface. The CPLD is pre-configured with a polling program that reads the internal PCIe error status register of the CPU under test every second via the SMBus. During a test run, when the CPU under test performs a PCIe write operation, it finds that it has not received the expected completion message after writing data to the NVMe solid-state drive. Therefore, the CPU records the error as "completion message timeout error" and writes the error information to the error status register. During the next round of polling, the CPLD detected a change in the error status register and immediately read the error information via SMBus. The error information read included: error type "Completion Message Timeout", error occurrence time "January 15, 2024, 14:32:17", PCIe port number involved "Port 2", and current link status "Gen4 x4, reduced to Gen3 x2". The CPLD encapsulated the read error information into a data packet conforming to the network transmission protocol and sent the data packet to the test management server via the Ethernet interface. After receiving the error information, the test management server displayed "CPU 2: PCIe Completion Message Timeout Error" in real time on the test monitoring interface and recorded the error information in the test log file. By reviewing the error report on the test management server, testers can promptly identify the abnormality of the CPU's PCIe interface and make a preliminary judgment on the fault type based on the content of the error information. If multiple CPUs report the same PCIe completion message timeout error at the same time, testers can initially determine that there is a problem with the NVMe solid-state drive or the PCIe switch unit 22, and thus prioritize checking the test equipment to avoid wasting unnecessary troubleshooting time on CPU issues.

[0084] To achieve the above objectives, this application also proposes a processor testing device, which includes the processor testing system described above.

[0085] It should be noted that the specific implementation of the processor testing device provided in this embodiment can refer to the above embodiments, and this embodiment will not elaborate on it further. Therefore, the effects achieved by the processor testing device in this embodiment can also refer to the above embodiments, and this embodiment will not elaborate on them further.

[0086] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A processor testing system, characterized in that, The system includes: several test hosting modules, resource expansion modules, and at least one PCIe test module; Each of the aforementioned test bearer modules is connected to the resource expansion module, and the resource expansion module is connected to the PCIe test module; The test bearer module is used to carry the processor under test, receive the PCIe test signal generated by the processor under test, and then transmit the PCIe test signal to the resource expansion module. The resource expansion module is used to receive the PCIe test signal and route the PCIe test signal to the PCIe test module; The PCIe test module is used to perform test operations on the processor under test according to the PCIe test signal. The resource expansion module includes: a PCIe expansion board and a PCIe switching unit disposed on the PCIe expansion board; The PCIe switching unit is disposed on the PCIe expansion board, and the PCIe expansion board is connected to the test bearer module and the PCIe test module respectively through the PCIe switching unit; The PCIe expansion board is used to carry the PCIe switching unit; The PCIe switching unit is used to receive PCIe test signals and route the PCIe test signals to the PCIe test module. The PCIe test module includes a test device with a PCIe interface. The PCIe switching unit includes a PCIe switching chip that supports multi-host functionality. The PCIe switching chip is used to simultaneously receive PCIe signals from multiple upstream host devices and forward the PCIe signals to downstream test devices according to preset routing rules, thereby enabling multiple hosts to share access to the same PCIe device. The resource expansion module also includes: a firmware configuration unit and a resource partition storage unit; The firmware configuration unit is connected to the PCIe switching unit and the resource partition storage unit, respectively. The firmware configuration unit is used to configure the resource partitioning of the PCIe switching unit; The resource partition storage unit is used to store the configuration information of the resource partition. The configuration information is used to divide the downlink port of the PCIe switching unit into multiple logical resource areas corresponding to each of the processors under test. The PCIe switching unit includes: several uplink ports, several downlink ports, a signal routing subunit, and a hardware isolation subunit; The signal routing subunit is connected to each of the uplink ports, the hardware isolation subunit, and the resource partition storage unit, respectively; the hardware isolation subunit is connected to each of the downlink ports. The uplink port is used to receive the PCIe test signal; The signal routing subunit is used to obtain the configuration information from the resource partition storage unit and send the PCIe test signal to the corresponding hardware isolation subunit according to the configuration information. The hardware isolation subunit is used to isolate PCIe test signals belonging to different logical resource regions and send the isolated PCIe test signals to the corresponding downlink ports. The downlink port is used to output the PCIe test signal to the PCIe test module.

2. The processor testing system as described in claim 1, characterized in that, The test support module includes: a test support board and connecting cables; The test carrier board is connected to the resource expansion module via the connecting cable; The test support board is used to support the processor under test; The connection cable is used to connect the PCIe port of the processor under test to the resource expansion module.

3. The processor testing system as described in claim 1, characterized in that, The PCIe test module includes: a storage device equipped with a PCIe interface; The storage device is connected to the resource expansion module; The storage device is used to perform data write operations or data read operations based on the PCIe test signal.

4. The processor testing system as described in claim 1, characterized in that, The PCIe test module includes: a network device equipped with a PCIe interface; The network device is connected to the resource expansion module; The network device is used to perform data transmission or data reception operations based on the PCIe test signal.

5. The processor testing system as described in claim 1, characterized in that, The system also includes: a test control module; The test control module is connected to the resource expansion module and each of the test carrier modules respectively; The test control module is used to control the power-on timing of the processor under test on each of the test carrier modules; The test control module is also used to initialize and configure the resource expansion module.

6. The processor testing system as described in claim 1, characterized in that, The test support module further includes: a fault reporting unit; The fault reporting unit is connected to the processor under test; The fault reporting unit is used to collect PCIe error information of the processor under test and report the PCIe error information to an external terminal.

7. A processor testing device, characterized in that, The processor testing equipment includes the processor testing system according to any one of claims 1 to 6.

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