A fault alarm method, device, equipment and computer readable storage medium

Abstract

The application discloses a kind of fault alarm method, device, equipment and computer readable storage medium, comprising: when system power-on is completed, starting basic input-output system initiative measurement flow to carry out motherboard bottom program fault detection;When motherboard bottom program fault detection is completed, carry out memory training fault detection, obtain memory training fault detection result;When memory training fault detection result is memory training detection pass, carry out peripheral detection, obtain peripheral detection result;Generate the target fault level corresponding to peripheral detection result, utilize the fault alarm strategy corresponding to target fault level to carry out fault alarm;When the motherboard bottom program fault detection result and / or memory training fault detection result obtained are detected and do not pass, determine as severe fault, and utilize severe fault alarm strategy to carry out fault alarm.The application improves fault positioning efficiency, fault diagnosis is more comprehensive, effectively avoids the problem of missed detection, improves the operation reliability and maintainability of computer.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and in particular to a fault alarm method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] The stability of computer system operation and the efficiency of fault handling are directly related to network information security and the normal operation of various business sectors. Current computer fault detection and alarm solutions mainly rely on serial port printing information to achieve basic hardware fault diagnosis and provide simple audio and visual prompts.

[0003] Current computer fault detection and alarm solutions have many shortcomings. On the one hand, they are cumbersome to operate, requiring staff to have professional software and hardware knowledge, and the efficiency of fault location is low. Fault diagnosis is limited in scope, mostly targeting core peripherals such as memory and hard drives, and the detection capabilities are insufficient. On the other hand, relying solely on fixed-frequency LED flashing and buzzer beeping to indicate faults makes it difficult for staff to quickly determine the urgency of the fault.

[0004] In summary, how to effectively address the problems of high requirements for software and hardware knowledge, low efficiency in fault location, insufficient fault detection capabilities, and difficulty in quickly determining the urgency of faults are urgent issues that need to be resolved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a fault alarm method that improves fault location efficiency, provides more comprehensive fault diagnosis, effectively avoids missed detections, and enhances the operational reliability and maintainability of the computer. Another purpose of this invention is to provide a fault alarm device, equipment, and computer-readable storage medium.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A fault alarm method, comprising: When the system power-on is complete, the basic input / output system active measurement process is started to detect faults in the motherboard's underlying program. When the motherboard's underlying program fault detection is completed, memory training fault detection is performed to obtain the memory training fault detection results. When the memory training failure detection result is that the memory training detection is passed, peripheral device detection is performed to obtain the peripheral device detection result. Generate a target fault level corresponding to the peripheral device detection result, and use the fault alarm strategy corresponding to the target fault level to perform a fault alarm; wherein, the target fault level is one of severe fault, moderate fault, and minor fault; When the obtained motherboard underlying program fault detection result and / or the memory training fault detection result are both failures, it is determined to be a severe fault, and a fault alarm is triggered using the severe fault alarm strategy.

[0007] In one specific embodiment of the present invention, the basic input / output system active measurement process is initiated to detect motherboard low-level program faults, including: The Basic Input / Output System Active Measurement Process is initiated to perform integrity verification on the Basic Input / Output System boot block, master image, key drivers, and configuration parameters in order to detect motherboard low-level program faults.

[0008] In one specific embodiment of the present invention, the Basic Input / Output System (PIOS) Active Measurement Process is initiated to perform integrity verification on the PIOS boot block, master image, key drivers, and configuration parameters, including: The active measurement process of the basic input / output system is initiated by performing hash digest calculations on the basic input / output system boot block, the master image, the key driver, and the configuration parameters using cryptographic algorithms to obtain the calculation results. The calculation results are compared with a preset trusted baseline.

[0009] In one specific embodiment of the present invention, memory training fault detection includes: The tests are performed in the following order: command address training test, read / write balancing test, reference voltage calibration test, eye diagram optimization test, and margin test, in order to detect memory training faults.

[0010] In one specific embodiment of the present invention, generating a target fault level corresponding to the peripheral device detection result, and using a fault alarm strategy corresponding to the target fault level to perform a fault alarm, includes: The target fault type is determined based on the peripheral device detection results, and the target fault level is determined based on the target fault type; When the target fault level is the minor fault, the alarm indicator light is set to flash at a frequency of flashing for a first preset duration and then pausing for the first preset duration. Set the audible alarm to sound at a first time interval and display the fault code corresponding to the target fault type on the fault display screen.

[0011] In one specific embodiment of the present invention, fault alarm is performed using a fault alarm strategy corresponding to the target fault level, including: When the target fault level is the moderate fault, the alarm indicator light is set to flash at a frequency of flashing for a second preset duration followed by a pause for a second preset duration; wherein the second preset duration is less than the first preset duration. The sound alarm is set to sound an alarm at a second time interval, and the fault type abbreviation and the target fault level corresponding to the target fault type are displayed on the fault prompt screen; wherein the second time interval is shorter than the first time interval.

[0012] In one specific embodiment of the present invention, a severe fault alarm strategy is used for fault alarm, including: Obtain the fault detection time; The alarm indicator light is set to a constant-on state, and the sound alarm is set to sound for a third duration followed by a fourth duration; wherein the third duration is longer than the first preset duration, and the third duration is longer than the fourth duration. The fault indication screen displays the fault type abbreviation corresponding to the target fault type, the target fault level, and the fault detection time in a scrolling manner.

[0013] A fault alarm device, comprising: The underlying program fault detection module is used to start the basic input / output system active measurement process to detect motherboard underlying program faults when the system is powered on. The memory training fault detection module is used to perform memory training fault detection and obtain memory training fault detection results when the motherboard's underlying program fault detection is completed. The peripheral detection module is used to perform peripheral detection and obtain peripheral detection results when the memory training failure detection result is that the memory training detection is passed. The first fault alarm module is used to generate a target fault level corresponding to the peripheral device detection result, and to perform a fault alarm using a fault alarm strategy corresponding to the target fault level; wherein, the target fault level is one of severe fault, moderate fault, and mild fault; The second fault alarm module is used to determine the severe fault when the obtained motherboard underlying program fault detection result and / or the memory training fault detection result is a failure to pass the detection, and to perform a fault alarm using a severe fault alarm strategy.

[0014] A fault alarm device, comprising: Memory, used to store computer programs; A processor is used to implement the steps of the fault alarm method as described above when executing the computer program.

[0015] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the aforementioned fault alarm method.

[0016] The fault alarm method provided by this invention includes: when the system is powered on, initiating a basic input / output system active measurement process to perform motherboard low-level program fault detection; when the motherboard low-level program fault detection is completed, performing memory training fault detection to obtain memory training fault detection results; when the memory training fault detection result is that the memory training detection is passed, performing peripheral device detection to obtain peripheral device detection results; generating a target fault level corresponding to the peripheral device detection results, and using a fault alarm strategy corresponding to the target fault level to perform a fault alarm; wherein, the target fault level is one of severe fault, moderate fault, and mild fault; when the obtained motherboard low-level program fault detection result and / or memory training fault detection result is that the detection is failed, it is determined to be a severe fault, and a severe fault alarm strategy is used to perform a fault alarm.

[0017] The beneficial effects of this invention lie in its ability to achieve comprehensive computer fault diagnosis through active measurement of the basic input / output system, memory training and detection, and peripheral device detection. Building upon traditional peripheral device detection such as memory and hard drives, it adds motherboard detection, covering the core aspects of computer startup and operation, resulting in more comprehensive fault diagnosis and effectively avoiding missed detections. By setting fault classifications and corresponding graded fault alarm strategies, staff can quickly determine the urgency and general type of faults without requiring specialized hardware or software knowledge, significantly improving fault location efficiency. It achieves an integrated design of active measurement, fault diagnosis, and alarm output for the basic input / output system, forming a complete computer fault detection and alarm system at the hardware and software level. This solves the problems of single system functionality and low identification rate, improving the computer's operational reliability and maintainability.

[0018] Accordingly, the present invention also provides a fault alarm device, equipment, and computer-readable storage medium corresponding to the above-mentioned fault alarm method, which have the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the implementation of a fault alarm method in an embodiment of the present invention. Figure 2 This is a flowchart illustrating the implementation of another fault alarm method in this invention. Figure 3 This is a structural block diagram of a fault intelligent diagnosis and linkage alarm system according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating the implementation of another fault alarm method in this invention. Figure 5 This is a structural block diagram of a fault alarm device according to an embodiment of the present invention; Figure 6 This is a structural block diagram of a fault alarm device according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the specific structure of a fault alarm device provided in an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] See Figure 1 , Figure 1 This is a flowchart illustrating an implementation of a fault alarm method according to an embodiment of the present invention. The method may include the following steps: S101: When the system power-on is complete, start the basic input / output system active measurement process to detect faults in the motherboard's underlying program.

[0023] The system performs a power-on test. When the system power-on is detected, the root of trust can initiate the Basic Input Output System (BIOS) active measurement process to detect motherboard low-level program faults.

[0024] A root of trust can be a Trusted Platform Control Module (TPCM), a Trusted Cryptography Module (TCM), or something similar.

[0025] The Basic Input / Output System Active Measurement includes a security mechanism that performs integrity verification on BIOS firmware, boot code, critical drivers, and configuration information based on the hardware root of trust during the computer startup process.

[0026] S102: When the motherboard's underlying program fault detection is completed, memory training fault detection is performed to obtain the memory training fault detection result.

[0027] After initiating the basic input / output system active measurement process to perform motherboard low-level program fault detection, it is determined whether the motherboard low-level program fault detection is complete. When it is determined that the motherboard low-level program fault detection is complete, memory training fault detection is performed to obtain the memory training fault detection result.

[0028] Memory training includes the hardware initialization process during computer startup, in which the BIOS or memory controller performs timing calibration, signal alignment, and impedance matching on the Dynamic Random Access Memory (DRAM) to ensure stable and reliable high-speed data transmission.

[0029] S103: When the memory training failure detection result is that the memory training detection is passed, perform peripheral detection and obtain the peripheral detection result.

[0030] After obtaining the memory training fault detection result, it is determined whether the memory training fault detection result is a pass. If the memory training fault detection result is a pass, peripheral device detection is performed to obtain the peripheral device detection result.

[0031] S104: Generate the target fault level corresponding to the peripheral device detection result, and use the fault alarm strategy corresponding to the target fault level to perform fault alarm.

[0032] The target fault level is one of the following: severe fault, moderate fault, and mild fault.

[0033] The faults detected by the system are pre-classified into three levels: minor, moderate, and severe. The fault definitions for each level can be set as follows: Minor faults: These refer to faults such as abnormal external interface communication or optical drive reading failures that do not affect the core operating functions of the computer, and the equipment can continue to work normally. Moderate failure: refers to failures such as abnormal fan speed or hard drive read / write lag that affect the stability of computer operation, but the device can still continue to work for a short period of time; Severe failure: refers to failures such as memory training failure, abnormal motherboard power supply, or graphics card failure that prevent the computer from starting normally or performing core functions.

[0034] After obtaining the peripheral device detection results, a target fault level corresponding to the peripheral device detection results is generated. The target fault level is one of severe fault, moderate fault, and minor fault. Fault alarm strategies corresponding to severe fault, moderate fault, and minor fault are preset, and fault alarms are generated using the fault alarm strategies corresponding to the target fault level.

[0035] S105: When the obtained motherboard underlying program fault detection result and / or memory training fault detection result is that the detection failed, it is determined to be a serious fault, and a fault alarm is triggered using the serious fault alarm strategy.

[0036] After obtaining the memory training fault detection results, if either the motherboard underlying program fault detection result or the memory training fault detection result fails, or both fail, it is determined to be a severe fault, and a severe fault alarm strategy is used to issue an alarm. This achieves multi-dimensional, full-process fault diagnosis and hierarchical fault alarms, solving the problems of incomplete system fault diagnosis and low alarm identification, improving the efficiency of computer fault location and maintenance convenience, and lowering the professional threshold for fault diagnosis.

[0037] As can be seen from the above technical solution, by actively measuring the basic input / output system, conducting memory training and testing, and detecting peripherals, a comprehensive fault diagnosis of the computer is achieved. In addition to traditional peripheral testing such as memory and hard drives, motherboard testing is added, covering the core aspects of computer startup and operation, resulting in more comprehensive fault diagnosis and effectively avoiding missed faults. By setting fault classifications and corresponding graded fault alarm strategies, staff can quickly determine the urgency and general type of faults without requiring specialized hardware and software knowledge, significantly improving fault location efficiency. The integrated design of active measurement, fault diagnosis, and alarm output of the basic input / output system forms a complete computer fault detection and alarm system at the hardware and software level, solving the problems of single system function and low identification rate, and improving the computer's operational reliability and maintainability.

[0038] It should be noted that, based on the above embodiments, the present invention also provides corresponding improvements. In subsequent embodiments, steps identical or corresponding to those in the above embodiments can be referenced interchangeably, and their respective beneficial effects can also be referred to each other. These improvements will not be elaborated upon in the following improved embodiments.

[0039] See Figure 2 , Figure 2 This is a flowchart illustrating another fault alarm method in an embodiment of the present invention. The method may include the following steps: S201: When the system power-on is complete, the Basic Input / Output System Active Measurement Process is started to perform integrity verification on the Basic Input / Output System boot block, master image, key drivers and configuration parameters in order to detect motherboard low-level program faults.

[0040] When the system powers on, the BIOS Active Measurement Process (APMP) is initiated to perform integrity checks on the BIOS boot block, master image, critical drivers, and configuration parameters, thereby enabling fault detection in the motherboard's underlying programs. By initiating the APMP Active Measurement Process to verify the integrity of the BIOS boot block, master image, critical drivers, and configuration parameters, issues such as measurement verification failures, process interruptions, and Platform Configuration Register (PCR) expansion anomalies can be promptly detected. This allows for the preliminary identification of underlying anomalies such as BIOS firmware tampering, flash memory chip damage, SPI communication anomalies, and root of trust module failures, improving fault diagnosis efficiency.

[0041] See Figure 3 , Figure 3 This is a structural block diagram of a fault intelligent diagnosis and linkage alarm system according to an embodiment of the present invention. The fault intelligent diagnosis and linkage alarm system mainly includes two core modules: a fault intelligent diagnosis module and an audible and visual graded alarm module. The fault intelligent diagnosis module consists of a Central Processing Unit (CPU), a Complex Programmable Logic Device (CPLD) / Embedded Controller (EC), BIOS, memory, a fault information storage unit, and a peripheral detection unit. The audible and visual graded alarm module consists of an audible and visual alarm output circuit and a graded control unit.

[0042] like Figure 3 As shown, the system hardware connection logic is as follows: The CPU establishes a bidirectional communication connection with the CPLD / EC via a Serial Peripheral Interface (SPI) bus and a Transistor-Transistor Logic (TTL) level debugging serial port. The CPLD / EC is connected to the BIOS and fault information storage unit via the SPI bus. The CPLD / EC's input / output (I / O) ports are connected to the peripheral detection unit. The CPLD / EC's custom general purpose input / output (GPIO) control signals are connected to the hierarchical control unit of the audible and visual hierarchical alarm module, which drives the audible and visual alarm output circuit to complete the alarm action. Communication between the modules is achieved through the standard SPI bus, TTL level debugging serial port, and custom GPIO port, and the level conversion chip ensures the stability of signal transmission.

[0043] In one specific embodiment of the present invention, initiating the Basic Input / Output System Active Measurement Process to perform integrity verification on the Basic Input / Output System boot block, master image, key drivers, and configuration parameters in order to detect motherboard low-level program faults may include the following steps: Step 1: Initiate the Basic Input / Output System Active Measurement Process. Calculate hash digests of the Basic Input / Output System boot block, master image, key drivers, and configuration parameters using cryptographic algorithms to obtain the results. Step 2: Compare the calculation results with the preset trusted baseline.

[0044] For ease of description, the two steps above can be combined for explanation.

[0045] The Initiation of the Basic Input / Output System (BIOS) Active Measurement Process utilizes cryptographic algorithms to perform hash digest calculations on the BIOS boot block, master image, key drivers, and configuration parameters. The calculated results are then compared with a pre-set trusted baseline to detect underlying motherboard program faults. By employing cryptographic algorithms to calculate hash digests of the BIOS boot block, master image, key drivers, and configuration parameters, and comparing the results with a pre-set trusted baseline, the reliability of underlying motherboard program fault detection is improved.

[0046] S202: When the motherboard's underlying program fault detection is completed, the tests are performed in the following order: command address training test, read / write balancing test, reference voltage calibration test, eye diagram optimization test, and margin test, in order to detect memory training faults and obtain the memory training fault detection results.

[0047] Once the motherboard's underlying program fault detection is complete, tests are performed in the following order: command address training test, read / write balancing test, reference voltage calibration test, eye diagram optimization test, and margin test. This process enables memory training fault detection and yields the results. By performing memory tests in this order, abnormal states such as timing offsets, signal distortion, read / write errors, and calibration timeouts during the training process can be monitored. Combined with training stage, error type, and slot information, problems such as damaged memory chips, poor slot contact, motherboard wiring impedance mismatch, excessive power supply noise, memory compatibility issues, and memory controller malfunctions can be diagnosed. This ensures the orderly execution of computer fault detection and further enhances the comprehensiveness of computer fault diagnosis.

[0048] S203: When the memory training failure detection result is that the memory training detection is passed, perform peripheral detection and obtain the peripheral detection result.

[0049] S204: Determine the target fault type based on the peripheral device detection results, and determine the target fault level based on the target fault type.

[0050] The target fault level is one of the following: severe fault, moderate fault, and mild fault.

[0051] After obtaining the peripheral device test results, the target fault type is determined based on the peripheral device test results. The fault type may include fan failure, hard drive failure, optical drive failure, etc., and the target fault level is determined based on the target fault type.

[0052] S205: Use the fault alarm strategy corresponding to the target fault level to perform fault alarm.

[0053] A pre-configured audible and visual alarm output circuit for fault detection is included. This circuit consists of multi-level light-emitting diode (LED) indicator lights, a frequency converter buzzer, and a fault indication screen. The multi-level LED indicator lights are divided into green, yellow, and red, corresponding to minor, moderate, and severe faults, respectively, conveying the fault level information through the light status. The fault indication screen is a small LCD display used to intuitively display the fault type abbreviation, assisting staff in quickly identifying the fault type.

[0054] See Table 1, which is a logic comparison table for fault classification audible and visual alarms.

[0055] Table 1

[0056] As shown in Table 1, the specific logic of the CPLD / EC driving the audible and visual alarm output circuit according to the fault type and fault level is as follows: Minor fault: The green LED indicator flashes continuously at a frequency of 1 second on and 1 second off, the frequency converter buzzer emits a low-frequency "beep" sound, the alarm interval is 5 seconds / time, and the fault prompt screen displays the fault code of the corresponding interface / peripheral. Medium fault: The yellow LED indicator flashes continuously at a frequency of 0.5s on and 0.5s off, the frequency converter buzzer emits a medium-frequency "beep" sound, the alarm interval is 2s / time, and the fault display screen shows the fault code and fault level of the corresponding peripheral device; Severe fault: The red LED indicator remains constantly lit, the frequency converter buzzer emits a high-frequency continuous "beep" sound, which pauses for 1 second after 3 seconds of sounding, and the alarm cycles in this manner. The fault display screen scrolls to show the fault type code, fault level, and fault detection time.

[0057] After obtaining the fault detection results, they can be stored in the fault information storage unit. This unit is a non-volatile memory chip with a storage capacity of at least 100 fault information entries. Each entry contains three core data points: fault occurrence time, fault type, and fault level. The CPLD / EC supports establishing a connection with an external terminal via the debug serial port to read and export fault information, providing data support for equipment maintenance and fault analysis. It achieves an integrated design for BIOS active measurement, fault diagnosis, alarm output, and information storage.

[0058] When the system detects a compound fault (i.e., multiple faults coexisting), the CPLD / EC will activate the audible and visual alarm output circuit according to the priority principle of "severe faults first, medium faults second, and minor faults last," prioritizing the highest-level faults. Simultaneously, all fault information is written sequentially to the fault information storage unit in the order of detection, and the fault display screen will scroll to show all relevant information, ensuring no fault information is missed. The coordinated operation of the three-color LEDs, the inverter buzzer, and the fault display screen achieves intuitive transmission of fault information.

[0059] In one specific embodiment of the present invention, step S205 may include the following steps: Step 1: Determine the target fault type based on the peripheral device test results, and then determine the target fault level based on the target fault type; Step 2: When the target fault level is a minor fault, the alarm indicator light is set to flash at a frequency of flashing for a first preset duration followed by a first preset duration. Step 3: Set the audible alarm to sound at the first time interval and display the fault code corresponding to the target fault type on the fault display screen.

[0060] For ease of description, the three steps above can be combined for explanation.

[0061] After determining the target fault level, the target fault type is determined based on the peripheral device detection results, and the target fault level is determined based on the target fault type. When the target fault level is a minor fault, the alarm indicator light is set to flash at a frequency of flashing for a first preset duration followed by a first preset duration, the audible alarm is set to sound at a first time interval, and the fault code corresponding to the target fault type is displayed on the fault display screen. By utilizing the flashing frequency of the alarm indicator light corresponding to a minor fault, the alarm time interval of the audible alarm, and the fault code corresponding to the target fault type displayed on the fault display screen, the fault information is conveyed intuitively and the minor fault is effectively indicated.

[0062] In one specific embodiment of the present invention, step S205 may include the following steps: Step 1: When the target fault level is a medium fault, the alarm indicator light is set to flash at a frequency of flashing for a second preset duration followed by a second preset duration; wherein the second preset duration is shorter than the first preset duration. Step 2: Set the audible alarm to sound at the second time interval, and display the fault type abbreviation and target fault level corresponding to the target fault type on the fault display screen; wherein the second time interval is shorter than the first time interval.

[0063] For ease of description, the two steps above can be combined for explanation.

[0064] After determining the target fault level, when the target fault level is a moderate fault, the alarm indicator light is set to flash at a frequency of a second preset duration followed by a second preset duration of pausing (the second preset duration is shorter than the first preset duration). The audible alarm is set to sound at a second time interval, and the fault type abbreviation and target fault level are displayed on the fault display screen (the second time interval is shorter than the first time interval). By setting the flashing frequency for moderate faults to be higher than that for minor faults, and setting the audible alarm frequency to be higher than that for minor faults, the flashing frequency of the alarm indicator light for moderate faults, the alarm time interval of the audible alarm, and the display of the fault type abbreviation and target fault level on the fault display screen achieve intuitive transmission of fault information and effective indication of moderate faults.

[0065] S206: When the obtained motherboard underlying program fault detection result and / or memory training fault detection result is that the detection failed, it is determined to be a serious fault, and a fault alarm is triggered using the serious fault alarm strategy.

[0066] In one specific embodiment of the present invention, using a severe fault alarm strategy to perform fault alarm may include the following steps: Step 1: Obtain the fault detection time; Step 2: Set the alarm indicator light to always be on and set the audible alarm to sound for a third duration followed by a fourth duration; wherein the third duration is longer than the first preset duration and the third duration is longer than the fourth duration. Step 3: Display the fault type abbreviation, target fault level, and fault detection time corresponding to the target fault type on the fault prompt screen.

[0067] For ease of description, the three steps above can be combined for explanation.

[0068] When a severe fault is identified, the fault detection time is obtained. This is achieved by keeping the alarm indicator light constantly on and setting the audible alarm to sound for a third duration followed by a fourth duration, with the third duration exceeding the first preset duration and also exceeding the fourth duration. The fault display screen scrolls to show the fault type abbreviation, target fault level, and fault detection time corresponding to the target fault type. By setting the alarm indicator light for severe faults to remain constantly on and setting the audible alarm duration to be longer, the system effectively conveys fault information and provides timely and effective alerts for severe faults.

[0069] See Figure 4 , Figure 4This is a flowchart illustrating another fault alarm method in this embodiment of the invention. The core working logic of the system is as follows: The CPLD / EC is responsible for controlling the power-on sequence of the computer, and works with the CPU and BIOS to complete the BIOS active measurement during the motherboard boot process, as well as memory training detection and diagnosis. During the platform power-on boot phase, the Trusted Root (TPCM / TCM) first initiates the BIOS active measurement process to perform integrity verification on the BIOS boot block, master image, key drivers, and configuration parameters. It calculates real-time hash digests using cryptographic algorithms (such as SM3 and SHA256) and compares them with a preset trusted baseline. It captures problems such as measurement verification failure, process interruption, and abnormal expansion of platform configuration registers, and preliminarily determines underlying anomalies such as BIOS firmware tampering, flash memory chip damage, SPI communication anomalies, and Trusted Root module failure. Simultaneously, the memory controller executes the memory training process, sequentially completing command address training, read / write balancing, voltage reference (Vref) calibration, eye diagram optimization, and margin testing. It monitors in real-time for abnormal states such as timing offsets, signal distortion, read / write errors, and calibration timeouts during the training process. Combining training stage, error type, and slot information, it diagnoses issues such as damaged memory chips, poor slot contact, motherboard wiring impedance mismatch, excessive power supply noise, memory incompatibility, and memory controller failure. Simultaneously, the peripheral detection unit performs comprehensive peripheral detection and diagnosis of the hard drive, optical drive, graphics card, fan, motherboard power supply, and external communication interfaces. In the default operating state, after the memory training test passes, the peripheral detection unit will perform initialization tests on various peripherals sequentially. If the memory and all peripherals pass the initialization tests, the system will start the system bootloader and enter normal operation. If any fault is detected, the BIOS will first determine the fault type and fault level, and then transmit the fault signal to the CPU. The CPU will send the fault type and fault level signal to the CPLD / EC through the TTL level debugging serial port. After receiving the fault signal, the CPLD / EC will write the fault information into the fault information storage unit for permanent storage, and on the other hand, drive the audible and visual alarm output circuit through the hierarchical control unit according to the fault level to execute the corresponding hierarchical audible and visual alarm action.

[0070] The peripheral device detection unit comprises three sub-modules: a power supply detection module, an interface detection module, and a general peripheral device detection module. The power supply detection module checks whether the voltage and current parameters of each power supply to the motherboard are within preset threshold ranges to determine if the motherboard power supply is normal. The interface detection module detects the communication status of external communication interfaces such as Universal Serial Bus (USB), Ethernet ports, and serial ports, identifying interface connection and data transmission faults. The general peripheral device detection module detects the operating status of general peripheral devices such as hard drives, optical drives, graphics cards, and fans, promptly identifying peripheral hardware faults.

[0071] In a specific application scenario, the specific workflow after the system is powered on may include: The CPLD / EC first controls the power-on sequence and starts the BIOS active measurement process. The CPU and CPLD / EC communicate via the SPI bus to complete the fault detection of the motherboard's underlying program. After the motherboard's underlying program detection is completed, the system enters the memory training, detection, and diagnostic phase. If memory training fails, the BIOS determines it as a severe fault and transmits the fault signal to the CPU. The CPU then sends the fault type and level signal to the CPLD / EC. The CPLD / EC immediately writes the fault occurrence time, fault type, and fault level to the non-volatile memory chip. Simultaneously, the hierarchical control unit drives the audible and visual alarm output circuit to execute a severe fault alarm action, namely, the red LED stays on, the frequency converter buzzer sounds continuously at high frequency, and the fault prompt screen scrolls to display "Memory Fault - Severe - XXXX.XX.XX XX:XX", where "XXXX.XX.XXXX:XX" represents the time. If the memory training test passes, the CPLD / EC will activate the peripheral detection unit and perform tests in the following order: "Power supply detection module → Interface detection module → Regular peripheral detection module". The power supply detection module detects the voltage and current parameters of each power supply to the motherboard, the interface detection module detects the communication status of external interfaces such as USB and network ports, and the regular peripheral detection module detects the working status of the hard drive, optical drive, graphics card and fan in sequence. Each module completes the fault detection by initializing the peripherals one by one and verifying whether the working parameters are within the preset threshold range. During peripheral device testing, if a moderate fault such as abnormal fan speed is detected, the BIOS determines the fault level, and the CPU sends a fault signal to the CPLD / EC. After the CPLD / EC completes the fault information storage, it drives the yellow LED to flash at a frequency of 0.5 seconds, the inverter buzzer emits a medium-frequency warning tone every 2 seconds, and the fault display screen shows "Fan Fault - Moderate". If a minor fault such as abnormal USB interface communication is detected, the CPLD / EC drives the green LED to flash at a frequency of 1 second, the buzzer emits a low-frequency warning tone every 5 seconds, and the fault display screen shows "USB Interface Fault - Minor". If a combined fault is detected, such as a hard drive fault (severe) and an optical drive fault (mild), the CPLD / EC will prioritize driving the audible and visual alarm output circuit according to the alarm logic of the severe fault. The red LED will be constantly lit, the buzzer will sound at a high frequency, and the fault display screen will first scroll to display the hard drive fault information, then display the optical drive fault information. At the same time, the complete information of the two faults will be written to the non-volatile memory chip in sequence. After the staff completes the repair, the computer is powered on again, and the system will perform a full-process fault detection again. If all detections pass, the CPLD / EC writes the fault repair information to the storage unit, the audible and visual alarms automatically stop, and the system enters normal operation. Staff can connect an external terminal to the CPLD / EC via the debugging serial port to read and export the fault information from the storage unit, enabling them to conduct equipment maintenance analysis and summarize fault patterns.

[0072] Corresponding to the above method embodiments, the present invention also provides a fault alarm device, and the fault alarm device described below can be referred to in correspondence with the fault alarm method described above.

[0073] See Figure 5 , Figure 5 This is a structural block diagram of a fault alarm device according to an embodiment of the present invention. The device may include: The underlying program fault detection module 51 is used to start the basic input / output system active measurement process to detect motherboard underlying program faults when the system is powered on. The memory training fault detection module 52 is used to perform memory training fault detection and obtain memory training fault detection results when the motherboard underlying program fault detection is completed. The peripheral detection module 53 is used to perform peripheral detection and obtain peripheral detection results when the memory training failure detection result is that the memory training detection is passed. The first fault alarm module 54 is used to generate the target fault level corresponding to the peripheral device detection result and to perform fault alarm using the fault alarm strategy corresponding to the target fault level; wherein, the target fault level is one of severe fault, moderate fault and mild fault. The second fault alarm module 55 is used to determine a severe fault when the obtained motherboard underlying program fault detection result and / or memory training fault detection result is a failure to pass the detection, and to use a severe fault alarm strategy to issue a fault alarm.

[0074] As can be seen from the above technical solution, by actively measuring the basic input / output system, conducting memory training and testing, and detecting peripherals, a comprehensive fault diagnosis of the computer is achieved. In addition to traditional peripheral testing such as memory and hard drives, motherboard testing is added, covering the core aspects of computer startup and operation, resulting in more comprehensive fault diagnosis and effectively avoiding missed faults. By setting fault classifications and corresponding graded fault alarm strategies, staff can quickly determine the urgency and general type of faults without requiring specialized hardware and software knowledge, significantly improving fault location efficiency. The integrated design of active measurement, fault diagnosis, and alarm output of the basic input / output system forms a complete computer fault detection and alarm system at the hardware and software level, solving the problems of single system function and low identification rate, and improving the computer's operational reliability and maintainability.

[0075] In one specific embodiment of the present invention, the underlying program fault detection module 51 is specifically a module that initiates the Basic Input / Output System Active Measurement Process to perform integrity verification on the Basic Input / Output System boot block, master image, key drivers and configuration parameters in order to perform motherboard underlying program fault detection.

[0076] In one specific embodiment of the present invention, the underlying program fault detection module 51 may include: The calculation result acquisition submodule is used to start the basic input / output system active measurement process. It uses cryptographic algorithms to perform hash digest calculations on the basic input / output system boot block, master image, key drivers and configuration parameters to obtain the calculation results. The comparison submodule is used to compare the calculation results with a preset trusted baseline.

[0077] In one specific embodiment of the present invention, the memory training fault detection module 52 is specifically a module that performs tests in the order of command address training test, read-write balancing test, reference voltage calibration test, eye diagram optimization test and margin test to detect memory training faults.

[0078] In one specific embodiment of the present invention, the first fault alarm module 54 may include: The fault level determination submodule is used to determine the target fault type based on the peripheral device detection results, and to determine the target fault level based on the target fault type. The first flashing frequency setting submodule is used to set the alarm indicator light to flash at a frequency of flashing for a first preset duration and then pausing for a first preset duration when the target fault level is a minor fault. The first display submodule is used to set the sound alarm to sound at a first time interval and to display the fault code corresponding to the target fault type on the fault prompt screen.

[0079] In one specific embodiment of the present invention, the first fault alarm module 54 may include: The second flashing frequency setting submodule is used to set the alarm indicator light to flash at a frequency of a second preset duration followed by a second preset duration when the target fault level is a medium fault; wherein, the second preset duration is less than the first preset duration. The second display submodule is used to set the sound alarm to sound at a second time interval, and to display the fault type abbreviation and target fault level corresponding to the target fault type on the fault prompt screen; wherein the second time interval is shorter than the first time interval.

[0080] In one specific embodiment of the present invention, the second fault alarm module 55 may include: The fault detection time acquisition submodule is used to acquire the fault detection time; The sound alarm submodule is used to set the alarm indicator light to a constant state and to set the sound alarm to sound for a third duration followed by a fourth duration; wherein the third duration is longer than the first preset duration and the third duration is longer than the fourth duration. The third display submodule is used to display the fault type abbreviation, target fault level, and fault detection time corresponding to the target fault type on a scrolling fault prompt screen.

[0081] For the method embodiments described above, see [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the fault alarm device provided by the present invention, which may include: Memory 332 is used to store computer programs; The processor 322 is used to implement the steps of the fault alarm method in the above method embodiment when executing a computer program.

[0082] For details, please refer to Figure 7 , Figure 7 This is a schematic diagram illustrating the specific structure of a fault alarm device provided in this embodiment. The fault alarm device can vary significantly due to differences in configuration or performance. It may include a processor (central processing unit, CPU) 322 (e.g., one or more processors) and a memory 332. The memory 332 stores one or more computer programs 342 or data 344. The memory 332 can be temporary or permanent storage. The program stored in the memory 332 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the data processing device. Furthermore, the processor 322 may be configured to communicate with the memory 332 and execute the series of instruction operations stored in the memory 332 on the fault alarm device 301.

[0083] The fault alarm device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input / output interfaces 358, and / or one or more operating systems 341.

[0084] The steps in the fault alarm method described above can be implemented by the structure of the fault alarm device.

[0085] Corresponding to the above method embodiments, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the following steps: When the system powers on, the Basic Input / Output System (BIOS) active measurement process is initiated to detect motherboard-level program faults. Once the motherboard-level program fault detection is complete, memory training fault detection is performed, yielding the results. If the memory training fault detection passes, peripheral device detection is performed, yielding the results. A target fault level corresponding to the peripheral device detection results is generated, and a fault alarm strategy corresponding to the target fault level is used to trigger an alarm. The target fault level is one of three: severe fault, moderate fault, or minor fault. If the obtained motherboard-level program fault detection result and / or memory training fault detection result are both failures, it is determined to be a severe fault, and a severe fault alarm strategy is used to trigger an alarm.

[0086] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] For a description of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0088] Corresponding to the above method embodiments, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the aforementioned fault alarm method.

[0089] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0090] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A failure alarm method characterized by comprising: include: When the system power-on is complete, the basic input / output system active measurement process is started to detect faults in the motherboard's underlying program. When the motherboard's underlying program fault detection is completed, memory training fault detection is performed to obtain the memory training fault detection results. When the memory training failure detection result is that the memory training detection is passed, peripheral device detection is performed to obtain the peripheral device detection result. Generate a target fault level corresponding to the peripheral device detection result, and use the fault alarm strategy corresponding to the target fault level to perform a fault alarm; wherein, the target fault level is one of severe fault, moderate fault, and minor fault; When the obtained motherboard underlying program fault detection result and / or the memory training fault detection result are both failures, it is determined to be a severe fault, and a fault alarm is triggered using the severe fault alarm strategy.

2. The fault alarm method according to claim 1, characterized in that, Initiate the Basic Input / Output System (BIOS) active measurement process to detect motherboard low-level program faults, including: The Basic Input / Output System Active Measurement Process is initiated to perform integrity verification on the Basic Input / Output System boot block, master image, key drivers, and configuration parameters in order to detect motherboard low-level program faults.

3. The fault alarm method according to claim 2, characterized in that, The Basic Input / Output System (BIOS) proactive measurement process is initiated to perform integrity checks on the BIOS boot block, master image, critical drivers, and configuration parameters, including: The active measurement process of the basic input / output system is initiated by performing hash digest calculations on the basic input / output system boot block, the master image, the key driver, and the configuration parameters using cryptographic algorithms to obtain the calculation results. The calculation results are compared with a preset trusted baseline.

4. The fault alarm method according to any one of claims 1 to 3, characterized in that, Perform memory training fault detection, including: The tests are performed in the following order: command address training test, read / write balancing test, reference voltage calibration test, eye diagram optimization test, and margin test, in order to detect memory training faults.

5. The fault alarm method according to claim 1, characterized in that, Generating a target fault level corresponding to the peripheral device detection result, and using a fault alarm strategy corresponding to the target fault level to perform a fault alarm, including: The target fault type is determined based on the peripheral device detection results, and the target fault level is determined based on the target fault type; When the target fault level is the minor fault, the alarm indicator light is set to flash at a frequency of flashing for a first preset duration and then pausing for the first preset duration. Set the audible alarm to sound at a first time interval and display the fault code corresponding to the target fault type on the fault display screen.

6. The fault alarm method according to claim 5, characterized in that, Fault alarms are generated using the fault alarm strategy corresponding to the target fault level, including: When the target fault level is the moderate fault, the alarm indicator light is set to flash at a frequency of flashing for a second preset duration followed by a pause for a second preset duration; wherein the second preset duration is less than the first preset duration. The sound alarm is set to sound an alarm at a second time interval, and the fault type abbreviation and the target fault level corresponding to the target fault type are displayed on the fault prompt screen; wherein the second time interval is shorter than the first time interval.

7. The fault alarm method according to claim 5, characterized in that, Fault alarms are generated using a severe fault alarm strategy, including: Obtain the fault detection time; The alarm indicator light is set to a constant-on state, and the sound alarm is set to sound for a third duration followed by a fourth duration; wherein the third duration is longer than the first preset duration, and the third duration is longer than the fourth duration. The fault indication screen displays the fault type abbreviation corresponding to the target fault type, the target fault level, and the fault detection time in a scrolling manner.

8. A fault alarm device, characterized in that, include: The underlying program fault detection module is used to start the basic input / output system active measurement process to detect motherboard underlying program faults when the system is powered on. The memory training fault detection module is used to perform memory training fault detection and obtain memory training fault detection results when the motherboard's underlying program fault detection is completed. The peripheral detection module is used to perform peripheral detection and obtain peripheral detection results when the memory training failure detection result is that the memory training detection is passed. The first fault alarm module is used to generate a target fault level corresponding to the peripheral device detection result, and to perform a fault alarm using a fault alarm strategy corresponding to the target fault level; wherein, the target fault level is one of severe fault, moderate fault, and mild fault; The second fault alarm module is used to determine the severe fault when the obtained motherboard underlying program fault detection result and / or the memory training fault detection result is a failure to pass the detection, and to perform a fault alarm using a severe fault alarm strategy.

9. A fault alarm device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the fault alarm method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the fault alarm method as described in any one of claims 1 to 7.

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