High-speed clock signal waveform reconstruction method and system, electronic device, medium and program product

Abstract

The application provides a high-speed clock signal waveform reconstruction method and system, electronic equipment, medium and program product, the method comprises the following steps: generating a low-speed sampling clock signal; at the preset fixed time of each cycle of the low-speed sampling clock signal, asynchronously equivalent time sampling is performed on the high-speed to-be-sampled clock signal to obtain a plurality of sampling points; during the asynchronous sampling process, based on the frequency difference, the equivalent phase of each sampling point relative to the high-speed to-be-sampled clock signal is synchronously calculated; the equivalent phase corresponding to all sampling points is mapped into at least one cycle of the high-speed to-be-sampled clock signal to reconstruct the actual waveform of the high-speed to-be-sampled clock signal. The application adopts the strategy of asynchronous equivalent time sampling combined with statistical reconstruction, and only needs to use a low-speed clock signal to perform high-resolution waveform reconstruction on a high-speed clock signal, breaks through the traditional "measuring low frequency with high frequency" measurement paradigm, and innovatively constructs a "measuring fast with slow" technical path.

Description

Technical Field

[0001] This application belongs to the field of signal acquisition and reconstruction technology, specifically relating to a high-speed clock signal waveform reconstruction method and system, electronic equipment, medium and program products. Background Technology

[0002] In modern communication systems, high-performance computing platforms, and industrial automation equipment, accurate measurement of high-speed clock signals (e.g., frequencies of 250 MHz and above) is a key technological foundation for achieving system synchronization, performance evaluation, and fault diagnosis.

[0003] Currently, the industry mainly uses two traditional methods to measure high-speed clock signals: one is to directly count the number of pulses per unit time using a high-speed counter; the other is to sample the clock signal in real time using a high sampling rate analog-to-digital converter (ADC) and then use digital signal processing algorithms to complete the subsequent analysis.

[0004] However, both of these traditional methods have significant technical limitations. First, the high-speed counter scheme requires its internal logic circuit to operate at a frequency significantly higher than the frequency of the clock signal being measured. This not only increases hardware design complexity but also leads to high costs and high power consumption, making it unsuitable for resource-constrained embedded systems or system-on-a-chip (SoC). Second, while the analog-to-digital converter (ADC) scheme can acquire complete waveform information, it also faces problems such as limited analog front-end bandwidth, high cost and power consumption of ADC devices, and stringent requirements for signal integrity. More importantly, when dealing with extremely high-frequency clock signals, the measurement accuracy and time resolution of both methods are directly limited by the physical performance bottlenecks of existing hardware, making further breakthroughs difficult and thus restricting the overall testing capability and reliability of the system.

[0005] To achieve high-precision, high-speed clock signal measurement, the key lies in the ability to completely reconstruct the waveform of the measured signal with a sufficiently high time resolution. Therefore, there is an urgent need in this field to achieve high-precision, low-power, and low-cost waveform reconstruction without relying on ultra-high-frequency counters or expensive ADCs, in order to meet the increasingly stringent requirements of future high-performance electronic systems for clock signal measurement. Summary of the Invention

[0006] This application provides a high-speed clock signal waveform reconstruction method and system, electronic device, medium and program product, to solve the technical problems of high cost, high power consumption, difficulty in integration and low measurement accuracy caused by the reliance on expensive hardware in the prior art.

[0007] In a first aspect, this application provides a high-speed clock signal waveform reconstruction method, including:

[0008] Generate a low-speed sampling clock signal;

[0009] At preset fixed times in each cycle of the low-speed sampling clock signal, the high-speed clock signal to be sampled is asynchronously sampled using equivalent time to obtain multiple sampling points; each sampling point includes a sampling level value and a corresponding sampling time.

[0010] During asynchronous sampling, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is synchronously calculated based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal.

[0011] The equivalent phase corresponding to all sampling points is mapped to at least one cycle of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

[0012] In one implementation of the first aspect, during asynchronous sampling, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is synchronously calculated based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal, including:

[0013] The estimated frequency of the high-speed clock signal to be sampled is multiplied by the sampling time of each sampling point to obtain the cumulative phase of each sampling point at the corresponding sampling time; the cumulative phase includes an integer part and a fractional part, wherein the integer part corresponds to the number of complete cycles experienced by the high-speed clock signal to be sampled, and the fractional part represents the normalized instantaneous phase;

[0014] The normalized instantaneous phase is modulo 1 to obtain the equivalent phase of each sampling point relative to the high-speed clock signal to be sampled.

[0015] One implementation of the first aspect also includes:

[0016] The ratio between the frequency difference and the frequency of the low-speed sampling clock signal is defined as the phase step coefficient;

[0017] The normalized instantaneous phase of each sampling point is obtained by multiplying the phase step coefficient by the index of each sampling point.

[0018] In one implementation of the first aspect, the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal satisfies:

[0019] ;

[0020] in The frequency of the low-speed sampling clock signal, The estimated frequency of the high-speed clock signal to be sampled; Let N be the frequency difference, where N is a positive integer.

[0021] In one implementation of the first aspect, mapping the equivalent phase corresponding to all sampling points to at least one period of the high-speed clock signal to be sampled, in order to reconstruct the actual waveform of the high-speed clock signal to be sampled, includes:

[0022] The equivalent phase corresponding to all sampling points is normalized to at least one cycle of the high-speed clock signal to be sampled, to obtain the normalized equivalent phase.

[0023] Sort all sampling points in ascending order according to the normalized equivalent phase to obtain the sorted sampling point sequence;

[0024] The sampling level values ​​corresponding to each sampling point are rearranged according to the sorted sampling point sequence to obtain the waveform of the high-speed clock signal to be sampled within at least one cycle.

[0025] One implementation of the first aspect also includes:

[0026] Edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled, and the edge feature analysis results are obtained.

[0027] Based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified.

[0028] Based on the interpolation algorithm, the zero-crossing moments are refined in time; the time resolution of the zero-crossing moments after time refinement reaches the preset target resolution requirement.

[0029] In one implementation of the first aspect, the interpolation algorithm includes at least one of linear interpolation, spline interpolation, or band-limited interpolation.

[0030] One implementation of the first aspect also includes:

[0031] Edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled, and the edge feature analysis results are obtained.

[0032] Based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified.

[0033] Based on the zero-crossing time, the time interval between two adjacent edges of the same type is calculated, and the time interval is defined as the single-cycle value of the high-speed sampling clock signal;

[0034] Based on the single-cycle value, the actual frequency of the high-speed sampling clock signal is obtained by taking its reciprocal.

[0035] Within a single cycle, the ratio of the high-level pulse width to the single-cycle value is calculated to obtain the duty cycle of the high-speed sampling clock signal;

[0036] Multiple consecutive single-cycle values ​​are obtained, and the offset of each single-cycle value relative to the average single-cycle value is calculated. The offset is defined as the period jitter of the high-speed sampling clock signal.

[0037] One implementation of the first aspect also includes:

[0038] Determine the maximum allowable phase change rate based on the preset measurement accuracy requirements;

[0039] Based on the preset response time constraint, determine the minimum allowable phase change rate;

[0040] The frequency of the low-speed sampling clock signal is dynamically adjusted in real time by combining the maximum phase change rate and the minimum phase change rate.

[0041] One implementation of the first aspect also includes:

[0042] Configure multiple low-speed sampling circuits, and the low-speed sampling clock signals generated by each low-speed sampling circuit have a preset and fixed phase offset relative to the same reference clock;

[0043] The multi-channel low-speed sampling circuit is divided into a coarse sampling group and a fine sampling group, wherein the sampling time interval of the coarse sampling group is a first time resolution, the sampling time interval of the fine sampling group is a second time resolution, and the first time resolution is greater than the second time resolution.

[0044] The coarse sampling group and the fine sampling group are controlled to perform asynchronous equivalent time sampling operations on the high-speed clock signal to be sampled in parallel, so as to obtain coarse-grained sampling data and fine-grained sampling data respectively.

[0045] The initial waveform of the high-speed clock signal to be sampled is constructed based on the coarse-grained sampling data, and the initial waveform is locally refined by combining the fine-grained sampling data.

[0046] One implementation of the first aspect also includes:

[0047] During waveform reconstruction, the distribution characteristics of the sampling points are monitored in real time.

[0048] When the distribution of the sampling points deviates from the preset pattern, it is determined to be an abnormal state;

[0049] In response to the abnormal state, an alarm signal is generated, and the system switches to a coarse measurement mode; the coarse measurement mode uses a reduced time resolution or a reduced sampling point density for waveform acquisition;

[0050] After completing waveform acquisition for a preset duration in the coarse measurement mode, the system automatically returns to the initial waveform reconstruction process based on asynchronous equivalent time sampling.

[0051] Secondly, this application provides a high-speed clock signal waveform reconstruction system, comprising:

[0052] The sampling clock generation module is used to generate a low-speed sampling clock signal;

[0053] The sampling module for the clock signal to be sampled is used to asynchronously sample the high-speed clock signal to be sampled at preset fixed times in each period of the low-speed sampling clock signal to obtain multiple sampling points; each sampling point includes a sampling level value and a corresponding sampling time.

[0054] The equivalent phase calculation module is used to synchronously calculate the equivalent phase of each sampling point relative to the high-speed sampling clock signal during asynchronous sampling, based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal.

[0055] The waveform reconstruction module is used to map the equivalent phase corresponding to all sampling points to at least one cycle of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

[0056] Thirdly, this application provides an electronic device, comprising:

[0057] The memory is used to store computer programs;

[0058] A processor, the processor being configured to execute a computer program stored in the memory, so as to cause the electronic device to perform the method described in any of the preceding descriptions.

[0059] Fourthly, this application provides a computer-readable storage medium storing executable instructions for implementing the method described in any of the above-mentioned embodiments when executed by a processor.

[0060] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method described in any of the above-mentioned embodiments.

[0061] As described above, the high-speed clock signal waveform reconstruction method and system, electronic device, medium, and program product described in this application have the following beneficial effects:

[0062] (1) It does not rely on expensive high-speed counters or high sampling rate analog-to-digital converters. It can achieve high-precision waveform reconstruction of GHz-level high-speed clock signals using only low-speed clock signals, which greatly reduces system complexity, power consumption and manufacturing costs. At the same time, it has good integrability and is easy to embed into SoC on-chip systems.

[0063] (2) Based on the principle of asynchronous equivalent time sampling and statistical reconstruction, the high-frequency time domain measurement problem is transformed into a phase calculation problem under low-frequency signals. By accumulating a large number of asynchronous sampling points and combining them with interpolation algorithms, picosecond-level time resolution can be achieved, and the measurement accuracy far exceeds the theoretical limit of traditional low-speed hardware.

[0064] (3) By dynamically adjusting the frequency of the low-speed sampling clock signal, the drift rate of the equivalent phase can be precisely controlled, thereby achieving an adaptive trade-off between the measurement accuracy of waveform reconstruction and the system response time. Attached Figure Description

[0065] Figure 1 The flowchart shown is a high-speed clock signal waveform reconstruction method according to an embodiment of this application.

[0066] Figure 2 The diagram shown is a flowchart of the mapping of equivalent phases according to an embodiment of this application.

[0067] Figure 3 The flowchart shown is a time refinement process for the actual waveform of a high-speed clock signal to be sampled, according to an embodiment of this application.

[0068] Figure 4 The flowchart shown is a process for calculating parameters of the actual waveform of a high-speed clock signal to be sampled, according to an embodiment of this application.

[0069] Figure 5 The flowchart shown is a process for dynamically adjusting the frequency of a low-speed sampling clock signal according to an embodiment of this application.

[0070] Figure 6 The flowchart shown is a coarse / fine dual-mode sampling strategy according to an embodiment of this application.

[0071] Figure 7 The flowchart shown is an example of an anomaly detection and fault-tolerant recovery mechanism according to an embodiment of this application.

[0072] Figure 8 The diagram shows the actual waveform of a high-speed clock signal to be sampled according to an embodiment of this application.

[0073] Figure 9 The diagram shown is a structural schematic of a high-speed clock signal waveform reconstruction system according to an embodiment of this application.

[0074] Figure 10The diagram shown is a structural schematic of an electronic device according to an embodiment of this application. Detailed Implementation

[0075] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0076] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] The following embodiments of this application provide a high-speed clock signal waveform reconstruction method and system, electronic device, medium, and program product. This solution employs an asynchronous equivalent time sampling combined with statistical reconstruction strategy, requiring only a low-speed clock signal to perform high-resolution waveform reconstruction of a high-speed clock signal. This breaks through the traditional paradigm of "measuring low frequency with high frequency" and innovatively constructs a technical path of "measuring fast with slow."

[0078] Compared to traditional solutions, this application does not rely on expensive high-speed counters or high sampling rate analog-to-digital converters. It can achieve high-precision waveform reconstruction of GHz-level high-speed clock signals using only low-speed clock signals, which greatly reduces system complexity, power consumption and manufacturing costs. At the same time, it has good integrability and is easy to embed into SoC systems on the chip.

[0079] The following will describe in detail the principles and implementation methods of a high-speed clock signal waveform reconstruction method and system, electronic device, medium and program product of this embodiment, so that those skilled in the art can understand the high-speed clock signal waveform reconstruction method and system, electronic device, medium and program product of this embodiment without creative labor.

[0080] Please see Figure 1 The above is a flowchart of a high-speed clock signal waveform reconstruction method according to an embodiment of this application.

[0081] like Figure 1 As shown, this embodiment provides a high-speed clock signal waveform reconstruction method, including the following steps S100 to S400.

[0082] In step S100, a low-speed sampling clock signal is generated.

[0083] In one embodiment of this application, the low-speed sampling clock signal is used to sample the high-speed clock signal to be sampled. Both the low-speed sampling clock signal and the high-speed clock signal to be sampled are repetitive and periodic signals. The frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed clock signal to be sampled satisfies:

[0084] ;

[0085] in The frequency of the low-speed sampling clock signal, The estimated frequency of the high-speed clock signal to be sampled is... Let N be the frequency difference, where N is a positive integer.

[0086] It should be noted that this application does not know the actual frequency value of the high-speed clock signal to be sampled in advance. In practical applications, it is usually necessary to obtain its estimated frequency using coarse measurement methods, which serves as the initial parameter for subsequent equivalent time sampling and waveform reconstruction processes. For example, in a certain communication or interface protocol, the nominal operating clock value of the high-speed clock signal to be sampled is explicitly specified as 250 MHz. In such scenarios, the estimated frequency of the high-speed clock signal to be sampled can be... Set it to 250 MHz, and select accordingly. With an integer N, the frequency difference It is small enough to meet the preset conditions for equivalent time sampling. Subsequently, through the proposed waveform reconstruction process, the system can not only verify whether the actual clock frequency is indeed close to 250 MHz, but also accurately reproduce its true frequency, duty cycle and period jitter, thereby achieving closed-loop verification and calibration from "rough estimation" to "fine measurement".

[0087] In this embodiment, the frequency difference This determines the phase drift rate of the sampling point within the high-speed clock signal cycle.

[0088] Specifically, if the frequency difference If the value is too large, the phase drift will be too fast, resulting in an excessively long sampling interval. This may result in only sparse sampling points within a complete cycle. This could lead to incomplete waveform coverage, loss of details, and ultimately, distortion of the reconstructed waveform.

[0089] If frequency difference If the sampling interval is too small, the phase drift will be too slow, resulting in an excessively short sampling interval. While theoretically higher resolution sampling points can be obtained, an extremely long acquisition time is required to traverse the entire high-speed clock signal cycle. This not only significantly reduces the system's response speed and real-time performance but also greatly increases the data caching requirements and backend computing burden, which is particularly detrimental to embedded or resource-constrained platforms.

[0090] Therefore, in engineering practice, a balance must be struck between measurement accuracy, acquisition time, and system resource consumption. Based on practical application experience, this application selects an appropriate frequency difference. This enables the acquisition of a sufficient number of equivalent sampling points to support high-fidelity waveform reconstruction; at the same time, it keeps the acquisition and processing delays within an acceptable range, meeting the near-real-time requirements of most application scenarios such as communication, testing, or monitoring.

[0091] In one embodiment of this application, a low-speed sampling clock frequency is set. =9.999MHz, estimated frequency of the high-speed clock signal to be sampled =250MHz. At this time, the frequency of the low-speed sampling clock signal... Estimated frequency of the high-speed clock signal to be sampled Frequency difference between = |250MHz-25×9.999MHz| = 0.025MHz.

[0092] The resulting phase drift characteristics are as follows:

[0093] (1) Phase drift rate: After each low-speed sampling cycle, the phase shift of the sampling point in the high-speed cycle is 0.01% (i.e., = ).

[0094] (2) Phase drift period: The time required for the sampling point to complete one high-speed clock cycle is Tdrift = 1 / Δf = 1 / 0.025MHz = 40ms.

[0095] (3) Number of sampling points: Within 40ms, the low-speed sampling clock signal triggers a total of M = 9.999MHz × 40ms ≈399,960 sampling points.

[0096] (4) Sampling density: Since 10,000,000 cycles of a high-speed clock signal with a frequency of 250MHz can be covered within 40ms, the number of sampling points corresponding to each high-speed clock signal cycle is K = 399,960 / 10,000,000 ≈ 0.04.

[0097] It should be noted that the high-speed clock signal to be sampled in this application is not only applicable to frequencies in the MHz range, but can also be effectively extended to the GHz range and even higher frequencies, thus having broad applicability. This application does not limit the specific frequency range of the high-speed clock signal to be sampled.

[0098] In step S200, at preset fixed times of each cycle of the low-speed sampling clock signal, the high-speed clock signal to be sampled is asynchronously sampled using equivalent time to obtain multiple sampling points.

[0099] The core of asynchronous equivalent time sampling lies in using a low-speed sampling clock signal that is not at the same frequency as the high-speed clock signal to be sampled and is not synchronized with it. Samples are gradually acquired in multiple signal cycles, and high-resolution reconstruction of the periodic waveform of the high-speed clock signal is achieved by accumulating phase offset.

[0100] Because the low-speed sampling clock signal is asynchronous with the high-speed sampling clock signal and their frequencies are not integer multiples of each other, the phase position of each low-speed sampling moment relative to the period of the high-speed clock signal will experience a small but predictable "drift". This drift is not noise or error, but a systematic phase shift that accumulates linearly over time.

[0101] Furthermore, since the high-speed clock signal to be sampled has strict periodicity, although a single sampling only obtains the state of the high-speed signal at a certain instant, through long-term accumulation, these discrete sampling points together cover each phase region within the entire high-speed clock signal period, thus forming a "sparse but complete" sampling set of the original high-speed waveform.

[0102] In one embodiment of this application, sampling of the high-speed sampling clock signal can be triggered by the rising or falling edge of each cycle of the low-speed sampling clock signal.

[0103] In one embodiment of this application, each sampling point includes a sampling level value and a corresponding sampling time. For example, for the kth sample point, ∈[1,2,3,…], and the corresponding sampling times are: = The sampling level value refers to the logic state of the high-speed clock signal to be sampled at the sampling time. For example, when the high-speed clock signal to be sampled is a square wave, the sampling level value is 0 or 1.

[0104] In this embodiment, the sampling time This refers to the physical moment on the global absolute time axis. All sampling points are uniformly distributed across absolute time. To achieve high-fidelity waveform reconstruction, the system needs to acquire a sufficient number of sampling points to obtain a sufficient equivalent sampling density within one cycle of the high-speed clock signal. For example, to achieve high-fidelity waveform reconstruction, it is generally recommended to set the equivalent sampling density to no less than 50 points per cycle, and further optimize it according to specific signal characteristics and application accuracy requirements.

[0105] In step S300, during the asynchronous sampling process, based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is calculated synchronously.

[0106] The equivalent phase represents the relative position of a certain low-speed sampling moment with respect to the period of the high-speed clock signal.

[0107] In one embodiment of this application, during asynchronous sampling, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is synchronously calculated based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal, including the following steps S301 and S302.

[0108] In step S301, the estimated frequency of the high-speed clock signal to be sampled is multiplied by the sampling time of each sampling point to obtain the cumulative phase of each sampling point at the corresponding sampling time; the cumulative phase includes an integer part and a fractional part, wherein the integer part corresponds to the number of complete cycles experienced by the high-speed clock signal to be sampled, and the fractional part represents the normalized instantaneous phase.

[0109] For example, for the k-th sampling point, the cumulative phase of the sampling point at the corresponding sampling time can be calculated using the following formula:

[0110] × =( × )× =( × )× = × ;

[0111] in The cumulative phase at the k-th sampling point is represented by... The estimated frequency of the high-speed clock signal to be sampled is... This represents the sampling time corresponding to the k-th sampling point. ∈[1,2,3,…], The frequency of the low-speed sampling clock signal is N, where N is a positive integer. The integer part of the frequency difference × The fractional part corresponds to the number of complete cycles experienced by the high-speed clock signal to be sampled. This represents the normalized instantaneous phase.

[0112] In step S302, the normalized instantaneous phase is modulo 1 to obtain the equivalent phase of each sampling point relative to the high-speed clock signal to be sampled.

[0113] For example, the equivalent phase of the k-th sampling point relative to the high-speed clock signal to be sampled can be expressed as:

[0114] =( )mod1.

[0115] In one embodiment of this application, the application further includes steps S303 and S304.

[0116] In step S303, the ratio between the frequency difference and the frequency of the low-speed sampling clock signal is defined as the phase step coefficient.

[0117] In step S304, the phase step coefficient is multiplied by the index of each sampling point to obtain the normalized instantaneous phase of each sampling point.

[0118] Specifically, based on the embodiments in steps S301 and S302, Defined as the phase step coefficient δ, the accumulated phase can then be expressed as:

[0119] × = × δ× .

[0120] Next, the normalized instantaneous phase is modulo 1 to obtain the equivalent phase of the k-th sampling point relative to the high-speed clock signal to be sampled:

[0121] =(δ× )mod1.

[0122] For example, in the above embodiments, the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal... = 0.025MHz. When the sampling point number k = 1, 2, 3, their corresponding sampling times are respectively With equivalent phase As shown in Table 1.

[0123] Table 1. Statistics of Sampling Time and Equivalent Phase at Different Sampling Points

[0124] 1 1 / 9.999MHz 1 × 0.00250025 = 0.00250025 = 0.250025% 2 2 / 9.999MHz 2 × 0.00250025 = 0.00500050 = 0.500050% 3 3 / 9.999MHz 3 × 0.00250025 = 0.00750075 = 0.750075%

[0125] In step S400, the equivalent phase corresponding to all sampling points is mapped to at least one period of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

[0126] Please see Figure 2 The diagram shows a flowchart of the equivalent phase mapping according to an embodiment of this application.

[0127] like Figure 2 As shown, mapping the equivalent phase corresponding to all sampling points to at least one period of the high-speed clock signal to be sampled, in order to reconstruct the actual waveform of the high-speed clock signal to be sampled, includes the following steps S401 to S403.

[0128] In step S401, the equivalent phase corresponding to all sampling points is normalized to at least one period of the high-speed clock signal to be sampled, so as to obtain the normalized equivalent phase.

[0129] Equivalent phase normalization can eliminate cross-cycle redundancy and provide a unified phase reference for subsequent waveform reconstruction.

[0130] In step S402, all sampling points are sorted in ascending order according to the normalized equivalent phase to obtain a sorted sampling point sequence.

[0131] This sorting process establishes the correct timing relationship of the sampling points within the high-speed clock signal period.

[0132] In step S403, the sampling level values ​​corresponding to each sampling point are rearranged according to the sorted sampling point sequence to obtain the waveform of the high-speed clock signal to be sampled within at least one cycle.

[0133] In some embodiments, if the sampling points cover more than one high-speed signal cycle, a single typical cycle waveform can be extracted by period folding or sliding window method to improve the stability and representativeness of the reconstruction results.

[0134] In one embodiment of this application, the high-speed clock signal waveform reconstruction method provided by this application further includes time refinement processing of the actual waveform of the reconstructed high-speed clock signal to be sampled, specifically including the following steps S500 to S502.

[0135] Please see Figure 3The above is a flowchart illustrating the time refinement process of the actual waveform of a high-speed clock signal to be sampled, according to an embodiment of this application.

[0136] In step S500, edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled to obtain the edge feature analysis result.

[0137] Specifically, the sorted sequence of sampling points is traversed to identify the locations where the sampling level values ​​transition, i.e., the rising edge region transitioning from low level ("0") to high level ("1"), or the falling edge region transitioning from high level to low level. By detecting changes in the level states of adjacent sampling points, local sampling intervals containing edge transitions are determined, and the normalized equivalent phase of each sampling point within this interval and its corresponding sampling level value are recorded to form the edge feature analysis results.

[0138] In step S501, based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified.

[0139] Based on the edge feature analysis results, within each identified rising or falling edge region, the positioning level crosses a rough position of a logic threshold (typically 0.5, corresponding to the decision midpoint of the digital signal). Specifically, if two adjacent sampling points exist... and If #imgpt64#=0, #imgpt65#=1 (rising edge) or #imgpt66#=1, #imgpt67#=0 (falling edge), then the zero-crossing point of the edge is determined to be within the phase interval corresponding to the two.

[0140] In step S502, based on the interpolation algorithm, the zero-crossing time is refined in time; the time resolution of the zero-crossing time after time refinement reaches the preset target resolution requirement.

[0141] Specifically, the interpolation algorithm includes at least one of linear interpolation, spline interpolation, or band-limited interpolation.

[0142] In this implementation, since the equivalent time sampling mechanism itself can provide sub-period-level phase resolution, combined with the above interpolation processing, the time measurement accuracy can be improved to the picosecond level.

[0143] In one embodiment of this application, the high-speed clock signal waveform reconstruction method provided by this application further includes parameter calculation of the actual waveform of the reconstructed high-speed clock signal to be sampled, specifically including the following steps S600 to S605.

[0144] Please see Figure 4The above is a flowchart illustrating parameter calculation of the actual waveform of a high-speed clock signal to be sampled, according to an embodiment of this application.

[0145] In step S600, edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled to obtain the edge feature analysis result.

[0146] In step S601, based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified.

[0147] It should be noted that the implementation principles of steps S600 and S601 correspond to those of steps S500 and S501 mentioned above, and will not be elaborated here to avoid repetition.

[0148] In step S602, based on the zero-crossing time, the time interval between two adjacent edges of the same type is calculated, and the time interval is defined as the single-cycle value of the high-speed sampling clock signal.

[0149] In step S603, the actual frequency of the high-speed clock signal to be sampled is obtained by taking the reciprocal of the single-cycle value.

[0150] In step S604, within a single cycle, the ratio of the high-level pulse width to the single-cycle value is calculated to obtain the duty cycle of the high-speed sampling clock signal.

[0151] In step S605, multiple consecutive single-cycle values ​​are obtained, and the offset of each single-cycle value relative to the average single-cycle value is calculated. The offset is defined as the period jitter of the high-speed sampling clock signal.

[0152] In this implementation, through steps S600 to S605, parameters such as the frequency, period, duty cycle, and period jitter of the high-speed clock signal can be calculated. These parameters can serve as important inputs for key aspects such as system performance evaluation, clock calibration, and fault diagnosis, significantly improving the technical capabilities and engineering practicality of embedded testing and high-speed interface monitoring.

[0153] In one embodiment of this application, the high-speed clock signal waveform reconstruction method provided by this application further includes real-time dynamic adjustment of the frequency of the low-speed sampling clock signal, specifically including the following steps S700 to S702.

[0154] Please see Figure 5 The above is a flowchart illustrating the dynamic adjustment of the low-speed sampling clock signal frequency according to an embodiment of this application.

[0155] In step S700, the maximum allowable phase change rate is determined according to the preset measurement accuracy requirements.

[0156] The maximum phase change rate is used to characterize the maximum permissible offset of the equivalent phase relative to the period of the high-speed sampled clock signal between two adjacent samples.

[0157] In step S701, the minimum allowable phase change rate is determined based on a preset response time constraint.

[0158] The minimum phase change rate is used to ensure that, within an acceptable time window, the equivalent phase can fully traverse the entire high-speed clock signal period interval, thereby achieving effective sampling.

[0159] In step S702, the frequency of the low-speed sampling clock signal is dynamically adjusted in real time by combining the maximum phase change rate and the minimum phase change rate.

[0160] In this implementation, the frequency of the low-speed sampling clock signal is dynamically adjusted in real time so that the phase change rate of the sampling point is always maintained within the optimal phase drift range [minimum phase change rate, maximum phase change rate].

[0161] In one embodiment of this application, the high-speed clock signal waveform reconstruction method provided in this application further includes a coarse / fine dual-mode sampling strategy, specifically including the following steps S800 to S803.

[0162] Please see Figure 6 The above is a flowchart of a coarse / fine dual-mode sampling strategy according to an embodiment of this application.

[0163] In step S800, multiple low-speed sampling circuits are configured, and the low-speed sampling clock signals generated by each low-speed sampling circuit have a preset and fixed phase offset relative to the same reference clock.

[0164] In step S801, the multi-channel low-speed sampling circuit is divided into a coarse sampling group and a fine sampling group, wherein the sampling time interval of the coarse sampling group is a first time resolution, the sampling time interval of the fine sampling group is a second time resolution, and the first time resolution is greater than the second time resolution.

[0165] In step S802, the coarse sampling group and the fine sampling group are controlled to perform asynchronous equivalent time sampling operations on the high-speed clock signal to be sampled in parallel, so as to obtain coarse-grained sampling data and fine-grained sampling data respectively.

[0166] In step S803, an initial waveform of the high-speed clock signal to be sampled is constructed based on the coarse-grained sampling data, and the initial waveform is locally refined in combination with the fine-grained sampling data.

[0167] In this implementation, by configuring multiple low-speed sampling circuits and adopting a coarse / fine dual-mode sampling strategy, the coarse sampling group ensures fast waveform acquisition capability, while the fine sampling group provides picosecond-level detail resolution in key areas. This significantly improves the engineering applicability and performance ceiling of the equivalent time sampling technology without significantly increasing the hardware complexity of a single channel.

[0168] In one embodiment of this application, the high-speed clock signal waveform reconstruction method provided by this application further includes introducing an anomaly detection and fault-tolerant recovery mechanism during the waveform reconstruction process, specifically including the following steps S900 to S903.

[0169] Please see Figure 7 The above is a flowchart of an anomaly detection and fault-tolerant recovery mechanism according to an embodiment of this application.

[0170] In step S900, during the waveform reconstruction process, the distribution characteristics of the sampling points are monitored in real time.

[0171] Specifically, the distribution characteristics include: the sampling points appearing significantly sparse or excessively clustered in local phase intervals, indicating uneven phase coverage; the phase jump amplitude between adjacent sampling points being too large, possibly reflecting abnormal clock jitter or sampling synchronization failure; certain specific phase regions not being updated for a long time, resulting in blind spots in waveform reconstruction; the sampling point sequence exhibiting a non-random periodic pattern, suggesting that there may be an approximately integer multiple frequency relationship between the sampling clock and the signal under test, thereby undermining the randomness assumption of equivalent time sampling.

[0172] In step S901, when the distribution of the sampling points is detected to deviate from the preset pattern, it is determined to be an abnormal state.

[0173] For example, if the phase coverage is below a threshold, local voids exceed the tolerance window, or the phase drift rate abruptly exceeds a preset threshold, the system determines that it is currently in an abnormal state.

[0174] In step S902, in response to the abnormal state, an alarm signal is generated and the system is switched to coarse measurement mode.

[0175] In one embodiment of this application, the coarse measurement mode employs reduced temporal resolution or reduced sampling point density for waveform acquisition.

[0176] In other embodiments, the coarse measurement mode may also employ a direct time-domain measurement method with non-equivalent time sampling, including: period counting, pulse width measurement, or long pulse duration conversion counting of a high-speed clock signal.

[0177] In step S903, after the waveform acquisition of the preset duration is completed in the coarse measurement mode, the process automatically returns to the initial waveform reconstruction process based on asynchronous equivalent time sampling.

[0178] The system runs continuously for a preset duration in the coarse measurement mode, during which it continuously evaluates the signal stability. If the coarse measurement results indicate that the signal has returned to stability (e.g., periodic fluctuations converge and there are no frequent jumps), the system automatically exits the coarse measurement mode and seamlessly returns to the initial high-precision waveform reconstruction process based on asynchronous equivalent time sampling, restarting high-resolution sampling and waveform reconstruction.

[0179] Please see Figure 8 The image shown is a schematic diagram of the actual waveform of a high-speed clock signal to be sampled according to an embodiment of this application.

[0180] like Figure 8 As shown, sampling points of different colors represent sampling periods. By mapping these sampling points to one period of the high-speed clock signal, the actual waveform of the high-speed clock signal to be sampled can be reconstructed.

[0181] In this implementation, by introducing a coarse measurement mode, it is possible to effectively avoid getting stuck in invalid or erroneous high-precision sampling loops during signal anomalies or system disturbances, preventing resource waste, data distortion, or even system deadlock caused by continuously attempting to reconstruct unstable waveforms. Simultaneously, the coarse measurement mode, as a safety degradation mechanism, still provides basic timing parameters, ensuring the system's basic monitoring capabilities. Once the environment recovers, the system can automatically return to its high-precision operating state, achieving intelligent fault tolerance and self-recovery, significantly enhancing the engineering robustness and long-term operational reliability of the entire waveform reconstruction method in real-world complex electronic systems.

[0182] It should be noted that the protection scope of the high-speed clock signal waveform reconstruction method described in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the protection scope of this application.

[0183] Please see Figure 9 The diagram shows a schematic representation of a high-speed clock signal waveform reconstruction system according to an embodiment of this application.

[0184] like Figure 9 As shown in the figure, this application provides a high-speed clock signal waveform reconstruction system, including a sampling clock generation module, a sampling module for the clock to be sampled, an equivalent phase calculation module, and a waveform reconstruction module.

[0185] The sampling clock generation module is used to generate a low-speed sampling clock signal.

[0186] The sampling module for the clock signal to be sampled is used to perform asynchronous equivalent time sampling on the high-speed clock signal to be sampled at preset fixed times in each period of the low-speed sampling clock signal to obtain multiple sampling points; each sampling point includes a sampling level value and a corresponding sampling time.

[0187] The equivalent phase calculation module is used to synchronously calculate the equivalent phase of each sampling point relative to the high-speed sampling clock signal during asynchronous sampling, based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal.

[0188] The waveform reconstruction module is used to map the equivalent phase corresponding to all sampling points to at least one cycle of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

[0189] It should be noted that the structure and principle of the sampling clock generation module, the sampling module of the clock to be sampled, the equivalent phase calculation module and the waveform reconstruction module described in this embodiment correspond one-to-one with the steps in the above-mentioned high-speed clock signal waveform reconstruction method, so they will not be repeated here.

[0190] The high-speed clock signal waveform reconstruction system provided in this application can implement the high-speed clock signal waveform reconstruction method described in this application. However, the implementation apparatus of the high-speed clock signal waveform reconstruction method described in this application includes, but is not limited to, the structure of the high-speed clock signal waveform reconstruction system listed in this embodiment. All structural modifications and substitutions of the prior art made in accordance with the principles of this application are included within the protection scope of this application.

[0191] Please see Figure 10 The image shown is a schematic diagram of the structure of an electronic device according to an embodiment of this application.

[0192] like Figure 10 As shown, this application provides an electronic device, including:

[0193] The memory is used to store computer programs;

[0194] A processor, the processor being configured to execute a computer program stored in the memory, so as to cause the electronic device to perform the method described in any of the preceding descriptions.

[0195] Preferably, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0196] In one embodiment of this application, a computer-readable storage medium is also provided, storing executable instructions for implementing the method described in any of the above-mentioned methods when executed by a processor.

[0197] In one embodiment of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the method described in any of the preceding claims.

[0198] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0199] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0200] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0201] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0202] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A high-speed clock signal waveform reconstruction method, characterized in that, include: Generate a low-speed sampling clock signal; At preset fixed times in each cycle of the low-speed sampling clock signal, the high-speed clock signal to be sampled is asynchronously sampled using equivalent time to obtain multiple sampling points; each sampling point includes a sampling level value and a corresponding sampling time. During asynchronous sampling, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is synchronously calculated based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal. The equivalent phase corresponding to all sampling points is mapped to at least one cycle of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

2. The method according to claim 1, characterized in that, During asynchronous sampling, based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal, the equivalent phase of each sampling point relative to the high-speed sampling clock signal is calculated synchronously, including: The estimated frequency of the high-speed clock signal to be sampled is multiplied by the sampling time of each sampling point to obtain the cumulative phase of each sampling point at the corresponding sampling time; the cumulative phase includes an integer part and a fractional part, wherein the integer part corresponds to the number of complete cycles experienced by the high-speed clock signal to be sampled, and the fractional part represents the normalized instantaneous phase; The normalized instantaneous phase is modulo 1 to obtain the equivalent phase of each sampling point relative to the high-speed clock signal to be sampled.

3. The method according to claim 2, characterized in that, Also includes: The ratio between the frequency difference and the frequency of the low-speed sampling clock signal is defined as the phase step coefficient; The normalized instantaneous phase of each sampling point is obtained by multiplying the phase step coefficient by the index of each sampling point.

4. The method according to claim 1, characterized in that, The frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal satisfies: ； in The frequency of the low-speed sampling clock signal, The estimated frequency of the high-speed clock signal to be sampled is... Let N be the frequency difference, where N is a positive integer.

5. The method according to claim 1, characterized in that, Mapping the equivalent phase corresponding to all sampling points to at least one period of the high-speed clock signal to be sampled, in order to reconstruct the actual waveform of the high-speed clock signal to be sampled, includes: The equivalent phase corresponding to all sampling points is normalized to at least one cycle of the high-speed clock signal to be sampled, to obtain the normalized equivalent phase. Sort all sampling points in ascending order according to the normalized equivalent phase to obtain the sorted sampling point sequence; The sampling level values ​​corresponding to each sampling point are rearranged according to the sorted sampling point sequence to obtain the waveform of the high-speed clock signal to be sampled within at least one cycle.

6. The method according to claim 1, characterized in that, Also includes: Edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled, and the edge feature analysis results are obtained. Based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified. Based on the interpolation algorithm, the zero-crossing moments are refined in time; the time resolution of the zero-crossing moments after time refinement reaches the preset target resolution requirement.

7. The method according to claim 6, characterized in that, The interpolation algorithm includes at least one of linear interpolation, spline interpolation, or band-limited interpolation.

8. The method according to claim 1, characterized in that, Also includes: Edge feature analysis is performed on the actual waveform of the reconstructed high-speed clock signal to be sampled, and the edge feature analysis results are obtained. Based on the edge feature analysis results, the zero-crossing time corresponding to the edge of the low-speed sampling clock signal is identified. Based on the zero-crossing time, the time interval between two adjacent edges of the same type is calculated, and the time interval is defined as the single-cycle value of the high-speed sampling clock signal; Based on the single-cycle value, the actual frequency of the high-speed sampling clock signal is obtained by taking its reciprocal. Within a single cycle, the ratio of the high-level pulse width to the single-cycle value is calculated to obtain the duty cycle of the high-speed sampling clock signal; Multiple consecutive single-cycle values ​​are obtained, and the offset of each single-cycle value relative to the average single-cycle value is calculated. The offset is defined as the period jitter of the high-speed sampling clock signal.

9. The method according to claim 1, characterized in that, Also includes: Determine the maximum allowable phase change rate based on the preset measurement accuracy requirements; Based on the preset response time constraint, determine the minimum allowable phase change rate; The frequency of the low-speed sampling clock signal is dynamically adjusted in real time by combining the maximum phase change rate and the minimum phase change rate.

10. The method according to claim 1, characterized in that, Also includes: Configure multiple low-speed sampling circuits, and the low-speed sampling clock signals generated by each low-speed sampling circuit have a preset and fixed phase offset relative to the same reference clock; The multi-channel low-speed sampling circuit is divided into a coarse sampling group and a fine sampling group, wherein the sampling time interval of the coarse sampling group is a first time resolution, the sampling time interval of the fine sampling group is a second time resolution, and the first time resolution is greater than the second time resolution. The coarse sampling group and the fine sampling group are controlled to perform asynchronous equivalent time sampling operations on the high-speed clock signal to be sampled in parallel, so as to obtain coarse-grained sampling data and fine-grained sampling data respectively. The initial waveform of the high-speed clock signal to be sampled is constructed based on the coarse-grained sampling data, and the initial waveform is locally refined by combining the fine-grained sampling data.

11. The method according to claim 1, characterized in that, Also includes: During waveform reconstruction, the distribution characteristics of the sampling points are monitored in real time. When the distribution of the sampling points deviates from the preset pattern, it is determined to be an abnormal state; In response to the abnormal state, an alarm signal is generated, and the system switches to a coarse measurement mode; the coarse measurement mode uses a reduced time resolution or a reduced sampling point density for waveform acquisition; After completing waveform acquisition for a preset duration in the coarse measurement mode, the system automatically returns to the initial waveform reconstruction process based on asynchronous equivalent time sampling.

12. A high-speed clock signal waveform reconstruction system, characterized in that, include: The sampling clock generation module is used to generate a low-speed sampling clock signal; The sampling module for the clock signal to be sampled is used to asynchronously sample the high-speed clock signal to be sampled at preset fixed times in each period of the low-speed sampling clock signal to obtain multiple sampling points; each sampling point includes a sampling level value and a corresponding sampling time. The equivalent phase calculation module is used to synchronously calculate the equivalent phase of each sampling point relative to the high-speed sampling clock signal during asynchronous sampling, based on the frequency difference between the frequency of the low-speed sampling clock signal and the estimated frequency of the high-speed sampling clock signal. The waveform reconstruction module is used to map the equivalent phase corresponding to all sampling points to at least one cycle of the high-speed clock signal to be sampled, so as to reconstruct the actual waveform of the high-speed clock signal to be sampled.

13. An electronic device, characterized in that, include: The memory is used to store computer programs; A processor for executing a computer program stored in the memory to cause the electronic device to perform the method of any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, It stores executable instructions for implementing the method of any one of claims 1 to 11 when executed by a processor.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 11.

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