Diode overload protection method based on semiconductor junction region impurity distribution

Abstract

The application discloses a diode overload protection method based on semiconductor junction zone impurity distribution; a multi-dimensional feature extraction is performed on real-time operation data of ion implantation equipment through a support vector machine regression algorithm, initial impurity distribution characteristics of a semiconductor junction zone are obtained, and a junction zone concentration gradient value is extracted to determine a process fluctuation condition; when the process fluctuation is detected, a random forest algorithm is used for nonlinear feature mapping to determine a breakdown voltage drift amount, and the modified target breakdown voltage is calculated by superimposing the reference breakdown voltage; the target breakdown voltage is used to extract an avalanche effect starting voltage, a conduction threshold calibration instruction is generated when the avalanche effect starting voltage deviates from a safe voltage interval, and the calibrated target conduction threshold is obtained by adjusting the impedance of an overload current conduction path; when the circuit detects an abnormally high voltage, diode overload protection of a core logic chip can be realized; and the precision and reliability of diode overload protection are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a diode overload protection method based on the impurity distribution in the semiconductor junction region. Background Technology

[0002] In the semiconductor manufacturing field, the overload protection mechanism of diodes plays a crucial role in ensuring the safety of core logic chips. However, traditional manufacturing processes often rely excessively on fixed physical structure designs and conventional electrical isolation methods when handling reverse voltage control of diodes. This approach is ill-suited to minor process fluctuations during manufacturing, easily leading to uncontrollable current leakage when the device is subjected to high voltage. It also fails to accurately respond to complex electrical stress changes, thus creating the potential for large-area chip damage.

[0003] The core challenge posed by this process defect lies in the difficulty of precisely controlling the impurity distribution in the semiconductor junction region. In actual wafer fabrication, even extremely small deviations in the parameters of the ion implantation equipment can directly alter the impurity concentration gradient in the junction region. Uncontrolled impurity distribution can trigger severe chain reactions, directly causing a drastic drift in the reverse breakdown voltage of the diode. This extreme instability in the breakdown voltage further makes the initiation voltage for collisional ionization of charge carriers and the resulting avalanche multiplication effect completely unpredictable.

[0004] Taking a specific chip manufacturing business as an example, it's like randomly piling up a large amount of silt in a previously smooth flood discharge channel, making the resistance and direction of water flow completely unpredictable. When an abnormally high voltage suddenly appears in the circuit, due to the breakdown voltage drift caused by uneven distribution of impurities in the junction region, the diode cannot trigger the avalanche effect on time at the pre-set safe voltage value. The massive overload current therefore cannot be smoothly guided to the grounding loop as planned, but instead directly breaks through the defenses, instantly burning out the extremely fragile core logic chip.

[0005] Precisely controlling the impurity distribution in the semiconductor junction region to stabilize the reverse breakdown voltage, and thus accurately calibrating the overload current conduction threshold, has become a key issue in perfecting the voltage clamping operation process of the core logic chip. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a diode overload protection method based on the impurity distribution in the semiconductor junction region, which can address the problem that fluctuations in the ion implantation process lead to unstable breakdown voltage in the semiconductor junction region, thereby affecting the reliability of overload protection.

[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is: a diode overload protection method based on semiconductor junction impurity distribution, the innovation of which is as follows: S101: Acquire real-time operating data of the ion implantation equipment, which includes five dimensions of parameters: implantation energy, beam dose, scanning speed, wafer temperature, and vacuum degree; use a support vector machine regression algorithm to perform multi-dimensional feature extraction and fitting processing on the real-time operating data to obtain the initial impurity distribution characteristics of the semiconductor junction region; S102: Extract the junction concentration gradient value in the spatial dimension based on the initial impurity distribution characteristics. If the junction concentration gradient value is greater than the preset concentration threshold, it is determined that there is a process fluctuation in the current manufacturing process, and the corresponding process fluctuation characteristics are obtained. S103: For the process fluctuation characteristics, a random forest algorithm is used to perform nonlinear feature mapping to determine the breakdown voltage drift ΔVb of the semiconductor junction region under the current manufacturing process; S104: The target breakdown voltage Vt is obtained by numerically superimposing the reference breakdown voltage V0 and the breakdown voltage drift ΔVb, i.e., Vt=V0+ΔVb, where Vt is the predicted value of the actual breakdown voltage of the device under the current environmental conditions. S105: Extract the corresponding avalanche effect initiation voltage based on the target breakdown voltage Vt; S106: Determine the corresponding overload current conduction path based on the range of the target breakdown voltage, and adjust the impedance of the determined conduction path through the conduction threshold calibration command to obtain the calibrated target conduction threshold. S107: When the detected actual current value reaches or exceeds the target conduction threshold, the discharge action is triggered to complete the diode overload protection operation of the core logic chip; at this time, the current actual current value is recorded as the conduction value, which is the current measurement value at the moment of triggering discharge, and is used for subsequent discharge effect evaluation and optimization analysis.

[0008] The advantages of this invention are: 1) This invention discloses a diode overload protection method based on semiconductor junction impurity distribution. Addressing the problem of unstable semiconductor junction breakdown voltage caused by ion implantation process fluctuations, which in turn affects the reliability of overload protection, this invention uses a support vector machine regression algorithm to extract multi-dimensional features from real-time operating data of the ion implantation equipment, obtaining the initial impurity distribution characteristics of the semiconductor junction, and extracting the junction concentration gradient value to determine the process fluctuation status. When a process fluctuation is detected, a random forest algorithm is used for nonlinear feature mapping to determine the breakdown voltage drift, and this drift is superimposed with a reference breakdown voltage to calculate the corrected target breakdown voltage. This invention extracts the avalanche effect initiation voltage based on the target breakdown voltage. When this voltage deviates from the safe voltage range, a conduction threshold calibration command is generated. The calibrated target conduction threshold is obtained by adjusting the impedance of the overload current conduction path. When the circuit detects an abnormal high voltage, the overload current discharge action is triggered based on this target conduction threshold, realizing diode overload protection for the core logic chip. This invention effectively improves the accuracy and reliability of diode overload protection by real-time monitoring of process fluctuations and dynamic correction of breakdown voltage parameters. Attached Figure Description

[0009] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0010] Figure 1 This is a flowchart of a diode overload protection method based on impurity distribution in a semiconductor junction region according to the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0012] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0013] like Figure 1 The diode overload protection method based on semiconductor junction impurity distribution is shown below. S101: Acquire real-time operating data of the ion implantation equipment, which includes five dimensions of parameters: implantation energy, beam dose, scanning speed, wafer temperature, and vacuum degree; use a support vector machine regression algorithm to perform multi-dimensional feature extraction and fitting processing on the real-time operating data to obtain the initial impurity distribution characteristics of the semiconductor junction region.

[0014] Specifically, the five-dimensional parameters are used as the input vector X=(x1, x2, x3, x4, x5). A nonlinear mapping is performed through the radial basis function kernel to map the operating parameter space to a high-dimensional feature space. In this feature space, a regression relationship is established between the operating parameters and the peak position, peak concentration, and distribution width of the impurity concentration distribution. The output is an impurity distribution feature vector containing three feature values: peak depth Rp, peak concentration Np, and longitudinal deviation ΔRp. This feature vector is the initial impurity distribution feature of the semiconductor junction region. The training samples of the support vector machine regression algorithm come from the labeled ion implantation parameters and the corresponding secondary ion mass spectrometry (SIMS) measured impurity distribution data in the historical process database. The number of training samples is no less than 1000 sets.

[0015] S102: Extract the junction concentration gradient value in the spatial dimension based on the initial impurity distribution characteristics. If the junction concentration gradient value is greater than the preset concentration threshold, it is determined that there is a process fluctuation in the current manufacturing process, and the corresponding process fluctuation characteristics are obtained.

[0016] Specifically, the process involves: acquiring the initial impurity distribution characteristics; calculating the first derivative of the impurity concentration along the depth direction to obtain the junction concentration gradient value G, in units of per cubic centimeter per micrometer; and comparing the junction concentration gradient value G with a preset concentration threshold of 5 × 10⁻⁶. 18 If G is greater than the threshold per cubic centimeter per micrometer, a process fluctuation is determined to exist in the manufacturing process, and a process fluctuation feature vector is obtained. This feature vector contains three dimensions: concentration gradient value, depth position, and horizontal coordinate. The process fluctuation feature vector is then used for anomaly detection processing using an isolated forest algorithm. A contamination rate of 0.05 is set, and training is performed based on 100 isolated trees and a sampling size of 256. Samples with anomaly scores below -0.5 are identified as abnormal fluctuation nodes. For each abnormal fluctuation node, the corresponding wafer identifier and implantation area coordinates are extracted from the initial data to obtain abnormal area location information. The abnormal area location information is then used to read the actual implantation depth dactual at that location and the process standard depth dstandard, calculating the depth deviation Δd = dactual. 实际 -d 标准When Δd is positive, it indicates that the injection is too deep. The annealing temperature compensation value ΔT = -50 × Δd is calculated, where Δd is in micrometers and ΔT is in °C. The negative sign indicates that the annealing temperature is reduced to slow down diffusion. When Δd is negative, it indicates that the injection is too shallow. ΔT is positive to increase the annealing temperature to promote diffusion. The annealing temperature compensation value ΔT is obtained and superimposed on the reference annealing temperature to generate the temperature control command of the rapid thermal annealing equipment, thereby obtaining the updated operating status of the rapid thermal annealing equipment.

[0017] S103: For the process fluctuation characteristics, a random forest algorithm is used to perform nonlinear feature mapping to determine the breakdown voltage drift ΔVb of the semiconductor junction region under the current manufacturing process.

[0018] Specifically, the process fluctuation characteristics are obtained, including 15 parameters such as doping concentration deviation, temperature fluctuation amplitude, and implantation energy deviation. These parameters are then input into a pre-trained random forest regression model, which contains 200 decision trees, each with an 8-layer depth, and outputs the breakdown voltage drift ΔVb. , These are the model's predicted values. The standard design value is used; after obtaining the breakdown voltage drift, it is superimposed and corrected with the preset standard voltage value to calculate the actual breakdown voltage value. The actual breakdown voltage value is obtained and compared with a preset voltage threshold. When the actual breakdown voltage value is less than the threshold of 60V, the depletion layer width value Wd corresponding to the semiconductor junction region is extracted from the inflection point of the capacitor voltage characteristic test curve. After obtaining the depletion layer width value, its value is calculated relative to the preset target width. The difference is used to obtain the width compensation amount. The width compensation amount is obtained by multiplying the depletion layer width with the doping concentration using the dose conversion factor K to obtain the ion implantation dose adjustment value ΔD = K × ΔWd, where K is determined by parameters such as the dielectric constant of the semiconductor material, the doping depth, and the ion implantation energy, with a typical value of 2.5 × 10⁻⁶. 12 per square centimeter per micrometer; after obtaining the ion implantation dose adjustment value, generate beam intensity and implantation time control commands for the ion implantation device based on the adjustment value, and obtain the updated operating status of the ion implantation device.

[0019] S104: The target breakdown voltage Vt is obtained by numerically superimposing the reference breakdown voltage V0 and the breakdown voltage drift ΔVb, i.e., Vt=V0+ΔVb, where Vt is the predicted value of the actual breakdown voltage of the device under the current environmental conditions.

[0020] In S104, during the device factory testing phase or the first calibration, under standard temperature of 25°C and standard humidity of 45%, a gradually increasing reverse voltage is applied to the device, and the voltage value at which the device breaks down is recorded as the reference breakdown voltage V0. This reference breakdown voltage is stored in the device's non-volatile memory as a reference for subsequent drift correction.

[0021] S105: Extract the corresponding avalanche effect initiation voltage based on the target breakdown voltage Vt.

[0022] Specifically, the avalanche effect initiation voltage Va and the target breakdown voltage Vt satisfy the relationship Va=k×Vt, where the coefficient k ranges from 0.75 to 0.85, preferably 0.8. After extracting the avalanche effect initiation voltage, it is determined whether the voltage value is within a pre-set safe voltage range, where the lower limit of the safe voltage range is 12V and the upper limit is 18V. If the avalanche effect initiation voltage is lower than the lower limit or higher than the upper limit, it indicates that the electric field intensity distribution in the semiconductor junction region is abnormal, which will cause the device to bear unexpected electric field stress during normal conduction, thereby affecting the stability of the conduction process. At this time, a conduction threshold calibration command is generated for the semiconductor junction region, and the electric field distribution is corrected by adjusting the gate bias voltage or substrate doping concentration, so that the conduction threshold offset is controlled within ±0.3V, ensuring that the device operates stably within the safe voltage range.

[0023] S106: Determine the corresponding overload current conduction path based on the range of the target breakdown voltage, and adjust the impedance of the determined conduction path through the conduction threshold calibration command to obtain the calibrated target conduction threshold.

[0024] Specifically, the overload current conduction path is determined based on the target breakdown voltage range. Specifically, when the target breakdown voltage is in the range of 15V to 30V, the first conduction path is used; when the target breakdown voltage is in the range of 30V to 50V, the second conduction path is used; and when the target breakdown voltage is greater than 50V, the third conduction path is used. The impedance of the determined conduction path is adjusted by the conduction threshold calibration command to obtain the calibrated target conduction threshold. The impedance adjustment is achieved by changing the resistance value of the resistive element in the conduction path. The adjustment range is 0.8 times to 1.2 times the initial resistance value, so that the target conduction threshold reaches the preset requirement.

[0025] S107: When the detected actual current value reaches or exceeds the target conduction threshold, the discharge action is triggered to complete the diode overload protection operation of the core logic chip; at this time, the current actual current value is recorded as the conduction value, which is the current measurement value at the moment of triggering discharge, and is used for subsequent discharge effect evaluation and optimization analysis.

[0026] Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the present invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed.

Claims

1. A diode overload protection method based on semiconductor junction impurity distribution, characterized in that: The specific method is as follows: S101: Acquire real-time operating data of the ion implantation equipment, which includes five dimensions of parameters: implantation energy, beam dose, scanning speed, wafer temperature, and vacuum degree; use a support vector machine regression algorithm to perform multi-dimensional feature extraction and fitting processing on the real-time operating data to obtain the initial impurity distribution characteristics of the semiconductor junction region; S102: Extract the junction concentration gradient value in the spatial dimension based on the initial impurity distribution characteristics. If the junction concentration gradient value is greater than the preset concentration threshold, it is determined that there is a process fluctuation in the current manufacturing process, and the corresponding process fluctuation characteristics are obtained. S103: For the process fluctuation characteristics, a random forest algorithm is used to perform nonlinear feature mapping to determine the breakdown voltage drift ΔVb of the semiconductor junction region under the current manufacturing process; S104: The target breakdown voltage Vt is obtained by numerically superimposing the reference breakdown voltage V0 and the breakdown voltage drift ΔVb, i.e., Vt=V0+ΔVb, where Vt is the predicted value of the actual breakdown voltage of the device under the current environmental conditions. S105: Extract the corresponding avalanche effect initiation voltage based on the target breakdown voltage Vt; S106: Determine the corresponding overload current conduction path based on the range of the target breakdown voltage, and adjust the impedance of the determined conduction path through the conduction threshold calibration command to obtain the calibrated target conduction threshold. S107: When the detected actual current value reaches or exceeds the target conduction threshold, the discharge action is triggered to complete the diode overload protection operation of the core logic chip; at this time, the current actual current value is recorded as the conduction value, which is the current measurement value at the moment of triggering discharge, and is used for subsequent discharge effect evaluation and optimization analysis.

2. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: Specifically, S101 involves taking five dimensional parameters as input vectors X=(x1, x2, x3, x4, x5), performing nonlinear mapping through a radial basis function to map the operating parameter space to a high-dimensional feature space, establishing a regression relationship between the operating parameters and the peak position, peak concentration, and distribution width of the impurity concentration distribution in this feature space, and outputting an impurity distribution feature vector containing three feature values: peak depth Rp, peak concentration Np, and longitudinal deviation ΔRp. This feature vector is the initial impurity distribution feature of the semiconductor junction region. The training samples for the support vector machine regression algorithm come from the labeled ion implantation parameters and the corresponding secondary ion mass spectrometry (SIMS) measured impurity distribution data in the historical process database, with a training sample size of no less than 1000 sets.

3. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: S102 specifically involves: acquiring the initial impurity distribution characteristics, calculating the first derivative of the impurity concentration along the depth direction to obtain the junction concentration gradient value G, in units of per cubic centimeter per micrometer; acquiring the junction concentration gradient value G, and comparing G with a preset concentration threshold of 5 × 10⁻⁶. 18 If G is greater than the threshold per cubic centimeter per micrometer, a process fluctuation is determined to exist in the manufacturing process, and a process fluctuation feature vector is obtained. This feature vector contains three dimensions: concentration gradient value, depth position, and horizontal coordinate. The process fluctuation feature vector is then used for anomaly detection processing using an isolated forest algorithm. A contamination rate of 0.05 is set, and training is performed based on 100 isolated trees and a sampling size of 256. Samples with anomaly scores below -0.5 are identified as abnormal fluctuation nodes. For each abnormal fluctuation node, the corresponding wafer identifier and implantation area coordinates are extracted from the initial data to obtain abnormal area location information. The abnormal area location information is then used to read the actual implantation depth dactual at that location and the process standard depth dstandard, calculating the depth deviation Δd = dactual. 实际 -d 标准 When Δd is positive, it indicates that the implantation is too deep. The annealing temperature compensation value ΔT = -50 × Δd is calculated, where Δd is in micrometers and ΔT is in °C. The negative sign indicates that the annealing temperature is reduced to slow down diffusion. When Δd is negative, it indicates that the implantation is too shallow. ΔT is positive to increase the annealing temperature to promote diffusion. The annealing temperature compensation value ΔT is obtained and superimposed on the reference annealing temperature to generate a temperature control command for the rapid thermal annealing equipment, thereby obtaining the updated operating status of the rapid thermal annealing equipment.

4. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: S103 specifically involves: acquiring the process fluctuation characteristics, including 15 parameters such as doping concentration deviation, temperature fluctuation amplitude, and implantation energy deviation, and inputting them into a pre-trained random forest regression model. This model contains 200 decision trees, each with a depth of 8 layers, and outputs the breakdown voltage drift ΔVb. , These are the model's predicted values. The standard design value is used; after obtaining the breakdown voltage drift, it is superimposed and corrected with the preset standard voltage value to calculate the actual breakdown voltage value. ; The actual breakdown voltage value is obtained and compared with a preset voltage threshold. When the actual breakdown voltage value is less than the threshold of 60V, the depletion layer width value Wd corresponding to the semiconductor junction region is extracted from the inflection point of the capacitor voltage characteristic test curve. After obtaining the depletion layer width value, its value is calculated and compared with the preset target width. The difference is used to obtain the width compensation amount. The width compensation amount is obtained by multiplying the depletion layer width with the doping concentration using the dose conversion factor K to obtain the ion implantation dose adjustment value ΔD = K × ΔWd, where K is determined by parameters such as the dielectric constant of the semiconductor material, the doping depth, and the ion implantation energy, with a typical value of 2.5 × 10⁻⁶. 12 per square centimeter per micrometer; after obtaining the ion implantation dose adjustment value, generate beam intensity and implantation time control commands for the ion implantation device based on the adjustment value, and obtain the updated operating status of the ion implantation device.

5. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: In S104, during the device factory testing phase or the first calibration, under standard temperature of 25°C and standard humidity of 45%, a gradually increasing reverse voltage is applied to the device, and the voltage value at which the device breaks down is recorded as the reference breakdown voltage V0. This reference breakdown voltage is stored in the non-volatile memory of the device as a reference for subsequent drift correction.

6. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: S105 specifically involves: the avalanche effect initiation voltage Va and the target breakdown voltage Vt satisfying the relationship Va=k×Vt, where the coefficient k ranges from 0.75 to 0.85, preferably 0.8; after extracting the avalanche effect initiation voltage, it is determined whether the voltage value is within a pre-set safe voltage range, where the lower limit of the safe voltage range is 12V and the upper limit is 18V; if the avalanche effect initiation voltage is lower than the lower limit or higher than the upper limit, it indicates that the electric field intensity distribution in the semiconductor junction region is abnormal, which will cause the device to bear unexpected electric field stress during normal conduction, thereby affecting the stability of the conduction process; at this time, a conduction threshold calibration command is generated for the semiconductor junction region, and the electric field distribution is corrected by adjusting the gate bias voltage or substrate doping concentration, so that the conduction threshold offset is controlled within ±0.3V, ensuring that the device operates stably within the safe voltage range.

7. The diode overload protection method based on semiconductor junction impurity distribution according to claim 1, characterized in that: S106 specifically involves: determining the corresponding overload current conduction path based on the target breakdown voltage range; specifically: when the target breakdown voltage is in the range of 15V to 30V, it corresponds to the first conduction path; when the target breakdown voltage is in the range of 30V to 50V, it corresponds to the second conduction path; when the target breakdown voltage is greater than 50V, it corresponds to the third conduction path; and adjusting the impedance of the determined conduction path through a conduction threshold calibration command to obtain the calibrated target conduction threshold. The impedance adjustment is achieved by changing the resistance value of the resistive element in the conduction path, with an adjustment range of 0.8 to 1.2 times the initial resistance value, so that the target conduction threshold reaches the preset requirement.

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