Identification generation method, apparatus, device, medium, and product

Abstract

Embodiments of the present application provide a kind of identification generation method, device, equipment, medium and product.The method comprises: obtaining the level state of specific pin on target mainboard;Dynamic key is generated using hardware root key and real-time timestamp;The level state is encrypted using the dynamic key, to obtain the encrypted mainboard number, and / or the original number of the specific pin is mapped and encrypted, to obtain the encrypted pin identifier;Based on the encrypted mainboard number and the encrypted pin identifier, the identity of the target mainboard is generated.The method of the present application dynamically associates the identity with hardware root key and time, avoids the identity being equivalent to static GPIO combination, improves the anti-counterfeiting, anti-replay capability and the security and reliability of acquisition result.

Description

Technical Field

[0001] This application relates to the field of identity authentication technology, and in particular to an identifier generation method, apparatus, device, medium and product. Background Technology

[0002] In embedded devices, existing hardware identities are typically generated based on combinations of levels from General Purpose Input / Output (GPIO) pins. Hardware identities are used for hardware adaptation, access control, and device authentication.

[0003] However, such schemes often use fixed level combinations and static verification to form identifiers, making the transmission and storage process easy to read or counterfeit. At the same time, GPIO acquisition is susceptible to electromagnetic interference, power fluctuations, and other factors that can lead to misreading, which reduces the accuracy of identifier recognition and makes it difficult to effectively distinguish between occasional acquisition anomalies and human tampering.

[0004] Therefore, how to improve the anti-counterfeiting properties and acquisition reliability of identity identifiers when using GPIO states for hardware identifier generation is a key question. Summary of the Invention

[0005] This application provides a method, apparatus, device, medium, and product for generating identifiers, which balances the security, anti-counterfeiting properties, and reliability of identifier generation during the process of generating hardware identifiers using GPIO states.

[0006] A method for generating identifiers, the method comprising:

[0007] Obtain the voltage level of a specific pin on the target motherboard;

[0008] A dynamic key is generated using a hardware root key and a real-time timestamp;

[0009] The encrypted motherboard number is obtained by encrypting the level state using a dynamic key, and / or the original number of a specific pin is mapped and encrypted to obtain the encrypted pin identifier;

[0010] Based on the encrypted motherboard number and encrypted pin identifier, generate the identity of the target motherboard.

[0011] In one possible embodiment, obtaining the voltage level of a specific pin on the target motherboard includes:

[0012] Acquire multiple voltage levels of a specific pin;

[0013] A majority voting mechanism is used to filter the multiple level states collected, and the integrity of the filtered level states is checked, retaining the level states that pass the check.

[0014] In one possible embodiment, the method further includes:

[0015] Determine the electromagnetic interference status based on the current electrical parameters of the target motherboard;

[0016] Based on the electromagnetic interference status, the number of times the level status is sampled and the voting threshold used by the majority voting mechanism are adjusted.

[0017] In one possible embodiment, the number of times the level state is sampled and the voting threshold used by the majority voting mechanism are adjusted based on the electromagnetic interference state, including:

[0018] If the electromagnetic interference status indicates that the target motherboard currently has high noise interference intensity, increase the number of data collections and decrease the voting threshold; otherwise, decrease the number of data collections and increase the voting threshold.

[0019] In one possible embodiment, a dynamic key is generated using a hardware root key and a real-time timestamp, including:

[0020] Collect real-time interference data of the target motherboard and generate a hardware root key based on the real-time interference data; the real-time interference data is used to indicate at least the temperature fluctuation, power supply noise and clock jitter of the target motherboard.

[0021] The initial dynamic key is obtained by combining the hardware root key and the real-time timestamp;

[0022] A dynamic key is generated using an initial dynamic key and a hardware root key.

[0023] In one possible embodiment, a dynamic key is generated using an initial dynamic key and a hardware root key, including:

[0024] The initial dynamic key is processed using a hash algorithm to generate an intermediate dynamic key;

[0025] The dynamic key is obtained by XORing the over-dynamic key with the hardware root key.

[0026] Secondly, embodiments of this application provide an identifier generation apparatus, the apparatus comprising:

[0027] The acquisition module is used to acquire the voltage level of a specific pin on the target motherboard.

[0028] The first generation module is used to generate a dynamic key using the hardware root key and the real-time timestamp;

[0029] The encryption module is used to encrypt the level state with a dynamic key to obtain the encrypted motherboard number, and / or to map and encrypt the original number of a specific pin to obtain the encrypted pin identifier;

[0030] The second generation module is used to generate the identity identifier of the target motherboard based on the encrypted motherboard number and the encrypted pin identifier.

[0031] Thirdly, embodiments of this application provide an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0032] The memory stores the instructions that the computer executes;

[0033] The processor executes computer execution instructions stored in memory to implement the methods provided above.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided above.

[0035] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the methods provided above.

[0036] The identifier generation method, apparatus, device, medium, and product provided in this application obtain the voltage level of specific pins on the target motherboard, generate a dynamic key using a hardware root key and a real-time timestamp, encrypt the motherboard number and / or the original number of the specific pin obtained from the voltage level, and then generate the target motherboard's identity identifier based on the encrypted motherboard number and the encrypted pin identifier. This avoids the direct reading, reuse, or counterfeiting of fixed voltage level combinations and static identifier information, improves the dynamic security protection capability of the identity identifier, and thus enhances the anti-counterfeiting and overall reliability of hardware identity identifier generation based on GPIO states. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0038] Figure 1 A flowchart illustrating an identifier generation method provided in an embodiment of this application;

[0039] Figure 2 A flowchart illustrating another identifier generation method provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the structure of an identifier generation device provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0042] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of the relevant data all comply with the relevant laws, regulations, and standards of the relevant countries and regions, have taken necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation access points for users to choose to authorize or refuse.

[0045] Furthermore, the technical solution involved in this application, which involves big data analysis of user information (including but not limited to personal biometrics, identity data, consumption data, asset data, electronic terminal operation data, etc.) and the use of artificial intelligence technology for automated decision-making, and makes decisions that have a significant impact on personal rights based on the results of automated decision-making, provides users with corresponding operation entry points for users to choose to agree to or reject the results of automated decision-making; if the user chooses to reject, the process will proceed to the expert decision-making process.

[0046] Hardware identity generation for embedded devices is commonly used in scenarios such as smartphones, tablets, IoT terminals, industrial controllers, automotive electronic devices, and smart home gateways. Its core purpose is to quickly identify the hardware version, function configuration, and authorization attributes of the target motherboard when the device is powered on, started, self-tested, or connected to the network, so as to complete driver adaptation, function activation, access control, and device authentication.

[0047] In common solutions, the high and low level states of several specific GPIO pins on the target motherboard are directly obtained and combined according to a pre-agreed encoding rule to form a board ID, which is then passed to an external authentication module.

[0048] This type of solution is widely used due to its simple structure, low cost, and ease of implementation. However, its shortcomings are also quite prominent. First, GPIO level combinations are essentially observable static physical information. Attackers can directly read, replay, or even forge the same level states using oscilloscopes, logic analyzers, debug interfaces, or external circuits, thereby impersonating a legitimate motherboard and allowing unauthorized devices to gain restricted driver adaptation, function activation, or system privileges. Second, since board IDs are often directly mapped from fixed level combinations, their formation logic is relatively clear. Once the encoding rules are reverse-analyzed, the risk of board ID tampering increases significantly. Third, the GPIO acquisition process is sensitive to the external environment. In the presence of electromagnetic interference, power supply jitter, ground bounce noise, temperature fluctuations, or circuit aging, individual pins may experience momentary flipping or edge instability, leading to sampling misreads and consequently, incorrect board ID identification.

[0049] Such errors can not only cause incorrect driver loading, hardware initialization failure, or functional abnormalities, but also make it difficult for the system to determine whether the problem originates from sporadic noise or malicious external interference. Especially when existing solutions mostly use fixed identifiers and static verification, even if inconsistencies are detected, only a rough conclusion of data anomaly can often be drawn, which cannot effectively improve the confidentiality of identity identifiers, nor can it improve the reliability and security of identity identifier generation based on GPIO state from the source.

[0050] Against the above background, this application provides an identifier generation system, including a target motherboard, specific GPIO pins distributed on the target motherboard, a controller for reading the pin status, and an external authentication module that is communicatively connected to the controller. The external authentication module is associated with the identifier generated by the controller.

[0051] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0052] Figure 1 This is a flowchart illustrating an identifier generation method provided in an embodiment of this application, as shown below. Figure 1 As shown, the identifier generation method includes:

[0053] S102. Obtain the voltage level of a specific pin on the target motherboard.

[0054] In this embodiment of the application, the target motherboard refers to the object to which the identity identifier is to be generated, which is used to carry out subsequent processing procedures such as obtaining the level status, generating dynamic keys and forming the motherboard identity identifier. The target motherboard is the hardware carrier that is identified in the embedded device.

[0055] Specific pins can be multiple GPIO pins that are pre-configured for the motherboard hardware identity. These GPIO pins have been assigned a predetermined combination of high and low levels during the design and manufacturing phases of the target motherboard through resistor pull-up, resistor pull-down, pad shorting, fuse configuration, or other hardware connection methods.

[0056] The level state of a specific pin is used to characterize the logic high or low level information of each specific GPIO pin at the acquisition time. It can be stored in the form of a binary bit sequence, or represented in the form of a register value, byte array, or state vector.

[0057] In one possible embodiment, to reduce the impact of power supply jitter, electromagnetic interference, ground bounce noise, and temperature changes on the acquisition results, the same set of specific pins can be sampled multiple times, and the consistency of the multiple sampling results can be screened.

[0058] Specifically, the controller can perform at least multiple reading operations at fixed sampling intervals within a preset time window.

[0059] S104. Generate a dynamic key using a hardware root key and a real-time timestamp.

[0060] In this embodiment of the application, the hardware root key can be a preset basic key material.

[0061] A real-time timestamp is used to represent the time information of the current moment. A real-time timestamp can be a time value at the second, millisecond, or finer granularity level, or it can be a time slice number discretized according to a preset time window.

[0062] Dynamic keys are time-varying keys generated based on the hardware root key and real-time timestamps. They are used to ensure that subsequent encryption results have both motherboard-bound attributes and time-varying attributes, thereby enhancing the identity's resistance to replay and forgery.

[0063] As an example, after the controller completes the acquisition of the specific pin level status, it first reads or calls the hardware root key from memory and obtains the currently valid real-time timestamp. Then, it performs a correlation operation between the two to obtain the dynamic key.

[0064] By introducing real-time timestamps, the dynamic key generates different results at different times; by introducing a hardware root key, the dynamic key is also bound to a legitimate hardware platform. Therefore, even if an external party observes the encryption result at a certain moment, it is difficult to reproduce the same key output at another moment.

[0065] S106. Use dynamic key encryption level state to obtain encrypted motherboard number, and / or map and encrypt the original number of a specific pin to obtain encrypted pin identifier.

[0066] In this embodiment of the application, the encrypted motherboard number refers to the protected encoding result generated under the action of a dynamic key, using the level state of a specific pin as the original input. This result is no longer directly equivalent to the original high and low level combination, but forms a secure expression associated with the current time and the target motherboard key environment.

[0067] The original number of a specific pin can be a predefined port number, pin number, logic index number, or a combination thereof.

[0068] Mapping encryption refers to transforming the original pin number according to a preset mapping relationship so that the final generated pin identifier cannot be directly deduced from the original pin number.

[0069] S108. Generate the identity identifier of the target motherboard based on the encrypted motherboard number and encrypted pin identifier.

[0070] In this embodiment, the identity identifier is the result data used to characterize the identity attributes of the target motherboard, which can be called by the bootloader, operating system, driver adaptation module, access control module, authorization verification module, and external authentication platform.

[0071] The identity can be a fixed-length encoded string, a digest value, structured field data, or an identifier object with version information, the content of which comes from the associated combination of the encrypted motherboard number and the encrypted pin identifier.

[0072] This embodiment constructs an identity identifier by using protected intermediate results. The final identifier is no longer a simple combination of GPIO plaintext, but a comprehensive expression that includes motherboard configuration information, pin association information, and dynamic time factors.

[0073] As an example, the controller can concatenate the encrypted motherboard number and the encrypted pin identifier in a preset format to obtain an identity identifier.

[0074] The aforementioned identifier generation method collects static GPIO level combinations from the target motherboard, combines this with a dynamic key mechanism involving a hardware root key and a real-time timestamp, and then encrypts the level states and original pin numbers. This ultimately generates an identity identifier related to the target motherboard and possessing time-varying characteristics. This transforms static hardware features, which are easily observed, reused, and forged, into a secure identifier expression that is difficult to replay directly. This not only improves the identifier generation process's tolerance to environmental interference and reduces identification errors caused by misreading data, but also prevents external tampering with GPIO levels, thus enhancing security.

[0075] In some alternative embodiments, S102 includes:

[0076] Acquire multiple voltage levels of a specific pin;

[0077] A majority voting mechanism is used to filter the multiple level states collected, and the integrity of the filtered level states is checked, retaining the level states that pass the check.

[0078] Among them, multiple level states refer to several level results obtained by repeatedly reading the same specific pin at different sampling times. This is used to form redundant sampling data to reduce the risk of misjudgment caused by electromagnetic interference, power fluctuations or line jitter in a single reading.

[0079] The majority voting mechanism refers to statistically comparing multiple level states and selecting the level state that appears most frequently as the filtering result, thereby suppressing the impact of occasional outliers on the final recognition result.

[0080] Integrity verification refers to the consistency confirmation or rule matching verification of the level state after majority voting to determine whether the filtering result meets the preset reliability requirements. Only the level state that passes the verification will be retained and used for subsequent processing.

[0081] The aforementioned identifier generation method obtains redundant information through repeated sampling, eliminates occasional noise using majority voting, and further removes abnormal results through integrity verification, making the final retained level state closer to the actual hardware state of the target motherboard. Therefore, the motherboard number or pin identifier subsequently generated based on this level state has higher stability and reliability, reduces identification errors caused by missampling, and improves the reliability and anti-interference capability of hardware identifier generation based on GPIO states.

[0082] In some optional embodiments, the identifier generation method further includes:

[0083] Determine the electromagnetic interference status based on the current electrical parameters of the target motherboard;

[0084] Based on the electromagnetic interference status, the number of times the level status is sampled and the voting threshold used by the majority voting mechanism are adjusted.

[0085] Among them, the electromagnetic interference status refers to the interference intensity status obtained by comprehensively judging the current electrical parameters of the target motherboard. The electrical parameters may include motherboard power supply ripple, power supply transient fluctuation, ground potential offset, clock jitter, signal edge glitches, and noise amplitude of circuits near the pins, etc., which are used to characterize whether there is strong external interference or internal coupling interference in the current acquisition environment.

[0086] The number of times the level status is sampled refers to the number of times a specific pin is repeatedly read.

[0087] The voting threshold used in the majority voting mechanism refers to the minimum number of consensuses required to determine whether a certain level state can be retained among multiple sampling results.

[0088] The target motherboard can acquire electrical parameters through power monitoring circuits, noise detection units, or firmware polling, and classify the interference status within a preset threshold range so as to link with subsequent acquisition strategies.

[0089] As an example, before reading the level of a specific pin, the controller first obtains the current electrical parameters of the target motherboard. The controller can then perform weighted processing based on various specific parameters included in the electrical parameters, and generate an interference score based on the weighted results of each parameter. Furthermore, based on multiple pre-set scoring ranges, the controller determines the interference state corresponding to the scoring range to which the interference score falls, where each scoring range has a pre-defined corresponding interference state.

[0090] The controller further adaptively sets the number of level acquisitions based on the interference status. When the interference status indicates strong interference, the controller increases the number of repeated readings to improve the ability to suppress transient glitches and jitter; when the interference status indicates weak interference, the controller reduces the number of repeated readings to reduce startup delay and acquisition overhead.

[0091] Meanwhile, the control unit will adjust the voting threshold of the majority voting mechanism in a coordinated manner. When the interference status indicates strong interference, the voting threshold will be lowered to allow more sampling results to participate in the retention, thereby enhancing stability. When the interference status indicates weak interference, the voting threshold will be raised to make the voting results more stringent, thereby improving the accuracy of the sampling consistency determination.

[0092] The aforementioned identifier generation method allows the target motherboard to first determine the current electrical environment and then dynamically configure the repeated sampling strategy and voting conditions accordingly. This ensures that pin levels can still obtain more reliable acquisition results even in complex electromagnetic environments. By adopting this identifier generation method, the anti-interference capability of level state acquisition can be improved, the probability of identification errors caused by noise, jitter, or external coupling can be reduced, and the majority voting mechanism can maintain adaptability and consistency in different electrical environments, thereby enhancing the reliability and practicality of motherboard identifier generation.

[0093] In some optional embodiments, the step of adjusting the number of level state samplings and the voting threshold used by the majority voting mechanism based on the electromagnetic interference state includes:

[0094] If the electromagnetic interference status indicates that the target motherboard currently has high noise interference intensity, increase the number of data collections and decrease the voting threshold; otherwise, decrease the number of data collections and increase the voting threshold.

[0095] Increasing the number of samplings allows for more sample support for subsequent majority voting, thereby improving the ability to suppress transient spikes and occasional flips; decreasing the voting threshold can prevent excessive rejection of effective levels due to local sample anomalies in high-noise environments; increasing the voting threshold can improve the strictness of result screening in low-noise environments.

[0096] As an example, if the controller detects that the noise interference intensity of the target motherboard's current environment is high, it can expand the sampling window of the level state and lower the voting threshold to enhance the fault tolerance of jitter signals; if it detects that the noise interference intensity of the target motherboard's current environment is not high, it can shorten the sampling window of the level state and increase the voting threshold to reduce the consumption of acquisition resources and reduce the number of low-quality samples entering the final judgment.

[0097] The aforementioned identifier generation method, by linking the number of samplings and the voting threshold with the electromagnetic interference status, can employ a more redundant sampling strategy when interference is strong and a more efficient sampling strategy when interference is weak. This ensures that the acquisition of the level status of a specific pin balances stability and resource utilization. Since the output result comes from a majority vote adapted to the current noise environment, it reduces the impact of transient interference on board ID generation, decreases false positives and false negatives, and thus improves the reliability and consistency of identity generation based on GPIO status.

[0098] In some alternative embodiments, S104 includes:

[0099] Collect real-time interference data of the target motherboard and generate a hardware root key based on the real-time interference data; the real-time interference data is used to indicate at least the temperature fluctuation, power supply noise and clock jitter of the target motherboard.

[0100] The initial dynamic key is obtained by combining the hardware root key and the real-time timestamp;

[0101] A dynamic key is generated using an initial dynamic key and a hardware root key.

[0102] Among them, real-time interference data refers to environmental disturbance information collected during the operation of the target motherboard. The disturbance information includes at least temperature fluctuations, power supply noise, and clock jitter, which are used to characterize the randomness of the current physical state of the motherboard.

[0103] In this embodiment, the hardware root key is a basic key generated based on real-time interference data. It is bound to the current state of the target motherboard and is used to provide an unpredictable entropy source for subsequent key construction.

[0104] The initial dynamic key is an intermediate key obtained by associating the hardware root key with the real-time timestamp, and is used to facilitate the conversion between the basic key and the final dynamic key.

[0105] The dynamic key is the key ultimately used for subsequent encryption processing. It is generated by further combining the initial dynamic key and the hardware root key to enhance the time-varying nature and device binding of the key.

[0106] As an example, a temperature sampling unit, a power ripple sampling unit, and a clock jitter sampling unit can be set on the target motherboard. The corresponding disturbance information is collected through the temperature sensor, the power monitoring circuit, and the clock jitter measurement module, respectively. The sampling results are then filtered, normalized, and quantized to form real-time interference data.

[0107] After obtaining real-time interference data, the controller can perform weighted fusion of multiple real-time interference data and convert the fusion result into a hardware root key according to a preset mapping rule. Subsequently, the controller can perform XOR, hash, or segmented mixed operation with the current real-time timestamp and the hardware root key to form an initial dynamic key. Then, the initial dynamic key is further derived from the hardware root key to obtain the final dynamic key.

[0108] The aforementioned identifier generation method makes key generation dependent on both real-time motherboard perturbation information and current time information. This gives the hardware root key environmental relevance, the initial dynamic key time-varying nature, and the final dynamic key greater unpredictability. Since the dynamic key is not directly generated from fixed static parameters, it reduces the risks of replay attacks, duplication, and forgery, and improves the security and resistance to attacks in subsequent encryption processes.

[0109] In some optional embodiments, the step of generating a dynamic key using an initial dynamic key and a hardware root key includes:

[0110] The initial dynamic key is processed using a hash algorithm to generate an intermediate dynamic key;

[0111] The dynamic key is obtained by XORing the over-dynamic key with the hardware root key.

[0112] Among them, the intermediate key refers to the intermediate key obtained by hashing the initial dynamic key. It is used to perform a one-way mapping on the initial dynamic key before entering the XOR obfuscation, thereby reducing the possibility that the original key can be directly derived.

[0113] XOR processing refers to performing a bitwise logical XOR operation between the over-dynamic key and the hardware root key to combine the over-dynamic key and the hardware root key, so that the final dynamic key is affected by both of them.

[0114] The aforementioned identifier generation method ensures that the dynamic key is no longer a direct result of the hardware root key and the real-time timestamp, but a derived key after one-way hashing and obfuscation of the hardware root key. This effectively enhances the anti-analysis, anti-spoofing, and anti-replay capabilities of the key generation chain, and reduces the risk of external attackers directly recovering the final key by observing the input value. It also helps to improve the security level of subsequent GPIO state encryption and motherboard identity generation.

[0115] like Figure 2 As shown, in one embodiment, the identifier generation method includes:

[0116] S201. Determine the electromagnetic interference status based on the current electrical parameters of the target motherboard.

[0117] S202. Based on the electromagnetic interference status, adjust the number of sampling times for the level status and the voting threshold used by the majority voting mechanism.

[0118] S203. Collect multiple level states of a specific pin according to the number of collections.

[0119] S204. According to the voting threshold, the majority voting mechanism is used to filter the multiple level states collected, and the integrity of the filtered multiple level states is checked, and the level states that pass the check are retained.

[0120] S205. Collect real-time interference data of the target motherboard and generate a hardware root key based on the real-time interference data; the real-time interference data is used at least to indicate temperature fluctuations, power supply noise and clock jitter of the target motherboard.

[0121] S206. Combine the hardware root key and the real-time timestamp to obtain the initial dynamic key.

[0122] S207. Generate a dynamic key using the initial dynamic key and the hardware root key.

[0123] S208. Use dynamic key encryption level state to obtain encrypted motherboard number, and / or map and encrypt the original number of a specific pin to obtain encrypted pin identifier.

[0124] S209. Generate the identity identifier of the target motherboard based on the encrypted motherboard number and the encrypted pin identifier.

[0125] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0126] Based on the same inventive concept, this application also provides an identifier generation apparatus for implementing the identifier generation method described above. The solution provided by this identifier generation apparatus is similar to the implementation scheme described in the identifier generation method above. Therefore, the specific limitations in one or more apparatus embodiments provided below can be found in the limitations of the identifier generation method described above, and will not be repeated here.

[0127] In one embodiment, such as Figure 3 As shown, an identifier generation device 300 is provided, comprising:

[0128] The acquisition module 302 is used to acquire the voltage level of a specific pin on the target motherboard;

[0129] The first generation module 304 is used to generate a dynamic key using a hardware root key and a real-time timestamp;

[0130] The encryption module 306 is used to encrypt the level state with a dynamic key to obtain the encrypted motherboard number, and / or to map and encrypt the original number of a specific pin to obtain the encrypted pin identifier;

[0131] The second generation module 308 is used to generate the identity identifier of the target motherboard based on the encrypted motherboard number and the encrypted pin identifier.

[0132] In some optional embodiments, the acquisition module 302 is further configured to:

[0133] Acquire multiple voltage levels of a specific pin;

[0134] A majority voting mechanism is used to filter the multiple level states collected, and the integrity of the filtered level states is checked, retaining the level states that pass the check.

[0135] In some optional embodiments, the acquisition module 302 is further configured to:

[0136] Determine the electromagnetic interference status based on the current electrical parameters of the target motherboard;

[0137] Based on the electromagnetic interference status, the number of times the level status is sampled and the voting threshold used by the majority voting mechanism are adjusted.

[0138] In some optional embodiments, the acquisition module 302 is further configured to:

[0139] If the electromagnetic interference status indicates that the target motherboard currently has high noise interference intensity, increase the number of data collections and decrease the voting threshold; otherwise, decrease the number of data collections and increase the voting threshold.

[0140] In some optional embodiments, the first generation module 304 is further configured to:

[0141] Collect real-time interference data of the target motherboard and generate a hardware root key based on the real-time interference data; the real-time interference data is used to indicate at least the temperature fluctuation, power supply noise and clock jitter of the target motherboard.

[0142] The initial dynamic key is obtained by combining the hardware root key and the real-time timestamp;

[0143] A dynamic key is generated using an initial dynamic key and a hardware root key.

[0144] In some optional embodiments, the first generation module 304 is further configured to:

[0145] The initial dynamic key is processed using a hash algorithm to generate an intermediate dynamic key;

[0146] The dynamic key is obtained by XORing the over-dynamic key with the hardware root key.

[0147] Each module in the above-mentioned device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0148] Figure 4 A schematic diagram of the structure of the electronic device provided in this application. Figure 4As shown, the electronic device 400 provided in this embodiment includes at least one processor 401 and a memory 402. Optionally, the device 400 further includes a communication component 403. The processor 401, memory 402, and communication component 403 are connected via a bus 404.

[0149] In a specific implementation, at least one processor 401 executes computer execution instructions stored in memory 402, causing at least one processor 401 to perform the above-described method.

[0150] The specific implementation process of processor 401 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0151] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0152] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0153] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0154] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0155] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0156] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0157] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0158] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0159] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0160] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0161] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0162] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0163] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for generating an identifier, characterized in that, The method includes: Obtain the voltage level of a specific pin on the target motherboard; A dynamic key is generated using a hardware root key and a real-time timestamp; The level state is encrypted using the dynamic key to obtain the encrypted motherboard number, and / or the original number of the specific pin is mapped and encrypted to obtain the encrypted pin identifier; The identity identifier of the target motherboard is generated based on the encrypted motherboard number and the encrypted pin identifier.

2. The method according to claim 1, characterized in that, The process of obtaining the voltage level of a specific pin on the target motherboard includes: Collect multiple level states of the specific pin; A majority voting mechanism is used to filter the multiple level states collected, and the integrity of the filtered level states is checked, retaining the level states that pass the check.

3. The method according to claim 2, characterized in that, The method further includes: The electromagnetic interference status is determined based on the current electrical parameters of the target motherboard; Based on the electromagnetic interference state, the number of times the level state is sampled and the voting threshold used by the majority voting mechanism are adjusted.

4. The method according to claim 3, characterized in that, The adjustment of the number of sampling times for the level state and the voting threshold used in the majority voting mechanism based on the electromagnetic interference state includes: If the electromagnetic interference status indicates that the target motherboard currently has high noise interference intensity, increase the number of data collections and decrease the voting threshold; otherwise, decrease the number of data collections and increase the voting threshold.

5. The method according to claim 1, characterized in that, The process of generating a dynamic key using a hardware root key and a real-time timestamp includes: Real-time interference data of the target motherboard is collected, and the hardware root key is generated based on the real-time interference data; the real-time interference data is used at least to indicate temperature fluctuations, power supply noise, and clock jitter of the target motherboard. By combining the hardware root key with the real-time timestamp, the initial dynamic key is obtained; The dynamic key is generated using the initial dynamic key and the hardware root key.

6. The method according to claim 5, characterized in that, The step of generating the dynamic key using the initial dynamic key and the hardware root key includes: The initial dynamic key is processed using a hash algorithm to generate an intermediate dynamic key; The dynamic key is obtained by XORing the over-dynamic key with the hardware root key.

7. A label generation device, characterized in that, The device includes: The acquisition module is used to acquire the voltage level of a specific pin on the target motherboard. The first generation module is used to generate a dynamic key using the hardware root key and the real-time timestamp; An encryption module is used to encrypt the level state using the dynamic key to obtain an encrypted motherboard number, and / or to map and encrypt the original number of the specific pin to obtain an encrypted pin identifier; The second generation module is used to generate the identity identifier of the target motherboard based on the encrypted motherboard number and the encrypted pin identifier.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 6.

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