A method of adding a network in an integrated circuit schematic

Abstract

The application relates to the chip design technical field, in particular to a method for adding a network in an integrated circuit schematic diagram. The method comprises the following steps: obtaining preset information of a pin needing to add a network in an integrated circuit schematic diagram, and outputting a preset type file; the preset type file comprises a plurality of entries, each entry comprises preset information of a pin needing to add a network in the integrated circuit schematic diagram, and the preset information comprises a device name to which the pin belongs, a bit number corresponding to the pin and a name of the pin; obtaining a user imported file; the user imported file is obtained by editing the preset type file by a user, the editing comprises adding a network name for each entry in the preset type file; the user imported file is of the same type as the preset type file; each entry in the user imported file is traversed, and a corresponding network name and a network line are added at a pin position corresponding to the entry in the integrated circuit schematic diagram. The application can improve the network adding efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip design, and in particular to a method for adding networks in an integrated circuit schematic. Background Technology

[0002] In traditional circuit schematic design, designers need to retrieve and place components, such as resistors, capacitors, and integrated circuit chips, one by one from a component library according to the circuit's functional requirements. After completing the component placement, designers also need to manually assign corresponding net connections to the pins of each component, that is, connect each pin to its corresponding net by drawing net lines and adding net names.

[0003] For complex circuit systems containing a large number of components or pins, manually adding nets to pins often requires repeated operations, which is not only inefficient but also prone to errors. How to accurately and efficiently add nets to integrated circuit schematics is a problem that urgently needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method for adding networks in an integrated circuit schematic, so as to solve the problems of low efficiency and error-proneness in manually adding networks to pins.

[0005] According to the present invention, a method for adding a network in an integrated circuit schematic is provided, the method comprising the following steps:

[0006] S100: Obtain the preset information of the pins in the integrated circuit schematic that need to have a network added, and output a preset type file; the preset type file includes several entries, each entry including the preset information of a pin in the integrated circuit schematic that needs to have a network added, the preset information of the pin includes the device name to which the pin belongs, the corresponding tag number of the pin and the name of the pin.

[0007] S200, Obtain the file imported by the user; the file imported by the user is obtained after the user edits the preset type file, the editing includes adding a network name to each entry in the preset type file; the file imported by the user is of the same type as the preset type file.

[0008] S300 iterates through each entry in the user-imported file and adds the corresponding network name and network line to the pin position of the entry in the integrated circuit schematic.

[0009] Compared with the prior art, the present invention has at least the following beneficial effects:

[0010] This invention outputs a preset type file containing pre-defined information (including the device name, pin number, and pin name) of pins in an integrated circuit schematic that require nets. Users can edit this file externally to add net names to the pins. By importing the edited file, the net names of the pins requiring nets can be obtained, thus automating the addition of net names and net lines. This eliminates the need for users to manually search for pins, draw net lines, and add net names in the schematic interface, enabling accurate and efficient addition of appropriate nets to specified pins of specified devices, thereby improving production efficiency. Furthermore, this invention supports batch pin addition (i.e., the preset type file includes multiple entries), further enhancing efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of a method for adding a network in an integrated circuit schematic according to Embodiment 1 of the present invention;

[0013] Figure 2 A schematic diagram of the device named D2 provided in Embodiment 1 of the present invention;

[0014] Figure 3 This is a schematic diagram of adding a network to a device named D2 according to Embodiment 1 of the present invention;

[0015] Figure 4 A schematic diagram showing the pin with pin number 234 after adding a network according to Embodiment 1 of the present invention;

[0016] Figure 5 This is a schematic diagram illustrating the wiring effect of batch wiring between two chips according to Embodiment 2 of the present invention;

[0017] Figure 6 This is a schematic diagram illustrating the wiring effect of batch wiring between chips and buses provided in Embodiment 2 of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1:

[0020] According to this embodiment, a method for adding a network in an integrated circuit schematic is provided, the method including the following steps, such as... Figure 1 As shown:

[0021] S100: Obtain the preset information of the pins in the integrated circuit schematic that need to have a network added, and output a preset type file; the preset type file includes several entries, each entry including the preset information of a pin in the integrated circuit schematic that needs to have a network added, the preset information of the pin includes the device name to which the pin belongs, the corresponding tag number of the pin and the name of the pin.

[0022] In this embodiment, the pins in the integrated circuit schematic that require netting can be determined by the user. As a specific implementation, the schematic software displays the names of existing devices and their pin designations and names to the user, allowing the user to select which devices and pins require netting. For example, if the user selects a device by checking a box but does not select any pins under that device, then all pins under that device are determined to require netting; conversely, if the user selects only some pins under a device by checking a box, then those specific pins under that device require netting, while the other pins do not.

[0023] As a specific implementation, the default file type is a CSV file. Those skilled in the art will know that CSV is an abbreviation for Comma-Separated Values, which is a plain text file format that can be used to store tabular data. Each row in a CSV file represents a row of records in a data table, and the fields in each row are usually separated by commas.

[0024] As a specific implementation, there is a device named D2 in the integrated circuit schematic, such as... Figure 2As shown, the device includes 48 pins. If the pins for which a net needs to be added in the integrated circuit schematic are all pins except for the pin with reference number 28, then the preset type file output by the schematic software includes the preset information for all pins of D2 except for the pin with reference number 28. If the user opens the output preset type file using an Excel tool, the resulting table is shown in Table 1 (only the parts corresponding to pins with reference numbers 39-45, 14, 38, 2, 34, and 27 are shown).

[0025] Table 1

[0026]

[0027] Those skilled in the art will know that, in addition to Excel, there are other tools that can also edit the output CSV file. This embodiment does not limit the tools used, as long as they can edit the output CSV file.

[0028] S200, Obtain the file imported by the user; the file imported by the user is obtained after the user edits the preset type file, the editing includes adding a network name to each entry in the preset type file; the file imported by the user is of the same type as the preset type file.

[0029] In one specific implementation, after obtaining the preset type file output by the circuit schematic software, the user edits each entry in the preset type file to add the network name that needs to be added to the corresponding pin of each entry.

[0030] As a specific implementation, the preset type file output by the circuit schematic software includes preset information for all pins except for the pin with tag number 28. Then, after editing Table 1, Table 2 is obtained (only showing the part corresponding to the pins with tag numbers 39-45, 14, 38, 2, 34, and 27).

[0031] Table 2

[0032]

[0033] It should be understood that the field names corresponding to different pins in Table 2 are added by the user. This embodiment does not restrict the network names added by the user, and the user can add any network name.

[0034] In this embodiment, after opening and editing the CSV file using tools such as Excel, the edited content can be saved as a CSV file, which can also import circuit schematic files.

[0035] S300 iterates through each entry in the user-imported file and adds the corresponding network name and network line to the pin position of the entry in the integrated circuit schematic.

[0036] In one specific implementation, S300 includes: if the field representing the network name of an entry contains only one network name, then add one network line to the pin position corresponding to the entry in the integrated circuit schematic, and determine the network name included in the field representing the network name of the entry as the network name corresponding to the network line. For example, as shown in Table 2, the content of the field representing the network name of the entry corresponding to pin 39 of D2 is Net Name RGB_IN0, which belongs to the case of containing only one network name (because the content does not include a preset separator, such as a comma, it is determined that it contains only one network name). Therefore, add one network line to the pin position of pin 39 of D2, and determine Net Name RGB_IN0 as the network name corresponding to the network line, as shown. Figure 3 As shown in Table 2, for example, the field representing the network name for the entry corresponding to pin 14 of D2 is "Net Name VCC1," which is a case of only including one network name. Therefore, add one network line to the pin position of D2 with pin number 14, and determine "Net Name VCC1" as the network name corresponding to this network line, as shown in Table 2. Figure 3 As shown.

[0037] As a specific implementation, S300 includes: if the field representing the network name of an entry includes two network names and the name of a newly added device, then two network lines and an electrical symbol representing the newly added device are added to the integrated circuit schematic, wherein the first network line is connected to the pin corresponding to the entry and the electrical symbol representing the newly added device, and the second network line is connected only to the electrical symbol representing the newly added device. For example, if the field representing the network name of the entry corresponding to pin 234 in a certain period contains Net1,Net2,res, since this content includes a preset separator, such as a comma, it is determined that this content includes two network names and the name of a newly added device (the order of the network names and the name of the newly added device in the content should be agreed upon in advance with the user). Net1 is the first network name, Net2 is the second network name, and res is the name of the newly added device. Therefore, a first network line is added at the position corresponding to pin 234 of this device. This first network line connects one end of the electrical symbol corresponding to the pin and res. A second network connection line is added at the other end of the electrical symbol corresponding to res, as follows. Figure 4 As shown.

[0038] In one specific implementation, S300 further includes: during the process of traversing each entry in the user-imported file, checking each entry, including checking whether the device name in the entry exists; if it does not exist, outputting an error message and not performing the operation of adding network names and network lines. For example, if the device name in an entry is D3, but there is no device named D3 in the integrated circuit schematic, then it is determined that the content of the entry is incorrect, and an error message is output to the user to indicate that the device name in the entry is incorrect.

[0039] In one specific implementation, the check further includes: checking whether the tag number and pin name corresponding to the pin in the entry match. If they do not match, an error message is output, and the operation of adding a net name and net line is not performed. For example, if the device name in an entry is D2, the tag number is 4, and the pin name is VCC1, while the tag number of the pin named VCC1 in the integrated circuit schematic is 14, then the content of the entry is determined to be incorrect, and an error message is output to the user to indicate that the tag number and pin name in the entry do not match and there is an error.

[0040] As a specific implementation, if the field representing the network name of an entry includes two network names and the name of a newly added device, the check further includes: checking whether the name of the newly added device is the name of a symbol in the schematic symbol library; if not, an error message is output to the user to indicate that the name of the newly added device in the entry is incorrect.

[0041] In this embodiment, the operation of adding network name and network line is performed on the pin corresponding to an item only when the requirements of all the check items are met.

[0042] In one specific implementation, the growth direction of the network line is determined according to the direction of the corresponding pin: when the corresponding pin is pointing to the left, the network line grows to the left; when the corresponding pin is pointing upwards, the network line grows upwards; when the corresponding pin is pointing to the right, the network line grows to the right; and when the corresponding pin is pointing downwards, the network line grows downwards. Figure 3 As shown.

[0043] In one specific implementation, the length of the network cable is a preset length or is set by the user. For example... Figure 3 As shown, the length of the grid lines is 4 grid side lengths (grid size).

[0044] In this embodiment, the relative positions of the added network name and the corresponding network line can be preset. For example, the added network name can be placed closer to the end of the corresponding network line furthest from the pin. Figure 3 As shown.

[0045] The method for adding networks in this embodiment can add specified networks to the pins of devices on a single page, or to the pins of devices throughout the entire design, making it highly versatile.

[0046] This embodiment outputs a preset type file containing preset information (including the device name, pin number, and pin name) of the pins in the integrated circuit schematic that require nets to be added. Users can edit this file externally to add the corresponding net names to the file. By obtaining the edited file imported by the user, the net names of the pins requiring nets can be obtained, thus automating the addition of net names and net lines. Therefore, users no longer need to search for each pin individually in the schematic interface and draw net lines and add net names, helping them accurately and efficiently add appropriate nets to specified pins of specified devices, thereby improving production efficiency. Furthermore, this embodiment supports batch pin addition operations (i.e., the preset type file includes multiple entries), further improving efficiency.

[0047] Example 2:

[0048] Those skilled in the art will understand that using nets to represent connections has advantages such as saving space and enabling cross-page connections; however, using nets to represent connections also has corresponding disadvantages, such as reduced readability and intuitiveness compared to direct wiring between two points. To balance the advantages and disadvantages of both methods, this embodiment, based on Embodiment 1, further includes, before S100: determining whether preset conditions are met; if met, executing S100-S300; if not met, entering the automatic routing process. Optionally, the preset conditions include at least one of the following: the page numbers of the schematics containing the two pins to be connected are different; a path cannot be obtained between the two pins using the A* algorithm; the user has a need to represent connections using nets.

[0049] In this embodiment, the automatic wiring process includes:

[0050] S1000, obtain the sequence P1 of merged path points between the starting point start and the target point end in the integrated circuit schematic diagram; the path between any two adjacent merged path points in P1 has a different direction from the adjacent path, and the path direction is horizontal or vertical; the merged path points are obtained by merging the initial path points between start and end obtained by using the A* algorithm to merge points in the same direction.

[0051] It should be understood that the starting point and the target point are the two points that need to be connected in the integrated circuit schematic. They can be two pins or a connection point between a pin and a bus.

[0052] As a specific implementation, P1=[P11,P12,…,P1 j ,…,P1 m ], P1 j It is the j-th merging point, where j ranges from 1 to m, and m is the number of merging points. P11 and start are the same point. m It is the same point as the end.

[0053] In this embodiment, the differences between initial path points, merged path points, and final path points are as follows: Initial path points are path points obtained using the A* algorithm without undergoing same-direction point merging or optimization processing. The paths between any two adjacent initial path points may have the same or different directions as adjacent paths. Merged path points are path points obtained after merging initial path points with the same direction. The set of merged path points belongs to the set of initial path points, and the paths between any two adjacent merged path points have different directions than adjacent paths. Final path points are path points obtained after optimizing merged path points. The set of final path points is equal to the set of merged path points (corresponding to the case where there are no merged path points that need to be optimized in the merged path point set), or the set of final path points does not belong to the set of merged path points (corresponding to the case where there are merged path points that need to be optimized in the merged path point set; optimization refers to being replaced by points outside the merged path point set, and the number of times the overall path direction changes after optimization is reduced). The paths between any two adjacent final path points have different directions than adjacent paths.

[0054] In one specific implementation, S1000 includes:

[0055] S1100, after rasterizing the integrated circuit schematic area, an obstacle map is created; the obstacle map includes obstacle points in the integrated circuit schematic area.

[0056] It should be understood that the schematic diagram area of ​​an integrated circuit is a continuous two-dimensional plane, while the A* algorithm is a path search algorithm in discrete space. By rasterization, the schematic diagram area of ​​an integrated circuit can be divided into grids, and each grid represents a point.

[0057] In this embodiment, the obstacle map is used to represent areas where wiring is prohibited. For example, components, existing traces, and vias in the schematic diagram are all areas where wiring is prohibited, i.e., obstacles. When a grid contains an obstacle, that grid is an obstacle point; when a grid does not contain an obstacle, that grid is not an obstacle point and is a passable point.

[0058] S1200, use the A* algorithm to solve for the sequence P0 of initial path points between start and end; P0=[P01,P02,…,P0…]. i ,…,P0 n ], P0 i It is the i-th initial waypoint, where i ranges from 1 to n, and n is the number of initial waypoints; the path between any two adjacent initial waypoints in P0 is either horizontal or vertical; P01 and start are the same point, P0 n It is the same point as the end.

[0059] As a specific implementation, the process of using the A* algorithm to solve for the sequence P0 of initial path points between start and end includes:

[0060] Let there be two sets, A representing points that can be visited in the future, and B representing points that have already been visited. Points in B cannot be visited again. Let the function total_cost(x) = already_cost(x) + heuristic(x), where already_cost(x) represents the Manhattan distance between the current point and the starting point, and Heuristic(x) represents the Manhattan distance between the current point and the target point.

[0061] Initialization begins by adding the starting point to set A, and then iterating. Each time, a point `current_point` is selected from set A that minimizes the `total_cost` function value. `current_point` cannot be contained within the obstacle map. Then, the four adjacent points of `current_point` are traversed: up, down, left, and right. If an adjacent point is already in set B, it has been traversed and is skipped; otherwise, the adjacent point is added to set A, and the current `total_cost(x)` function is checked. If its value is smaller, it is updated. The parent node (i.e., the previous point) of the current adjacent point needs to be recorded.

[0062] The algorithm iterates until current_point equals the target point, or the number of searches exceeds a preset value (e.g., 400,000 times), at which point the algorithm ends.

[0063] Finally, output the recorded points in reverse order to obtain P0.

[0064] S1300: Based on whether the path between any two adjacent initial passing points in P0 is in the same direction as the adjacent path, merge the initial passing points in P0 to obtain P1.

[0065] As one specific implementation, S1300 includes:

[0066] S1310, initialize an empty list P and add P01 to P.

[0067] S1320, Starting from P02, determine the initial waypoints in P0. If the path between an initial waypoint and the previous initial waypoint has a different direction than the path between the current initial waypoint and the next initial waypoint, then add the initial waypoint to P and determine the next initial waypoint, until the next initial waypoint is P0. n If the directions are the same, the initial path point is not added to P, and the next initial path point is checked until the next initial path point is P0. n .

[0068] S1330, P0 n Add to P, and set the latest P as P1.

[0069] For example, P0 = [P01, P02, P03, P04, P05], where the path between P01 and P02 is horizontal, the path between P02 and P03 is horizontal, the path between P03 and P04 is vertical, and the path between P04 and P05 is vertical. Then P1 = [P11, P12, P13], where P11 and P01 are the same point, P12 and P03 are the same point, and P13 and P05 are the same point.

[0070] S2000, select at least one merging path point from P1 as the optimization starting point. For each optimization starting point, start the optimization process on the merging path points in P1 to obtain the final path point between start and end corresponding to the optimization starting point. The optimization process is used to reduce the number of times the path direction changes between start and end.

[0071] In one specific implementation, between S1000 and S2000, the method further includes a step of determining whether m≥4 is satisfied. If satisfied, the process proceeds to S2000; otherwise, the process does not proceed to S2000, and the merging path point in P1 is determined as the final path point between start and end.

[0072] As a specific implementation method, for each optimization starting point, the merged path points in P1 are optimized starting from that optimization starting point to obtain the final path points between the start and end points corresponding to that optimization starting point, including:

[0073] S2100, obtain the index k of the optimization starting point; 2≤k≤m-2.

[0074] S2200, will be based on P1 k and P1 k+2The rectangle constructed for the diagonal vertices is determined as the latest bounding box, and the process proceeds to S2300.

[0075] S2300: Determine if all points on the first and second sides of the latest bounding box are traversable. If so, replace the merged path point in P1 that is on the latest bounding box but not on its first and second sides with the intersection of the first and second sides of the latest bounding box, and proceed to S2400; otherwise, proceed to S2500; the second side is the path point on P1. k+2 The endpoint is P1 k and P1 k+1 Edges in the same direction on paths between them, the first edge being not starting with P1 k+2 The endpoint is P1 k and P1 k+1 Edges with different directions on the paths between them.

[0076] In this embodiment, the value of m remains unchanged during the execution of S2100-S2600.

[0077] As a specific implementation, determining whether all points on the first and second sides of the latest bounding box are walkable points includes: if a point on the first and second sides of the latest bounding box is an obstacle point in the obstacle map, then the point is determined not to be a walkable point; otherwise, the point is determined to be a walkable point.

[0078] S2400, determine if m≥k+4 is satisfied. If so, update k to k+2, using the intersection of the first and second sides of the latest bounding box and P1. k+2 Construct a new rectangle for the diagonal vertices and define this new rectangle as the latest rectangle, then proceed to S2300; if the condition is not met, proceed to S2600.

[0079] S2500: Determine if m≥k+3 is satisfied. If satisfied, update k to k+1 and proceed to S2200; otherwise, proceed to S2600.

[0080] S2600 performs point merging on the latest points in P1, and determines the points obtained after processing as the final path points between the start and end points corresponding to the optimization starting point.

[0081] In this embodiment, for each optimization starting point, based on S2100-S2600, optimization processing of the merged path points in P1 can be implemented starting from the optimization starting point to obtain the final path point between start and end corresponding to the optimization starting point.

[0082] As a preferred implementation, two or more merging waypoints are selected as the optimization starting point to avoid the problem that the final path direction still changes frequently due to obstacles when only one merging waypoint is selected as the optimization starting point. Optionally, a preset number (e.g., 2, 3, 5, etc.) of merging waypoints are selected as the optimization starting point, and merging waypoints close to the start are selected as the optimization starting point, such as P12, P13, etc.

[0083] S3000: If only one optimization starting point is selected, then the final path point between start and end corresponding to that optimization starting point is determined as the final path point between start and end; otherwise, the final path point between start and end corresponding to the optimization starting point with the smallest number of corresponding final path points is determined as the final path point between start and end.

[0084] In one specific implementation, start and end are any connection points on any pin or bus in the integrated circuit schematic.

[0085] As a specific implementation, before S1000, the method further includes: if the user specifies more than two starting points and more than two target points, then S1000-S3000 are executed for each pair of starting points and target points respectively.

[0086] This embodiment supports routing between any two points in the integrated circuit schematic, batch routing between chips, and batch routing between a chip and a bus. When batch routing is required, steps S1000-S3000 are executed for each pair of points to be routed in a preset order. Figure 5 This is the wiring effect obtained by using the automatic routing process of this embodiment to wire between multiple pairs of pins of the two chips. Figure 6 The wiring effect is obtained by using the automatic routing process of this embodiment to route multiple pins of a chip and multiple connection points of a bus.

[0087] This embodiment merges the initial path points between the start and end points obtained using the A* algorithm, eliminating redundant intermediate nodes in the initial horizontal or vertical directions and ensuring that adjacent paths have different directions. Based on this, one or more merged path points are selected as optimization starting points, and optimization is performed on each. The path with the fewest final path points is then selected as the global result. This mechanism allows the optimization process to attempt path optimization from different positions (the optimization aims to reduce the number of changes in path direction between start and end), effectively overcoming the local optima defect of a single optimization starting point. This ensures that the final output path has fewer inflection points, reducing the complexity of the integrated circuit schematic and increasing its readability.

[0088] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A method for adding networks in an integrated circuit schematic, characterized in that, The method includes the following steps: S100: Obtain the preset information of the pins in the integrated circuit schematic that need to have a network added, and output a preset type file; the preset type file includes several entries, each entry including the preset information of a pin in the integrated circuit schematic that needs to have a network added, the preset information of the pin includes the device name to which the pin belongs, the corresponding tag number of the pin and the name of the pin; S200, Obtain the file imported by the user; the file imported by the user is obtained after the user edits the preset type file, the editing includes adding a network name to each entry in the preset type file; the file imported by the user is of the same type as the preset type file; S300 iterates through each entry in the user-imported file and adds the corresponding network name and network line to the pin position of the entry in the integrated circuit schematic.

2. The method for adding a network in an integrated circuit schematic according to claim 1, characterized in that, S300 also includes: during the process of traversing each entry in the user-imported file, each entry is checked, including checking whether the device name in the entry exists. If it does not exist, an error message is output and the operation of adding network name and network line is not performed.

3. The method for adding a network in an integrated circuit schematic according to claim 2, characterized in that, The check also includes: checking whether the pin number and pin name in the entry match. If they do not match, an error message is output and the operation of adding network name and network line is not performed.

4. The method for adding a network in an integrated circuit schematic according to claim 1, characterized in that, The S300 includes: If the field representing the network name of an entry contains only one network name, then add a network line to the pin position corresponding to that entry in the integrated circuit schematic, and determine the network name included in the field representing the network name of that entry as the network name corresponding to that network line.

5. The method for adding a network in an integrated circuit schematic according to claim 4, characterized in that, S300 includes: if the field representing the network name of an entry includes two network names and the name of a newly added device, then two network lines and an electrical symbol representing the newly added device are added to the integrated circuit schematic, wherein the first network line is connected to the pin corresponding to the entry and the electrical symbol representing the newly added device, and the second network line is connected only to the electrical symbol representing the newly added device.

6. The method for adding a network in an integrated circuit schematic according to claim 1, characterized in that, The preset file type is a CSV file.

7. The method for adding a network in an integrated circuit schematic according to claim 1, characterized in that, The growth direction of the network line is determined by the direction of the corresponding pin: when the corresponding pin is facing left, the network line grows to the left; when the corresponding pin is facing up, the network line grows upward; when the corresponding pin is facing right, the network line grows to the right; and when the corresponding pin is facing down, the network line grows downward.

8. The method for adding a network in an integrated circuit schematic according to claim 1, characterized in that, The length of the network line is a preset length or can be set by the user.

Images