FPGA chip resource storage and visualization method based on xml and json cooperation

Abstract

The application discloses an FPGA chip resource storage and visualization method based on XML and JSON cooperation, comprising the following steps: constructing an XML file and multiple JSON files, the XML file storing type definitions and hierarchical relationships of various resource types in the FPGA chip, the JSON files storing type identification information of resources at various grid positions, one JSON file being associated with one preset FPGA chip and identification information thereof; mapping and associating type identification information at various grid positions with corresponding type definitions and hierarchical relationships in the XML file; loading corresponding JSON files according to target chip identification, combining the XML file to construct a wiring resource dataset containing graphic items, each graphic item corresponding to one resource and carrying geometric position information and type definitions and hierarchical relationships; and generating a visual graphic interface based on the dataset and responding to positioning and display feedback operations of a user. The application realizes decoupled storage of architecture description and instance data and supports visualization of multiple FPGA chip models.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design of integrated circuits, and specifically relates to a method for storing and visualizing FPGA chip resources based on XML and JSON collaboration. Background Technology

[0002] An FPGA chip primarily consists of three core resources: programmable logic units, programmable interconnect resources, and programmable input / output units. These resources have a clearly defined physical hierarchy and spatial layout. In the FPGA EDA tool flow, particularly in placement and routing verification, timing analysis, and debugging, accurately and efficiently storing the chip's complete resource information and presenting it graphically is a fundamental and crucial technology supporting upper-layer applications.

[0003] Existing technologies typically use custom binary formats or flat text files (such as .txt and .dat) to store resource information for specific FPGA chip models, and build independent, self-contained storage files and corresponding parsing modules for each chip model. When multiple chip models need to be supported, a complete description file is maintained for each model.

[0004] In this type of scheme, the static architecture information of the chip (such as tile type definition, cell internal structure, and interconnect topology) and the instantiated layout information of the specific chip (such as the specific type of tile at each grid position) are mixed and stored in the same data structure. Since the architecture information is not extracted from the instance data, all referenced architecture definitions must be completely copied for each new chip model, resulting in storage redundancy and a sharp increase in maintenance costs. At the same time, the flat storage structure lacks an explicit expression of the resource hierarchy, making it difficult for the parser to extract the hierarchical relationship of "repeatable physical layout unit Tile → minimum circuit module Cell → pin / interconnection Wire". The visualization tool cannot achieve general, data-driven hierarchical rendering and must write dedicated parsing code for each chip. Furthermore, due to the lack of a unified data model, such visualization tools usually only provide basic zoom and pan, and cannot achieve fast retrieval and positioning of specific resources and attribute viewing, resulting in low debugging efficiency.

[0005] Therefore, there is an urgent need to construct a storage and visualization method that decouples architecture description from instance data, explicitly describes resource hierarchy relationships, and provides general data support for efficient interactive visualization. Summary of the Invention

[0006] To address the aforementioned problems in existing technologies, this invention provides a method for storing and visualizing FPGA chip resources based on XML and JSON collaboration. The technical problem to be solved by this invention is achieved through the following technical solution: A method for storing and visualizing FPGA chip resources based on XML and JSON collaboration, comprising: Construct an XML file and multiple JSON files. The XML file is used to store the type definitions and hierarchical relationships of various resource types inside the FPGA chip. The JSON files are used to store the type identification information of resources at each grid location. Each JSON file corresponds to a preset FPGA chip and is associated with the chip identification information of the preset FPGA chip. For each resource at each grid position in the JSON file, establish a mapping association between the type identification information and the type definition and hierarchical relationship corresponding to the resource in the XML file; The corresponding JSON file is loaded according to the chip identification information of the target FPGA chip. Based on the mapping association of the resources corresponding to each grid position in the JSON file, a routing resource dataset containing multiple graphic items is constructed. Each graphic item corresponds to a resource inside the target FPGA chip and carries the geometric position information of the resource, as well as the type definition and hierarchical relationship. A visual graphical interface is generated based on the aforementioned cabling resource dataset; In response to user actions on the graphical interface, the system performs location and display feedback on the target resource.

[0007] In one embodiment of the present invention, the resource type includes repeatable physical layout units, minimum circuit modules, pins, interconnects, programmable switches, and basic logic units; The hierarchical relationship includes: The repeatable physical layout unit includes the minimum circuit module; the minimum circuit module includes the basic logic unit and the pin; the interconnect line connects each of the minimum circuit modules starting from the pin; the programmable switch is disposed between each of the repeatable physical layout units and is used to achieve signal interconnection between the repeatable physical layout units together with the interconnect line.

[0008] In one embodiment of the present invention, the XML file includes: A chip label is used to describe a preset FPGA chip, including a model name field and a repeatable physical layout unit type name list field. The model name field is used to record the model name of the preset FPGA chip, and the repeatable physical layout unit type name list field is used to record the type names of all repeatable physical layout units contained in the preset FPGA chip. A repeatable physical layout unit tag is used to describe a repeatable physical layout unit, including a name field of the repeatable physical layout unit, a list field of type names of the minimum circuit modules contained therein, and a shape coordinate field, wherein the shape coordinate field is used to represent the shape of the repeatable physical layout unit. Minimum circuit module label, used to describe a minimum circuit module, including the name field, first geometric position information field, shape coordinate field, pin information field, basic logic unit information field, and interconnect information field of the minimum circuit module, wherein the first geometric position information field is used to describe the geometric position of the minimum circuit module relative to its topping repeatable physical layout unit; A programmable switch label is used to describe a programmable switch, including a switch name field, a drawing shape type field, a second geometric position information field, and a connection relationship information field. The connection relationship information field includes an input signal source list field and an output signal target list field for the programmable switch. The second geometric position information field is used to describe the geometric position of the programmable switch relative to its respective repeatable physical layout unit.

[0009] In one embodiment of the present invention, the pin information field in the minimum circuit module label is used to describe the pin information of the minimum circuit module. The pin information includes the name, drawing shape type, pin type and orientation of each pin included in the minimum circuit module, as well as the spacing between pins and the geometric position information of each pin relative to the minimum circuit module. The interconnection information field is used to describe the interconnection information of interconnections originating from the pins of the minimum circuit module. The interconnection information includes at least one of the following connection relationship description methods: Direct interconnection between the two pins; Jump connections implemented via hard channels; An interconnecting line is composed of multiple line segments, and the path of each line segment is defined by multiple coordinate points; Interconnecting lines, consisting of a set of line segments, are described in batches by defining the coordinates of the first line segment and the offset rules of subsequent line segments.

[0010] In one embodiment of the present invention, the JSON file includes an FPGA chip model name field and a layout data array field. The layout data array field contains multiple layout record objects, and each layout record object records the column number, row number, and type name of the repeatable physical layout unit of its corresponding grid position in the form of key-value pairs.

[0011] In one embodiment of the present invention, the type identification information is the type name of the resource, and the chip identification information is the model name of the FPGA chip; the step of establishing a mapping association between the type identification information of the resource at each grid position in the JSON file and the type definition and hierarchical relationship corresponding to the resource in the XML file includes: Using the resource type name as the key field, the resource type name recorded in each grid position of the JSON file is associated with the type definition and hierarchical relationship of the resource type corresponding to that type name in the XML file. Each grid position indexes the corresponding type definition and hierarchical relationship in the XML file through its corresponding type name.

[0012] In one embodiment of the present invention, the step of constructing a wiring resource dataset containing multiple graphical items based on the mapping associations corresponding to the resources at each grid position in the JSON file includes: Obtain the grid positions and their corresponding type identifiers from the JSON file, and based on the obtained type identifiers and their corresponding mapping associations, obtain the corresponding type definitions and hierarchical relationships from the XML file; Resource objects are instantiated based on the type definition and hierarchical relationship corresponding to each grid position in the JSON file, and the graphic position of the corresponding resource object is calculated based on the position information of each grid position, thereby generating graphic items corresponding to each resource object.

[0013] In one embodiment of the present invention, generating a visual graphical interface based on the cabling resource dataset includes: The display hierarchy is determined based on the display parameters of the current view; Select a graphic item from the wiring resource dataset that matches the display level and the view extent of the current view; The selected graphic items are converted into drawing data and then drawn to generate the visual graphical interface. The display layers are multiple, each display layer corresponds to a different resource type, and different display layers correspond to different resource display granularities. The display layers include at least a repeatable physical layout unit layer, a minimum circuit module layer, and an interconnection resource layer.

[0014] In one embodiment of the present invention, the step of responding to a user's operation on the visual graphical interface to perform positioning and display feedback on the target resource includes at least one of the following: In response to the target resource identifier entered by the user, locate and highlight the corresponding graphical item in the view; In response to a user's hover or click action on a graphical item, display the attribute information of the resource corresponding to that graphical item; In response to the user's color selection operation for the target mesh, change the drawing color of the graphic items covered by the target mesh.

[0015] In one embodiment of the present invention, changing the drawing color of the graphic item covered by the target graticule in response to a user's color selection operation on the target graticule includes: Establish and maintain the mapping relationship between each net and the graphic items it covers; In response to the user's color selection operation for the target mesh, all graphic items covered by the target mesh are obtained according to the mapping relationship; Change the drawing color of all the obtained graphic items uniformly, and refresh the view.

[0016] The beneficial effects of this invention are: This invention stores the type definitions and hierarchical relationships of various resource types within an FPGA chip, as well as the type identification information of resources at each grid location, using XML files and multiple JSON files. Each JSON file corresponds to a pre-defined FPGA chip and is associated with its chip identification information. This allows the type definitions and hierarchical relationships to be reused across multiple pre-defined FPGA chip JSON files. When adding a new chip model, only a JSON file describing its grid layout needs to be added, without repeatedly storing the type definitions and hierarchical relationships of each resource type. This significantly reduces storage redundancy and development / maintenance costs associated with multi-chip support, effectively solving the problems of poor multi-chip scalability and file size expansion caused by tight coupling between architecture and instance in existing technologies. Furthermore, this invention establishes corresponding type definitions and hierarchical relationships for the type identification information at each grid location within the XML file. The mapping and association between hierarchical relationships enable each grid position in the JSON file to be indexed by its type identifier information to the corresponding complete type definition and hierarchical relationship in the XML file, achieving decoupling between architecture and instance. Each graphic item in the constructed wiring resource dataset carries the geometric position information of the resource and the aforementioned type definition and hierarchical relationship, allowing the generation of a visual graphical interface to directly select the matching graphic item for drawing based on the view's display parameters, eliminating the need to write dedicated parsing and rendering code for each chip. This solves the problem in existing technologies where visualization tools are difficult to directly parse and display in layers due to the lack of explicit expression of hierarchical relationships in the storage structure. Furthermore, the visual graphical interface responds to user operations on target resources, performing positioning and display feedback, enabling users to quickly locate and analyze specific resources, improving the efficiency of FPGA design verification and debugging.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a method for storing and visualizing FPGA chip resources based on XML and JSON collaboration, provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] Example 1 The English descriptions appearing in this embodiment will be explained in a consistent Chinese style: Tile - Repeatable physical layout unit; Cell - Minimal circuit module; Pin - Pin; Mux - Programmable switch; Wire - Interconnect; BLE (Basic Logic Element) - Basic logic element; FPGA (Field-Programmable Gate Array) - Field-Programmable Gate Array; XML (Extensible Markup Language) - Extensible Markup Language; JSON (JavaScript Object Notation) is a lightweight data exchange format; Qt is a cross-platform application development framework.

[0021] It should be noted that FPGA chips are mainly composed of three core resources: programmable logic units, programmable interconnect resources, and programmable input / output units. These resources have a clear physical hierarchy and spatial layout relationship. In the FPGA EDA tool flow, especially in placement and routing verification, timing analysis and debugging, accurately and efficiently storing the complete resource information of the chip and presenting it intuitively in a graphical manner is a fundamental and critical technology supporting upper-layer applications. In existing technologies, the static architecture information of the chip and the instantiated placement information of the specific chip are stored together in the same data structure, resulting in poor multi-chip scalability, difficulty in achieving universal layered rendering in visualization tools, and low debugging efficiency.

[0022] To address the aforementioned technical problems, this embodiment provides a method for storing and visualizing FPGA chip resources based on XML and JSON collaboration, such as... Figure 1 As shown, it includes: S1. Construct an XML file and multiple JSON files. The XML file is used to store the type definitions and hierarchical relationships of various resource types inside the FPGA chip. The JSON files are used to store the type identification information of resources at each grid location. One JSON file corresponds to one preset FPGA chip and is associated with the chip identification information of the preset FPGA chip. Specifically, in this embodiment, the hierarchical architecture information of each resource type inside the FPGA chip is stored in an XML file. This XML file serves as a general architecture template for the FPGA chip, used to describe the type definition and hierarchical relationship of each resource type inside the FPGA chip. The instantiation layout information is stored in a JSON file. The JSON file records the type name of the repeatable physical layout unit placed at each grid position. One JSON file corresponds to one preset FPGA chip and is associated with its chip identification information.

[0023] Understandably, by storing hierarchical architecture information in XML files and instantiated layout information in JSON files, the separation of type definitions and hierarchical relationships from instance data is achieved. This allows the type definitions of repeatable physical layout units defined in XML to be reused in JSON files of multiple chip models, laying the foundation for subsequent multi-chip expansion.

[0024] Furthermore, in step S1, The resource types include repeatable physical layout units, minimum circuit modules, pins, interconnects, programmable switches, and basic logic units; The hierarchical relationship includes: The repeatable physical layout unit includes the minimum circuit module; the minimum circuit module includes the basic logic unit and the pin; the interconnect line connects each of the minimum circuit modules starting from the pin; the programmable switch is disposed between each of the repeatable physical layout units and is used to achieve signal interconnection between the repeatable physical layout units together with the interconnect line.

[0025] Specifically, in this embodiment, repeatable physical layout units constitute the FPGA core array; minimum circuit modules implement specific functions; pins are the input / output ports on the minimum circuit modules; programmable switches are programmable interconnect switches; interconnects, starting from pins, serve as signal lines connecting the minimum circuit modules, connecting different minimum circuit modules within the same repeatable physical layout unit or connecting minimum circuit modules within different repeatable physical layout units, thus connecting different repeatable physical layout units; basic logic units are the smallest units within the minimum circuit modules that implement basic logic functions. The hierarchical relationship is as follows: the FPGA chip contains multiple repeatable physical layout units; each repeatable physical layout unit contains multiple minimum circuit modules; each minimum circuit module contains a basic logic unit and its own pins; minimum circuit modules are connected by interconnects starting from pins; programmable switches are placed between the minimum circuit modules. The XML file explicitly records the above hierarchical nesting relationship of "repeatable physical layout unit → minimum circuit module / programmable switch → pin / interconnect / basic logic unit" through a nested tag structure.

[0026] It is understandable that the above resource types cover the core components inside the FPGA chip, and there is a clear hierarchical nesting relationship between the resource types. The hierarchical nesting relationship between resources is explicitly expressed through the tree structure of the XML file, which enables the parser to directly extract the hierarchical belonging relationship, providing structured data support for data-driven hierarchical rendering.

[0027] Furthermore, in step S1, the XML file includes: A chip label is used to describe a preset FPGA chip, including a model name field and a repeatable physical layout unit type name list field. The model name field is used to record the model name of the preset FPGA chip, and the repeatable physical layout unit type name list field is used to record the type names of all repeatable physical layout units contained in the preset FPGA chip. A repeatable physical layout unit tag is used to describe a repeatable physical layout unit, including a name field of the repeatable physical layout unit, a list field of type names of the minimum circuit modules contained therein, and a shape coordinate field, wherein the shape coordinate field is used to represent the shape of the repeatable physical layout unit. Minimum circuit module label, used to describe a minimum circuit module, including the name field, first geometric position information field, shape coordinate field, pin information field, basic logic unit information field, and interconnect information field of the minimum circuit module, wherein the first geometric position information field is used to describe the geometric position of the minimum circuit module relative to its topping repeatable physical layout unit; A programmable switch label is used to describe a programmable switch, including a switch name field, a drawing shape type field, a second geometric position information field, and a connection relationship information field. The connection relationship information field includes an input signal source list field and an output signal target list field for the programmable switch. The second geometric position information field is used to describe the geometric position of the programmable switch relative to its respective repeatable physical layout unit.

[0028] Specifically, in this embodiment, the XML file records the chip name and a list of type names of all repeatable physical layout units (PSUs) it contains through chip tags. One chip tag corresponds to one FPGA chip model, thereby enabling the storage of architecture information for multiple different chips within a single XML document. The XML file records the name of the repeatable physical layout unit (PSU), a list of type names of its constituent minimum circuit modules, and coordinate information representing the shape of the PSU through repeatable physical layout unit tags. The XML file defines the type of each minimum circuit module through minimum circuit module tags. This type definition includes the name of the minimum circuit module, its geometric position relative to its constituent PSU, its shape coordinates, pin information and basic logic unit information contained within the minimum circuit module, and interconnection information for interconnects originating from the pins of the minimum circuit module. The XML file defines the type of each programmable switch through programmable switch tags. This type definition includes the switch name, drawing shape type, geometric position relative to its constituent PSU, and connection relationship information, including a list of input signal sources and a list of output signal targets.

[0029] For example, a chip tag is used to describe a preset FPGA chip, including a model name field and a list field of repeatable physical placeholder (PPT) type names. The model name field records the model name of the preset FPGA chip (e.g., "SA5Z-30"). One chip tag corresponds to one FPGA chip model, and multiple chip tags can describe various different chip models in a single XML document. The list field of repeatable PPT type names records the type names of all repeatable PPTs contained in the FPGA chip, separated by delimiters (e.g., "PT,CIB,PB,PLB,DDRCTRL,MULT…"), indicating which types of repeatable PPTs constitute the chip.

[0030] The repeatable physical layout unit label describes a repeatable physical layout unit (Tile), containing a name field, a list of type names of the contained minimum circuit modules, and a shape coordinate field. The name field records the type name of the repeatable physical layout unit (e.g., "PLB"), which serves as a key field associated with the type name list in the chip label and the type names recorded at each grid position in the JSON file. The list of type names of the contained minimum circuit modules records the type names of all the minimum circuit modules contained within the repeatable physical layout unit (e.g., "SLICEL, SLICEM…"), indicating which types of Cells constitute the Tile. The shape coordinate field records the outline shape of the repeatable physical layout unit in the chip, represented by coordinate information separated by three spaces (e.g., "(2380,0) (2380,3513) (0,3513)"), used to subsequently determine the drawing boundary of the Tile.

[0031] The minimum circuit module label is used to describe a minimum circuit module (Cell), which includes a name field, a first geometric location information field, a shape coordinate field, as well as a pin information field, an interconnect information field, and a basic logic unit information field.

[0032] The Name field records the type name of the minimum circuit module (such as "SLICEL"), which is associated with the list of minimum circuit module type names in the repeatable physical layout cell label.

[0033] The first geometric position information field records the geometric position offset of the smallest circuit module relative to its repeatable physical layout unit (e.g., "(1380,2645)"), which is used to calculate the actual drawing position of the cell based on the global coordinates of the tile.

[0034] The shape coordinate field records the outline shape of the smallest circuit module, represented by coordinate information separated by three spaces (such as "(280,0) (280,400) (0,400)"), which is used to determine the drawing boundary of the cell.

[0035] The pin information field describes all the pin information contained in this minimum circuit module. The information for each pin includes: pin name (e.g., "L_A[1:6]"), drawing shape type (e.g., "top"), pin spacing (used to determine the relative spacing between pins in the same group), the geometric position information of the pin relative to this minimum circuit module (e.g., "(50,0)"), pin type (e.g., "PI"), and pin orientation (e.g., "inout"). The pin information is used to determine the specific location and electrical properties of each pin within the cell.

[0036] The interconnect information field describes interconnect information starting from the pins inside the minimum circuit module. It supports multiple ways of describing connection relationships: direct interconnection between two pins, described by the starting pin name and the ending pin name; jump connection implemented through hard channels, described by the starting / ending pin name and the hard channel name. Each repeatable physical layout unit has horizontal and vertical hard channels distributed to connect jump lines and clock lines; interconnection composed of multiple segments, defining the complete segment path through the starting pin name, the ending pin name, and multiple segment coordinates, used to describe double-line connections and long-line connections on the switch box; interconnection composed of a group of segments, achieving batch description of a group of interconnections by defining the coordinates of the first segment and the offset rules of subsequent segments.

[0037] The Basic Logic Unit Information field describes the Basic Logic Unit (BLE) information contained within the minimum circuit module. Each BLE includes its name, geometric position relative to the minimum circuit module, and shape coordinates.

[0038] The programmable switch label describes a programmable switch (Mux) and includes a switch name field, a drawing shape type field, a second geometric position information field, and a connection relationship information field. The switch name field records the name of the programmable switch; the drawing shape type field determines the drawing style of the switch in the visual graphical interface; the second geometric position information field records the geometric position of the programmable switch relative to its belonging repeatable physical layout unit, used to determine the drawing position of the switch in the Tile; the connection relationship information field includes a list of input signal sources and a list of output signal targets, used to describe the input sources and output targets of the programmable switch to support signal path tracing and display.

[0039] Understandably, through the above four-layer tag structure (chip tag, repeatable physical layout unit tag, minimum circuit module tag, programmable switch tag), the XML file fully describes the type definition and hierarchical nesting relationship of each resource type inside the FPGA chip. Each tag is associated with the others through the name field to form a complete architecture definition. Furthermore, the type definition of the same repeatable physical layout unit can be reused by multiple chip models, avoiding duplicate storage.

[0040] Furthermore, in step S1, the pin information field in the minimum circuit module label is used to describe the pin information of the minimum circuit module. The pin information includes the name, drawing shape type, pin type and orientation of each pin contained in the minimum circuit module, as well as the spacing between pins and the geometric position information of each pin relative to the minimum circuit module. The interconnection information field is used to describe the interconnection information of interconnections originating from the pins of the minimum circuit module. The interconnection information includes at least one of the following connection relationship description methods: Direct interconnection between the two pins; Jump connections implemented via hard channels; An interconnecting line is composed of multiple line segments, and the path of each line segment is defined by multiple coordinate points; Interconnecting lines, consisting of a set of line segments, are described in batches by defining the coordinates of the first line segment and the offset rules of subsequent line segments.

[0041] Specifically, pin information includes attributes such as pin name, drawing shape type, pin spacing, geometric position relative to the smallest circuit module, pin type, and orientation. Interconnect information supports multiple ways to describe connection relationships: direct interconnection between two pins, with the start and end points identified by the pin name; jump connections implemented via hard channels, with horizontal and vertical hard channels distributed on each repeatable physical layout unit to connect jump lines and clock lines; interconnections composed of multiple segments, with the segment path defined by multiple coordinate points; and interconnections composed of a set of segments, where a set of interconnects can be described in batches by defining the coordinates of the first segment and the offset rules for subsequent segments.

[0042] Understandably, the specific content of pin information, interconnect information, and programmable switch information is the core part of the resource type definition in the XML file. Pin information defines the input and output port attributes of the minimum circuit module, interconnect information defines the transmission path of signals within the minimum circuit module, and programmable switch information defines the programmable interconnection relationship of signals between repeatable physical layout units, providing a complete data foundation for subsequent instantiation of resource objects and calculation of graphics positions.

[0043] Furthermore, in step S1, the JSON file includes an FPGA chip model name field and a layout data array field. The layout data array field contains multiple layout record objects, and each layout record object records the column number, row number, and type name of the repeatable physical layout unit of its corresponding grid position in key-value pairs.

[0044] Specifically, in this embodiment, the JSON file stores the instantiation layout information of the FPGA chip, including the FPGA chip model name field and the layout data array field. The layout data array field contains multiple layout record objects. Each layout record object records the column number, row number, and type name of the repeatable physical layout cell of its corresponding grid position in the form of key-value pairs. Each record contains three key-value pairs: column number, row number, and type name.

[0045] Understandably, JSON files store instantiated layout information in a lightweight key-value pair format, allowing each grid position to be uniquely located by its column and row numbers, and to be indexed to the corresponding type definition in the XML file by its type name, thus providing a data foundation for subsequent relational modeling.

[0046] S2. For the type identification information of the resource at each grid position in the JSON file, establish a mapping association between the type definition and hierarchical relationship corresponding to the resource in the XML file; Specifically, in this embodiment, the FPGA chip determines the type name of the repeatable physical layout unit at each row and column position through the instantiation layout information in the JSON file, and then associates the type name with the type definition of the repeatable physical layout unit in the XML file. Each grid position in the JSON records the type name of a repeatable physical layout unit, which serves as an index to the type definition of the repeatable physical layout unit with the same name in the XML. This allows the FPGA chip to obtain the shape coordinates of the repeatable physical layout unit, the list of its internal minimum circuit modules, and the type definition of each minimum circuit module. Ultimately, the FPGA chip determines the geometric position information of the repeatable physical layout unit at that grid position during drawing, as well as the complete hierarchical structure of its internal minimum circuit modules, pins, interconnects, programmable switches, and basic logic units.

[0047] It is understandable that this embodiment establishes a mapping relationship so that each grid position in the JSON file can be indexed by its type name to the corresponding complete type definition and hierarchical relationship in the XML file, thus realizing a collaborative storage mode of "one set of architecture definition and multiple sets of instance data".

[0048] Further, in step S2, the type identification information is the type name of the resource, and the chip identification information is the model name of the FPGA chip; establishing a mapping association between the type identification information of the resource at each grid position in the JSON file and the type definition and hierarchical relationship corresponding to the resource in the XML file includes: Using the resource type name as the key field, the resource type name recorded in each grid position of the JSON file is associated with the type definition and hierarchical relationship of the resource type corresponding to that type name in the XML file. Each grid position indexes the corresponding type definition and hierarchical relationship in the XML file through its corresponding type name.

[0049] Specifically, in this embodiment, each layout record object in the JSON file contains a column number, a row number, and a type name for the repeatable physical layout unit. The value of the type name field of the repeatable physical layout unit is used as the key field to search for the type definition of the repeatable physical layout unit with the same name in the XML file, thereby obtaining complete definition information such as the shape coordinates and the list of the minimum circuit modules contained in the repeatable physical layout unit.

[0050] It is understandable that this embodiment uses the type name as the key field to establish a mapping relationship, which is a simple and efficient indexing method that can achieve fast location from instance data to type definition without the need for additional mapping tables or complex data structures.

[0051] S3. Load the corresponding JSON file according to the chip identification information of the target FPGA chip, and construct a routing resource dataset containing multiple graphic items based on the mapping association of resources corresponding to each grid position in the JSON file. Each graphic item corresponds to a resource inside the target FPGA chip and carries the geometric position information of the resource and the type definition and hierarchical relationship. Specifically, in this embodiment, an XML parser is first used to read the XML file, traverse each tag in the file, and extract information from the chip tag, repeatable physical layout unit tag, minimum circuit module tag, and programmable switch tag in sequence. That is, the correspondence between the chip and the repeatable physical layout unit, the relationship between the repeatable physical layout unit and the minimum circuit module, the type definition of each minimum circuit module (including pin, interconnect and basic logic unit information), and the relationship between the programmable switch and the repeatable physical layout unit are extracted. The extracted type definition of each repeatable physical layout unit and its complete internal hierarchical structure are stored in memory in the form of key-value pairs to build a resource type definition library.

[0052] Subsequently, based on the model name of the target FPGA chip, the corresponding JSON file is searched from multiple JSON files and loaded. The JSON parser is used to read the file and obtain the layout data array recorded therein, including the type name of the repeatable physical layout cell for each grid position.

[0053] Then, the layout data array is traversed. For each layout record object, the column number, row number, and type name of the repeatable physical layout unit corresponding to its grid position are obtained. The corresponding type definition is searched from the resource type definition library in memory using the type name as an index. Based on the definition, the repeatable physical layout unit object and its internal minimum circuit modules, pins, interconnects, programmable switches, basic logic units, and other resource objects are instantiated. At the same time, the actual geometric position of the repeatable physical layout unit and its internal sub-resources in the chip global coordinate system is calculated based on the column number and row number of the grid position (where the position of the repeatable physical layout unit is determined by multiplying the column number and row number by the basic size of the repeatable physical layout unit, the position of the minimum circuit module is determined by adding the offset of the minimum circuit module relative to the repeatable physical layout unit to the position of the repeatable physical layout unit, and the positions of pins and interconnects are determined in the same way).

[0054] Simultaneously, based on the second geometric position information field and connection relationship information field in the programmable switch label, programmable switch objects are instantiated between the corresponding repeatable physical layout units, and their actual geometric position in the chip global coordinate system is calculated based on their geometric position information relative to their respective repeatable physical layout units.

[0055] Finally, a wiring resource dataset containing graphical information (type, coordinates, shape, and relationships) of all chip resources is generated.

[0056] Understandably, by associating and instantiating XML type definitions and hierarchical relationships with JSON instance data, the generated wiring resource dataset contains complete graphical information of all chip resources, providing a unified data source for subsequent rendering and interaction.

[0057] Furthermore, in step S3, constructing a wiring resource dataset containing multiple graphical items based on the mapping associations corresponding to the resources at each grid location in the JSON file includes: The grid positions and their corresponding type identifiers are obtained from the JSON file. Based on the obtained type identifiers and their corresponding mapping associations, the repeatable physical layout units and their internal nested resources are instantiated according to the type names of each grid position in the layout matrix. The programmable switches are instantiated between the corresponding repeatable physical layout units according to the position information and connection relationship information in their tags. The corresponding type definitions and hierarchical relationships are obtained from the XML file. Resource objects are instantiated based on the type definition and hierarchical relationship corresponding to each grid position in the JSON file, and the graphic position of the corresponding resource object is calculated based on the position information of each grid position, thereby generating graphic items corresponding to each resource object.

[0058] Specifically, in this embodiment, each layout record object in the JSON layout data array is traversed to obtain the column number, row number, and type name of the repeatable physical layout unit corresponding to its grid position. The same type definition is searched from the resource type definition library to obtain the shape coordinates and the list of minimum circuit modules contained in the repeatable physical layout unit. Then, the actual position of the repeatable physical layout unit in the chip global coordinate system is calculated (horizontal coordinate = column number × repeatable physical layout unit width, vertical coordinate = row number × repeatable physical layout unit height). For the minimum circuit module inside the repeatable physical layout unit, its global coordinates are calculated based on the position offset of the minimum circuit module relative to the repeatable physical layout unit. For the pins inside the minimum circuit module and the interconnects corresponding to the minimum circuit module, the global position is also calculated based on their relative position or coordinate information. Finally, a corresponding graphic item is generated for each resource, and its type, coordinates, shape, hierarchical relationship, and other information are stored in the graphic item.

[0059] Understandably, by traversing the layout data array and instantiating it according to the mapping association, the abstract type definition and layout data are transformed into specific graphic items, so that each resource has a clear geometric position and hierarchical affiliation, thus preparing the data for visualization rendering.

[0060] S4. Generate a visual graphical interface based on the cabling resource dataset; Specifically, in this embodiment, visualization is implemented based on the Qt graphics view framework. During rendering, wiring resources within the visible area are selected from the wiring resource dataset generated in step S3, and the shape and position information of each resource are converted into a vector path data structure. These paths are then added to the scene for drawing.

[0061] Understandably, by pre-converting resource data into a vector path data structure and combining it with a layered rendering strategy, the number of graphics objects and computational overhead during dynamic rendering can be effectively reduced, supporting smooth scaling, panning, and real-time refreshing of large-scale resource nodes.

[0062] Furthermore, in step S4, generating a visual graphical interface based on the cabling resource dataset includes: The display hierarchy is determined based on the display parameters of the current view; Select a graphic item from the wiring resource dataset that matches the display level and the view extent of the current view; The selected graphic items are converted into drawing data and then drawn to generate the visual graphical interface. The display layers are multiple, each display layer corresponds to a different resource type, and different display layers correspond to different resource display granularities. The display layers include at least a repeatable physical layout unit layer, a minimum circuit module layer, and an interconnection resource layer.

[0063] Specifically, in this embodiment, the visible area of ​​the current view is first obtained, and the row and column range of repeatable physical layout units that need to be loaded within the current field of view is dynamically calculated based on the scene's visible width and the preset basic size of repeatable physical layout units.

[0064] The formula for calculating the column range is as follows: ; in, and These are the smallest and largest column numbers within the visible area, respectively; A mapping object from view coordinates to scene coordinates; The top left corner of the visible area in the scene coordinate system coordinate; This represents the width of the visible area in the scene coordinate system. The width of the preset repeatable physical layout unit; and These are the functions for rounding down and rounding up, respectively.

[0065] The formula for calculating the row range is as follows: ; in, and These are the minimum and maximum row numbers within the visible area, respectively; This is the height of the visible area in the current view scene; The top left corner of the visible area in the scene coordinate system coordinate; The height of the preset repeatable physical layout unit is 2380 in width and 3513 in height. In this embodiment, the basic dimensions of the preset repeatable physical layout unit are 2380 and 3513 respectively.

[0066] The calculated row and column ranges are then clipped to ensure they do not exceed the actual size of the chip, i.e., the total number of columns and rows. Subsequently, the current display level is determined based on the scene's visible width, which is divided into six levels: The first level is the repeatable physical layout unit (PROM) level display, which takes effect when the scene's visible width is greater than or equal to 40 times the width of a single repeatable PROM unit, and only displays the boundary outline of each repeatable PROM unit. The second level is the minimum circuit module level display, which takes effect when the scene's visible width is less than 40 times the width of a single repeatable PROM unit but greater than or equal to 8 times it, displaying the repeatable PROM unit and its internal minimum circuit modules. The third level is the interconnect level display, which takes effect when the scene's visible width is less than 8 times the width of a single repeatable PROM unit but greater than or equal to 4 times it, and only displays the boundary outline of each repeatable PROM unit. The first level further displays interconnects based on the previous level. The fourth level is a pin-level display, effective when the scene's visible width is less than four times the width of a single repeatable physical layout unit but greater than or equal to twice that width. It further displays pins and the smallest logic unit. The fifth level is a programmable switch-level display, effective when the scene's visible width is less than twice the width of a single repeatable physical layout unit but greater than or equal to 600. It further displays programmable switches. The sixth level displays pin names, effective when the scene's visible width is less than 600. It further displays pin names. The scene visible width conditions and display characteristics corresponding to each level are shown in the table below.

[0067] Here, sceneWidth is the visible width of the scene.

[0068] Based on the calculated visible row and column range and display layer, only resources within the current field of view are created and added to the scene for drawing. The drawing details of each graphic item are controlled by the current display layer. Resources are dynamically created and loaded as the layer increases, and resources not displayed at the current layer are dynamically hidden as the layer decreases.

[0069] Net grid graphics items are managed in an independent layer, separate from basic resource graphics items, allowing for individual control over their display, hiding, and color changes. Upon initial load, rough path graphics items are created for all nets and added to the scene. When switching from a lower to a higher level, the rough graphics items for all nets are hidden, and detailed interconnect resource graphics items used by the nets are created and displayed based on the visible area. When switching from a higher to a lower level, the detailed interconnect resource graphics items used by the nets are hidden, and the rough graphics items for all nets are displayed again.

[0070] Understandably, by using layered rendering and on-demand loading strategies, the creation and hiding of graphical items are dynamically managed when the layer changes, so that users can obtain an appropriate amount of visual information at different scaling levels. This avoids information overload at high scaling ratios and loss of detail at low scaling ratios, while also supporting the smooth display of large-scale graphical items.

[0071] S5. In response to the user's operation on the visual graphical interface, perform positioning and display feedback on the target resource.

[0072] It is understood that in this embodiment, interactive functions such as search and location, click feedback, and custom coloring are provided on the generated FPGA chip resource map. By providing rich interactive functions, users can quickly locate and analyze specific resources, combining abstract design data with intuitive visual feedback, which greatly shortens the time for FPGA design verification and debugging.

[0073] Furthermore, in step S5, the action of locating and displaying feedback on the target resource in response to the user's operation on the graphical interface includes at least one of the following: In response to the target resource identifier entered by the user, locate and highlight the corresponding graphical item in the view; In response to a user's hover or click action on a graphical item, display the attribute information of the resource corresponding to that graphical item; In response to the user's color selection operation for the target mesh, change the drawing color of the graphic items covered by the target mesh.

[0074] Specifically, in this embodiment, the retrieval and location function is as follows: The system provides a search box to obtain the target resource identifier (i.e., the target resource name, such as the net name, repeatable physical layout unit name or location, minimum circuit module name or pin name) entered by the user in the search box. It then traverses all graphic items in the current scene, accurately matches the resource identifier information stored in the graphic items with the target resource identifier entered by the user, and automatically adjusts the view position to move the graphic item into the visible area and sets it to the selected state for visual feedback with a highlight style.

[0075] The click highlight and hover tooltip functions are as follows: In response to user mouse click events, the clicked resource graphic item is highlighted, with the complete connection relationship of the interconnect segment displayed when an interconnect is clicked. In response to user mouse hover operations, a custom hover event handling method is overloaded for each graphic item. This method is triggered when the mouse hovers over a graphic item to obtain the attribute information of the resource corresponding to that graphic item, including but not limited to resource name, resource type, and row and column coordinates. If the resource is an interconnect or a programmable switch, the attribute information also includes the net to which it belongs; if the resource is a pin, the attribute information also includes the pin direction and custom attributes. The above attribute information is formatted into a string and a floating tooltip is displayed near the mouse position.

[0076] The custom coloring feature is as follows: The system maintains an independent data structure for each net, storing all graphic items contained within that net (including the interconnect graphic items and programmable switch graphic items it occupies). Upon initial loading or parsing of the routing results, a mapping table is established, reflecting the mapping relationship between net identifiers and sets of graphic items. The system provides user interface controls for selecting the target net and desired color. After the user confirms the color selection, the system retrieves the corresponding set of graphic items from the mapping relationship based on the selected net name, iterates through all graphic items in that set, and sets the new drawing color. After all graphic item colors are updated, the view is refreshed, and the user can immediately see the color change effect. The system supports users setting different colors for multiple different nets simultaneously. Each net independently maintains its color configuration and provides a clear coloring function, which can restore the color of a specified net or all nets to the system default color.

[0077] Understandably, through interactive functions such as retrieval and positioning, clicking / hovering to view properties, and customizing netting, users can quickly locate and analyze specific resources, significantly improving the efficiency of FPGA design verification and debugging.

[0078] Furthermore, in step S5, changing the drawing color of the graphic item covered by the target mesh in response to the user's color selection operation includes: Establish and maintain the mapping relationship between each net and the graphic items it covers; In response to the user's color selection operation for the target mesh, all graphic items covered by the target mesh are obtained according to the mapping relationship; Change the drawing color of all the obtained graphic items uniformly, and refresh the view.

[0079] Specifically, in this embodiment, the system uses a mapping table data structure to maintain the correspondence between net identifiers and graphic item sets. When the user selects the target net and desired color through interface controls, the system retrieves the corresponding graphic item set from the mapping table based on the net name, iterates through each graphic item in the set to update its drawing color, and finally refreshes the view to display the updated color effect.

[0080] Understandably, by establishing and maintaining the mapping relationship between nets and graphic items, independent management and batch updates of net colors are achieved, enabling users to flexibly highlight key nets of interest, facilitating design verification and debugging.

[0081] In summary, this embodiment stores the type definitions and hierarchical relationships of various resource types within the FPGA chip, as well as the type identification information of resources at each grid location, using XML files and multiple JSON files respectively. It associates the JSON files with chip identification information and establishes mapping relationships using resource type names as key fields. This allows the type definitions and hierarchical relationships defined in the XML to be reused by the JSON files of multiple preset FPGA chips. When adding a new chip model, only a lightweight JSON file associated with the chip's identification information needs to be added to describe its grid layout, eliminating the need to repeatedly store the type definitions and hierarchical relationships of each resource type. This significantly reduces storage redundancy and development and maintenance costs associated with multi-chip support, effectively solving the problem of poor multi-chip scalability caused by tight coupling between architecture and instance in existing technologies. Furthermore, since the XML file explicitly records the hierarchical inclusion relationship of "repeatable physical layout unit → minimum circuit module / programmable switch → pin / interconnect / basic logic unit," and the JSON file records each grid location in key-value pairs... The data includes type identification information. Each graphic item in the constructed wiring resource dataset carries the geometric location information, type definition, and hierarchical relationship of the resource. This enables visualization tools to achieve data-driven general layered rendering based on this dataset, eliminating the need to write dedicated parsing code for each chip. This solves the problem in existing technologies where flat storage lacks explicit expression of hierarchical relationships, making it difficult for visualization tools to directly parse and display layered data. Furthermore, this visualization graphical interface responds to user operations such as retrieval, hovering or clicking to view attributes, and customizing netting coloring. This allows users to quickly locate and analyze specific resources, combining abstract design data with intuitive visual feedback, significantly improving the efficiency of FPGA design verification and debugging. Simultaneously, this embodiment pre-converts resource data into a vector path data structure and combines layered rendering and on-demand loading strategies to dynamically determine the display granularity based on the view scaling ratio. This effectively reduces the number of graphic objects and computational overhead during dynamic drawing, supporting smooth scaling, panning, and real-time refreshing of large-scale resource nodes.

[0082] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0083] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0084] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for storing and visualizing FPGA chip resources based on XML and JSON collaboration, characterized in that, include: Construct an XML file and multiple JSON files. The XML file is used to store the type definitions and hierarchical relationships of various resource types inside the FPGA chip. The JSON files are used to store the type identification information of resources at each grid location. Each JSON file corresponds to a preset FPGA chip and is associated with the chip identification information of the preset FPGA chip. For each resource at each grid position in the JSON file, establish a mapping association between the type identification information and the type definition and hierarchical relationship corresponding to the resource in the XML file; The corresponding JSON file is loaded according to the chip identification information of the target FPGA chip. Based on the mapping association of the resources corresponding to each grid position in the JSON file, a routing resource dataset containing multiple graphic items is constructed. Each graphic item corresponds to a resource inside the target FPGA chip and carries the geometric position information of the resource, as well as the type definition and hierarchical relationship. A visual graphical interface is generated based on the aforementioned cabling resource dataset; In response to user actions on the graphical interface, the system performs location and display feedback on the target resource.

2. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 1, characterized in that, The resource types include repeatable physical layout units, minimum circuit modules, pins, interconnects, programmable switches, and basic logic units; The hierarchical relationship includes: The repeatable physical layout unit includes the minimum circuit module; the minimum circuit module includes the basic logic unit and the pin; the interconnect line connects each of the minimum circuit modules starting from the pin; the programmable switch is disposed between each of the repeatable physical layout units and is used to achieve signal interconnection between the repeatable physical layout units together with the interconnect line.

3. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 2, characterized in that, The XML file includes: A chip label is used to describe a preset FPGA chip, including a model name field and a repeatable physical layout unit type name list field. The model name field is used to record the model name of the preset FPGA chip, and the repeatable physical layout unit type name list field is used to record the type names of all repeatable physical layout units contained in the preset FPGA chip. A repeatable physical layout unit tag is used to describe a repeatable physical layout unit, including a name field of the repeatable physical layout unit, a list field of type names of the minimum circuit modules contained therein, and a shape coordinate field, wherein the shape coordinate field is used to represent the shape of the repeatable physical layout unit. Minimum circuit module label, used to describe a minimum circuit module, including the name field, first geometric position information field, shape coordinate field, pin information field, basic logic unit information field, and interconnect information field of the minimum circuit module, wherein the first geometric position information field is used to describe the geometric position of the minimum circuit module relative to its topping repeatable physical layout unit; A programmable switch label is used to describe a programmable switch, including a switch name field, a drawing shape type field, a second geometric position information field, and a connection relationship information field. The connection relationship information field includes an input signal source list field and an output signal target list field for the programmable switch. The second geometric position information field is used to describe the geometric position of the programmable switch relative to its respective repeatable physical layout unit.

4. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 3, characterized in that, In the minimum circuit module label, the pin information field describes the pin information of the minimum circuit module. The pin information includes the name, drawing shape type, pin type, and orientation of each pin in the minimum circuit module, as well as the spacing between pins and the geometric position of each pin relative to the minimum circuit module. The interconnect information field describes the interconnect information of interconnects originating from the pins of the minimum circuit module. The interconnect information includes at least one of the following connection relationship description methods: Direct interconnection between the two pins; Jump connections implemented via hard channels; An interconnecting line is composed of multiple line segments, and the path of each line segment is defined by multiple coordinate points; Interconnecting lines, consisting of a set of line segments, are described in batches by defining the coordinates of the first line segment and the offset rules of subsequent line segments.

5. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 3, characterized in that, The JSON file includes an FPGA chip model name field and a layout data array field. The layout data array field contains multiple layout record objects. Each layout record object records the column number, row number, and type name of the repeatable physical layout unit of its corresponding grid position in key-value pairs.

6. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 2, characterized in that, The type identifier information is the type name of the resource, and the chip identifier information is the model name of the FPGA chip; the step of establishing a mapping association between the type identifier information of the resource at each grid position in the JSON file and the type definition and hierarchical relationship corresponding to the resource in the XML file includes: Using the resource type name as the key field, the resource type name recorded in each grid position of the JSON file is associated with the type definition and hierarchical relationship of the resource type corresponding to that type name in the XML file. Each grid position indexes the corresponding type definition and hierarchical relationship in the XML file through its corresponding type name.

7. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 1, characterized in that, The wiring resource dataset, which is constructed based on the mapping associations corresponding to the resources at each grid position in the JSON file and contains multiple graphical items, includes: Obtain the grid positions and their corresponding type identifiers from the JSON file, and based on the obtained type identifiers and their corresponding mapping associations, obtain the corresponding type definitions and hierarchical relationships from the XML file; Resource objects are instantiated based on the type definition and hierarchical relationship corresponding to each grid position in the JSON file, and the graphic position of the corresponding resource object is calculated based on the position information of each grid position, thereby generating graphic items corresponding to each resource object.

8. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 1, characterized in that, The step of generating a visual graphical interface based on the cabling resource dataset includes: The display hierarchy is determined based on the display parameters of the current view; Select a graphic item from the wiring resource dataset that matches the display level and the view extent of the current view; The selected graphic items are converted into drawing data and then drawn to generate the visual graphical interface. The display layers are multiple, each display layer corresponds to a different resource type, and different display layers correspond to different resource display granularities. The display layers include at least a repeatable physical layout unit layer, a minimum circuit module layer, and an interconnection resource layer.

9. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 1, characterized in that, The response to a user's operation on the graphical interface, performing location and display feedback on the target resource, includes at least one of the following: In response to the target resource identifier entered by the user, locate and highlight the corresponding graphical item in the view; In response to a user's hover or click action on a graphical item, display the attribute information of the resource corresponding to that graphical item; In response to the user's color selection operation for the target mesh, change the drawing color of the graphic items covered by the target mesh.

10. The FPGA chip resource storage and visualization method based on XML and JSON collaboration according to claim 9, characterized in that, The step of changing the drawing color of the graphic items covered by the target mesh in response to the user's color selection operation includes: Establish and maintain the mapping relationship between each net and the graphic items it covers; In response to the user's color selection operation for the target mesh, all graphic items covered by the target mesh are obtained according to the mapping relationship; Change the drawing color of all the obtained graphic items uniformly, and refresh the view.

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